JP2008311347A5 - - Google Patents
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- Publication number
- JP2008311347A5 JP2008311347A5 JP2007156303A JP2007156303A JP2008311347A5 JP 2008311347 A5 JP2008311347 A5 JP 2008311347A5 JP 2007156303 A JP2007156303 A JP 2007156303A JP 2007156303 A JP2007156303 A JP 2007156303A JP 2008311347 A5 JP2008311347 A5 JP 2008311347A5
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- interposer
- wiring pattern
- tape substrate
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 claims 14
- 239000000758 substrate Substances 0.000 claims 9
- 239000000853 adhesive Substances 0.000 claims 2
- 230000001070 adhesive effect Effects 0.000 claims 2
- 238000000034 method Methods 0.000 claims 2
- 239000011347 resin Substances 0.000 claims 2
- 229920005989 resin Polymers 0.000 claims 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 claims 1
Claims (4)
集積回路が形成された能動面及び前記能動面の反対面となる裏面を有し、前記インターポーザにフリップチップ実装された半導体チップと、
配線パターンが形成された第1の面及び前記第1の面の反対面となる第2の面を有し、前記第2の面と前記半導体チップの前記裏面とが接着剤によって接続されたテープ基板と、
前記インターポーザの前記電極パッドに電気的に接続されており、前記インターポーザに実装された第1の受動部品と、
前記配線パターンに電気的に接続しており、前記テープ基板の前記第1の面に実装された第2の受動部品と、
を備え、
前記テープ基板は、前記配線パターンに電気的に接続している外延リードを有し、
前記外延リードを介して前記配線パターンと前記インターポーザとが電気的に接続しており、
前記半導体チップ、前記テープ基板並びに前記第1及び第2の受動部品は、樹脂によって覆われており、
前記電極パッドは、前記半導体チップを囲むように設けられていることを特徴とする半導体モジュール。 An interposer having electrode pads ;
A semiconductor chip having an active surface on which an integrated circuit is formed and a back surface opposite to the active surface, and flip-chip mounted on the interposer ;
A tape having a first surface on which a wiring pattern is formed and a second surface opposite to the first surface, wherein the second surface and the back surface of the semiconductor chip are connected by an adhesive. A substrate,
A first passive component electrically connected to the electrode pad of the interposer and mounted on the interposer;
A second passive component electrically connected to the wiring pattern and mounted on the first surface of the tape substrate;
With
The tape substrate has an extended lead electrically connected to the wiring pattern,
The wiring pattern and the interposer are electrically connected through the extended lead ,
The semiconductor chip, the tape substrate, and the first and second passive components are covered with resin,
The semiconductor module , wherein the electrode pad is provided so as to surround the semiconductor chip .
複数の電極パッドを有するインターポーザに、前記半導体チップが複数の前記電極パッドに囲まれるようにして前記半導体チップをフリップチップ実装する工程と、
前記半導体チップの前記裏面に、前記第1の面とは反対側の第2の面を対向させて前記テープ基板を接着剤により貼り合わせる工程と、
前記インターポーザ上に第1の受動部品を実装する工程と、
前記テープ基板の前記第1の面上に第2の受動部品を実装する工程と、
前記インターポーザと前記配線パターンとを、前記外延リードを介して電気的に接続する工程と、
前記半導体チップ、前記テープ基板並びに前記第1及び第2の受動部品を樹脂により覆う工程と、
を含むことを特徴とする半導体モジュールの製造方法。 A semiconductor chip having a rear surface on the opposite side of the active surface and the active surface of the integrated circuit is formed, and the tape substrate having the extension leads connecting the wiring pattern and the wiring pattern formed on the first surface, Prepare
Flip chip mounting the semiconductor chip on an interposer having a plurality of electrode pads so that the semiconductor chip is surrounded by the plurality of electrode pads ;
Bonding the tape substrate with an adhesive with the second surface opposite to the first surface facing the back surface of the semiconductor chip;
Mounting a first passive component on the interposer;
Mounting a second passive component on the first surface of the tape substrate;
Electrically connecting the interposer and the wiring pattern via the extension leads;
Covering the semiconductor chip, the tape substrate, and the first and second passive components with a resin;
A method for manufacturing a semiconductor module, comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007156303A JP2008311347A (en) | 2007-06-13 | 2007-06-13 | Semiconductor module and its manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007156303A JP2008311347A (en) | 2007-06-13 | 2007-06-13 | Semiconductor module and its manufacturing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008311347A JP2008311347A (en) | 2008-12-25 |
JP2008311347A5 true JP2008311347A5 (en) | 2010-07-22 |
Family
ID=40238719
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007156303A Withdrawn JP2008311347A (en) | 2007-06-13 | 2007-06-13 | Semiconductor module and its manufacturing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2008311347A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7989942B2 (en) * | 2009-01-20 | 2011-08-02 | Altera Corporation | IC package with capacitors disposed on an interposal layer |
JP6015144B2 (en) | 2012-06-04 | 2016-10-26 | 富士通株式会社 | Electronic device and semiconductor device |
-
2007
- 2007-06-13 JP JP2007156303A patent/JP2008311347A/en not_active Withdrawn
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