JP2008311347A5 - - Google Patents

Download PDF

Info

Publication number
JP2008311347A5
JP2008311347A5 JP2007156303A JP2007156303A JP2008311347A5 JP 2008311347 A5 JP2008311347 A5 JP 2008311347A5 JP 2007156303 A JP2007156303 A JP 2007156303A JP 2007156303 A JP2007156303 A JP 2007156303A JP 2008311347 A5 JP2008311347 A5 JP 2008311347A5
Authority
JP
Japan
Prior art keywords
semiconductor chip
interposer
wiring pattern
tape substrate
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2007156303A
Other languages
Japanese (ja)
Other versions
JP2008311347A (en
Filing date
Publication date
Application filed filed Critical
Priority to JP2007156303A priority Critical patent/JP2008311347A/en
Priority claimed from JP2007156303A external-priority patent/JP2008311347A/en
Publication of JP2008311347A publication Critical patent/JP2008311347A/en
Publication of JP2008311347A5 publication Critical patent/JP2008311347A5/ja
Withdrawn legal-status Critical Current

Links

Claims (4)

電極パッドを有するインターポーザと、
集積回路が形成された能動面及び前記能動面の反対面となる裏面を有し、前記インターポーザにフリップチップ実装された半導体チップと、
配線パターンが形成された第1の面及び前記第1の面の反対面となる第2の面を有し、前記第2の面と前記半導体チップの前記裏面とが接着剤によって接続されたテープ基板と、
前記インターポーザの前記電極パッドに電気的に接続されており、前記インターポーザに実装された第1の受動部品と、
前記配線パターンに電気的に接続しており、前記テープ基板の前記第1の面に実装された第2の受動部品と、
を備え、
前記テープ基板は、前記配線パターンに電気的に接続している外延リードを有し、
前記外延リードを介して前記配線パターン前記インターポーザとが電気的に接続しており、
前記半導体チップ、前記テープ基板並びに前記第1及び第2の受動部品は、樹脂によって覆われており、
前記電極パッドは、前記半導体チップを囲むように設けられていることを特徴とする半導体モジュール。
An interposer having electrode pads ;
A semiconductor chip having an active surface on which an integrated circuit is formed and a back surface opposite to the active surface, and flip-chip mounted on the interposer ;
A tape having a first surface on which a wiring pattern is formed and a second surface opposite to the first surface, wherein the second surface and the back surface of the semiconductor chip are connected by an adhesive. A substrate,
A first passive component electrically connected to the electrode pad of the interposer and mounted on the interposer;
A second passive component electrically connected to the wiring pattern and mounted on the first surface of the tape substrate;
With
The tape substrate has an extended lead electrically connected to the wiring pattern,
The wiring pattern and the interposer are electrically connected through the extended lead ,
The semiconductor chip, the tape substrate, and the first and second passive components are covered with resin,
The semiconductor module , wherein the electrode pad is provided so as to surround the semiconductor chip .
前記外延リードは、その先端に金バンプまたはハンダバンプを有していることを特徴とする請求項1記載の半導体モジュール。   2. The semiconductor module according to claim 1, wherein the extended lead has a gold bump or a solder bump at its tip. 集積回路が形成された能動面及び前記能動面の反対面となる裏面を有する半導体チップと、第1の面側に形成された配線パターン及び前記配線パターンに接続する外延リードを有するテープ基板と、を用意し、
複数の電極パッドを有するインターポーザに、前記半導体チップが複数の前記電極パッドに囲まれるようにして前記半導体チップをフリップチップ実装する工程と、
前記半導体チップの前記裏面に、前記第1の面とは反対側の第2の面を対向させて前記テープ基板を接着剤により貼り合わせる工程と、
前記インターポーザ上に第1の受動部品を実装する工程と、
前記テープ基板の前記第1の面上に第2の受動部品を実装する工程と、
前記インターポーザと前記配線パターンとを、前記外延リードを介して電気的に接続する工程と、
前記半導体チップ、前記テープ基板並びに前記第1及び第2の受動部品を樹脂により覆う工程と、
を含むことを特徴とする半導体モジュールの製造方法。
A semiconductor chip having a rear surface on the opposite side of the active surface and the active surface of the integrated circuit is formed, and the tape substrate having the extension leads connecting the wiring pattern and the wiring pattern formed on the first surface, Prepare
Flip chip mounting the semiconductor chip on an interposer having a plurality of electrode pads so that the semiconductor chip is surrounded by the plurality of electrode pads ;
Bonding the tape substrate with an adhesive with the second surface opposite to the first surface facing the back surface of the semiconductor chip;
Mounting a first passive component on the interposer;
Mounting a second passive component on the first surface of the tape substrate;
Electrically connecting the interposer and the wiring pattern via the extension leads;
Covering the semiconductor chip, the tape substrate, and the first and second passive components with a resin;
A method for manufacturing a semiconductor module, comprising:
前記第1のインターポーザに前記半導体チップを実装した後、前記半導体チップに前記テープ基板を貼り合わせることを特徴とする請求項3に記載の半導体モジュールの製造方法。 After mounting the semiconductor chip on the first interposer The method as claimed in claim 3, characterized in that bonding the tape substrate to the semiconductor chip.
JP2007156303A 2007-06-13 2007-06-13 Semiconductor module and its manufacturing method Withdrawn JP2008311347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007156303A JP2008311347A (en) 2007-06-13 2007-06-13 Semiconductor module and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007156303A JP2008311347A (en) 2007-06-13 2007-06-13 Semiconductor module and its manufacturing method

Publications (2)

Publication Number Publication Date
JP2008311347A JP2008311347A (en) 2008-12-25
JP2008311347A5 true JP2008311347A5 (en) 2010-07-22

Family

ID=40238719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007156303A Withdrawn JP2008311347A (en) 2007-06-13 2007-06-13 Semiconductor module and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2008311347A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7989942B2 (en) * 2009-01-20 2011-08-02 Altera Corporation IC package with capacitors disposed on an interposal layer
JP6015144B2 (en) 2012-06-04 2016-10-26 富士通株式会社 Electronic device and semiconductor device

Similar Documents

Publication Publication Date Title
US9449941B2 (en) Connecting function chips to a package to form package-on-package
JP5320611B2 (en) Stack die package
US7871865B2 (en) Stress free package and laminate-based isolator package
WO2006105015A3 (en) Flip chip interconnection having narrow interconnection sites on the substrate
US20060192294A1 (en) Chip scale package having flip chip interconnect on die paddle
US20120199960A1 (en) Wire bonding for interconnection between interposer and flip chip die
JP2006093189A5 (en)
JP2008283195A5 (en)
JP2014515187A5 (en)
WO2007086937A3 (en) Land grid array semiconductor device packages, assemblies including same, and methods of fabrication
SG149896A1 (en) Methods of fabrication of lead frame-based semiconductor device packages incorporating at least one land grid array package
JP2008091719A5 (en)
TW200636951A (en) Pillar grid array package
JP2008311347A5 (en)
TW200743198A (en) COB type IC package for improving bonding of bumps embedded in substrate and method for fabricating the same
JP2013125765A (en) Semiconductor device
US20150115437A1 (en) Universal encapsulation substrate, encapsulation structure and encapsulation method
US11862544B2 (en) Electronic assembly
JP2012146882A (en) Semiconductor device
US7781898B2 (en) IC package reducing wiring layers on substrate and its chip carrier
JP2009177123A (en) Stacked-chip package structure and manufacturing method thereof
JP2007234960A5 (en)
TWI272729B (en) Multi-chip sensor package
JP6320681B2 (en) Semiconductor device
JP5377366B2 (en) Semiconductor device