JP2008288287A - Trench gate semiconductor device - Google Patents

Trench gate semiconductor device Download PDF

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JP2008288287A
JP2008288287A JP2007129934A JP2007129934A JP2008288287A JP 2008288287 A JP2008288287 A JP 2008288287A JP 2007129934 A JP2007129934 A JP 2007129934A JP 2007129934 A JP2007129934 A JP 2007129934A JP 2008288287 A JP2008288287 A JP 2008288287A
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type semiconductor
trench
semiconductor layer
electrode
gate
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Ryosuke Okawa
亮介 大河
Takashi Miura
孝 三浦
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Panasonic Corp
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Panasonic Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a trench gate semiconductor device capable of increasing a device breakdown strength by equalizing a field strength on the bottom section of a trench extensively over the overall length of the trench. <P>SOLUTION: The trench gate semiconductor device has a plurality of the trenches 55 reaching an N-type semiconductor layer 53 by penetrating a P-type semiconductor layer 54 placed on one main surface side of a semiconductor substrate 100, has N<SP>+</SP>type semiconductor layers 59 along both sides of the trenches 55 and has P<SP>+</SP>type semiconductor layers 60 among the N<SP>+</SP>type semiconductor layers 59. The trench gate semiconductor device further has gate electrodes 27 to the trenches 55 and source electrodes 62 joined with the N<SP>+</SP>type semiconductor layers 59 and the P<SP>+</SP>type semiconductor layers 60. The P<SP>+</SP>type semiconductor layers 60 are extended substantially along the overall lengths of the trenches 55. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明はトレンチゲート型半導体装置に関し、トレンチ内に絶縁膜を介して埋め込まれた制御用のゲート電極を有するＭＯＳＦＥＴ（Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ：電解効果トランジスタ）やＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｔｒａｎｓｉｓｔｏｒ）、絶縁ゲートサイリスタ等のトレンチゲート構造を有するＭＯＳ型トランジスタ等の技術に係るものである。   The present invention relates to a trench gate type semiconductor device, and relates to a MOSFET (Metal Oxide Semiconductor Field Transistor Transistor), an IGBT (Insulated Gate Transistor), an insulating gate transistor, and an insulating gate transistor having a control gate electrode embedded in an insulating film through an insulating film. The present invention relates to a technology such as a MOS transistor having a trench gate structure such as a gate thyristor.

従来、この種のトレンチゲート型半導体装置においては、そのゲート終端構造として、酸化膜成長時に発生する応力を緩和するためにプロセスの高温化や丸め酸化などを用いるもの、終端部構造に曲率を持たせるもの、隣接するトレンチラインの終端部同士を緩やかな曲率を持たせて結合することで応力を緩和しているものがあった。   Conventionally, in this type of trench gate type semiconductor device, the gate termination structure uses a high temperature process or rounding oxidation in order to relieve stress generated during oxide film growth, and the termination structure has a curvature. In some cases, the stress is relieved by joining the end portions of adjacent trench lines with a gentle curvature.

従来のトレンチゲート型半導体装置としては、例えば図７〜図９に示すものがある。このトレンチゲート型半導体装置は、半導体基板が基層をなすＰ＋＋型基板２０の表面に複数の半導体層をエピタキシャル成長により形成してなり、Ｐ＋＋型基板２０の表面にＮ＋型半導体層２１を形成し、Ｎ＋型半導体層２１の表面にＮ−型半導体層２２を形成し、Ｎ−型半導体層２２の表面にＮ型半導体層２３を形成し、Ｎ型半導体層２３の表面にＰ型半導体層２４を形成している。 Examples of conventional trench gate type semiconductor devices include those shown in FIGS. In this trench gate type semiconductor device, a plurality of semiconductor layers are formed by epitaxial growth on the surface of a P ++ type substrate 20 whose semiconductor substrate forms a base layer, and an N + type semiconductor layer 21 is formed on the surface of the P ++ type substrate 20. Then, an N − type semiconductor layer 22 is formed on the surface of the N + type semiconductor layer 21, an N type semiconductor layer 23 is formed on the surface of the N − type semiconductor layer 22, and a P type semiconductor is formed on the surface of the N type semiconductor layer 23. Layer 24 is formed.

さらにＰ型半導体層２４貫通してＮ型半導体層２３に達する複数のトレンチ２５を形成しており、トレンチ２５の内部に酸化膜（ゲート酸化膜）２６、ポリシリコンからなるゲート電極２７及び絶縁膜２８が形成してある。隣接し合うトレンチ２５の間には、Ｐ型半導体層２４の表面にＮ＋型半導体層２９及びＰ＋型半導体層３０を形成しており、ソースとなるＮ＋型半導体層２９は酸化膜２６および絶縁膜２８に隣接し、Ｎ＋型半導体層２９の間にＰ＋型半導体層３０が位置している。このＰ＋型半導体層３０は接触抵抗を下げるためのものである。 Further, a plurality of trenches 25 that penetrate the P-type semiconductor layer 24 and reach the N-type semiconductor layer 23 are formed. Inside the trench 25, an oxide film (gate oxide film) 26, a gate electrode 27 made of polysilicon, and an insulating film are formed. 28 is formed. Between adjacent mutually trench 25 forms a N + -type semiconductor layer 29 and the P + -type semiconductor layer 30 on the surface of the P-type semiconductor layer 24, N + -type semiconductor layer 29 serving as the source oxide film 26 The P + type semiconductor layer 30 is located between the N + type semiconductor layer 29 and adjacent to the insulating film 28. This P + type semiconductor layer 30 is for lowering the contact resistance.

トレンチ２５の終端部はゲート電極２７の引き出し部をなし、各ゲート電極２７の端部を相互に接続する埋め込みゲート電極（ポリシリコン）３１がトレンチ２５の終端部上から半導体素子の端部縁までを覆っている。   The terminal portion of the trench 25 forms a lead-out portion of the gate electrode 27, and a buried gate electrode (polysilicon) 31 that connects the end portions of the gate electrodes 27 to each other extends from the end portion of the trench 25 to the end edge of the semiconductor element. Covering.

半導体基板の一方の主面側にはソース電極３２がＮ＋型半導体層２９及びＰ＋型半導体層３０の表面に形成してあり、他方の主面側にはドレイン電極（図示省略）がＰ＋＋型基板２０の裏面に形成してある。Ｐ＋型半導体層３０は一般にボディコンタクト電極と呼ばれ、ソース電極３２と同電位になるように接続している。埋め込みゲート電極３１は絶縁膜３３によってソース電極３２と絶縁してある。半導体基板の外側部には複数のガードリング層３４を形成している。 A source electrode 32 is formed on the surface of the N + type semiconductor layer 29 and the P + type semiconductor layer 30 on one main surface side of the semiconductor substrate, and a drain electrode (not shown) is formed on the other main surface side. It is formed on the back surface of the ++ type substrate 20. The P + type semiconductor layer 30 is generally called a body contact electrode and is connected so as to have the same potential as the source electrode 32. The buried gate electrode 31 is insulated from the source electrode 32 by an insulating film 33. A plurality of guard ring layers 34 are formed on the outer side of the semiconductor substrate.

このトレンチゲート型半導体装置では、ドレイン電極（図示省略）に正電位の電圧を印加し、ソース電極３２を接地する。この条件下で、埋め込みゲート電極３１を通して各ゲート電極２７に閾値以上の正電位の電圧を印加すると、各トレンチ２５のゲート電極２７と酸化膜２６を介して隣接するＰ型半導体層２４にチャネルが形成され、ドレイン電極からソース電極３２に向かって電流が流れて動作状態となる。   In this trench gate type semiconductor device, a positive potential voltage is applied to the drain electrode (not shown), and the source electrode 32 is grounded. Under this condition, when a voltage having a positive potential equal to or higher than the threshold is applied to each gate electrode 27 through the buried gate electrode 31, a channel is formed in the P-type semiconductor layer 24 adjacent to the gate electrode 27 of each trench 25 through the oxide film 26. As a result, a current flows from the drain electrode toward the source electrode 32 to be in an operating state.

以下にトレンチゲート型半導体装置の製造方法を説明する。図１０〜図１２は、各製造工程における断面を示し、図１０（ａ）のＡ−Ａ’線断面に対応している。図１３〜図１４は、各製造工程における断面を示し、図１３（ａ）のＡ−Ａ’線断面に対応している。   A method for manufacturing the trench gate type semiconductor device will be described below. 10 to 12 show cross sections in each manufacturing process, and correspond to the cross section taken along the line A-A 'of FIG. 13 to 14 show cross sections in each manufacturing process, and correspond to the cross section taken along the line A-A 'of FIG.

図１０（ｂ）および図１３（ｂ）に示すように、基層をなすＰ＋＋型基板２０の表面上にＰ＋＋型基板２０と異なる導電型で高濃度のＮ＋型半導体層２１をエピタキシャル成長させ、Ｎ＋型半導体層２１の表面上に同導電型で低濃度のＮ−型半導体層２２をエピタキシャル成長させる。 As shown in FIGS. 10B and 13B, a high-concentration N + type semiconductor layer 21 having a conductivity type different from that of the P ++ type substrate 20 is epitaxially grown on the surface of the P ++ type substrate 20 forming the base layer. The low conductivity N − type semiconductor layer 22 is epitaxially grown on the surface of the N + type semiconductor layer 21.

図１０（ｃ）および図１３（ｃ）に示すように、Ｎ−型半導体層２２にドーパントを拡散させて、Ｎ−型半導体層２２の上側域に異なる導電型のＰ型半導体層２４を形成し、Ｐ型半導体層２４の下側域にＮ型半導体層２３を形成する。 As shown in FIG. 10 (c) and FIG. 13 (c), N - -type semiconductor layer 22 by diffusing a dopant, N - -type semiconductor layer P-type semiconductor layer 24 of different conductivity type in the upper region of 22 Then, the N-type semiconductor layer 23 is formed in the lower region of the P-type semiconductor layer 24.

図１０（ｄ）および図１３（ｄ）に示すように、Ｐ型半導体層２４を貫通し、Ｎ型半導体層２３に達する複数のトレンチ２５を形成する。
図１１（ａ）および図１４（ａ）に示すように、トレンチ２５の内壁面およびＰ型半導体層２４の表面にＳｉＯ２の酸化膜２６を形成し、酸化膜２６に囲まれたトレンチ２５の内部および酸化膜２６を介したＰ型半導体層２４の上側域にポリシリコンを積層する。 As shown in FIGS. 10D and 13D, a plurality of trenches 25 that penetrate the P-type semiconductor layer 24 and reach the N-type semiconductor layer 23 are formed.
As shown in FIGS. 11A and 14A, an SiO 2 oxide film 26 is formed on the inner wall surface of the trench 25 and the surface of the P-type semiconductor layer 24, and the trench 25 surrounded by the oxide film 26 is formed. Polysilicon is laminated inside and on the upper region of the P-type semiconductor layer 24 via the oxide film 26.

図１１（ｂ）に示すように、ポリシリコン層および酸化膜２６を選択的にエッチングしてトレンチ２５に残るポリシリコン層でゲート電極２７を形成し、トレンチ２５の終端部上から半導体素子の端部縁までを覆って残るポリシリコン層で埋め込みゲート電極３１を形成する。   As shown in FIG. 11B, the polysilicon layer and the oxide film 26 are selectively etched to form the gate electrode 27 with the polysilicon layer remaining in the trench 25, and the end of the semiconductor element is formed from the terminal portion of the trench 25. A buried gate electrode 31 is formed of a polysilicon layer that covers up to the edge.

図１１（ｃ）に示すように、Ｐ型半導体層２４にドーパントを拡散させて、トレンチ２５に隣接してソース（エミッター）のＮ＋型半導体層２９を形成する。
図１２（ａ）に示すように、マスク３５を介してドーパントを拡散させて、Ｎ＋型半導体層２９を貫通してＰ型半導体層２４に達するＰ＋型半導体層３０を形成する。 As shown in FIG. 11C, a dopant is diffused into the P-type semiconductor layer 24 to form a source (emitter) N + -type semiconductor layer 29 adjacent to the trench 25.
As shown in FIG. 12A, a dopant is diffused through a mask 35 to form a P + type semiconductor layer 30 that reaches the P type semiconductor layer 24 through the N + type semiconductor layer 29.

図１２（ｂ）および図１４（ｂ）に示すように、半導体基板の一方の主面を覆ってＳｉＯ２の層間絶縁膜を積層し、選択的なエッチングによりトレンチ２５の内部のゲート電極２７の上に絶縁膜２８を形成し、埋め込みゲート電極３１の上に絶縁膜３３を形成する。 As shown in FIGS. 12B and 14B, a SiO 2 interlayer insulating film is laminated so as to cover one main surface of the semiconductor substrate, and the gate electrode 27 inside the trench 25 is selectively etched. An insulating film 28 is formed thereon, and an insulating film 33 is formed on the buried gate electrode 31.

図１２（ｃ）および図１４（ｃ）に示すように、半導体基板の一方の主面を覆ってアルミからなるソース電極３２を形成し、ソース電極３２をＮ＋型半導体層２９とＰ＋型半導体層３０に接合し、ソース電極３２とゲート電極２７を絶縁膜２８で絶縁し、ソース電極３２と埋め込みゲート電極３１を絶縁膜３３で絶縁する。
特開平１０−２５６５４５号公報 As shown in FIGS. 12C and 14C, a source electrode 32 made of aluminum is formed so as to cover one main surface of the semiconductor substrate, and the source electrode 32 is formed of an N + type semiconductor layer 29 and a P + type. Bonded to the semiconductor layer 30, the source electrode 32 and the gate electrode 27 are insulated by the insulating film 28, and the source electrode 32 and the buried gate electrode 31 are insulated by the insulating film 33.
Japanese Patent Laid-Open No. 10-256545

ところで、トレンチゲート構造を有するデバイスにおいては、トレンチ２５の底部で起きる電界集中がデバイスの耐圧を決めており、ブレークダウンはトレンチ２５の底部で発生する。   By the way, in a device having a trench gate structure, the electric field concentration occurring at the bottom of the trench 25 determines the breakdown voltage of the device, and breakdown occurs at the bottom of the trench 25.

しかしながら、上述した構成においては、各ゲート電極２７の端部を相互に接続する埋め込みゲート電極（ポリシリコン）３１がトレンチ２５の終端部上から半導体素子の端部縁までを帯状に覆っており、ソースとなるＮ＋型半導体層２９およびボディコンタクト電極のＰ＋型半導体層３０をトレンチ２５の終端部にまで形成していない。これは製造工程において、埋め込みゲート電極３１を形成した後にＮ＋型半導体層２９およびＰ＋型半導体層３０を形成するからである。 However, in the above-described configuration, the buried gate electrode (polysilicon) 31 that connects the ends of the gate electrodes 27 to each other covers the band from the terminal end of the trench 25 to the edge of the semiconductor element, The N + type semiconductor layer 29 serving as the source and the P + type semiconductor layer 30 serving as the body contact electrode are not formed up to the end of the trench 25. This is because the N + type semiconductor layer 29 and the P + type semiconductor layer 30 are formed after forming the buried gate electrode 31 in the manufacturing process.

このように、トレンチ２５の終端部では、ソース電極３２と同電位のボディコンタクト電極であるＰ＋型半導体層３０が存在しないので、終端部における半導体基板の表面上の電位をソース電位に固定することができない。電位を固定していない場合には、トレンチ２５の底部の電界強度はコレクタの電位によって決まり、その値は電位を固定している場合よりも高くなる。 Thus, since the P + -type semiconductor layer 30 that is the body contact electrode having the same potential as the source electrode 32 does not exist at the termination portion of the trench 25, the potential on the surface of the semiconductor substrate at the termination portion is fixed to the source potential. I can't. When the potential is not fixed, the electric field strength at the bottom of the trench 25 is determined by the potential of the collector, and the value is higher than when the potential is fixed.

この結果、トレンチ２５の底部で起きる電界集中は、中間部よりも終端部において大きくなり、デバイス耐圧が低下する要因となっている。
本発明は上記の課題を解決するものであり、トレンチの底部における電界強度をトレンチの全長にわたって均一化してデバイス耐圧を向上させることができるトレンチゲート型半導体装置を提供することを目的とする。 As a result, the electric field concentration occurring at the bottom of the trench 25 becomes larger at the terminal portion than at the middle portion, which causes a reduction in device breakdown voltage.
An object of the present invention is to provide a trench gate type semiconductor device capable of improving the device breakdown voltage by making the electric field strength at the bottom of the trench uniform over the entire length of the trench.

上記課題を解決するために、本発明のトレンチゲート型半導体装置は、半導体基板が基層上に複数の半導体領域を層状に重ねて形成してなり、前記半導体基板の一方の主面側に位置する第１の半導体領域を貫通して下層の第２の半導体領域に達する複数のトレンチを有し、第１の半導体領域中に前記トレンチの両側に沿って第３の半導体領域を有するとともに、前記トレンチの相互間において第３の半導体領域間に第４の半導体領域を有し、第１の半導体領域と第４の半導体領域が同じ導電型をなし、第２の半導体領域と第３の半導体領域が同じ導電型をなし、前記トレンチに電気的に周囲から絶縁した第１の電極を有し、第３の半導体領域および第４の半導体領域に接合する第２の電極を有し、前記半導体基板を介して第２の電極に対向する第３の電極を有し、第４の半導体領域が実質的に前記トレンチの全長に沿って延在することを特徴とする。   In order to solve the above-described problems, a trench gate type semiconductor device according to the present invention is formed by stacking a plurality of semiconductor regions on a base layer in a layered manner and located on one main surface side of the semiconductor substrate. A plurality of trenches that penetrate the first semiconductor region and reach the second semiconductor region in the lower layer; and a third semiconductor region along both sides of the trench in the first semiconductor region, and the trench A fourth semiconductor region between the third semiconductor regions, the first semiconductor region and the fourth semiconductor region have the same conductivity type, and the second semiconductor region and the third semiconductor region are A first electrode having the same conductivity type and electrically insulated from the surroundings in the trench; a second electrode joined to a third semiconductor region and a fourth semiconductor region; Through the second electrode And a third electrode, the fourth semiconductor region, characterized in that extending along the entire length of substantially the trench.

また、各トレンチの第１の電極に接合する埋め込み電極が前記トレンチの終端部を覆って前記半導体基板の端部縁にまで延在し、かつ第４の半導体領域の上側に存在せず、前記埋め込み電極は前記トレンチの相互間に少なくとも前記トレンチの終端部にまで後退した切欠き部を有し、かつ前記切欠き部において第４の半導体領域の終端部に沿うことを特徴とする。   Further, a buried electrode joined to the first electrode of each trench extends to the edge of the semiconductor substrate so as to cover the terminal end of the trench, and does not exist on the upper side of the fourth semiconductor region, The buried electrode has a notch that is recessed at least to the end of the trench between the trenches, and extends along the end of the fourth semiconductor region in the notch.

以上のように本発明によれば、第１の電極がゲート電極をなし、第２の電極および第３の電極のそれそれがソース電極もしくはドレイン電極をなす。ドレイン電極に正電位の電圧を印加し、ソース電極を接地する条件下で、埋め込み電極を通して各ゲート電極に閾値以上の正電位の電圧を印加すると、各トレンチのゲート電極に絶縁層を介して隣接する第１の半導体領域に、ソースの第３の半導体領域からドレインの第２の半導体領域にまでチャネルが形成され、ドレイン電極からソース電極に向かって電流が流れて動作状態となる。   As described above, according to the present invention, the first electrode forms a gate electrode, and the second electrode and the third electrode form a source electrode or a drain electrode. Under the condition that a positive potential voltage is applied to the drain electrode and the source electrode is grounded, a positive potential voltage higher than the threshold value is applied to each gate electrode through the buried electrode, and the gate electrode of each trench is adjacent to each other through an insulating layer. In the first semiconductor region, a channel is formed from the third semiconductor region of the source to the second semiconductor region of the drain, and a current flows from the drain electrode to the source electrode to be in an operating state.

この際に、第４の半導体領域がボディコンタクト電極をなしてソース電極と同電位をなし、この第４の半導体領域が実質的にトレンチの全長に沿って延在することで、トレンチの終端部においてもゲート電極に対向してボディコンタクト電極が存在し、トレンチの終端部における半導体基板の表面上の電位をソース電位に固定することができるので、トレンチの底部で起きる電界集中は、中間部および終端部において等しい電界強度となる。よって、トレンチの終端部での電界集中に起因するデバイス耐圧の低下を防止することができ、トレンチの底部における電界強度をトレンチの全長にわたって均一化してデバイス耐圧を向上させることができる。   At this time, the fourth semiconductor region forms the body contact electrode and has the same potential as the source electrode, and this fourth semiconductor region extends substantially along the entire length of the trench, thereby allowing the end portion of the trench to end. In FIG. 5B, the body contact electrode is present opposite to the gate electrode, and the potential on the surface of the semiconductor substrate at the end of the trench can be fixed to the source potential. The electric field strength is equal at the terminal portion. Therefore, it is possible to prevent the device breakdown voltage from being lowered due to the electric field concentration at the end of the trench, and to improve the device breakdown voltage by making the electric field strength at the bottom of the trench uniform over the entire length of the trench.

以下、本発明の実施の形態を図面に基づいて説明する。図１および図２（ａ）、（ｂ）において、トレンチゲート型半導体装置は、半導体基板１００が基層をなすＰ＋＋型基板５０の表面に複数の半導体層をエピタキシャル成長により形成してなり、Ｐ＋＋型基板５０の表面にＮ＋型半導体層５１を形成し、Ｎ＋型半導体層５１の表面にＮ−型半導体層５２を形成し、Ｎ−型半導体層５２の表面にＮ型半導体層５３を形成し、Ｎ型半導体層５３の表面にＰ型半導体層５４を形成している。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 and 2 (a), (b), the trench gate type semiconductor device, the semiconductor substrate 100 is formed by epitaxial growth a plurality of semiconductor layers on the surface of the P ++ type substrate 50 forming the base layer, P ++ the N + -type semiconductor layer 51 is formed on the surface of the mold substrate 50, N + -type on the surface of the semiconductor layer 51 N - -type semiconductor layer 52 is formed, N - a N-type semiconductor layer 53 on the surface of the type semiconductor layer 52 A P-type semiconductor layer 54 is formed on the surface of the N-type semiconductor layer 53.

半導体基板１００には複数のトレンチ５５を形成しており、トレンチ５５は半導体基板１００の一方の主面側に位置する第１の半導体領域であるＰ型半導体層５４を貫通して下層の第２の半導体領域であるＮ型半導体層５３に達している。トレンチ５５には酸化膜（ゲート酸化膜）５６および絶縁膜５８により電気的に周囲から絶縁した第１の電極をなすポリシリコンのゲート電極５７が形成してある。   A plurality of trenches 55 are formed in the semiconductor substrate 100, and the trenches 55 penetrate the P-type semiconductor layer 54, which is a first semiconductor region located on one main surface side of the semiconductor substrate 100, and form a second lower layer. It reaches the N-type semiconductor layer 53 which is the semiconductor region. In the trench 55, a polysilicon gate electrode 57 is formed as a first electrode electrically insulated from the surroundings by an oxide film (gate oxide film) 56 and an insulating film 58.

トレンチ５５の相互間には、Ｐ型半導体層５４の表層部にＮ＋型半導体層５９及びＰ＋型半導体層６０を形成しており、Ｎ＋型半導体層５９はトレンチ５５の両側に沿って形成し、Ｎ＋型半導体層５９の間にＰ＋型半導体層６０が位置している。ソースとなるＮ＋型半導体層５９は酸化膜５６および絶縁膜５８に隣接し、Ｐ＋型半導体層６０はボディコンタクト電極をなして接触抵抗を下げる。Ｐ＋型半導体層６０は実質的にトレンチ５５の全長に沿って延在しており、トレンチ５５の全長と実質的に同等以上の長さを有している。 Between the trenches 55, an N + type semiconductor layer 59 and a P + type semiconductor layer 60 are formed in the surface layer portion of the P type semiconductor layer 54, and the N + type semiconductor layer 59 extends along both sides of the trench 55. A P + type semiconductor layer 60 is formed between the N + type semiconductor layers 59 formed. The N + type semiconductor layer 59 serving as a source is adjacent to the oxide film 56 and the insulating film 58, and the P + type semiconductor layer 60 forms a body contact electrode to lower the contact resistance. The P + type semiconductor layer 60 extends substantially along the entire length of the trench 55, and has a length substantially equal to or greater than the entire length of the trench 55.

トレンチ５５の終端部はゲート電極５７の引き出し部をなし、各ゲート電極５７の端部を相互に接続する埋め込みゲート電極（ポリシリコン）６１がトレンチ５５の終端部上から半導体素子の端部縁までを覆って延在している。   The end portion of the trench 55 forms a lead portion of the gate electrode 57, and a buried gate electrode (polysilicon) 61 that connects the end portions of the gate electrodes 57 to each other from the end portion of the trench 55 to the end edge of the semiconductor element. It extends over.

埋め込みゲート電極（ポリシリコン）６１は、Ｐ＋型半導体層６０の上側に存在せず、トレンチ５５の相互間に少なくともトレンチ５５の終端部にまで後退した切欠き部６１ａを有し、切欠き部６１ａがＰ＋型半導体層６０の終端部に沿った形状をなす。 The buried gate electrode (polysilicon) 61 does not exist on the upper side of the P + -type semiconductor layer 60, and has a notch 61 a that retreats at least to the end of the trench 55 between the trenches 55. 61 a forms a shape along the terminal portion of the P + -type semiconductor layer 60.

半導体基板１００の一方の主面側にはＮ＋型半導体層５９及びＰ＋型半導体層６０に接合する第２の電極をなすソース電極６２が形成してあり、他方の主面側には半導体基板１００を介してソース電極６２に対向する第３の電極をなすドレイン電極（図示省略）がＰ＋＋型基板５０の裏面に形成してある。Ｐ＋型半導体層５０はソース電極６２と同電位になるように接続してあり、埋め込みゲート電極６１は絶縁膜６３によってソース電極６２と絶縁しており、図１においてソース電極６２および絶縁膜６３は部分的に表現した記載となっている。また、半導体基板の外側部には複数のガードリング層６４を形成している。 A source electrode 62 forming a second electrode joined to the N + type semiconductor layer 59 and the P + type semiconductor layer 60 is formed on one main surface side of the semiconductor substrate 100, and a semiconductor is formed on the other main surface side. A drain electrode (not shown) forming a third electrode facing the source electrode 62 through the substrate 100 is formed on the back surface of the P ++ type substrate 50. The P + type semiconductor layer 50 is connected so as to have the same potential as the source electrode 62, and the embedded gate electrode 61 is insulated from the source electrode 62 by the insulating film 63. In FIG. Is a partially expressed description. A plurality of guard ring layers 64 are formed on the outer side of the semiconductor substrate.

このトレンチゲート型半導体装置では、ドレイン電極（図示省略）に正電位の電圧を印加し、ソース電極６２を接地する。この条件下で、埋め込みゲート電極６１を通して各ゲート電極５７に閾値以上の正電位の電圧を印加すると、各トレンチ５５のゲート電極５７に酸化膜５６を介して隣接するＰ型半導体層５４に、ソースのＮ＋型半導体層５９からドレインのＮ型半導体層５３にまでチャネルが形成され、ドレイン電極からソース電極６２に向かって電流が流れて動作状態となる。 In this trench gate type semiconductor device, a positive potential voltage is applied to the drain electrode (not shown), and the source electrode 62 is grounded. Under this condition, when a voltage having a positive potential equal to or higher than the threshold value is applied to each gate electrode 57 through the buried gate electrode 61, the source is applied to the P-type semiconductor layer 54 adjacent to the gate electrode 57 of each trench 55 through the oxide film 56. A channel is formed from the N + type semiconductor layer 59 to the N type semiconductor layer 53 of the drain, and a current flows from the drain electrode to the source electrode 62 to be in an operating state.

この際に、Ｐ＋型半導体層６０がボディコンタクト電極をなしてソース電極６２と同電位をなし、このＰ＋型半導体層６０が実質的にトレンチ５５の全長に沿って延在することで、トレンチ５５の終端部においてもゲート電極５７に対向してボディコンタクト電極が存在し、トレンチ５５の終端部における半導体基板１００の表面上の電位をソース電位に固定することができるので、トレンチ５５の底部で起きる電界集中は、中間部および終端部において等しい電界強度となる。よって、トレンチ５５の終端部での電界集中に起因するデバイス耐圧の低下を防止することができ、トレンチ５５の底部における電界強度をトレンチ５５の全長にわたって均一化してデバイス耐圧を向上させることができる。 At this time, the P + type semiconductor layer 60 forms a body contact electrode and has the same potential as the source electrode 62, and the P + type semiconductor layer 60 extends substantially along the entire length of the trench 55. The body contact electrode is also present at the terminal portion of the trench 55 so as to face the gate electrode 57, and the potential on the surface of the semiconductor substrate 100 at the terminal portion of the trench 55 can be fixed to the source potential. The electric field concentration that occurs in FIG. Therefore, it is possible to prevent the device breakdown voltage from being lowered due to the electric field concentration at the terminal end of the trench 55, and to improve the device breakdown voltage by making the electric field strength at the bottom of the trench 55 uniform over the entire length of the trench 55.

本実施の形態では、トレンチ５５の終端部においてゲート電極５７を円形状に形成しているが、図２（ｃ）に示すように、トレンチ５５の終端部においてゲート電極５７を矩形に形成することも可能である。   In the present embodiment, the gate electrode 57 is formed in a circular shape at the end portion of the trench 55, but as shown in FIG. 2C, the gate electrode 57 is formed in a rectangular shape at the end portion of the trench 55. Is also possible.

また、本実施の形態では、埋め込みゲート電極（ポリシリコン）６１の切欠き部６１ａがＰ＋型半導体層６０の終端部に沿った形状をなし、Ｐ＋型半導体層６０の縁部と埋め込みゲート電極（ポリシリコン）６１の切欠き部６１ａの縁部との間にＰ型半導体層５４が介在しているが、図３に示すように、埋め込みゲート電極（ポリシリコン）６１の切欠き部６１ａの全域に、切欠き部６１ａの縁部に接してＰ＋型半導体層６０の終端部を形状することも可能である。 Further, in the present embodiment, embedding notch 61a of the gate electrode (polysilicon) 61 is a shape along the end portion of the P + -type semiconductor layer 60, the gate embedding the edge of the P + -type semiconductor layer 60 Although the P-type semiconductor layer 54 is interposed between the edge of the notch 61a of the electrode (polysilicon) 61, as shown in FIG. 3, the notch 61a of the buried gate electrode (polysilicon) 61 is provided. It is also possible to form the terminal portion of the P + type semiconductor layer 60 in contact with the edge of the notch 61a over the entire area.

以下にトレンチゲート型半導体装置の製造方法を説明する。図４〜図６は、各製造工程における断面を示し、図４（ａ）のＡ−Ａ’線断面に対応している。
図４（ｂ）に示すように、基層をなすＰ＋＋型基板５０の表面上にＰ＋＋型基板５０と異なる導電型で高濃度のＮ＋型半導体層５１をエピタキシャル成長させ、Ｎ＋型半導体層５１の表面上に同導電型で低濃度のＮ−型半導体層５２をエピタキシャル成長させる。 A method for manufacturing the trench gate type semiconductor device will be described below. 4 to 6 show cross sections in each manufacturing process, and correspond to the cross section along the line AA ′ in FIG.
FIG 4 (b) as shown in, the high concentration of the N + -type semiconductor layer 51 in a conductivity type different from that of the P ++ type substrate 50 on the surface of the P ++ type substrate 50 forming the base layer is epitaxially grown, N + -type semiconductor layer An N − type semiconductor layer 52 of the same conductivity type and a low concentration is epitaxially grown on the surface of 51.

図４（ｃ）に示すように、Ｎ−型半導体層５２にドーパントを拡散させて、Ｎ−型半導体層５２の上側域に異なる導電型のＰ型半導体層５４を形成し、Ｐ型半導体層５４の下側域にＮ型半導体層５３を形成する。 As shown in FIG. 4 (c), N - -type semiconductor layer 52 by diffusing a dopant, N - -type semiconductor layer 52 of P-type semiconductor layer 54 of different conductivity type in the upper region formed of, P-type semiconductor layer An N-type semiconductor layer 53 is formed in a lower region of 54.

図４（ｄ）に示すように、Ｐ型半導体層５４を貫通し、Ｎ型半導体層５３に達する複数のトレンチ５５を形成する。
図５（ａ）に示すように、トレンチ５５の内壁面およびＰ型半導体層５４の表面にＳｉＯ２の酸化膜５６を形成し、酸化膜５６に囲まれたトレンチ５５の内部および酸化膜５６を介したＰ型半導体層５４の上方にポリシリコンを積層する。 As shown in FIG. 4D, a plurality of trenches 55 that penetrate the P-type semiconductor layer 54 and reach the N-type semiconductor layer 53 are formed.
As shown in FIG. 5A, a SiO 2 oxide film 56 is formed on the inner wall surface of the trench 55 and the surface of the P-type semiconductor layer 54, and the inside of the trench 55 surrounded by the oxide film 56 and the oxide film 56 are formed. Polysilicon is laminated above the interposed P-type semiconductor layer 54.

図５（ｂ）に示すように、ポリシリコン層および酸化膜５６を選択的にエッチングしてトレンチ５５に残るポリシリコン層でゲート電極５７を形成し、トレンチ５５の終端部上から半導体素子の端部縁までを覆って残るポリシリコン層で埋め込みゲート電極６１を形成する。この埋め込みゲート電極６１は、後述するＰ＋型半導体層６０の形成予定部の上側に存在せず、トレンチ５５の相互間に少なくともトレンチ５５の終端部にまで後退した切欠き部６１ａを有し、切欠き部６１ａがＰ＋型半導体層６０の形成予定部の終端部に沿った形状をなす（図１参照）。 As shown in FIG. 5B, the polysilicon layer and the oxide film 56 are selectively etched to form the gate electrode 57 with the polysilicon layer remaining in the trench 55, and the end of the semiconductor element is formed from the terminal portion of the trench 55. A buried gate electrode 61 is formed of a polysilicon layer that covers up to the edge. The buried gate electrode 61 does not exist above a portion where a P + -type semiconductor layer 60 to be described later is to be formed, and has a notch 61 a that retreats at least to the end of the trench 55 between the trenches 55. The notch 61a has a shape along the end of the portion where the P + -type semiconductor layer 60 is to be formed (see FIG. 1).

次に、Ｐ型半導体層５４にドーパントを拡散させて、半導体基板１００の中央部側にトレンチ５５に隣接してソース（エミッター）のＮ＋型半導体層５９を形成する（図１参照）。 Next, a dopant is diffused in the P-type semiconductor layer 54 to form a source (emitter) N + -type semiconductor layer 59 adjacent to the trench 55 on the central side of the semiconductor substrate 100 (see FIG. 1).

図５（ｃ）に示すように、マスク６５を介してドーパントを拡散させて、Ｐ型半導体層５４にＰ＋型半導体層６０を実質的にトレンチ５５の全長にわたって形成する。半導体基板１００の中央部側では、Ｎ＋型半導体層５９を貫通してＰ型半導体層５４に達するＰ＋型半導体層６０を形成し、半導体基板１００の外側部にガードリング６４を形成する。 As shown in FIG. 5C, a dopant is diffused through a mask 65 to form a P + type semiconductor layer 60 in the P type semiconductor layer 54 substantially over the entire length of the trench 55. On the central side of the semiconductor substrate 100, a P + type semiconductor layer 60 that penetrates the N + type semiconductor layer 59 and reaches the P type semiconductor layer 54 is formed, and a guard ring 64 is formed on the outer side of the semiconductor substrate 100.

この際に、本実施の形態では、図２（ｃ）に示すように、埋め込みゲート電極（ポリシリコン）６１の切欠き部６１ａの縁部とＰ＋型半導体層６０の縁部との間にＰ型半導体層５４が介在しているが、図３に示すように、埋め込みゲート電極（ポリシリコン）６１の切欠き部６１ａの全域に、切欠き部６１ａの縁部に接してＰ＋型半導体層６０の終端部を形状することも可能である。 At this time, in this embodiment, as shown in FIG. 2C, the gap between the notched portion 61 a of the buried gate electrode (polysilicon) 61 and the edge of the P + -type semiconductor layer 60 is provided. Although the P-type semiconductor layer 54 is interposed, as shown in FIG. 3, the P + -type semiconductor is in contact with the edge of the notch 61a over the entire area of the notch 61a of the buried gate electrode (polysilicon) 61. It is also possible to shape the end of layer 60.

図６（ａ）に示すように、半導体基板の一方の主面を覆ってＳｉＯ２の層間絶縁膜を積層し、選択的なエッチングによりトレンチ５５の内部のゲート電極５７の上に絶縁膜５８を形成し（図１参照）、埋め込みゲート電極６１の上に絶縁膜６３を形成する。 As shown in FIG. 6A, an SiO 2 interlayer insulating film is laminated so as to cover one main surface of the semiconductor substrate, and an insulating film 58 is formed on the gate electrode 57 inside the trench 55 by selective etching. Then, an insulating film 63 is formed on the buried gate electrode 61 (see FIG. 1).

図６（ｂ）に示すように、半導体基板の一方の主面を覆ってアルミからなるソース電極６２を形成し、ソース電極６２をＮ＋型半導体層５９とＰ＋型半導体層６０に接合し、ソース電極６２とゲート電極５７を絶縁膜５８で絶縁し、ソース電極６２と埋め込みゲート電極６１を絶縁膜６３で絶縁する（図１参照）。 As shown in FIG. 6B, a source electrode 62 made of aluminum is formed so as to cover one main surface of the semiconductor substrate, and the source electrode 62 is joined to the N + type semiconductor layer 59 and the P + type semiconductor layer 60. The source electrode 62 and the gate electrode 57 are insulated by the insulating film 58, and the source electrode 62 and the buried gate electrode 61 are insulated by the insulating film 63 (see FIG. 1).

本発明はトレンチの底部における電界強度をトレンチの全長にわたって均一化してデバイス耐圧を向上させることができるので、トレンチ内に絶縁膜を介して埋め込まれた制御用のゲート電極を有するＭＯＳＦＥＴ、ＩＧＢＴ、絶縁ゲートサイリスタ等のトレンチゲート構造を有するＭＯＳ型トランジスタ等に有用である。   Since the present invention can improve the device breakdown voltage by making the electric field strength at the bottom of the trench uniform over the entire length of the trench, MOSFET, IGBT, insulation having a control gate electrode embedded in the trench through an insulating film This is useful for a MOS transistor having a trench gate structure such as a gate thyristor.

本発明の実施の形態におけるトレンチゲート型半導体装置を示す斜視図The perspective view which shows the trench gate type semiconductor device in embodiment of this invention （ａ）は同トレンチゲート型半導体装置を示す平断面図、（ｂ）は（ａ）のＡ−Ａ’線断面図、（ｃ）は他の構成のトレンチゲート型半導体装置を示す平断面図(A) is a plan sectional view showing the trench gate type semiconductor device, (b) is a sectional view taken along line A-A 'of (a), and (c) is a plan sectional view showing a trench gate type semiconductor device of another configuration. 本発明の他の構成のトレンチゲート型半導体装置を示す平断面図Plan sectional view showing a trench gate type semiconductor device of another configuration of the present invention 本発明に係るトレンチゲート型半導体装置の製造過程を示すものであり、（ａ）は同トレンチゲート型半導体装置を示す平断面図、（ｂ）〜（ｄ）は各製造過程における（ａ）のＡ−Ａ’線断面図1 shows a manufacturing process of a trench gate type semiconductor device according to the present invention, wherein (a) is a plan sectional view showing the trench gate type semiconductor device, and (b) to (d) are (a) in each manufacturing process. AA 'line sectional view 本発明に係るトレンチゲート型半導体装置の製造過程を示すものであり、（ａ）〜（ｃ）は各製造過程における図４（ａ）のＡ−Ａ’線断面図FIGS. 4A and 4B show a manufacturing process of a trench gate type semiconductor device according to the present invention, and FIGS. 4A to 4C are cross-sectional views taken along line A-A 'of FIG. 本発明に係るトレンチゲート型半導体装置の製造過程を示すものであり、（ａ）〜（ｂ）は各製造過程における図４（ａ）のＡ−Ａ’線断面図FIGS. 4A and 4B show a manufacturing process of a trench gate type semiconductor device according to the present invention, and FIGS. 4A and 4B are cross-sectional views taken along line A-A 'of FIG. 従来のトレンチゲート型半導体装置を示す平断面図Plan sectional view showing a conventional trench gate type semiconductor device 従来のトレンチゲート型半導体装置を示す斜視図A perspective view showing a conventional trench gate type semiconductor device （ａ）は同トレンチゲート型半導体装置を示す平断面図、（ｂ）は（ａ）のＡ−Ａ’線断面図(A) is a plane sectional view showing the trench gate type semiconductor device, and (b) is a sectional view taken along line A-A ′ of (a). 本発明に係るトレンチゲート型半導体装置の製造過程を示すものであり、（ａ）は同トレンチゲート型半導体装置を示す平断面図、（ｂ）〜（ｄ）は各製造過程における（ａ）のＡ−Ａ’線断面図1 shows a manufacturing process of a trench gate type semiconductor device according to the present invention, wherein (a) is a plan sectional view showing the trench gate type semiconductor device, and (b) to (d) are (a) in each manufacturing process. AA 'line sectional view 本発明に係るトレンチゲート型半導体装置の製造過程を示すものであり、（ａ）〜（ｃ）は各製造過程における図９（ａ）のＡ−Ａ’線断面図FIGS. 9A to 9C show a manufacturing process of a trench gate type semiconductor device according to the present invention, and FIGS. 9A to 9C are cross-sectional views taken along line A-A 'in FIG. 本発明に係るトレンチゲート型半導体装置の製造過程を示すものであり、（ａ）〜（ｃ）は各製造過程における図９（ａ）のＡ−Ａ’線断面図FIGS. 9A to 9C show a manufacturing process of a trench gate type semiconductor device according to the present invention, and FIGS. 9A to 9C are cross-sectional views taken along line A-A 'in FIG. 本発明に係るトレンチゲート型半導体装置の製造過程を示すものであり、（ａ）は同トレンチゲート型半導体装置を示す平断面図、（ｂ）〜（ｄ）は各製造過程における（ａ）のＡ−Ａ’線断面図1 shows a manufacturing process of a trench gate type semiconductor device according to the present invention, wherein (a) is a plan sectional view showing the trench gate type semiconductor device, and (b) to (d) are (a) in each manufacturing process. AA 'line sectional view 本発明に係るトレンチゲート型半導体装置の製造過程を示すものであり、（ａ）〜（ｃ）は各製造過程における図１３（ａ）のＡ−Ａ’線断面図The manufacturing process of the trench gate type semiconductor device which concerns on this invention is shown, (a)-(c) is the A-A 'line sectional drawing of Fig.13 (a) in each manufacturing process.

符号の説明Explanation of symbols

２０、５０ Ｐ＋＋型基板
２１、５１ Ｎ＋型半導体層
２２、５２ Ｎ−型半導体層
２３、５３ Ｎ型半導体層
２４、５４ Ｐ型半導体層
２５、５５ トレンチ
２６、５６ 酸化膜（ゲート酸化膜）
２７、５７ ゲート電極
２８、５８ 絶縁膜
２９、５９ Ｎ＋型半導体層
３０、６０ Ｐ＋型半導体層
３１、６１ 埋め込みゲート電極
３２、６２ ソース電極
３３、６３ 絶縁膜
３４、６４ ガードリング層
３５、６５ マスク
６１ａ 切欠き部
１００ 半導体基板 20, 50 P ++ type substrate 21, 51 N + type semiconductor layer 22, 52 N − type semiconductor layer 23, 53 N type semiconductor layer 24, 54 P type semiconductor layer 25, 55 Trench 26, 56 Oxide film (gate oxide film) )
27, 57 Gate electrode 28, 58 Insulating film 29, 59 N + type semiconductor layer 30, 60 P + type semiconductor layer 31, 61 Embedded gate electrode 32, 62 Source electrode 33, 63 Insulating film 34, 64 Guard ring layer 35, 65 Mask 61a Notch 100 Semiconductor substrate

Claims (2)

半導体基板が基層上に複数の半導体領域を層状に重ねて形成してなり、前記半導体基板の一方の主面側に位置する第１の半導体領域を貫通して下層の第２の半導体領域に達する複数のトレンチを有し、第１の半導体領域中に前記トレンチの両側に沿って第３の半導体領域を有するとともに、前記トレンチの相互間において第３の半導体領域間に第４の半導体領域を有し、第１の半導体領域と第４の半導体領域が同じ導電型をなし、第２の半導体領域と第３の半導体領域が同じ導電型をなし、前記トレンチに電気的に周囲から絶縁した第１の電極を有し、第３の半導体領域および第４の半導体領域に接合する第２の電極を有し、前記半導体基板を介して第２の電極に対抗する第３の電極を有し、第４の半導体領域が実質的に前記トレンチの全長に沿って延在することを特徴とするトレンチゲート型半導体装置。   A semiconductor substrate is formed by laminating a plurality of semiconductor regions on a base layer, and penetrates through a first semiconductor region located on one main surface side of the semiconductor substrate to reach a lower second semiconductor region. A plurality of trenches; a first semiconductor region having third semiconductor regions along both sides of the trench; and a fourth semiconductor region between the third semiconductor regions between the trenches. The first semiconductor region and the fourth semiconductor region have the same conductivity type, the second semiconductor region and the third semiconductor region have the same conductivity type, and the trench is electrically insulated from the surroundings. A second electrode joined to the third semiconductor region and the fourth semiconductor region, a third electrode opposed to the second electrode through the semiconductor substrate, 4 semiconductor regions are substantially the entire length of the trench Trench gate type semiconductor device which is characterized in that extending along. 各トレンチの第１の電極に接合する埋め込み電極が前記トレンチの終端部を覆って前記半導体基板の端部縁にまで延在し、かつ第４の半導体領域の上側に存在せず、前記埋め込み電極は前記トレンチの相互間に少なくとも前記トレンチの終端部にまで後退した切欠き部を有し、かつ前記切欠き部において第４の半導体領域の終端部に沿うことを特徴とする請求項１に記載のトレンチゲート型半導体装置。   A buried electrode joined to the first electrode of each trench extends to the edge of the semiconductor substrate and covers the terminal end of the trench, and does not exist above the fourth semiconductor region. 2. The semiconductor device according to claim 1, further comprising: a notch that is retreated to at least the end of the trench between the trenches, and that extends along the end of the fourth semiconductor region in the notch. Trench gate type semiconductor device.
JP2007129934A 2007-05-16 2007-05-16 Trench gate semiconductor device Withdrawn JP2008288287A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8853792B2 (en) 2009-09-28 2014-10-07 Freescale Semiconductor, Inc. Transistors and semiconductor devices with oxygen-diffusion barrier layers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8853792B2 (en) 2009-09-28 2014-10-07 Freescale Semiconductor, Inc. Transistors and semiconductor devices with oxygen-diffusion barrier layers

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