JP2008277691A - Mounting structure of electronic part to double-sided mounting circuit substrate, semiconductor device, and method of manufacturing double-sided mounting semiconductor device - Google Patents

Mounting structure of electronic part to double-sided mounting circuit substrate, semiconductor device, and method of manufacturing double-sided mounting semiconductor device Download PDF

Info

Publication number
JP2008277691A
JP2008277691A JP2007122342A JP2007122342A JP2008277691A JP 2008277691 A JP2008277691 A JP 2008277691A JP 2007122342 A JP2007122342 A JP 2007122342A JP 2007122342 A JP2007122342 A JP 2007122342A JP 2008277691 A JP2008277691 A JP 2008277691A
Authority
JP
Japan
Prior art keywords
circuit board
double
electronic component
mounting
package substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007122342A
Other languages
Japanese (ja)
Other versions
JP4952365B2 (en
Inventor
Daisuke Mizutani
大輔 水谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2007122342A priority Critical patent/JP4952365B2/en
Publication of JP2008277691A publication Critical patent/JP2008277691A/en
Application granted granted Critical
Publication of JP4952365B2 publication Critical patent/JP4952365B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mounting structure of electronic parts to a double-sided mounting circuit substrate wherein the high-density mounting of the electronic part is performed while improving a mounting intensity of the electronic part mounted to the double-sided mounting circuit substrate and improving mounting reliability, a semiconductor device equipped with the mounting structure, and a method of manufacturing the double-sided mounting semiconductor device. <P>SOLUTION: The mounting structure of the electronic parts to the double-sided mounting circuit substrate is characterized in that: a primary electronic part 2 is mounted on the front surface of a circuit substrate 1; a secondary electronic part 3 is mounted on the rear face of the circuit substrate 1; and an electrode 9 of the primary electronic part 2 and an electrode 9 of the secondary electronic part 3 of at least one set which face each other at both sides of the circuit substrate 1 are connected by a conductive member 25 which is formed in one body in a via hole 5 formed at the circuit substrate 1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、両面実装回路基板に対する電子部品の実装構造、半導体装置、及び両面実装半導体装置の製造方法に関する。より具体的には、半導体素子又はパッケージ基板等の電子部品を回路基板の両面に実装する構造、当該実装構造を備えた半導体装置、及び両面実装半導体装置の製造方法に関する。   The present invention relates to a mounting structure of an electronic component on a double-sided mounted circuit board, a semiconductor device, and a method for manufacturing the double-sided mounted semiconductor device. More specifically, the present invention relates to a structure for mounting an electronic component such as a semiconductor element or a package substrate on both sides of a circuit board, a semiconductor device provided with the mounting structure, and a method for manufacturing a double-sided mounting semiconductor device.

近年の電子機器の小型化・高密度化・高機能化に伴い、電子部品の小型化・薄型化が要求されている。そこで、小型化により実装面積を低減させた高密度実装に優れたパッケージとして、ボール・グリッド・アレイ（ＢＧＡ： Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）等の表面実装型パッケージが提案されている。   With recent miniaturization, high density, and high functionality of electronic devices, there is a demand for miniaturization and thinning of electronic components. Therefore, surface mount packages such as a ball grid array (BGA) have been proposed as packages excellent in high-density mounting in which the mounting area is reduced by downsizing.

かかるＢＧＡ表面実装型パッケージは、配線基板の一方の主面上に、半導体集積回路素子（以下半導体素子と称する）が搭載・接続され、当該配線基板の他方の主面上においては、銅（Ｃｕ）等からなる導電層に、半田を主体とする球状電極端子（バンプ）がグリッド状に複数配設された構造を有する。   In such a BGA surface-mount package, a semiconductor integrated circuit element (hereinafter referred to as a semiconductor element) is mounted and connected on one main surface of a wiring board, and copper (Cu ) Etc., a plurality of spherical electrode terminals (bumps) mainly composed of solder are arranged in a grid.

このような構造を有するＢＧＡ表面実装型パッケージの配線基板を、マザーボードとも称される回路基板の両主面に実装することにより、配線長の短縮化と回路基板の面積の縮小化とを図り、電子部品を高密度に実装する実装構造が提案されている。   By mounting the wiring board of the BGA surface mounting type package having such a structure on both main surfaces of the circuit board, also referred to as a mother board, the wiring length is shortened and the area of the circuit board is reduced. A mounting structure for mounting electronic components at high density has been proposed.

なお、セラミック基板に、制御用ＩＣ及びパワートランジスタを実装し、制御用ＩＣに形成された貫通突起電極を介して、セラミック基板に、制御用ＩＣ及びパワートランジスタを電気的に接続する態様も提案されている（特許文献１参照）。   A mode is also proposed in which a control IC and a power transistor are mounted on a ceramic substrate, and the control IC and the power transistor are electrically connected to the ceramic substrate via a through-projection electrode formed on the control IC. (See Patent Document 1).

更に、基板本体に接合されたインターポーザを貫通してその両面から突出した半田材料の接続部材の一端が前記基板本体に接続し、他端が半導体チップとの接続部を形成し、当該接続部と前記半導体チップの半田バンプとをリフローにより接続してなる態様も提案されている（特許文献２参照）。   Furthermore, one end of a connecting member of solder material that protrudes from both sides of the interposer bonded to the substrate body is connected to the substrate body, and the other end forms a connection portion with the semiconductor chip. An aspect in which the solder bumps of the semiconductor chip are connected by reflow has also been proposed (see Patent Document 2).

また、半導体チップの突起電極が、フレキシブル配線基板のフィルム基板の上面に設けられた配線を介して、前記フィルム基板に形成された貫通孔内に埋め込まれた柱状電極に接続された態様も提案されている（特許文献３参照）。
特許第２５６９７８９号公報 特開２００６−３５１９３５号公報 特開２００２−３０５３６１号公報 Further, there is also proposed an aspect in which the protruding electrode of the semiconductor chip is connected to the columnar electrode embedded in the through hole formed in the film substrate via the wiring provided on the upper surface of the film substrate of the flexible wiring substrate. (See Patent Document 3).
Japanese Patent No. 2569789 JP 2006-351935 A JP 2002-305361 A

ところで、小型化・高密度化・高機能化が求められる電子機器にあっては、電子部品のみならず当該電子部品が実装される回路基板の小型化・薄型化が要求されている。   Incidentally, in an electronic device that is required to be downsized, highly densified, and highly functional, not only electronic components but also circuit boards on which the electronic components are mounted are required to be downsized and thinned.

しかしながら、回路基板が小型化・薄型化すると、それに伴って回路基板としての剛性が低下するおそれがある。   However, when the circuit board is reduced in size and thickness, the rigidity as the circuit board may be reduced accordingly.

また、前記電子機器内における実装レイアウトの自由度を拡大するために、電子部品が実装される回路基板としてフレキシブルな回路基板が用いられ、かかる回路基板を折り曲げて使用することも少なくない。   In order to increase the degree of freedom of the mounting layout in the electronic device, a flexible circuit board is used as a circuit board on which electronic components are mounted, and the circuit board is often used by being bent.

一方、回路基板に実装される電子部品は、シリコン（Ｓｉ）等、機械的なフレキシビリティを有しない材料を基材として用いることが多く、電子部品そのものは本質的に機械的なフレキシビリティを有していない場合がある。   On the other hand, electronic components mounted on a circuit board often use a material that does not have mechanical flexibility such as silicon (Si) as a base material, and the electronic components themselves have inherent mechanical flexibility. May not have.

そのため、フレキシブルな回路基板とかかる電子部品との接合箇所に於いて機械的な応力が発生し易く、電子機器の使用環境における振動又は衝撃等に対する実装信頼性の低下を招くおそれがある。   For this reason, mechanical stress is likely to occur at the joint between the flexible circuit board and the electronic component, and there is a risk that the mounting reliability against vibration or impact in the environment where the electronic device is used will be reduced.

なお、特許文献１に記載の態様では、半田の表面上にニッケルめっき層が形成され、当該ニッケルめっき層上に半田めっき層が形成されて、貫通突起電極が形成される。従って、貫通突起電極は、均一の単一の材料から構成されておらず、半田とニッケルめっき層との間、及びニッケルめっき層と半田めっき層との間に、接合界面が形成されてしまう。よって、セラミック基板に、制御用ＩＣ及びパワートランジスタの接合強度を高くすることができず、外力に対して弱い構造となっている。   In the aspect described in Patent Document 1, a nickel plating layer is formed on the surface of the solder, the solder plating layer is formed on the nickel plating layer, and the penetrating protrusion electrode is formed. Therefore, the through-projection electrode is not composed of a uniform single material, and a bonding interface is formed between the solder and the nickel plating layer and between the nickel plating layer and the solder plating layer. Therefore, the bonding strength between the control IC and the power transistor cannot be increased on the ceramic substrate, and the structure is weak against external force.

また、特許文献２に記載の態様では、インターポーザ内に形成された貫通孔内に半田ペーストを充填され、当該半田ペーストと基板本体の半田材料を加熱によりリフローさせて一体化させている。従って、基板本体と半導体チップとの接続箇所は、均一の材料から構成されておらず、当該接続箇所内に接合界面が形成されてしまう。よって、両者の接合強度を高くすることができず、外力に対して弱い構造となっている。   Moreover, in the aspect described in Patent Document 2, a solder paste is filled in a through hole formed in the interposer, and the solder paste and the solder material of the substrate body are reflowed by heating to be integrated. Therefore, the connection location between the substrate body and the semiconductor chip is not made of a uniform material, and a bonding interface is formed in the connection location. Therefore, the joint strength between the two cannot be increased, and the structure is weak against external force.

更に、特許文献３に記載の態様では、半導体チップの突起電極とフィルム基板に形成された貫通孔内に埋め込まれた柱状電極との接続には、フィルム基板の上面に設けられた配線が介在しており、半導体チップとフィルム基板との接続箇所は略Ｌ字形状を有している。従って、半導体チップとフィルム基板との十分な接合強度を確保することができず、外力に対して弱い構造となっている。   Furthermore, in the aspect described in Patent Document 3, the wiring provided on the upper surface of the film substrate is interposed between the protruding electrode of the semiconductor chip and the columnar electrode embedded in the through hole formed in the film substrate. The connection portion between the semiconductor chip and the film substrate has a substantially L shape. Therefore, sufficient bonding strength between the semiconductor chip and the film substrate cannot be ensured, and the structure is weak against external force.

そこで、本発明は、上記の点に鑑みてなされたものであって、両面実装回路基板に対する電子部品の実装構造であって、両面実装回路基板に実装する電子部品の実装強度を向上して実装信頼性の向上を図りつつ、当該電子部品の高密度実装を実現する実装構造、当該実装構造を備えた半導体装置、及び両面実装半導体装置の製造方法を提供することを本発明の目的とする。   Therefore, the present invention has been made in view of the above points, and is a mounting structure of an electronic component on a double-sided mounting circuit board, which is mounted with improved mounting strength of the electronic component to be mounted on the double-sided mounting circuit board. It is an object of the present invention to provide a mounting structure that realizes high-density mounting of the electronic component while improving reliability, a semiconductor device including the mounting structure, and a method for manufacturing a double-sided mounting semiconductor device.

本発明の一観点によれば、回路基板の表面に第１の電子部品が実装され、前記回路基板の裏面に第２の電子部品が実装され、前記回路基板を挟んで互いに対向する少なくとも一組の前記第１の電子部品の電極部と前記第２の電子部品の電極部とが、前記回路基板に形成された貫通孔部内に一体形成された導体部材によって、接続されることを特徴とする両面実装回路基板に対する電子部品の実装構造が提供される。   According to one aspect of the present invention, a first electronic component is mounted on the front surface of the circuit board, a second electronic component is mounted on the back surface of the circuit board, and at least one pair facing each other with the circuit board interposed therebetween. The electrode portion of the first electronic component and the electrode portion of the second electronic component are connected by a conductor member integrally formed in a through-hole portion formed in the circuit board. An electronic component mounting structure for a double-sided mounting circuit board is provided.

前記導体部材は、前記回路基板の主面に対して略垂直の方向に略直線状に形成され、少なくとも一組の前記第１の電子部品の前記電極部と前記第２の電子部品の前記電極部とが、前記導体部材によって一体的に接続されてもよい。また、前記導体部材は、均一の材料から構成されていてもよい。   The conductor member is formed in a substantially straight line in a direction substantially perpendicular to the main surface of the circuit board, and at least one set of the electrode portion of the first electronic component and the electrode of the second electronic component. The part may be integrally connected by the conductor member. The conductor member may be made of a uniform material.

更に、前記貫通孔部は、前記第１の電子部品及び前記第２の電子部品の主面の外周近傍に形成された電極部と対向して、前記回路基板に貫通形成されてもよい。   Furthermore, the through-hole portion may be formed through the circuit board so as to face an electrode portion formed in the vicinity of the outer periphery of the main surface of the first electronic component and the second electronic component.

本発明の別の観点によれば、回路基板の表面に、第１の半導体素子を備えた第１のパッケージ基板が実装され、前記回路基板の裏面に、第２の半導体素子を備えた第２のパッケージ基板が実装され、前記回路基板を挟んで互いに対向する少なくとも一組の前記第１のパッケージ基板の電極部と前記第２のパッケージ基板の電極部とが、前記回路基板に形成された貫通孔部内に一体形成された導体部材によって、接続されることを特徴とする半導体装置が提供される。   According to another aspect of the present invention, a first package substrate provided with a first semiconductor element is mounted on a surface of a circuit board, and a second semiconductor element provided with a second semiconductor element on the back surface of the circuit board. The package substrate is mounted, and at least one pair of the electrode portion of the first package substrate and the electrode portion of the second package substrate facing each other across the circuit substrate are formed in the circuit board. A semiconductor device is provided which is connected by a conductor member integrally formed in the hole.

本発明の更に別の観点によれば、両面実装半導体装置の製造方法であって、熱処理を施して、回路基板の表面に、第１の半導体素子を備えた第１のパッケージ基板が実装する際、及び前記回路基板の裏面に、第２の半導体素子を備えた第２のパッケージ基板を実装する際に、前記回路基板に形成された貫通孔部内に、溶融した導体部材を流れ込ませて、前記回路基板を挟んで互いに対向する少なくとも一組の前記第１のパッケージ基板の電極部と前記第２のパッケージ基板の電極部とを前記導体部材を介して接続することを特徴とする両面半導体装置の製造方法が提供される。   According to still another aspect of the present invention, there is provided a method for manufacturing a double-sided mounted semiconductor device, wherein heat treatment is performed to mount a first package substrate having a first semiconductor element on a surface of a circuit board. When the second package substrate having the second semiconductor element is mounted on the back surface of the circuit board, the molten conductor member is caused to flow into the through hole formed in the circuit board, A double-sided semiconductor device characterized in that at least one pair of the electrode portions of the first package substrate and the electrode portions of the second package substrate facing each other across the circuit board are connected via the conductor member. A manufacturing method is provided.

本発明によれば、両面実装回路基板に対する電子部品の実装構造であって、両面実装回路基板に実装する電子部品の実装強度を向上して実装信頼性の向上を図りつつ、当該電子部品の高密度実装を実現する実装構造、当該実装構造を備えた半導体装置、及び両面実装半導体装置の製造方法を提供することができる。   According to the present invention, there is provided a structure for mounting an electronic component on a double-sided mounted circuit board, and the mounting strength of the electronic component to be mounted on the double-sided mounted circuit board is improved to improve the mounting reliability. A mounting structure that realizes density mounting, a semiconductor device including the mounting structure, and a method for manufacturing a double-sided mounting semiconductor device can be provided.

以下、図面を参照して本発明の実施の形態について説明する。説明の便宜上、本発明の実施の形態に係る両面実装回路基板に対する電子部品の実装構造（両面実装半導体装置）の例について説明し、次いで、当該両面実装半導体装置の製造方法の例について説明する。   Embodiments of the present invention will be described below with reference to the drawings. For convenience of explanation, an example of an electronic component mounting structure (double-sided mounting semiconductor device) on a double-sided mounting circuit board according to an embodiment of the present invention will be described, and then an example of a method for manufacturing the double-sided mounting semiconductor device will be described.

１．本発明の実施の形態に係る両面実装回路基板に対する電子部品の実装構造（両面実装半導体装置）
図１に、本発明の実施の形態に係る両面実装回路基板に対する電子部品の実装構造（両面実装半導体装置）の例を示す。 1. Electronic component mounting structure (double-sided mounting semiconductor device) on double-sided mounting circuit board according to an embodiment of the present invention
FIG. 1 shows an example of an electronic component mounting structure (double-sided mounting semiconductor device) on a double-sided mounting circuit board according to an embodiment of the present invention.

図１を参照するに、本発明の実施の形態に係る両面実装半導体装置１０は、回路基板１の表面に第１の電子部品として第１パッケージ基板２が実装され、回路基板１の裏面に第２の電子部品として第２パッケージ基板３が実装された構造を有する。即ち、第１パッケージ基板２と第２パッケージ基板３とは、回路基板１を挟んで互いに対向している。   Referring to FIG. 1, in a double-sided mounted semiconductor device 10 according to an embodiment of the present invention, a first package substrate 2 is mounted as a first electronic component on the surface of a circuit board 1, and The second package substrate 3 is mounted as the second electronic component. That is, the first package substrate 2 and the second package substrate 3 are opposed to each other with the circuit board 1 interposed therebetween.

回路基板１は、マザーボードとも称され、例えば０．５ｍｍの厚さを有する。回路基板１は、例えば、ガラスエポキシ樹脂等の絶縁性樹脂を基材とし、表面及び裏面に銅（Ｃｕ）等からなる導電層が選択的に配設され、当該導電層はソルダーレジスト層により選択的に被覆されている。当該ソルダーレジスト層により画定された導電層は、電極パッド４として機能する。   The circuit board 1 is also called a mother board, and has a thickness of 0.5 mm, for example. The circuit board 1 is made of, for example, an insulating resin such as glass epoxy resin as a base material, and a conductive layer made of copper (Cu) or the like is selectively disposed on the front and back surfaces, and the conductive layer is selected by a solder resist layer Is covered. The conductive layer defined by the solder resist layer functions as the electrode pad 4.

また、当該電極パッド４の形成位置よりも回路基板１の外周側に、回路基板１を貫通して貫通孔部（ビアホール）５が形成されている。図１に示す例では、回路基板１の２箇所に、貫通孔部５が形成されている。貫通孔部５は、例えば、０．２ｍｍの直径を有し、内壁部分に金属部として銅（Ｃｕ）メッキ６が施されている。   Further, a through-hole portion (via hole) 5 is formed through the circuit board 1 on the outer peripheral side of the circuit board 1 from the position where the electrode pad 4 is formed. In the example shown in FIG. 1, through-hole portions 5 are formed at two locations on the circuit board 1. The through-hole part 5 has a diameter of 0.2 mm, for example, and a copper (Cu) plating 6 is applied to the inner wall part as a metal part.

回路基板１の内部には、接地（グランド）層又は電源層として機能する導電層７が形成されており、当該導電層７は、貫通孔部５の内壁部分に形成された銅（Ｃｕ）メッキ部６に接続し、貫通孔部５は接地（グランド）電極又は電源電極として機能する。   A conductive layer 7 that functions as a ground (ground) layer or a power supply layer is formed inside the circuit board 1, and the conductive layer 7 is plated with copper (Cu) formed on the inner wall portion of the through-hole portion 5. The through-hole part 5 is connected to the part 6 and functions as a ground (ground) electrode or a power supply electrode.

一方、インターポーザ又は支持基板とも称される第１パッケージ基板２及び／又は第２パッケージ基板３の一方の主面上には、図示を省略する半導体素子がワイヤーボンディング法、フリップチップ実装法等により実装されている。なお、第１パッケージ基板２及び／又は第２パッケージ基板３上であって前記半導体素子の近傍に、コンデンサ（容量素子）、サーミスタ等の受動素子又は能動素子が実装されていてもよい。   On the other hand, a semiconductor element (not shown) is mounted on one main surface of the first package substrate 2 and / or the second package substrate 3, which is also called an interposer or a support substrate, by a wire bonding method, a flip chip mounting method, or the like. Has been. A passive element or active element such as a capacitor (capacitance element) or thermistor may be mounted on the first package substrate 2 and / or the second package substrate 3 and in the vicinity of the semiconductor element.

第１パッケージ基板２及び第２パッケージ基板３の主面のうち、回路基板１に対向している面、即ち、上述の半導体素子等が実装されている面と反対の面には、電極パッド８と貫通孔部用電極パッド９が電極部として形成されている。より具体的には、当該面のうち、回路基板１の電極パッド４に対向する箇所に電極パッド８が形成され、貫通孔部５に対向する箇所に貫通孔部用電極パッド９が形成されている。即ち、第１パッケージ基板２の電極パッド８と第２パッケージ基板３の電極パッド８とは、また、第１パッケージ基板２の貫通孔部用電極パッド９と第２パッケージ基板３の貫通孔部用電極パッド９とは、回路基板１を挟んで互いに対向している。   Of the main surfaces of the first package substrate 2 and the second package substrate 3, an electrode pad 8 is provided on the surface facing the circuit substrate 1, that is, the surface opposite to the surface on which the above-described semiconductor elements are mounted. A through-hole electrode pad 9 is formed as an electrode portion. More specifically, an electrode pad 8 is formed in a portion of the surface facing the electrode pad 4 of the circuit board 1, and a through hole electrode pad 9 is formed in a portion facing the through hole portion 5. Yes. That is, the electrode pad 8 of the first package substrate 2 and the electrode pad 8 of the second package substrate 3 are also used for the through-hole portion electrode pad 9 of the first package substrate 2 and the through-hole portion of the second package substrate 3. The electrode pads 9 face each other across the circuit board 1.

第１パッケージ基板２及び第２パッケージ基板３の電極パッド８上には、半田を主体とする球状電極端子（バンプ）２０が配設されている。当該球状電極端子（バンプ）２０を介して、第１パッケージ基板２及び第２パッケージ基板３の電極パッド８と回路基板１の電極パッド４とが接続されている。   On electrode pads 8 of the first package substrate 2 and the second package substrate 3, spherical electrode terminals (bumps) 20 mainly composed of solder are disposed. Via the spherical electrode terminals (bumps) 20, the electrode pads 8 of the first package substrate 2 and the second package substrate 3 and the electrode pads 4 of the circuit substrate 1 are connected.

また、第１パッケージ基板２の貫通孔部用電極パッド９と第２パッケージ基板３の貫通孔部用電極パッド９との間は、貫通孔部５内に充填され一体形成された半田を主体とする導体部材２５によって接合されてなるリベット構造が形成されている。より具体的には、導体部材２５が、回路基板１の主面に対して略垂直の方向に略直線状に形成され、第１パッケージ基板２の貫通孔部用電極パッド９と第２パッケージ基板３の貫通孔部用電極パッド９とを一体的に接続している。   The space between the through hole electrode pad 9 of the first package substrate 2 and the through hole electrode pad 9 of the second package substrate 3 is mainly composed of the solder filled in the through hole 5 and integrally formed. A rivet structure is formed which is joined by the conductor member 25. More specifically, the conductor member 25 is formed in a substantially linear shape in a direction substantially perpendicular to the main surface of the circuit board 1, and the through hole electrode pad 9 of the first package substrate 2 and the second package substrate. 3 through-hole electrode pads 9 are integrally connected.

本例のリベット構造により、回路基板１の表面及び裏面において、球状電極端子（バンプ）２０のみを介して第１パッケージ基板２及び第２パッケージ基板３が表面実装されている構造よりも、回路基板１と第１パッケージ基板２及び第２パッケージ基板３の接合強度を向上させることができる。よって、電子機器の使用環境における振動又は衝撃等に対する実装信頼性を向上することができる。   With the rivet structure of this example, the circuit board 1 has a circuit board 1 rather than a structure in which the first package board 2 and the second package board 3 are mounted on the front and back surfaces of the circuit board 1 via only spherical electrode terminals (bumps) 20. The bonding strength between the first package substrate 2 and the second package substrate 3 can be improved. Therefore, it is possible to improve the mounting reliability against vibration or impact in the environment where the electronic device is used.

上述のように、導体部材２５は、回路基板１の主面に対して略垂直の方向に略直線状に形成されている。従って、例えば、導体部材２５が略Ｌ字状に形成されている場合に比し、回路基板１と第１パッケージ基板２及び第２パッケージ基板３の接合強度を向上させることができ、外力に対して強い構造となっている。   As described above, the conductor member 25 is formed in a substantially linear shape in a direction substantially perpendicular to the main surface of the circuit board 1. Therefore, for example, the bonding strength between the circuit board 1, the first package board 2, and the second package board 3 can be improved as compared with the case where the conductor member 25 is formed in a substantially L shape. It has a strong structure.

また、導体部材２５は、どの箇所においても均一の材料から構成されている。よって、導体部材２５内において材料の相違等に因る界面は存在しないため、前記界面が形成されている場合に比し、回路基板１と第１パッケージ基板２及び第２パッケージ基板３の接合強度を向上させることができ、外力に対して強い構造となっている。   Moreover, the conductor member 25 is comprised from the uniform material in any location. Therefore, since there is no interface due to the difference in material or the like in the conductor member 25, the bonding strength between the circuit board 1, the first package substrate 2 and the second package substrate 3 compared to the case where the interface is formed. The structure is strong against external forces.

更に、本例では、回路基板１の電極パッド４の形成位置よりも回路基板１の外周側に形成され、導体部材２５が充填された貫通孔部５は、第１パッケージ基板２及び第２パッケージ基板３の外周近傍に形成された第１パッケージ基板２の貫通孔部用電極パッド９と第２パッケージ基板３の貫通孔部用電極パッド９に対向して形成されている。   Furthermore, in this example, the through hole portion 5 formed on the outer peripheral side of the circuit board 1 with respect to the position where the electrode pads 4 of the circuit board 1 are formed and filled with the conductor member 25 is formed in the first package substrate 2 and the second package. The through hole electrode pad 9 of the first package substrate 2 and the through hole electrode pad 9 of the second package substrate 3 formed in the vicinity of the outer periphery of the substrate 3 are formed to face each other.

よって、貫通孔部５が形成された領域の剛直性が向上するため、電子機器の使用環境における振動又は衝撃等に起因して、回路基板１が変形し、その結果、機械的な応力が発生しても、貫通孔部５に囲まれた部分に配置された電極パッド４や、貫通孔部用電極パッド９に囲まれた部分に配置された電極パッド８に作用する応力を軽減することができる。即ち、実装信頼性を向上することができる。   Therefore, since the rigidity of the region where the through-hole portion 5 is formed is improved, the circuit board 1 is deformed due to vibration or impact in the use environment of the electronic device, and as a result, mechanical stress is generated. Even so, the stress acting on the electrode pad 4 disposed in the portion surrounded by the through-hole portion 5 and the electrode pad 8 disposed in the portion surrounded by the through-hole portion electrode pad 9 can be reduced. it can. That is, mounting reliability can be improved.

なお、上述の貫通孔部５は、回路基板１において、第１パッケージ基板２及び第２パッケージ基板３の外周近傍に対向する箇所の少なくとも１箇所に貫通形成されていればよく、その形成箇所の数に特に制限はない。   In addition, the above-mentioned through-hole part 5 should just be penetrated and formed in at least one place of the circuit board 1 facing the outer periphery vicinity of the 1st package board | substrate 2 and the 2nd package board | substrate 3, There is no particular limitation on the number.

従って、例えば、回路基板１において、第１パッケージ基板２及び第２パッケージ基板３の外周近傍に対向する２箇所に、或いは、回路基板１において、第１パッケージ基板２及び第２パッケージ基板３の主面の四隅（４つのコーナ部）の近傍に対向する箇所に、貫通孔部５が形成されていてもよい。   Therefore, for example, in the circuit board 1, two locations facing the vicinity of the outer periphery of the first package board 2 and the second package board 3, or in the circuit board 1, the main package board 2 and the main package board 3. The through-hole part 5 may be formed in the location facing the vicinity of the four corners (four corner parts) of the surface.

また、本例では、回路基板１の内部に形成され、接地（グランド）層又は電源層として機能する導電層７が、貫通孔部５に接続し、貫通孔部５が接地（グランド）電極又は電源電極として機能している。そして、導体部材２５を介して当該貫通孔部５に接合された貫通孔部用電極パッド９も、接地（グランド）電極又は電源電極として機能する。   In this example, the conductive layer 7 formed inside the circuit board 1 and functioning as a ground (ground) layer or a power supply layer is connected to the through-hole portion 5, and the through-hole portion 5 is connected to a ground (ground) electrode or It functions as a power supply electrode. The through-hole electrode pad 9 joined to the through-hole 5 via the conductor member 25 also functions as a ground (ground) electrode or a power supply electrode.

よって、第１パッケージ基板２及び第２パッケージ基板３の電極パッド８及び貫通孔部用電極パッド９のレイアウトの自由度を損なうことなく、第１パッケージ基板２の貫通孔部用電極パッド９と第２パッケージ基板３の貫通孔部用電極パッド９との間に、貫通孔部５内に充填され一体形成された半田を主体とする導体部材２５によって接合されてなるリベット構造を形成することができる。   Therefore, the through hole electrode pads 9 of the first package substrate 2 and the first electrode pads 8 and the through hole electrode pads 9 of the first package substrate 2 and the second package substrate 3 are not impaired without sacrificing the layout flexibility. A rivet structure can be formed which is joined to the through hole portion electrode pad 9 of the two package substrate 3 by a conductor member 25 mainly composed of solder filled in the through hole portion 5 and integrally formed. .

貫通孔部５が接地（グランド）電極又は電源電極として機能し、更に、貫通孔部５の内壁部分に形成された銅（Ｃｕ）メッキ部６が回路基板１の内層として機能して、回路基板１内で大きな面積を占め接地（グランド）層又は電源層として機能する導電層７と接合している。よって、回路基板１と貫通孔部５内に充填された導体部材２５との機械的な接合強度を向上することができる。即ち、電子機器の使用環境における振動又は衝撃等に対する実装信頼性を向上することができる。   The through-hole portion 5 functions as a ground (ground) electrode or a power supply electrode, and the copper (Cu) plating portion 6 formed on the inner wall portion of the through-hole portion 5 functions as an inner layer of the circuit board 1. 1 is connected to a conductive layer 7 that occupies a large area in 1 and functions as a ground layer or a power supply layer. Therefore, the mechanical joint strength between the circuit board 1 and the conductor member 25 filled in the through hole portion 5 can be improved. That is, it is possible to improve the mounting reliability against vibration or impact in the environment where the electronic device is used.

このように、本発明の実施の形態に係る両面実装回路基板に対する電子部品の実装構造（両面実装半導体装置１０）によれば、回路基板１に対して電子部品である第１パッケージ基板２及び第２パッケージ基板３を高密度に実装、即ち、両面実装する態様において、第１パッケージ基板２及び第２パッケージ基板３の実装強度を向上させることができる。   Thus, according to the mounting structure of electronic components (double-sided mounting semiconductor device 10) on the double-sided mounting circuit board according to the embodiment of the present invention, the first package board 2 and the first package board 2 which are electronic parts with respect to the circuit board 1 In the aspect in which the two-package substrate 3 is mounted with high density, that is, double-sided mounting, the mounting strength of the first package substrate 2 and the second package substrate 3 can be improved.

なお、本例では上述のように、回路基板１に実装される第１の電子部品及び第２の電子部品として、第１パッケージ基板２及び第２パッケージ基板３が用いられているが、本発明はかかる例に限定されない。回路基板１に実装される第１の電子部品及び第２の電子部品として、例えば半導体素子を用いてもよい。   In this example, as described above, the first package substrate 2 and the second package substrate 3 are used as the first electronic component and the second electronic component mounted on the circuit substrate 1, but the present invention is not limited thereto. Is not limited to such an example. For example, semiconductor elements may be used as the first electronic component and the second electronic component mounted on the circuit board 1.

２．本発明の実施の形態に係る両面実装半導体装置の製造方法
次に、上述の構造を備えた両面実装半導体装置１０の製造方法の例について、図２及び図３を参照して説明する。ここで、図２及び図３は、本発明の実施の形態に係る両面実装半導体装置の製造方法の例を説明するための図（その１）及び（その２）である。 2. Next, an example of a method for manufacturing the double-sided mounted semiconductor device 10 having the above-described structure will be described with reference to FIGS. 2 and 3. 2 and 3 are views (No. 1) and (No. 2) for explaining an example of the method for manufacturing the double-sided mounted semiconductor device according to the embodiment of the present invention.

図２（ａ）に示すように、例えば、ガラスエポキシ樹脂等の絶縁性樹脂を基材とし、表面及び裏面に銅（Ｃｕ）等からなる導電層が選択的に配設され、当該導電層はソルダーレジスト層により選択的に被覆されてなる回路基板１を準備する。なお、前記ソルダーレジスト層により画定された導電層は、電極パッド４として機能する。   As shown in FIG. 2A, for example, an insulating resin such as a glass epoxy resin is used as a base material, and a conductive layer made of copper (Cu) or the like is selectively disposed on the front and back surfaces, and the conductive layer is A circuit board 1 that is selectively covered with a solder resist layer is prepared. The conductive layer defined by the solder resist layer functions as the electrode pad 4.

また、当該電極パッド４の形成位置よりも回路基板１の外周側に、回路基板１を貫通して貫通孔部５が形成されている。貫通孔部５は、回路基板１の製造過程において、例えば、フォトレジスト法及びエッチング法を用いて、或いは、レーザ光照射等を用いて、回路基板１に貫通形成されている。貫通孔部５の内壁部分には、銅（Ｃｕ）メッキ６が施されている。   Further, a through-hole portion 5 is formed through the circuit board 1 on the outer peripheral side of the circuit board 1 from the position where the electrode pad 4 is formed. The through-hole portion 5 is formed through the circuit board 1 in the manufacturing process of the circuit board 1 using, for example, a photoresist method and an etching method, or using laser beam irradiation or the like. Copper (Cu) plating 6 is applied to the inner wall portion of the through-hole portion 5.

回路基板１の内部には、接地（グランド）層又は電源層として機能する導電層７が形成されており、当該導電層７は、貫通孔部５の内壁部分に形成された銅（Ｃｕ）メッキ部６に接続し、貫通孔部５は接地（グランド）電極又は電源電極として機能する。   A conductive layer 7 that functions as a ground (ground) layer or a power supply layer is formed inside the circuit board 1, and the conductive layer 7 is plated with copper (Cu) formed on the inner wall portion of the through-hole portion 5. The through-hole part 5 is connected to the part 6 and functions as a ground (ground) electrode or a power supply electrode.

更に、本工程においては、回路基板１の上方に、第２パッケージ基板３を配置する。   Further, in this step, the second package substrate 3 is disposed above the circuit substrate 1.

第２パッケージ基板３の一方の主面上には、図示を省略する半導体素子がワイヤーボンディング法、フリップチップ実装法等により実装されている。   A semiconductor element (not shown) is mounted on one main surface of the second package substrate 3 by a wire bonding method, a flip chip mounting method, or the like.

第２パッケージ基板３の主面のうち、回路基板１に対向している面、即ち、上述の半導体素子等が実装されている面と反対の面には、電極パッド８と貫通孔部用電極パッド９が形成されており、当該電極パッド８と貫通孔部用電極パッド９上には、半田を主体とする球状電極端子（バンプ）２０が配設されている。   Of the main surface of the second package substrate 3, the electrode pad 8 and the through hole electrode are provided on the surface facing the circuit substrate 1, that is, on the surface opposite to the surface on which the above-described semiconductor elements are mounted. Pads 9 are formed, and spherical electrode terminals (bumps) 20 mainly composed of solder are disposed on the electrode pads 8 and the through-hole electrode pads 9.

電極パッド８上に形成された球状電極端子２０が回路基板１の電極パッド４に対向するように、更に、貫通孔部用電極パッド９上に形成された球状電極端子２０が回路基板１に貫通形成された貫通孔部５に対向するように、第２パッケージ基板３を回路基板１の上方に配置する。   Further, the spherical electrode terminal 20 formed on the through hole electrode pad 9 penetrates the circuit board 1 so that the spherical electrode terminal 20 formed on the electrode pad 8 faces the electrode pad 4 of the circuit board 1. The second package substrate 3 is disposed above the circuit substrate 1 so as to face the formed through-hole portion 5.

次に、図２（ｂ）に示すように、例えば約２００℃の温度の下、約２分間リフロー加熱処理を施し、第２パッケージ基板３を回路基板１上に実装する。   Next, as shown in FIG. 2 (b), for example, a reflow heat treatment is performed at a temperature of about 200 ° C. for about 2 minutes, and the second package substrate 3 is mounted on the circuit substrate 1.

これにより、第２パッケージ基板３の電極パッド８上に形成された球状電極端子（バンプ）２０は溶融し、第２パッケージ基板３の電極パッド８と回路基板１の電極パッド４とは、当該球状電極端子（バンプ）２０を介して接合する。   Thereby, the spherical electrode terminals (bumps) 20 formed on the electrode pads 8 of the second package substrate 3 are melted, and the electrode pads 8 of the second package substrate 3 and the electrode pads 4 of the circuit substrate 1 are in the spherical shape. Bonding is performed via electrode terminals (bumps) 20.

更に、第２パッケージ基板３の貫通孔部用電極パッド９上に形成された球状電極端子（バンプ）２０も溶融して、回路基板１に貫通形成され内壁部分に銅（Ｃｕ）メッキ６が施されている貫通孔部５内に流れ込む。   Further, the spherical electrode terminals (bumps) 20 formed on the through-hole electrode pads 9 of the second package substrate 3 are also melted to penetrate the circuit board 1 and the inner wall portion is subjected to copper (Cu) plating 6. It flows into the through-hole part 5 currently made.

このようにして第２パッケージ基板３が実装された回路基板１を反転し、更に、反転した状態の回路基板１の上方に、第１パッケージ基板２を配置する。この状態を図３（ｃ）に示す。   In this way, the circuit board 1 on which the second package board 3 is mounted is inverted, and the first package board 2 is disposed above the inverted circuit board 1. This state is shown in FIG.

第１パッケージ基板２の一方の主面上には、図示を省略する半導体素子がワイヤーボンディング法、フリップチップ実装法等により実装されている。   On one main surface of the first package substrate 2, a semiconductor element (not shown) is mounted by a wire bonding method, a flip chip mounting method, or the like.

第１パッケージ基板２の主面のうち、回路基板１に対向している面、即ち、上述の半導体素子等が実装されている面と反対の面には、電極パッド８と貫通孔部用電極パッド９が形成されており、当該電極パッド８と貫通孔部用電極パッド９上には、半田を主体とする球状電極端子（バンプ）２０が配設されている。   Of the main surface of the first package substrate 2, the electrode pad 8 and the through hole electrode are provided on the surface facing the circuit substrate 1, that is, on the surface opposite to the surface on which the semiconductor element or the like is mounted. Pads 9 are formed, and spherical electrode terminals (bumps) 20 mainly composed of solder are disposed on the electrode pads 8 and the through-hole electrode pads 9.

電極パッド８上に形成された球状電極端子２０が回路基板１の電極パッド４に対向するように、更に、貫通孔部用電極パッド９上に形成された球状電極端子２０が回路基板１に貫通形成された貫通孔部５に対向するように、第１パッケージ基板２を回路基板１の上方に配置する。   Further, the spherical electrode terminal 20 formed on the through hole electrode pad 9 penetrates the circuit board 1 so that the spherical electrode terminal 20 formed on the electrode pad 8 faces the electrode pad 4 of the circuit board 1. The first package substrate 2 is disposed above the circuit substrate 1 so as to face the formed through-hole portion 5.

次に、図３（ｄ）に示すように、例えば約２００℃の温度の下、約２分間リフロー加熱処理を施し、第１パッケージ基板２を回路基板１上に実装する。   Next, as shown in FIG. 3D, for example, a reflow heating process is performed for about 2 minutes at a temperature of about 200 ° C., and the first package substrate 2 is mounted on the circuit substrate 1.

これにより、第１パッケージ基板２の電極パッド８上に形成された球状電極端子（バンプ）２０は溶融し、第１パッケージ基板２の電極パッド８と回路基板１の電極パッド４とが、当該球状電極端子（バンプ）２０を介して接合する。   Thereby, the spherical electrode terminals (bumps) 20 formed on the electrode pads 8 of the first package substrate 2 are melted, and the electrode pads 8 of the first package substrate 2 and the electrode pads 4 of the circuit substrate 1 are in the spherical shape. Bonding is performed via electrode terminals (bumps) 20.

更に、第１パッケージ基板２の貫通孔部用電極パッド９形成された球状電極端子（バンプ）２０も溶融して、回路基板１に貫通形成され内壁部分に銅（Ｃｕ）メッキ６が施されている貫通孔部５内に流れ込む。   Further, the spherical electrode terminals (bumps) 20 formed on the through hole electrode pads 9 of the first package substrate 2 are also melted and formed to penetrate the circuit board 1 and the inner wall portion is subjected to copper (Cu) plating 6. It flows into the through-hole portion 5 that is present.

このようにして、第１パッケージ基板２の貫通孔部用電極パッド９と第２パッケージ基板３の貫通孔部用電極パッド９との間に、貫通孔部５内に充填され一体形成された半田を主体とする導体部材２５によって接合されてなるリベット構造が形成される。   In this way, the solder that is filled in and integrally formed in the through-hole portion 5 between the through-hole portion electrode pad 9 of the first package substrate 2 and the through-hole portion electrode pad 9 of the second package substrate 3. A rivet structure is formed which is joined by a conductor member 25 mainly composed of

即ち、球状電極端子（バンプ）２０の構成材料と同じ材料の半田を主体とする導体部材２５が、回路基板１の主面に対して略垂直の方向に略直線状に形成され、第１パッケージ基板２の貫通孔部用電極パッド９と第２パッケージ基板３の貫通孔部用電極パッド９とを一体的に接続する構造が形成される。   That is, the conductor member 25 mainly composed of solder of the same material as the constituent material of the spherical electrode terminal (bump) 20 is formed in a substantially straight line in a direction substantially perpendicular to the main surface of the circuit board 1, and the first package A structure in which the through hole electrode pad 9 of the substrate 2 and the through hole electrode pad 9 of the second package substrate 3 are integrally connected is formed.

以上説明したように、上述の構造を備えた両面実装半導体装置１０の製造方法の例によれば、特段の工程を設けることなく、第１パッケージ基板２及び第２パッケージ基板３を回路基板１に両面実装する際に施されるリフロー加熱処理を利用して、第１パッケージ基板２及び第２パッケージ基板３の外周部近傍に設けられた貫通孔部用電極パッド９上に形成された球状電極端子（バンプ）２０を構成する半田を溶融して回路基板１に形成された貫通孔部５に流し込み、これを第１パッケージ基板２及び第２パッケージ基板３と回路基板１とを接合する導体部材２５としている。   As described above, according to the example of the method of manufacturing the double-sided mounting semiconductor device 10 having the above-described structure, the first package substrate 2 and the second package substrate 3 are attached to the circuit substrate 1 without providing a special process. A spherical electrode terminal formed on a through-hole electrode pad 9 provided in the vicinity of the outer peripheral portions of the first package substrate 2 and the second package substrate 3 by using a reflow heating process applied when mounting on both sides. The solder constituting the (bump) 20 is melted and poured into the through-hole portion 5 formed in the circuit board 1, and the first package board 2 and the conductor member 25 that joins the second package board 3 and the circuit board 1 to each other. It is said.

よって、両面実装回路基板に対する電子部品の両面実装の通常のプロセスにおいて、新たな工程を設けたり、工程を変更することなく、上述のリベット構造を備えた両面実装半導体装置１０を形成することができる。   Therefore, in the normal process of double-sided mounting of electronic components on the double-sided mounted circuit board, the double-sided mounted semiconductor device 10 having the above-described rivet structure can be formed without providing a new process or changing the process. .

以上、本発明の実施の形態について詳述したが、本発明は特定の実施形態に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形及び変更が可能である。   Although the embodiment of the present invention has been described in detail above, the present invention is not limited to the specific embodiment, and various modifications and changes are within the scope of the gist of the present invention described in the claims. It can be changed.

本発明の実施の形態に係る両面実装回路基板に対する電子部品の実装構造（両面実装半導体装置）の例を示す断面図である。It is sectional drawing which shows the example of the mounting structure (double-sided mounting semiconductor device) of the electronic component with respect to the double-sided mounting circuit board concerning embodiment of this invention. 本発明の実施の形態に係る両面実装半導体装置の製造方法の例を説明するための図（その１）である。It is FIG. (1) for demonstrating the example of the manufacturing method of the double-sided mounting semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る両面実装半導体装置の製造方法の例を説明するための図（その２）である。It is FIG. (2) for demonstrating the example of the manufacturing method of the double-sided mounting semiconductor device which concerns on embodiment of this invention.

符号の説明Explanation of symbols

１ 回路基板
２ 第１パッケージ基板
３ 第２パッケージ基板
４、８ 電極パッド
５ 貫通孔部
６ 銅メッキ部
７ 導電層
９ 貫通孔部用電極パッド
１０ 両面実装半導体装置
２０ 球状電極端子
２５ 導体部材 DESCRIPTION OF SYMBOLS 1 Circuit board 2 1st package board | substrate 3 2nd package board | substrates 4 and 8 Electrode pad 5 Through-hole part 6 Copper plating part 7 Conductive layer 9 Electrode pad 10 for through-hole parts Double-sided mounting semiconductor device 20 Spherical electrode terminal 25 Conductive member

Claims (6)

回路基板の表面に第１の電子部品が実装され、
前記回路基板の裏面に第２の電子部品が実装され、
前記回路基板を挟んで互いに対向する少なくとも一組の前記第１の電子部品の電極部と前記第２の電子部品の電極部とが、前記回路基板に形成された貫通孔部内に一体形成された導体部材によって、接続されることを特徴とする両面実装回路基板に対する電子部品の実装構造。 A first electronic component is mounted on the surface of the circuit board;
A second electronic component is mounted on the back surface of the circuit board;
The electrode part of the first electronic component and the electrode part of the second electronic component facing each other across the circuit board are integrally formed in a through hole formed in the circuit board. A mounting structure of an electronic component on a double-sided mounting circuit board, which is connected by a conductor member. 請求項１記載の両面実装回路基板に対する電子部品の実装構造であって、
前記導体部材は、前記回路基板の主面に対して略垂直の方向に略直線状に形成され、少なくとも一組の前記第１の電子部品の前記電極部と前記第２の電子部品の前記電極部とが、前記導体部材によって一体的に接続されることを特徴とする両面実装回路基板に対する電子部品の実装構造。 An electronic component mounting structure for the double-sided mounting circuit board according to claim 1,
The conductor member is formed in a substantially straight line in a direction substantially perpendicular to the main surface of the circuit board, and at least one set of the electrode portion of the first electronic component and the electrode of the second electronic component. An electronic component mounting structure on a double-sided mounting circuit board, wherein the parts are integrally connected by the conductor member. 請求項１又は２記載の両面実装回路基板に対する電子部品の実装構造であって、
前記導体部材は、均一の材料から構成されていることを特徴とする両面実装回路基板に対する電子部品の実装構造。 An electronic component mounting structure for the double-sided mounting circuit board according to claim 1 or 2,
The mounting structure of an electronic component on a double-sided mounting circuit board, wherein the conductor member is made of a uniform material. 請求項１乃至３いずれか一項記載の両面実装回路基板に対する電子部品の実装構造であって、
前記貫通孔部は、前記第１の電子部品及び前記第２の電子部品の主面の外周近傍に形成された電極部と対向して、前記回路基板に貫通形成されていることを特徴とする両面実装回路基板に対する電子部品の実装構造。 An electronic component mounting structure for a double-sided mounting circuit board according to any one of claims 1 to 3,
The through-hole portion is formed through the circuit board so as to face an electrode portion formed near the outer periphery of the main surface of the first electronic component and the second electronic component. Electronic component mounting structure on a double-sided mounting circuit board. 回路基板の表面に、第１の半導体素子を備えた第１のパッケージ基板が実装され、
前記回路基板の裏面に、第２の半導体素子を備えた第２のパッケージ基板が実装され、
前記回路基板を挟んで互いに対向する少なくとも一組の前記第１のパッケージ基板の電極部と前記第２のパッケージ基板の電極部とが、前記回路基板に形成された貫通孔部内に一体形成された導体部材によって、接続されることを特徴とする半導体装置。 A first package substrate including a first semiconductor element is mounted on the surface of the circuit board,
A second package substrate having a second semiconductor element is mounted on the back surface of the circuit board,
The electrode part of the first package substrate and the electrode part of the second package substrate facing each other across the circuit board are integrally formed in a through-hole part formed in the circuit board. A semiconductor device connected by a conductor member. 両面実装半導体装置の製造方法であって、
熱処理を施して、回路基板の表面に、第１の半導体素子を備えた第１のパッケージ基板が実装する際、及び前記回路基板の裏面に、第２の半導体素子を備えた第２のパッケージ基板を実装する際に、
前記回路基板に形成された貫通孔部内に、溶融した導体部材を流れ込ませて、前記回路基板を挟んで互いに対向する少なくとも一組の前記第１のパッケージ基板の電極部と前記第２のパッケージ基板の電極部とを前記導体部材を介して接続することを特徴とする両面半導体装置の製造方法。 A method of manufacturing a double-sided mounted semiconductor device,
When the first package substrate having the first semiconductor element is mounted on the surface of the circuit board by performing heat treatment, and the second package substrate having the second semiconductor element on the back surface of the circuit board When implementing
At least one set of the electrode part of the first package substrate and the second package substrate facing each other with the circuit substrate interposed therebetween by flowing a molten conductor member into the through-hole portion formed in the circuit substrate A method for manufacturing a double-sided semiconductor device, comprising: connecting a plurality of electrode portions to each other through the conductor member.
JP2007122342A 2007-05-07 2007-05-07 Electronic component mounting structure on a double-sided mounting circuit board, semiconductor device, and manufacturing method of double-sided mounting semiconductor device Expired - Fee Related JP4952365B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007122342A JP4952365B2 (en) 2007-05-07 2007-05-07 Electronic component mounting structure on a double-sided mounting circuit board, semiconductor device, and manufacturing method of double-sided mounting semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007122342A JP4952365B2 (en) 2007-05-07 2007-05-07 Electronic component mounting structure on a double-sided mounting circuit board, semiconductor device, and manufacturing method of double-sided mounting semiconductor device

Publications (2)

Publication Number Publication Date
JP2008277691A true JP2008277691A (en) 2008-11-13
JP4952365B2 JP4952365B2 (en) 2012-06-13

Family

ID=40055272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007122342A Expired - Fee Related JP4952365B2 (en) 2007-05-07 2007-05-07 Electronic component mounting structure on a double-sided mounting circuit board, semiconductor device, and manufacturing method of double-sided mounting semiconductor device

Country Status (1)

Country Link
JP (1) JP4952365B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2284887A2 (en) 2009-08-06 2011-02-16 Fujitsu Limited Module comprising semiconductor devices and module manufacturing method
JP2011103441A (en) * 2009-10-14 2011-05-26 Fujitsu Ltd Semiconductor device and method of manufacturing the same
JP2014013826A (en) * 2012-07-04 2014-01-23 Yazaki Corp Electronic component mounting board

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09283698A (en) * 1996-04-15 1997-10-31 Nisshin:Kk Semiconductor device, connection of semiconductor device and connector for semiconductor device
JP2001257453A (en) * 2000-03-09 2001-09-21 Shinko Electric Ind Co Ltd Wiring board, semiconductor device, and method of manufacturing them
JP2002305361A (en) * 2001-04-05 2002-10-18 Casio Micronics Co Ltd Flexible wiring board, manufacturing method therefor, joining structure of flexible wiring board and joining method therefor
JP2005347513A (en) * 2004-06-03 2005-12-15 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2007173583A (en) * 2005-12-22 2007-07-05 Olympus Corp Laminated mounting structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09283698A (en) * 1996-04-15 1997-10-31 Nisshin:Kk Semiconductor device, connection of semiconductor device and connector for semiconductor device
JP2001257453A (en) * 2000-03-09 2001-09-21 Shinko Electric Ind Co Ltd Wiring board, semiconductor device, and method of manufacturing them
JP2002305361A (en) * 2001-04-05 2002-10-18 Casio Micronics Co Ltd Flexible wiring board, manufacturing method therefor, joining structure of flexible wiring board and joining method therefor
JP2005347513A (en) * 2004-06-03 2005-12-15 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2007173583A (en) * 2005-12-22 2007-07-05 Olympus Corp Laminated mounting structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2284887A2 (en) 2009-08-06 2011-02-16 Fujitsu Limited Module comprising semiconductor devices and module manufacturing method
JP2011103441A (en) * 2009-10-14 2011-05-26 Fujitsu Ltd Semiconductor device and method of manufacturing the same
JP2014013826A (en) * 2012-07-04 2014-01-23 Yazaki Corp Electronic component mounting board

Also Published As

Publication number Publication date
JP4952365B2 (en) 2012-06-13

Similar Documents

Publication Publication Date Title
JP6325605B2 (en) Electronic component built-in substrate
TWI466265B (en) Stacked package and method for manufacturing the package
JP2007158279A (en) Semiconductor device and electronic controller using the same
KR20070010915A (en) Substrate having heat spreading layer and semiconductor package using the same
JP4218434B2 (en) Electronic equipment
JP2007258430A (en) Semiconductor device
JP2005064479A (en) Circuit module
JP2007142097A (en) Semiconductor device
JP4494249B2 (en) Semiconductor device
JP2006173493A (en) Semiconductor device and manufacturing method therefor
JP4952365B2 (en) Electronic component mounting structure on a double-sided mounting circuit board, semiconductor device, and manufacturing method of double-sided mounting semiconductor device
JP4810235B2 (en) Semiconductor device and electronic component module using the same
JP5358515B2 (en) Semiconductor device and electronic control device using the same
JP2007251225A (en) Semiconductor package and stacked semiconductor package
JP2007299887A (en) Substrate for mounting semiconductor integrated circuit element, and semiconductor device
JP2004087936A (en) Semiconductor device, manufacturing method thereof, and electronic appliance
JP2008141036A (en) Printed substrate and method of manufacturing the same
JP4193702B2 (en) Semiconductor package mounting structure
JP2006286660A (en) Three-dimensional electronic circuit apparatus
JP2006049720A (en) Electronic circuit device
US11670574B2 (en) Semiconductor device
JP2024027289A (en) semiconductor equipment
JP2004172425A (en) Electronic apparatus
JP2008085222A (en) Printed wiring board, method of mounting exterior component on printed wiring board and electronic apparatus
JP2010251566A (en) Wiring board, semiconductor device, semiconductor module, and method of manufacturing the module

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100119

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20111026

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20111108

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120106

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120214

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120227

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150323

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees