JP2008277660A - Lga semiconductor mounting structure - Google Patents

Lga semiconductor mounting structure Download PDF

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JP2008277660A
JP2008277660A JP2007121795A JP2007121795A JP2008277660A JP 2008277660 A JP2008277660 A JP 2008277660A JP 2007121795 A JP2007121795 A JP 2007121795A JP 2007121795 A JP2007121795 A JP 2007121795A JP 2008277660 A JP2008277660 A JP 2008277660A
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substrate
mounting structure
semiconductor mounting
lga semiconductor
thickness
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Jiatou Hong
嘉▲鍮▼ 洪
Zhaoxiang Lu
肇祥 呂
Zhengxian Qiu
政賢 邱
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Powertech Technology Inc
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Powertech Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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Abstract

<P>PROBLEM TO BE SOLVED: To provide an LGA mounting-type electronic product which can avoid scratches and collisions of a metal pad group or a solder bonding layer. <P>SOLUTION: An LGA semiconductor mounting structure 200 is provided with a substrate 210, a chip 220, the solder bonding layer 230 and a foot stand 240. The substrate 210 has an upper surface 211 and a lower surface 212. A plurality of metal pads 213 are arranged on the lower surface 212 into an array shape. The chip 220 is installed on the upper surface 211 of the substrate 210 and is electrically connected to the metal pads 213. The solder bonding layer 230 is arranged in the metal pad group 213 and has first thickness which slightly projects to the lower surface 212 of the substrate 210. The foot stand 240 is disposed below the substrate 210 and has second thickness projecting to the lower surface 212 of the substrate, and Second thickness becomes thicker than first thickness. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は半導体集積回路実装構造に関し、特にＬＧＡ（Land Grid Array）半導体実装構造に関する。   The present invention relates to a semiconductor integrated circuit mounting structure, and more particularly to an LGA (Land Grid Array) semiconductor mounting structure.

以前のＬＧＡ半導体実装構造中が、対外電気接続用とする複数の金属パッドが製品の底面にアレイ状に設置されることに比べ、現在のＬＧＡ半導体実装構造中は、対外電気接続用とする複数の金属針で探ることを採用している。このようなＬＧＡ半導体実装構造と接合するＰＣＢ（Printed Circuit Board）は必ず蓋を具する特殊なソケットを設置し、金属針群はこの蓋を具する特殊ソケット内に配列されることによって、従来のＬＧＡ半導体実装構造に位置定めと押し付けを行うことができる。   In the previous LGA semiconductor mounting structure, a plurality of metal pads for external electrical connection are arranged in an array on the bottom surface of the product. Adopting searching with metal needles. A PCB (Printed Circuit Board) to be joined to such an LGA semiconductor mounting structure always has a special socket having a lid, and the metal needle group is arranged in the special socket having the lid. Positioning and pressing can be performed on the LGA semiconductor mounting structure.

図１に示すように、従来のＬＧＡ半導体実装構造１００は、主に基板１１０、及びチップ１２０を備える。その基板１１０は上表面１１１、下表面１１２、及びその下表面１１２に設置される複数の金属パッド１１３を備える。そのチップ１２０は基板１１０の上表面１１１に設置され、複数のバンプ１４０を介して基板１１０と電気接続している。そのＬＧＡ半導体実装構造１００はさらに封止体１３０を有し、この封止体１３０は基板１１０の上表面１１１に形成されてバンプ１４０群を密封している。また、そのＬＧＡ半導体実装構造１００はさらに複数の受動素子１５０を有し、それらの受動素子１５０は基板１１０の下表面１１２に設置されている。放熱フィン１６０は基板１１０の上表面１１１に設置される。このような従来のＬＧＡ半導体実装構造１００に対し、金属針群の電気接触方式は唯一外部と電気接続できるので、製品に応用面が狭くなり、そして、運搬と貯蔵の過程では、ＬＧＡ半導体実装構造１００が搭載面１０に載せられて金属パッド１１３群と底面の受動素子１５０群とは傷付きや衝突などに遭い易くなる。   As shown in FIG. 1, the conventional LGA semiconductor mounting structure 100 mainly includes a substrate 110 and a chip 120. The substrate 110 includes an upper surface 111, a lower surface 112, and a plurality of metal pads 113 disposed on the lower surface 112. The chip 120 is placed on the upper surface 111 of the substrate 110 and is electrically connected to the substrate 110 via a plurality of bumps 140. The LGA semiconductor mounting structure 100 further includes a sealing body 130, which is formed on the upper surface 111 of the substrate 110 and seals the bump 140 group. The LGA semiconductor mounting structure 100 further includes a plurality of passive elements 150, and these passive elements 150 are installed on the lower surface 112 of the substrate 110. The radiation fins 160 are installed on the upper surface 111 of the substrate 110. In contrast to the conventional LGA semiconductor mounting structure 100, the metal contact group can be electrically connected only to the outside, so that the application of the product is narrow, and the LGA semiconductor mounting structure is in the process of transportation and storage. 100 is placed on the mounting surface 10 and the metal pad 113 group and the passive element 150 group on the bottom surface are easily damaged or collided.

本発明の主な目的は一種のＬＧＡ半導体実装構造を提供し、このＬＧＡ半導体実装構造は、ＳＭＴ（Surface Mount Technology）方式を用いて電気接続を達成することができ、電気接触方式で特殊ソケット及び金属針を具するＰＣＢと接合する必要がなくなり、また、従来の金属パッド群或は半田接合層が傷付きや衝突などの問題に遭うことを避けられてＬＧＡ実装型電子製品の応用範囲を有効に拡大している。   The main object of the present invention is to provide a kind of LGA semiconductor mounting structure, which can achieve an electrical connection using an SMT (Surface Mount Technology) method, a special socket and an electrical contact method. Eliminates the need for bonding with PCBs with metal needles, and avoids problems such as scratches and collisions with conventional metal pad groups or solder bonding layers, making the LGA-mountable electronic products more effective Has expanded to.

本発明のもう一つの目的は一種のＬＧＡ半導体実装構造を提供し、このＬＧＡ半導体実装構造は、以前に放置や運搬の過程に受動素子群を傷をつける問題を解決することができる。
本発明のまたもう一つの目的は一種のＬＧＡ半導体実装構造を提供し、このＬＧＡ半導体実装構造はフートスタンドの設置コストを低下可能である。 Another object of the present invention is to provide a kind of LGA semiconductor mounting structure, which can solve the problem of scratching the passive element group in the process of leaving and transporting before.
Another object of the present invention is to provide a kind of LGA semiconductor mounting structure, which can reduce the installation cost of the foot stand.

本発明の問題を下記の技術を採用して解決する。本発明により、ＬＧＡ半導体実装構造は、主要に基板、チップ、半田接合層、及びフートスタンドを備える。その基板は上表面と下表面とを有し、下表面に複数の金属パッドがアレイ状に配列されている。そのチップは基板の上表面に設置され且つそれらの金属パッドに電気接続されている。その半田接合層は金属パッド群に設置されて基板の下表面にわずかに突出する第一厚さを有し、そのフートスタンドは基板の下方に設置されて基板の下表面に突出する第二厚さを有し、第二厚さは第一厚さよりも厚くなる。   The problems of the present invention are solved by employing the following technique. According to the present invention, the LGA semiconductor mounting structure mainly includes a substrate, a chip, a solder bonding layer, and a foot stand. The substrate has an upper surface and a lower surface, and a plurality of metal pads are arranged in an array on the lower surface. The chip is placed on the top surface of the substrate and electrically connected to those metal pads. The solder bonding layer is disposed on the metal pad group and has a first thickness that slightly protrudes from the lower surface of the substrate. The foot stand is disposed below the substrate and protrudes from the lower surface of the substrate. The second thickness is greater than the first thickness.

上記のＬＧＡ半導体実装構造において、さらに封止体を有し、その封止体は基板の上表面に形成されて少なくともチップの一部を密封している。
上記のＬＧＡ半導体実装構造において、そのフートスタンドは封止体と一体に連結されることができる。
上記のＬＧＡ半導体実装構造において、基板は対称的に並ぶ複数の貫通孔を具し、そのフートスタンドはそれらの貫通孔と結合している。 The above LGA semiconductor mounting structure further includes a sealing body, which is formed on the upper surface of the substrate and seals at least a part of the chip.
In the above LGA semiconductor mounting structure, the foot stand can be integrally connected to the sealing body.
In the LGA semiconductor mounting structure described above, the substrate has a plurality of symmetrically arranged through holes, and the foot stand is coupled to the through holes.

上記のＬＧＡ半導体実装構造において、基板はスロットを具し、そのスロットを介してフートスタンドは封止体と一体に連結されている。
上記のＬＧＡ半導体実装構造において、さらに複数のボンディングワイヤを有し、それらのボンディングワイヤはスロットを通してチップと基板とを電気接続し、そのフートスタンドに覆われている。 In the above LGA semiconductor mounting structure, the substrate has a slot, and the foot stand is integrally connected to the sealing body through the slot.
The above-described LGA semiconductor mounting structure further includes a plurality of bonding wires, and these bonding wires electrically connect the chip and the substrate through the slots and are covered with the foot stand.

上記のＬＧＡ半導体実装構造において、さらに複数のバンプを有し、それらのバンプを介してチップと基板とを電気接続している。
上記のＬＧＡ半導体実装構造において、そのフートスタンドは複数の支持ブロックから成って基板の下表面の角や周縁部に位置されている。
上記のＬＧＡ半導体実装構造において、そのフートスタンドは細長い形状になって基板の中心線に位置されている。 The above LGA semiconductor mounting structure further includes a plurality of bumps, and the chip and the substrate are electrically connected through the bumps.
In the above-described LGA semiconductor mounting structure, the foot stand is composed of a plurality of support blocks and is positioned at the corner or peripheral edge of the lower surface of the substrate.
In the above LGA semiconductor mounting structure, the foot stand has an elongated shape and is positioned on the center line of the substrate.

上記のＬＧＡ半導体実装構造において、そのフートスタンドは誘電物になってもよい。
上記のＬＧＡ半導体実装構造において、さらに複数の受動素子を有し、それらの受動素子は基板の下表面に設置されて基板の下表面に突出する第三厚さを有し、第二厚さも第三厚さよりも厚くなる。
上記のＬＧＡ半導体実装構造において、さらに放熱フィンを有し、その放熱フィンは基板の上表面に設置されている。 In the above LGA semiconductor mounting structure, the foot stand may be a dielectric.
In the above-described LGA semiconductor mounting structure, the semiconductor device further includes a plurality of passive elements. The passive elements are disposed on the lower surface of the substrate and have a third thickness protruding from the lower surface of the substrate. It becomes thicker than three thicknesses.
In the above-described LGA semiconductor mounting structure, a heat dissipating fin is further provided, and the heat dissipating fin is disposed on the upper surface of the substrate.

図２は、本発明の第一実施例によるＬＧＡ半導体実装構造の断面を示し、図３はＬＧＡ半導体実装構造の一部を拡大する断面を示し、図４はＬＧＡ半導体実装構造の底面を示している。
図２に示すように、そのＬＧＡ半導体実装構造２００は、主要に基板２１０、チップ２２０、半田接合層２３０、及びフートスタンド２４０を備える。その基板２１０は上表面２１１と下表面２１２を有し、下表面２１２にアレイ状に並ぶ複数の金属パッド２１３が設置される。その基板２１０は多層ＰＣＢであってもよい。本実施例では、基板２１０は対称的に並ぶ複数の貫通孔２１４を具し、そのフートスタンド２４０は貫通孔２１４群と結合している。 2 shows a cross-section of the LGA semiconductor mounting structure according to the first embodiment of the present invention, FIG. 3 shows a cross-sectional view enlarging a part of the LGA semiconductor mounting structure, and FIG. 4 shows a bottom surface of the LGA semiconductor mounting structure. Yes.
As shown in FIG. 2, the LGA semiconductor mounting structure 200 mainly includes a substrate 210, a chip 220, a solder bonding layer 230, and a foot stand 240. The substrate 210 has an upper surface 211 and a lower surface 212, and a plurality of metal pads 213 arranged in an array on the lower surface 212 are provided. The substrate 210 may be a multilayer PCB. In the present embodiment, the substrate 210 has a plurality of through holes 214 arranged symmetrically, and the foot stand 240 is coupled to the group of through holes 214.

チップ２２０は、基板２１０の上表面２１１に設置されて金属パッド２１３群に電気接続される。本実施例では、そのＬＧＡ半導体実装構造２００はさらに複数のバンプ２６０を有し、それらのバンプ２６０はチップ２２０の下方に形成されてフリップチップとしてチップ２２０と基板２１０とを電気接続している。再び基板２１０の内部配線を介して基板２１０と金属パッド２１３群とを電気接続している。   The chip 220 is installed on the upper surface 211 of the substrate 210 and is electrically connected to the metal pads 213 group. In the present embodiment, the LGA semiconductor mounting structure 200 further includes a plurality of bumps 260, which are formed below the chip 220 and electrically connect the chip 220 and the substrate 210 as a flip chip. Again, the substrate 210 and the metal pad 213 group are electrically connected via the internal wiring of the substrate 210.

図３に示すように、その半田接合層２３０は金属パッド２１３群上に配置されて基板２１０の下表面２１２にわずかに突出する第一厚さ２３１を具する。半田接合層２３０は、球状ではなく円弧状にリフロー（reflow）する錫‐鉛半田材料や無鉛半田材料などから成ることができるが、しかし、通常、半田接合層２３０の提供量は球状にリフローすることに対して不足している。   As shown in FIG. 3, the solder bonding layer 230 has a first thickness 231 disposed on the metal pad 213 group and slightly protruding from the lower surface 212 of the substrate 210. The solder bonding layer 230 may be formed of a tin-lead solder material or a lead-free solder material that reflows in an arc shape instead of a spherical shape. However, the amount of the solder bonding layer 230 is generally reflowed in a spherical shape. There is a lack of that.

フートスタンド２４０は基板２１０に設置されて基板２１０の下表面２１２に突出する第二厚さ２４１を具し、第二厚さ２４１は第一厚さ２３１よりも厚くなる。従って、フートスタンド２４０を介してそのＬＧＡ半導体実装構造２００を搭載物の搭載面２０、例え机の表面やキャリアー収容底面に置くことにより、半田接合層２３０は搭載面２０に接触せず、金属パッド２１３群或は半田接合層２３０が傷付きと衝突などの問題に遭うことを避ける。図３と図４に示すように、フートスタンド２４０は複数の支持ブロックから構成され、基板２１０の下表面２１２の角や周縁部に位置している。本実施例では、そのフートスタンド２４０は誘電性を具する。   The foot stand 240 has a second thickness 241 that is installed on the substrate 210 and protrudes from the lower surface 212 of the substrate 210, and the second thickness 241 is thicker than the first thickness 231. Therefore, by placing the LGA semiconductor mounting structure 200 on the mounting surface 20 of the mounted object, for example, the surface of the desk or the carrier receiving bottom surface via the foot stand 240, the solder bonding layer 230 does not contact the mounting surface 20, and the metal pad The 213 group or the solder bonding layer 230 avoids problems such as scratches and collisions. As shown in FIGS. 3 and 4, the foot stand 240 is composed of a plurality of support blocks, and is located at the corner or peripheral edge of the lower surface 212 of the substrate 210. In the present embodiment, the foot stand 240 is dielectric.

図２及び図３に示すように、具体的に言えば、そのＬＧＡ半導体実装構造２００はさらに複数の受動素子２７０を有し、それらの受動素子２７０は基板２１０の下表面２１２に設置されて基板２１０の下表面２１２に突出する第三厚さ２７１を具し、第二厚さ２４１も第三厚さ２７１よりも厚くなる。第二厚さ２４１は第一厚さ２３１より、且つ第三厚さ２７１よりも厚くなるので、ＬＧＡ半導体実装構造２００を放置する際に、受動素子２７０群は搭載面２０に接触しなくなって傷付きを避けられる。   Specifically, as shown in FIGS. 2 and 3, the LGA semiconductor mounting structure 200 further includes a plurality of passive elements 270, which are installed on the lower surface 212 of the substrate 210. A third thickness 271 protruding from the lower surface 212 of 210 is provided, and the second thickness 241 is also thicker than the third thickness 271. Since the second thickness 241 is thicker than the first thickness 231 and thicker than the third thickness 271, when the LGA semiconductor mounting structure 200 is left untouched, the passive elements 270 do not contact the mounting surface 20 and are damaged. You can avoid it.

もっと詳しく言えば、そのＬＧＡ半導体実装構造２００はさらに封止体２５０を有し、その封止体２５０は基板２１０の上表面２１１に形成されて少なくともチップ２２０の一部を密封している。本実施例では、封止体２５０はディスペンス（dispense）材料或はアンダーフィル（underfill）材料から成ってもよく、チップ２２０の能動面とバンプ２６０群とを密封している。そのＬＧＡ半導体実装構造２００はさらに放熱フィン２８０を有することが好ましく、その放熱フィン２８０は基板２１０の上表面２１１に設置されて放熱効率を向上させる。ゆえに、そのＬＧＡ半導体実装構造２００は、金属針を具する特殊ソケットの設置を必要とせずＳＭＴ方式でＰＣＢと接合することができ、そして、半田接合層２３０と金属パッド２１３群とに良好な保護が得られる。   More specifically, the LGA semiconductor mounting structure 200 further includes a sealing body 250, which is formed on the upper surface 211 of the substrate 210 and seals at least a part of the chip 220. In this embodiment, the sealing body 250 may be made of a dispense material or an underfill material, and seals the active surface of the chip 220 and the bumps 260. The LGA semiconductor mounting structure 200 preferably further includes heat radiation fins 280. The heat radiation fins 280 are installed on the upper surface 211 of the substrate 210 to improve heat radiation efficiency. Therefore, the LGA semiconductor mounting structure 200 can be bonded to the PCB by the SMT method without requiring the installation of a special socket having a metal needle, and provides good protection for the solder bonding layer 230 and the metal pads 213 group. Is obtained.

また、図５は、本発明の第二実施例によるもう一種のＬＧＡ半導体実装構造３００の断面を示し、図６はそのＬＧＡ半導体実装構造３００の底面を示す。図５及び図６に示すように、そのＬＧＡ半導体実装構造３００は、主に基板３１０、チップ３２０、半田接合層３３０、及びフートスタンド３４０を備える。その基板３１０は上表面３１１と及び下表面３１２を有し、その下表面３１２に複数の金属パッド３１３がアレイ状に配列されている。本実施例では、基板３１０はさらにスロット３１４を具する。   FIG. 5 shows a cross section of another type of LGA semiconductor mounting structure 300 according to the second embodiment of the present invention, and FIG. 6 shows the bottom surface of the LGA semiconductor mounting structure 300. As shown in FIGS. 5 and 6, the LGA semiconductor mounting structure 300 mainly includes a substrate 310, a chip 320, a solder bonding layer 330, and a foot stand 340. The substrate 310 has an upper surface 311 and a lower surface 312, and a plurality of metal pads 313 are arranged on the lower surface 312 in an array. In this example, the substrate 310 further comprises a slot 314.

そのチップ３２０の能動面３２２は粘着方式を用いて基板３１０の上表面３１１に設置され、チップ電極として複数のボンディングパッド３２１がチップ３２０のその能動面３２２に設置され、それらのボンディングパッド３２１は基板３１０のスロット３１４内に向かっている。他に、複数のボンディングワイヤ３６０を用いてそのスロット３１４を通してボンディングパッド３２１群と基板３１０のワイヤボンディングフィンガー群（wire bonding finger）（図面に示していない）とを電気接続し、再び基板３１０の内部配線を介して基板３１０と金属パッド３１３群とを電気接続している。   The active surface 322 of the chip 320 is installed on the upper surface 311 of the substrate 310 using an adhesion method, and a plurality of bonding pads 321 are installed on the active surface 322 of the chip 320 as chip electrodes, and these bonding pads 321 are formed on the substrate. Into the slot 314 of 310. In addition, a plurality of bonding wires 360 are used to electrically connect bonding pads 321 and wire bonding fingers (not shown in the drawing) of the substrate 310 through the slots 314, and again to the inside of the substrate 310. The substrate 310 and the metal pad 313 group are electrically connected through wiring.

その半田接合層３３０は金属パッド３１３群に設置されて基板３１０の下表面３１２にわずかに突出する第一厚さ３３１を有し、そのフートスタンド３４０は基板３１０の下方に設置されて基板３１０の下表面３１２に突出する第二厚さ３４１を有し、第二厚さ３４１は第一厚さ３３１よりも厚くなる。本実施例では、半田接合層３３０の第一厚さ３３１は約８０ｕｍ〜１２０ｕｍの厚みであり、フートスタンド３４０の第二厚さ３４１は約１６０ｕｍ〜２００ｕｍの厚みである。再び図５に示すように、そのＬＧＡ半導体実装構造３００は水平に放置されることができ、第二厚さ３４１は第一厚さ３３１よりも厚くなるのでフートスタンド３４０は搭載面３０と接触し、半田接合層３３０は搭載面３０に接触しなくなり、運搬や貯蔵の過程での半田接合層３３０の傷付きや汚染を避けることが可能である。本実施例では、フートスタンド３４０は長細い形状になって基板３１０の中心線に置かれ、もっと詳しく言えば、フートスタンド３４０の“Ｉ”形或は他の形になってもよい（図６参照）。   The solder bonding layer 330 is disposed on the metal pad 313 group and has a first thickness 331 that slightly protrudes from the lower surface 312 of the substrate 310, and the foot stand 340 is disposed below the substrate 310 to form the substrate 310. The second thickness 341 protrudes from the lower surface 312, and the second thickness 341 is thicker than the first thickness 331. In the present embodiment, the first thickness 331 of the solder bonding layer 330 is about 80 μm to 120 μm, and the second thickness 341 of the foot stand 340 is about 160 μm to 200 μm. As shown in FIG. 5 again, the LGA semiconductor mounting structure 300 can be left horizontally, and the second thickness 341 is thicker than the first thickness 331, so that the foot stand 340 is in contact with the mounting surface 30. The solder bonding layer 330 does not come into contact with the mounting surface 30, and it is possible to avoid damage and contamination of the solder bonding layer 330 during transportation and storage. In this embodiment, the foot stand 340 is elongated and placed on the center line of the substrate 310, and more specifically, may be an “I” shape or other shape of the foot stand 340 (FIG. 6). reference).

そのＬＧＡ半導体実装構造３００はさらに封止体３５０を有し、その封止体３５０は基板３１０の上表面３１１に形成されて少なくともチップ３２０の一部を密封している。本実施例では、封止体３５０がＥＭＣ材（epoxy molding compound）から成り、完全にチップ３２０を密封することができる。また、フートスタンド３４０はスロット３１４を介して封止体３５０と一体的に連結されることが好ましく、それにより、フートスタンド３４０の設置コストを減らすことが可能となり、そして、フートスタンド３４０もボンディングワイヤ３６０群を覆うことができる。   The LGA semiconductor mounting structure 300 further includes a sealing body 350, which is formed on the upper surface 311 of the substrate 310 and seals at least a part of the chip 320. In this embodiment, the sealing body 350 is made of an EMC material (epoxy molding compound), and the chip 320 can be completely sealed. Further, it is preferable that the foot stand 340 is integrally connected to the sealing body 350 through the slot 314, so that the installation cost of the foot stand 340 can be reduced, and the foot stand 340 is also bonded to the bonding wire. 360 groups can be covered.

図７に示すように、そのＬＧＡ半導体実装構造３００はＳＭＴ方式でＰＣＢ４１０に半田接合されることが可能である。そのＰＣＢ４１０の表面では、複数の半田ボール４２０或はソルダペースト（solder paste）の接合用として複数のボールパッド４１１を備える。それらの半田ボール４２０の直径と半田接合層３３０の第一厚さ３３１との合計高さはフートスタンド３４０の第二厚さ３４１よりも高くなることより、リフロー過程において、半田接合層３３０と半田ボール４２０群とは一緒にリフローされて熔融になってしまう。そのＬＧＡ半導体実装構造３００は外部のＰＣＢ４１０と電気接続し、そのＰＣＢ４１０には特殊なソケットと金属針とを設置する必要がなく、ＰＣＢの製造コストを大幅に減少することとなる。ゆえに、そのＬＧＡ半導体実装構造３００は、ＬＧＡ半導体実装構造型電子製品の応用範囲を有効に拡大することができ、かつ半田接合層３３０に傷や汚染などを防止することができる。例えば、そのＬＧＡ半導体実装構造３００はメモリモジュール（memory module）に応用されることが可能であるが、従来のＬＧＡ半導体実装構造ではなかなか実現できない。   As shown in FIG. 7, the LGA semiconductor mounting structure 300 can be soldered to the PCB 410 by the SMT method. On the surface of the PCB 410, a plurality of ball pads 411 are provided for joining a plurality of solder balls 420 or a solder paste. Since the total height of the diameters of the solder balls 420 and the first thickness 331 of the solder bonding layer 330 is higher than the second thickness 341 of the foot stand 340, the solder bonding layer 330 and the solder in the reflow process. The balls 420 are reflowed together and become molten. The LGA semiconductor mounting structure 300 is electrically connected to an external PCB 410, and it is not necessary to install a special socket and metal needle on the PCB 410, which greatly reduces the PCB manufacturing cost. Therefore, the LGA semiconductor mounting structure 300 can effectively expand the application range of the LGA semiconductor mounting structure type electronic product, and can prevent the solder joint layer 330 from being scratched or contaminated. For example, the LGA semiconductor mounting structure 300 can be applied to a memory module, but cannot be realized with a conventional LGA semiconductor mounting structure.

図８は、本発明の第三実施例によるＬＧＡ半導体実装構造５００を示し、主に基板５１０、チップ５２０、及びフートスタンド５３０を有し、その基板５１０は上表面５１１及び下表面５１２を具し、下表面５１２にアレイ状に並ぶ複数の金属パッド５１３が設置される。本実施例では、基板５１０はさらにフートスタンド５３０の設置用としてスロット５１４を具する。   FIG. 8 shows an LGA semiconductor mounting structure 500 according to a third embodiment of the present invention, which mainly includes a substrate 510, a chip 520, and a foot stand 530. The substrate 510 includes an upper surface 511 and a lower surface 512. A plurality of metal pads 513 arranged in an array on the lower surface 512 are provided. In this embodiment, the substrate 510 further includes a slot 514 for installing the foot stand 530.

チップ５２０の能動面５２２を基板５１０の上表面５１１に貼着し、チップ５２０の能動面５２２に複数のボンディングパッド５２１が設置され、それらのボンディングパッド５２１はそのスロット５１４内に向かっている。また、複数のボンディングワイヤ５５０を用いてスロット５１４を通してボンディングパッド５２１群と基板５１０とを電気接続している。フートスタンド５３０は、基板５１０の下方に設置される際に基板５１０の下表面５１２に突出して、金属パッド５１３を摩擦や傷付きから保護している。フートスタンド５３０はボンディングワイヤ５５０群を覆うこともできる。   The active surface 522 of the chip 520 is attached to the upper surface 511 of the substrate 510, and a plurality of bonding pads 521 are installed on the active surface 522 of the chip 520, and these bonding pads 521 are directed into the slots 514. In addition, the bonding pads 521 and the substrate 510 are electrically connected through the slot 514 using a plurality of bonding wires 550. The foot stand 530 protrudes from the lower surface 512 of the substrate 510 when installed below the substrate 510 to protect the metal pad 513 from friction and scratches. The foot stand 530 may cover the bonding wires 550 group.

そして、半田接合層は（図面に示していない）、例えばＮＩ‐Ａｕ層であって、それらの金属パッド５１３に配置され、フートスタンド５３０の突出高度を超えないことによって、ＬＧＡ半導体実装構造５００は水平に放置されて運搬と貯蔵されることができ、さらにＳＭＴ作業を行える。本実施例では、そのＬＧＡ半導体実装構造５００はさらに封止体５４０を有し、その封止体５４０は基板５１０の上表面５１１に形成されて少なくともチップ５２０の一部を密封している。   The solder bonding layer (not shown in the drawing) is, for example, an NI-Au layer, which is disposed on the metal pads 513 and does not exceed the protruding height of the foot stand 530, whereby the LGA semiconductor mounting structure 500 is It can be left horizontally and transported and stored, and further SMT work can be performed. In this embodiment, the LGA semiconductor mounting structure 500 further includes a sealing body 540, which is formed on the upper surface 511 of the substrate 510 and seals at least a part of the chip 520.

従って、従来のＬＧＡ半導体実装構造に相対し、そのＬＧＡ半導体実装構造５００は、一回の半田ボール植入を需要とする赤外線リフローステップを減少することができるので、リフロープロセスにより起きる熱応力を避けられる。なお、そのＬＧＡ半導体実装構造５００はＳＭＴ作業を行った後に、金属パッド５１３群がＰＣＢ上の半田ボール群と接合することによって、金属拡散や金属脆化などの有害作用が減って金属パッド５１３群と半田ボール群との間の接合界面が断裂しないようになる。   Therefore, in contrast to the conventional LGA semiconductor mounting structure, the LGA semiconductor mounting structure 500 can reduce the infrared reflow step requiring a single solder ball implantation, thereby avoiding the thermal stress caused by the reflow process. It is done. In the LGA semiconductor mounting structure 500, after performing the SMT operation, the metal pad 513 group is bonded to the solder ball group on the PCB, thereby reducing harmful effects such as metal diffusion and metal embrittlement, and the metal pad 513 group. The joint interface between the solder ball group and the solder ball group does not tear.

また、本発明の実施例のフートスタンドはさまざまな形状と数量を持ってもよく、図９に示すように、本発明の第四実施例によるＬＧＡ半導体実装構造６００は、主要に基板６１０、チップ６２０、及び複数のフートスタンド６３１、６３２を備える。その基板６１０は上表面６１１と下表面６１２とを具し、下表面６１２にアレイ状に並ぶ複数の金属パッド６１３が設置される。本実施例では、基板６１０はさらにそれらのフートスタンド６３１、６３２の設置用として複数の結合孔６１４、６１５を具する。   Further, the foot stand of the embodiment of the present invention may have various shapes and quantities. As shown in FIG. 9, the LGA semiconductor mounting structure 600 according to the fourth embodiment of the present invention mainly includes a substrate 610, a chip. 620 and a plurality of foot stands 631 and 632. The substrate 610 has an upper surface 611 and a lower surface 612, and a plurality of metal pads 613 arranged in an array on the lower surface 612 are provided. In this embodiment, the substrate 610 further includes a plurality of coupling holes 614 and 615 for installing the foot stands 631 and 632.

チップ６２０の表面６２１を基板６１０の上表面６１１に貼着し、その表面６２１に複数のボンディングパッドを配置している。さらに複数のボンディングワイヤ６５０を用いそれらの結合孔６１４、６１５を通してチップ６２０と基板６１０とを電気接続している。それらのフートスタンド６３１、６３２が基板６１０に設置される際に、それらの結合孔６１４、６１５は基板６１０の下表面６１２に突出して金属パッド６１３を摩擦や傷付きから保護している。また、それらのフートスタンド６３１、６３２は中央に位置する中央フートスタンド６３１と複数の側辺フートスタンド６３２とに区分され、それらの側辺フートスタンド６３２は基板６１０の側辺に設置されかつ基板６１０の下表面６１２に突出している。金属パッド６１３群は中央フートスタンド６３１と側辺フートスタンド６３２群との間に位置して傷付きの防止効果を増加している。そして、中央フートスタンド６３１とそれらの側辺フートスタンド６３２群とはさらに基板６１０の中央と側辺とに置くボンディングワイヤ６５０群を覆うことができる。   The surface 621 of the chip 620 is attached to the upper surface 611 of the substrate 610, and a plurality of bonding pads are arranged on the surface 621. Further, a plurality of bonding wires 650 are used to electrically connect the chip 620 and the substrate 610 through their coupling holes 614 and 615. When the foot stands 631 and 632 are installed on the substrate 610, the coupling holes 614 and 615 protrude to the lower surface 612 of the substrate 610 to protect the metal pad 613 from friction and scratches. The foot stands 631 and 632 are divided into a central foot stand 631 located at the center and a plurality of side foot stands 632, and the side foot stands 632 are installed on the side of the substrate 610 and the substrate 610. Projecting to the lower surface 612 of the substrate. The metal pad 613 group is located between the central foot stand 631 and the side foot stand 632 group to increase the damage prevention effect. The center foot stand 631 and the side foot stand 632 group can further cover the bonding wire 650 group placed at the center and the side of the substrate 610.

ゆえに、そのＬＧＡ半導体実装構造６００は水平に放置されて運搬と貯蔵されることができ、さらにＳＭＴ作業を行える。本実施例では、そのＬＧＡ半導体実装構造６００はさらに封止体６４０を有し、その封止体６４０は基板６１０の上表面６１１に形成されてチップ６２０を密封している。
以上、本発明をその好適な実施例に基づいて説明したが、本発明の保護範囲は後付の特許申請範囲で限定されて、この保護範囲に基準して、本発明の精神と範囲内に触れるどんな変更や修正は本発明の保護範囲に属する。 Therefore, the LGA semiconductor mounting structure 600 can be left horizontally to be transported and stored, and can perform SMT operations. In this embodiment, the LGA semiconductor mounting structure 600 further includes a sealing body 640, which is formed on the upper surface 611 of the substrate 610 and seals the chip 620.
Although the present invention has been described based on the preferred embodiments thereof, the scope of protection of the present invention is limited by the scope of patent application that is attached later, and within the spirit and scope of the present invention based on this scope of protection. Any changes or modifications mentioned are within the protection scope of the present invention.

従来のＬＧＡ半導体実装構造を示す断面図である。It is sectional drawing which shows the conventional LGA semiconductor mounting structure. 本発明の第一実施例によるＬＧＡ半導体実装構造を示す断面図である。It is sectional drawing which shows the LGA semiconductor mounting structure by 1st Example of this invention. 本発明の第一実施例によるＬＧＡ半導体実装構造の一部を拡大する断面図である。It is sectional drawing which expands a part of LGA semiconductor mounting structure by 1st Example of this invention. 本発明の第一実施例によるＬＧＡ半導体実装構造の底面を示す。1 shows a bottom surface of an LGA semiconductor mounting structure according to a first embodiment of the present invention. 本発明の第二実施例によるＬＧＡ半導体実装構造を示す断面図である。It is sectional drawing which shows the LGA semiconductor mounting structure by the 2nd Example of this invention. 本発明の第二実施例によるＬＧＡ半導体実装構造の底面を示す。7 shows a bottom surface of an LGA semiconductor mounting structure according to a second embodiment of the present invention. 本発明の第二実施例によるＬＧＡ半導体実装構造の使用中の状態を示す断面図である。It is sectional drawing which shows the state in use of the LGA semiconductor mounting structure by 2nd Example of this invention. 本発明の第三実施例によるＬＧＡ半導体実装構造を示す断面図である。It is sectional drawing which shows the LGA semiconductor mounting structure by the 3rd Example of this invention. 本発明の第四実施例によるＬＧＡ半導体実装構造を示す断面図である。It is sectional drawing which shows the LGA semiconductor mounting structure by 4th Example of this invention.

符号の説明Explanation of symbols

２０：搭載面、３０：搭載面、２００：ＬＧＡ半導体実装構造、２１０：基板、２１１：上表面、２１２：下表面、２１３：金属パッド、２１４：貫通孔、２２０：チップ、２３０：半田接合層、２３１：第一厚さ、２４０：フートスタンド、２４１：第二厚さ、２５０：封止体、２６０：バンプ、２７０：受動素子、２７１：第三厚さ、２８０：放熱フィン、３００：ＬＧＡ半導体実装構造、３１０：基板、３１１：上表面、３１２：下表面、３１３：金属パッド、３１４：スロット、３２０：チップ、３２１：ボンディングパッド、３２２：能動面、３３０：半田接合層、３３１：第一厚さ、３４０：フートスタンド、３４１：第二厚さ、３５０：封止体、３６０：ボンディングワイヤ、４１０：ＰＣＢ、４１１：ボールパッド、４２０：半田ボール、５００：ＬＧＡ半導体実装構造、５１０：基板、５１１：上表面、５１２：下表面、５１３：金属パッド、５１４：スロット、５２０：チップ、５２１：ボンディングパッド、５２２：能動面、５３０：フートスタンド、５４０：封止体、５５０：ボンディングワイヤ、６００：ＬＧＡ半導体実装構造、６１０：基板、６１１：上表面、６１２：下表面、６１３：金属パッド、６１４：結合孔、６１５：結合孔、６２０：チップ、６２１：表面、６３１：中央フートスタンド、６３２：側辺フートスタンド、６４０：封止体、６５０：ボンディングワイヤ   20: mounting surface, 30: mounting surface, 200: LGA semiconductor mounting structure, 210: substrate, 211: upper surface, 212: lower surface, 213: metal pad, 214: through-hole, 220: chip, 230: solder joint layer 231: first thickness 240: foot stand 241: second thickness 250: sealing body 260: bump 270: passive element 271: third thickness 280: heat dissipation fin 300: LGA Semiconductor mounting structure, 310: substrate, 311: upper surface, 312: lower surface, 313: metal pad, 314: slot, 320: chip, 321: bonding pad, 322: active surface, 330: solder bonding layer, 331: first One thickness, 340: Foot stand, 341: Second thickness, 350: Sealed body, 360: Bonding wire, 410: PCB, 411: Ball pad, 420 Solder balls, 500: LGA semiconductor mounting structure, 510: substrate, 511: upper surface, 512: lower surface, 513: metal pad, 514: slot, 520: chip, 521: bonding pad, 522: active surface, 530: foot Stand, 540: Sealing body, 550: Bonding wire, 600: LGA semiconductor mounting structure, 610: Substrate, 611: Upper surface, 612: Lower surface, 613: Metal pad, 614: Bonding hole, 615: Bonding hole, 620 : Chip, 621: Surface, 631: Center foot stand, 632: Side foot stand, 640: Sealed body, 650: Bonding wire

Claims (8)

上表面と下表面とを有し、前記下表面にアレイ状に並ぶ複数の金属パッドを設置している基板と、
基板の上表面に設置されかつ金属パッド群に電気接続されているチップと、
金属パッド群上に配置されて基板の下表面にわずかに突出する第一厚さを有する半田接合層と、
基板の下方に設置されて基板の下表面に突出する第二厚さを有し、第二厚さは第一厚さよりも厚くなるフートスタンドと、
を備えることを特徴とするＬＧＡ半導体実装構造。 A substrate having an upper surface and a lower surface, and a plurality of metal pads arranged in an array on the lower surface;
A chip installed on the upper surface of the substrate and electrically connected to a metal pad group;
A solder bonding layer disposed on the metal pad group and having a first thickness slightly protruding from the lower surface of the substrate;
A foot stand installed below the substrate and projecting to the lower surface of the substrate, the second thickness being thicker than the first thickness;
An LGA semiconductor mounting structure comprising: 封止体を有し、前記封止体は基板の上表面に形成されて少なくともチップの一部を密封していることを特徴とする請求項1に記載のＬＧＡ半導体実装構造。   2. The LGA semiconductor mounting structure according to claim 1, further comprising a sealing body, wherein the sealing body is formed on an upper surface of the substrate and seals at least a part of the chip. 前記フートスタンドは封止体と一体に連結されていることを特徴とする請求項２に記載のＬＧＡ半導体実装構造。   The LGA semiconductor mounting structure according to claim 2, wherein the foot stand is integrally connected to the sealing body. 前記フートスタンドは複数の支持ブロックから成って基板の下表面の角や周縁部に位置することを特徴とする請求項１に記載のＬＧＡ半導体実装構造。   2. The LGA semiconductor mounting structure according to claim 1, wherein the foot stand includes a plurality of support blocks and is positioned at a corner or a peripheral portion of a lower surface of the substrate. 前記フートスタンドは細長い形状の誘電物であり基板の中心線に位置することを特徴とする請求項１に記載のＬＧＡ半導体実装構造。   2. The LGA semiconductor mounting structure according to claim 1, wherein the foot stand is a long and narrow dielectric and is located at the center line of the substrate. 複数の受動素子を有し、前記受動素子は基板の下表面に設置されて基板の下表面に突出する第三厚さを有し、第二厚さも第三厚さよりも厚いことを特徴とする請求項１に記載のＬＧＡ半導体実装構造。   A plurality of passive elements, wherein the passive elements are disposed on the lower surface of the substrate and have a third thickness protruding from the lower surface of the substrate, wherein the second thickness is greater than the third thickness; The LGA semiconductor mounting structure according to claim 1. 放熱フィンを有し、前記放熱フィンは基板の上表面に設置されることを特徴とする請求項１に記載のＬＧＡ半導体実装構造。   2. The LGA semiconductor mounting structure according to claim 1, further comprising a radiation fin, wherein the radiation fin is disposed on an upper surface of the substrate. 上表面と下表面とを有し、前記下表面にアレイ状に並ぶ複数の金属パッドを設置している基板と、
基板の上表面に設置されかつ金属パッド群と電気接続しているチップと、
基板の下方に設置されて基板の下表面に突出する厚さを有する少なくとも一つのフートスタンドと、
を備えることを特徴とするＬＧＡ半導体実装構造。 A substrate having an upper surface and a lower surface, and a plurality of metal pads arranged in an array on the lower surface;
A chip installed on the upper surface of the substrate and electrically connected to the metal pad group;
At least one foot stand installed below the substrate and having a thickness protruding from the lower surface of the substrate;
An LGA semiconductor mounting structure comprising:
JP2007121795A 2007-05-02 2007-05-02 Lga semiconductor mounting structure Pending JP2008277660A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9049789B2 (en) 2012-03-28 2015-06-02 Fujitsu Limited Mounting adapter, printed board, and manufacturing method thereof
JP2015523742A (en) * 2012-08-02 2015-08-13 テッセラ，インコーポレイテッド Multiple die face down stacking on two or more dies

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000022046A (en) * 1998-07-02 2000-01-21 Sony Corp Semiconductor device and manufacture thereof
JP2001024097A (en) * 1999-07-05 2001-01-26 Kyokutoku Kagi Kofun Yugenkoshi Chip package substrate structure and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000022046A (en) * 1998-07-02 2000-01-21 Sony Corp Semiconductor device and manufacture thereof
JP2001024097A (en) * 1999-07-05 2001-01-26 Kyokutoku Kagi Kofun Yugenkoshi Chip package substrate structure and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9049789B2 (en) 2012-03-28 2015-06-02 Fujitsu Limited Mounting adapter, printed board, and manufacturing method thereof
JP2015523742A (en) * 2012-08-02 2015-08-13 テッセラ，インコーポレイテッド Multiple die face down stacking on two or more dies

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