JP2008270689A - GaN-BASED LIGHT EMITTING DIODE ELEMENT AND MANUFACTURING METHOD THEREOF - Google Patents

GaN-BASED LIGHT EMITTING DIODE ELEMENT AND MANUFACTURING METHOD THEREOF Download PDF

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JP2008270689A
JP2008270689A JP2007115334A JP2007115334A JP2008270689A JP 2008270689 A JP2008270689 A JP 2008270689A JP 2007115334 A JP2007115334 A JP 2007115334A JP 2007115334 A JP2007115334 A JP 2007115334A JP 2008270689 A JP2008270689 A JP 2008270689A
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substrate
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Hiromitsu Kudo
広光 工藤
Teruhisa Nakai
輝久 中井
Hiroaki Okagawa
広明 岡川
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Mitsubishi Chemical Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a GaN-based light emitting diode element constituted by forming an LED structure comprising a GaN-based semiconductor on a surface of a semiconductor, while forming irregularities desirable for the purpose of improving light extraction efficiency on the surface of the substrate. <P>SOLUTION: The GaN-based light emitting diode element 10 includes the substrate 11 and the GaN-based semiconductor 12. A region 11A in which the irregularities capable of scattering the light are formed is partially provided to the surface of the substrate 11. The GaN-based semiconductor 12 includes a GaN system semiconductor crystal film which has laterally grown from a region 11B where no irregularity is formed on the surface of the substrate 11 to the region 11A where the irregularities are formed. In a desirable manufacturing method, a part of the surface of the substrate having a mirror-polished surface is etched to form the irregularities capable of scattering the light, and the GaN-based semiconductor crystal film is laterally grown from the region where no irregularity is formed to the region where the irregularities are formed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、化学式ＡｌａＩｎｂＧａ１−ａ−ｂＮ（０≦ａ≦１、０≦ｂ≦１、０≦ａ＋ｂ≦１）で表されるＧａＮ系半導体を用いて発光ダイオード構造（以下、「ＬＥＤ構造」ともいう。）を形成してなるＧａＮ系発光ダイオード素子と、その製造方法に関し、とりわけ、光を散乱可能な凹凸を表面に形成した基板の上にＧａＮ系半導体からなるＬＥＤ構造を形成してなるＧａＮ系発光ダイオード素子と、その製造方法に関する。 The present invention uses a GaN-based semiconductor represented by the chemical formula Al a In b Ga 1-ab N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1) to form a light emitting diode structure (hereinafter referred to as “light emitting diode structure”). In particular, an LED structure made of a GaN-based semiconductor on a substrate having irregularities capable of scattering light formed on a surface thereof. The present invention relates to a GaN-based light-emitting diode element formed by forming and a manufacturing method thereof.

ＧａＮ系発光ダイオード素子において、基板の表面に光を散乱させるための凹凸を形成して、光の取出し効率を向上させることが行われている（特許文献１〜３）。凹凸形成の一方法として、加工しようとする基板の表面上に微細な粒子状物をランダムに堆積し、この粒子状物をマスク（ランダムエッチングマスク）として用いて該表面をエッチング処理する方法がある。かかるエッチング処理の一形態として、ドライエッチング装置を用いて、エッチングとデポジションが同時に生じるようにして行う基板表面のエッチング処理が知られている（特許文献１）。
特開２００６−１００５１８号公報 特開２００３−２１８３８３号公報 特開２００５−３５４０２０号公報 In a GaN-based light emitting diode element, it has been practiced to improve the light extraction efficiency by forming irregularities for scattering light on the surface of a substrate (Patent Documents 1 to 3). As a method for forming irregularities, there is a method in which fine particulate matter is randomly deposited on the surface of a substrate to be processed, and the surface is etched using the particulate matter as a mask (random etching mask). . As one form of such an etching process, there is known an etching process for a substrate surface that is performed using a dry etching apparatus so that etching and deposition occur simultaneously (Patent Document 1).
JP 2006-100518 A JP 2003-218383 A JP 2005-354020 A

発光ダイオード素子の光取出し効率の向上という観点から、基板の表面に形成する凹凸には、（イ）ＬＥＤ構造を構成する層状のＧａＮ系半導体の層方向に平行な平坦面部分を有さないこと、また、（ロ）形状の周期性が低いこと、が望まれる。ランダムエッチングマスクを用いたエッチング処理によれば、かかる性質を備えた凹凸を好ましく形成することができる。しかしながら、かかる凹凸を形成した基板の表面上には、エピタキシャル成長によってＧａＮ系半導体の単結晶層を形成することが難しいという問題、つまり、ＬＥＤ構造を形成することが難しいという問題がある。 From the viewpoint of improving the light extraction efficiency of the light-emitting diode element, the unevenness formed on the surface of the substrate should not have a flat surface portion parallel to the layer direction of the layered GaN-based semiconductor constituting the LED structure. In addition, (b) it is desired that the periodicity of the shape is low. According to the etching process using a random etching mask, it is possible to preferably form irregularities having such properties. However, there is a problem that it is difficult to form a single crystal layer of a GaN-based semiconductor by epitaxial growth on the surface of the substrate having such irregularities, that is, it is difficult to form an LED structure.

本発明はかかる事情に鑑みなされたものであり、その主な目的は、光取出し効率の向上のうえで好ましい凹凸を基板表面に形成しつつ、該基板表面上にＧａＮ系半導体からなるＬＥＤ構造を形成してなる、ＧａＮ系発光ダイオード素子を提供することである。本発明は、また、かかるＧａＮ系発光ダイオード素子の好ましい製造方法を提供することを、ひとつの目的とする。 The present invention has been made in view of such circumstances, and its main object is to form an LED structure made of a GaN-based semiconductor on the substrate surface while forming preferable irregularities on the substrate surface in order to improve light extraction efficiency. It is an object to provide a GaN-based light emitting diode element formed. Another object of the present invention is to provide a preferred method for producing such a GaN-based light emitting diode element.

上記目的を達成するための好適な手段として、次の発明を開示する。
（１）基板と、該基板上に形成されたＧａＮ系半導体とを有し、前記基板の表面には光を散乱可能な凹凸が形成された領域が部分的に設けられており、前記ＧａＮ系半導体は、前記基板の表面の前記凹凸が形成されていない領域上から前記凹凸が形成された領域上にラテラル成長したＧａＮ系半導体結晶膜を含んでいる、ＧａＮ系発光ダイオード素子。
（２）前記凹凸がランダムエッチングマスクを用いたエッチング処理によって形成された凹凸である、前記（１）に記載のＧａＮ系発光ダイオード素子。
（３）前記凹凸に含まれる凸部が錐体状である、前記（１）または（２）に記載のＧａＮ系発光ダイオード素子。
（４）前記凹凸の高低差が０．１μｍ〜３μｍである前記（１）〜（３）のいずれかに記載のＧａＮ系発光ダイオード素子。
（５）鏡面研磨された表面を有する基板の前記表面の一部をエッチング処理して光を散乱可能な凹凸を形成する工程と、ＧａＮ系半導体結晶膜を前記基板の表面の前記凹凸が形成されていない領域上から前記凹凸が形成された領域上にラテラル成長させる工程と、を有するＧａＮ系発光ダイオード素子の製造方法。
（６）前記エッチング処理が、ランダムエッチングマスクを用いたエッチング処理である、前記（５）に記載の製造方法。
（７）前記エッチング処理が、ドライエッチング装置を用いてエッチングとデポジションが同時に生じるように行うエッチング処理である、前記（６）に記載の製造方法。
（８）前記凹凸に含まれる凸部が錐体状である、前記（５）〜（７）のいずれかに記載の製造方法。
（９）前記凹凸の高低差が０．１μｍ〜３μｍである前記（５）〜（８）のいずれかに記載の製造方法。 The following invention is disclosed as a suitable means for achieving the above object.
(1) It has a substrate and a GaN-based semiconductor formed on the substrate, and the surface of the substrate is partially provided with a region on which irregularities capable of scattering light are formed, the GaN-based semiconductor The semiconductor includes a GaN-based light-emitting diode element, wherein the semiconductor includes a GaN-based semiconductor crystal film laterally grown on a region where the unevenness is formed from a region where the unevenness is not formed on the surface of the substrate.
(2) The GaN-based light-emitting diode element according to (1), wherein the unevenness is an unevenness formed by an etching process using a random etching mask.
(3) The GaN-based light-emitting diode element according to (1) or (2), wherein the convex portions included in the concave and convex portions have a cone shape.
(4) The GaN-based light-emitting diode element according to any one of (1) to (3), wherein the height difference of the unevenness is 0.1 μm to 3 μm.
(5) a step of etching a part of the surface of the substrate having a mirror-polished surface to form unevenness capable of scattering light; and a GaN-based semiconductor crystal film is formed with the unevenness on the surface of the substrate. And a step of laterally growing on the region where the projections and depressions are formed from a region that is not formed, a method for manufacturing a GaN-based light-emitting diode element.
(6) The manufacturing method according to (5), wherein the etching process is an etching process using a random etching mask.
(7) The manufacturing method according to (6), wherein the etching process is an etching process performed using a dry etching apparatus so that etching and deposition occur simultaneously.
(8) The manufacturing method in any one of said (5)-(7) whose convex part contained in the said unevenness is a cone shape.
(9) The manufacturing method according to any one of (5) to (8), wherein a height difference of the unevenness is 0.1 μm to 3 μm.

本発明の実施形態に係るＧａＮ系発光ダイオード素子は、光取出し効率の向上のうえで好ましい凹凸を基板表面に有し、該基板表面上にＧａＮ系半導体からなるＬＥＤ構造を形成したものであるため、高い発光効率を示し、照明用途や表示用途をはじめとする、高出力が要求される各種の用途に、好適に用いることができる。 The GaN-based light-emitting diode device according to the embodiment of the present invention has preferable irregularities on the substrate surface for improving light extraction efficiency, and an LED structure made of a GaN-based semiconductor is formed on the substrate surface. It exhibits high luminous efficiency and can be suitably used for various applications that require high output, including lighting applications and display applications.

本発明の実施形態に係るＧａＮ系発光ダイオード素子の製造方法によれば、光取出し効率の向上のうえで好ましい凹凸を基板表面に有し、該基板表面上にＧａＮ系半導体からなるＬＥＤ構造が形成されたＧａＮ系発光ダイオード素子を、容易に製造することができる。 According to the method for manufacturing a GaN-based light-emitting diode element according to the embodiment of the present invention, the substrate surface has preferable irregularities for improving light extraction efficiency, and an LED structure made of a GaN-based semiconductor is formed on the substrate surface. The manufactured GaN-based light emitting diode element can be easily manufactured.

本発明の好適な一実施形態に係るＧａＮ系発光ダイオード素子は、基板と、該基板上に形成されたＧａＮ系半導体とを有し、前記基板の表面には光を散乱可能な凹凸が形成された領域が部分的に設けられており、前記ＧａＮ系半導体は、前記基板の表面の前記凹凸が形成されていない領域上から前記凹凸が形成された領域上にラテラル成長したＧａＮ系半導体結晶膜を含んでいる。図１は、このように構成されたＧａＮ系発光ダイオード素子の構造例を示す断面図である。図１に示すＧａＮ発光ダイオード素子１０は、基板１１と、該基板上に形成されたＧａＮ系半導体１２とを有している。基板１１の、ＧａＮ系半導体１２が形成された側の表面は、光を散乱可能な凹凸が形成された領域である第１領域１１Ａと、鏡面状の平坦領域である第２領域１１Ｂとを有している。ＧａＮ系半導体１２は、基板１１側に設けられた基層部１２１と、その上に設けられたＬＥＤ構造形成部１２２とを有している。基層部１２１は、基板１１の表面を完全に覆っており、その上面は平坦面となっている。基層部１２１は、その一部に、基板表面の第２領域１１Ｂ上から第１領域１１Ａ上にラテラル成長したＧａＮ系半導体結晶膜を含んでいる。ＬＥＤ構造形成部１２２は、基層部１２１側から順に、第１導電型層１２２１と第２導電型層１２２２とを有している。第１導電型層１２２１と第２導電型層１２２２により、キャリア注入により発光し得るｐｎ接合が形成されている。第１導電型層１２２１には下部電極１３が形成され、第２導電型層１２２２には上部電極１４が形成されている。 A GaN-based light-emitting diode element according to a preferred embodiment of the present invention includes a substrate and a GaN-based semiconductor formed on the substrate, and unevenness capable of scattering light is formed on the surface of the substrate. The GaN-based semiconductor is formed by laterally growing a GaN-based semiconductor crystal film on a region where the irregularities are formed from a region where the irregularities are not formed on the surface of the substrate. Contains. FIG. 1 is a cross-sectional view showing a structural example of a GaN-based light emitting diode element configured as described above. A GaN light-emitting diode element 10 shown in FIG. 1 has a substrate 11 and a GaN-based semiconductor 12 formed on the substrate. The surface of the substrate 11 on the side where the GaN-based semiconductor 12 is formed has a first region 11A, which is a region where irregularities capable of scattering light are formed, and a second region 11B, which is a mirror-like flat region. is doing. The GaN-based semiconductor 12 has a base layer part 121 provided on the substrate 11 side and an LED structure forming part 122 provided thereon. The base layer portion 121 completely covers the surface of the substrate 11, and the upper surface thereof is a flat surface. The base layer portion 121 includes, in part, a GaN-based semiconductor crystal film that is laterally grown from the second region 11B on the substrate surface to the first region 11A. The LED structure forming part 122 includes a first conductivity type layer 1221 and a second conductivity type layer 1222 in order from the base layer part 121 side. The first conductivity type layer 1221 and the second conductivity type layer 1222 form a pn junction that can emit light by carrier injection. A lower electrode 13 is formed on the first conductivity type layer 1221, and an upper electrode 14 is formed on the second conductivity type layer 1222.

ＧａＮ系発光ダイオード素子１０の各部の好ましい構成を説明する。 A preferred configuration of each part of the GaN-based light emitting diode element 10 will be described.

（基板）
基板１１は、ＧａＮ系半導体結晶のエピタキシャル成長に用い得る基板であればよく、サファイア、ＳｉＣ、ＧａＮ、ＡｌＧａＮ、ＡｌＮ、Ｓｉ、ＧａＡｓ、ＧａＰ、スピネル、ＺｎＯ、ＮＧＯ（ＮｄＧａＯ３）、ＬＧＯ（ＬｉＧａＯ２）、ＬＡＯ（ＬａＡｌＯ３）、ＺｒＢ２、ＴｉＢ２などの材料からなる単結晶基板を好ましく用いることができる。これらの材料からなる単結晶層を、結晶成長面側に表層として有するテンプレート（多層構造の基板）であってもよい。単結晶基板であってもテンプレートであっても、基板１１は、当該素子から放出される光に対して透過性を有するものであることが好ましい。 (substrate)
The substrate 11 may be any substrate that can be used for epitaxial growth of GaN-based semiconductor crystals. Sapphire, SiC, GaN, AlGaN, AlN, Si, GaAs, GaP, spinel, ZnO, NGO (NdGaO 3 ), LGO (LiGaO 2 ) A single crystal substrate made of a material such as LAO (LaAlO 3 ), ZrB 2 , or TiB 2 can be preferably used. A template (a substrate having a multilayer structure) having a single crystal layer made of these materials as a surface layer on the crystal growth surface side may be used. Whether it is a single crystal substrate or a template, the substrate 11 is preferably transparent to light emitted from the element.

基板表面の第１領域１１Ａの凹凸は、好ましくは、ランダムエッチングマスクを用いたエッチング処理により形成される凹凸である。即ち、基板の表面に微細な粒子状物をランダムに堆積し、この粒子状物をマスクとして用いて、該表面をエッチング処理することによって形成される凹凸である。このようにして形成される凹凸は形状の周期性が低くなるために、強い光散乱作用を示す。更に、この凹凸に含まれる凸部を錐体状とすると、該凹凸による光散乱作用を特に強くすることができる。これは、凹凸に含まれる、層状のＧａＮ系半導体１２の層方向に平行な平坦面が少なくなるからである。第１領域１１Ａにおける凹凸の高低差（凹部の底から見た凸部の頂の高さ）は、例えば、０．０５μｍ〜５μｍとすることができるが、好ましくは０．１μｍ〜３μｍであり、より好ましくは０．３μｍ〜１μｍである。凹凸の高低差が光の波長と比べて小さ過ぎると、光波と凹凸の相互作用が小さくなるため光散乱効果が弱くなる。凹凸の高低差を大きくし過ぎたときには、凸部と凹部の分布密度が低くなるために、光散乱効果が弱くなる。 The unevenness of the first region 11A on the substrate surface is preferably an unevenness formed by an etching process using a random etching mask. That is, the unevenness is formed by randomly depositing fine particulate matter on the surface of the substrate and etching the surface using the particulate matter as a mask. The unevenness formed in this way exhibits a strong light scattering action because the periodicity of the shape is low. Furthermore, if the convex portions included in the concaves and convexes are conical, the light scattering action by the concaves and convexes can be particularly strengthened. This is because the flat surface parallel to the layer direction of the layered GaN-based semiconductor 12 included in the unevenness is reduced. The height difference of the unevenness in the first region 11A (the height of the top of the convex portion viewed from the bottom of the concave portion) can be, for example, 0.05 μm to 5 μm, preferably 0.1 μm to 3 μm, More preferably, it is 0.3 μm to 1 μm. If the height difference of the unevenness is too small compared to the wavelength of light, the light scattering effect is weakened because the interaction between the light wave and the unevenness is reduced. When the height difference of the unevenness is excessively increased, the light scattering effect is weakened because the distribution density of the protrusions and recesses is lowered.

基板１１の表面において第１領域１１Ａと第２領域１１Ｂとがなすパターンは、少なくともあるひとつの方向に沿って、第１領域１１Ａと第２領域１１Ｂとが交互に並ぶパターンとする。ひとつのパターンとして、第１領域と第２領域のそれぞれをストライプ状に形成し、平行かつ交互に並べたパターンが例示される。この場合、第２領域のストライプ幅は、例えば０．５μｍ〜２０μｍとすることができるが、好ましくは１μｍ〜１０μｍであり、より好ましくは２μｍ〜５μｍである。他のパターンとして、複数の孤立した島状の第１領域が、第２領域で隔てられたパターンや、その逆に、複数の孤立した島状の第２領域が、第１領域で隔てられたパターンが挙げられる。その他、複数の第１領域および第２領域を、あるひとつの点の周りを囲む環状に形成しつつ、交互に並べたパターンなどが例示される。いかなるパターンを採用する場合においても、基板の表面に占める第１領域１１Ａの面積比率は、好ましくは４０％〜９０％であり、より好ましくは５０％〜８５％であり、更に好ましくは６０％〜８０％である。第１領域１１Ａの面積比率が小さ過ぎると、該領域に形成された凹凸による光取出し効率の向上効果が十分に発揮されない。第１領域１１Ａの面積比率を大きくし過ぎると、換言すれば、基板１１とＧａＮ系半導体１２との接触面積（≒第２領域の面積）を小さくし過ぎると、熱応力によって基板１１とＧａＮ系半導体１２との間で剥離が発生する恐れがある。また、いかなるパターンを採用する場合においても、基板表面における第１領域１１Ａと第２領域１１Ｂとの境界の全てを、該基板上にエピタキシャル成長するＧａＮ系半導体単結晶のＡ面に平行な方向に形成することが好ましい。そのように構成すると、第１領域１１Ａ上から第２領域１１Ｂ上へのＧａＮ系半導体結晶のラテラル成長が速くなるので、第１領域の面積を大きく設定した場合でも、広い第１領域上をＧａＮ系半導体結晶で覆うことが容易となる。 The pattern formed by the first region 11A and the second region 11B on the surface of the substrate 11 is a pattern in which the first region 11A and the second region 11B are alternately arranged along at least one direction. As one pattern, a pattern in which each of the first region and the second region is formed in a stripe shape and arranged in parallel and alternately is exemplified. In this case, the stripe width of the second region can be, for example, 0.5 μm to 20 μm, preferably 1 μm to 10 μm, more preferably 2 μm to 5 μm. As another pattern, a plurality of isolated island-like first regions are separated by the second region, and conversely, a plurality of isolated island-like second regions are separated by the first region. Patterns. In addition, a pattern in which a plurality of first regions and second regions are formed in an annular shape surrounding a certain point and the like are exemplified. In any case, the area ratio of the first region 11A in the surface of the substrate is preferably 40% to 90%, more preferably 50% to 85%, and still more preferably 60% to 80%. When the area ratio of the first region 11A is too small, the effect of improving the light extraction efficiency due to the unevenness formed in the region is not sufficiently exhibited. If the area ratio of the first region 11A is too large, in other words, if the contact area between the substrate 11 and the GaN-based semiconductor 12 (≈the area of the second region) is too small, the substrate 11 and the GaN-based material due to thermal stress. There is a possibility that peeling occurs with the semiconductor 12. In any case, any boundary between the first region 11A and the second region 11B on the substrate surface is formed in a direction parallel to the A plane of the GaN-based semiconductor single crystal epitaxially grown on the substrate. It is preferable to do. With such a configuration, since the lateral growth of the GaN-based semiconductor crystal from the first region 11A to the second region 11B is accelerated, even when the area of the first region is set large, the GaN-based semiconductor crystal is grown on the wide first region. It becomes easy to cover with a system semiconductor crystal.

（基層部）
ＧａＮ系半導体１２の基層部１２１は、ＬＥＤ構造にとって必須の構成要素ではないが、この層を設けることで、その上に形成するＬＥＤ構造形成部１２２の結晶品質を改善し、ひいては、発光効率（内部量子効率）を改善することができる。そのためには、この基層部１２１は、厚さを１μｍ以上とすることが好ましく、２μｍ以上とすることがより好ましく、３μｍ以上とすることが更に好ましい。また、基層部１２１の結晶性を良好なものとするには、基板１１と基層部１２１との間にはバッファ層を介在させることが好ましく、更に、基層部１２１に不純物の添加を行わないことが好ましい。ただし、Ｍｇ（マグネシウム）の添加はＧａＮ系半導体結晶のラテラル成長を促進させる効果があるため、基板１１の表面の第１領域１１Ａの面積を大きく設定する場合には、基層部１２１の成長初期にＭｇを添加すると、広い第１領域上を覆って基層部１２１を形成することが容易となる。基板１１の第１領域１１Ａ上にラテラル成長したＧａＮ系半導体結晶膜は転移欠陥密度の低いものとなるので、その上に成長するＧａＮ系半導体結晶は特に高品質なものとなる。基層部１２１を構成するＧａＮ系半導体結晶の組成に限定はないが、ＬＥＤ構造形成部１２２の結晶性を高める目的からは、基層部１２１は数μｍ以上の膜厚を有するＧａＮ（窒化ガリウム）層を含むことが好ましい。その場合、基層部１２１はＧａＮ層のみからなるものであってもよい。また、基板１１と基層部１２１との界面で格子不整合に起因して発生する貫通転移が、基層部１２１内を上方に伝播するのを抑制するために、基層部１２１内に歪超格子構造を設けてもよい。 (Base layer)
The base layer portion 121 of the GaN-based semiconductor 12 is not an essential component for the LED structure, but by providing this layer, the crystal quality of the LED structure forming portion 122 formed thereon is improved, and as a result, the luminous efficiency ( (Internal quantum efficiency) can be improved. For this purpose, the thickness of the base layer portion 121 is preferably 1 μm or more, more preferably 2 μm or more, and further preferably 3 μm or more. In order to improve the crystallinity of the base layer portion 121, it is preferable to interpose a buffer layer between the substrate 11 and the base layer portion 121, and further, no impurity should be added to the base layer portion 121. Is preferred. However, since the addition of Mg (magnesium) has an effect of promoting lateral growth of the GaN-based semiconductor crystal, when the area of the first region 11A on the surface of the substrate 11 is set to be large, the base layer portion 121 is initially grown. When Mg is added, it becomes easy to form the base layer portion 121 covering the wide first region. Since the GaN-based semiconductor crystal film laterally grown on the first region 11A of the substrate 11 has a low transition defect density, the GaN-based semiconductor crystal grown thereon has a particularly high quality. The composition of the GaN-based semiconductor crystal constituting the base layer part 121 is not limited, but for the purpose of improving the crystallinity of the LED structure forming part 122, the base layer part 121 is a GaN (gallium nitride) layer having a thickness of several μm or more. It is preferable to contain. In that case, the base layer portion 121 may be composed only of the GaN layer. In addition, a strained superlattice structure is formed in the base layer portion 121 in order to suppress the penetration transition caused by lattice mismatch at the interface between the substrate 11 and the base layer portion 121 from propagating upward in the base layer portion 121. May be provided.

（ＬＥＤ構造形成部）
ＬＥＤ構造形成部１２２を構成する第１導電型層１２２１と第２導電型層は、いずれか一方がｎ型半導体を含む層であり、他方がｐ型半導体を含む層であればよい。好ましくは、先に成長させる第１導電型層１２２１を、ｎ型半導体を用いて形成する。第１導電型層１２２１と第２導電型層１２２２との接合部分に活性層を設けてダブルヘテロ構造を構成すると、発光効率が飛躍的に向上する。活性層は、好ましくは多重量子井戸構造とする。 (LED structure forming part)
Any one of the first conductivity type layer 1221 and the second conductivity type layer constituting the LED structure forming portion 122 may be a layer including an n-type semiconductor and the other including a p-type semiconductor. Preferably, the first conductivity type layer 1221 to be grown first is formed using an n-type semiconductor. When an active layer is provided at the junction between the first conductivity type layer 1221 and the second conductivity type layer 1222 to form a double heterostructure, the light emission efficiency is dramatically improved. The active layer preferably has a multiple quantum well structure.

（電極その他）
第１導電型層１２２１に形成する下部電極１３、第２導電型層１２２２に形成する上部電極１４の、材料、構造などについては、公知技術を適宜参照することができる。具体例を挙げると、ｎ型ＧａＮ系半導体の表面に形成する電極は、Ｔｉ（チタン）、Ａｌ（アルミニウム）、Ｗ（タングステン）、Ｖ（バナジウム）、Ｃｒ（クロム）などの単体、または、これらから選ばれる１種以上の金属を含む合金を用いて形成することができる。また、ｐ型ＧａＮ系半導体の表面に形成する電極は、Ｎｉ（ニッケル）、Ｃｏ（コバルト）、白金族（Ｐｔ、Ｐｄ、Ｒｈ、Ｉｒ、Ｏｓ、Ｒｕ）、Ａｕ（金）などの単体、または、これらから選ばれる１種以上の金属を含む合金を用いて形成することができる。酸化インジウム、酸化錫、酸化亜鉛、酸化ガリウム、ＩＴＯ（インジウム錫酸化物）、ＩＺＯ（インジウム亜鉛酸化物）、ＡＺＯ（アルミニウム亜鉛酸化物）、ＦＴＯ（フッ素ドープ酸化錫）などの導電性酸化物は、ｎ型ＧａＮ系半導体とｐ型ＧａＮ系半導体のいずれの表面に形成する電極にも使用できる。また、下部電極１３および上部電極１４のそれぞれには、外部電極との接続が容易となるように、表層としてＡｇ（銀）、Ａｕ（金）、Ｓｎ（錫）、Ｉｎ（インジウム）、Ｂｉ（ビスマス）、Ｃｕ（銅）、Ｚｎ（亜鉛）などからなる層を設けることが好ましい。上部電極１４を、第２導電型層１２２２の上面を略全面的に覆う全面電極と、該全面電極の一部上に形成されるパッド電極とから構成してもよいが、その場合には、パッド電極に上記材料からなる表層を設ければよい。下部電極１３および上部電極１４と、外部電極との接続は、Ａｕなどからなるボンディングワイヤを用いて行うこともできるし、ハンダ、共晶合金、導電ペーストなどの導電性接合材料を用いて行うこともできる。好ましい実施形態では、上部電極１４を、導電性酸化物からなる透光性の全面電極と、その一部上に形成されるパッド電極とから構成したうえ、発光ダイオード素子１０をフリップチップ実装する。フリップチップ実装では、一般的に、導電性接合材料を用いて下部電極１３および上部電極１４を外部電極に接続する。 (Electrodes and others)
For the material, structure, and the like of the lower electrode 13 formed on the first conductivity type layer 1221 and the upper electrode 14 formed on the second conductivity type layer 1222, well-known techniques can be referred to as appropriate. Specifically, the electrodes formed on the surface of the n-type GaN-based semiconductor are simple substances such as Ti (titanium), Al (aluminum), W (tungsten), V (vanadium), and Cr (chromium), or these It can form using the alloy containing 1 or more types of metals chosen from these. In addition, the electrode formed on the surface of the p-type GaN-based semiconductor may be a single substance such as Ni (nickel), Co (cobalt), platinum group (Pt, Pd, Rh, Ir, Os, Ru), Au (gold), or , And an alloy containing one or more metals selected from these. Conductive oxides such as indium oxide, tin oxide, zinc oxide, gallium oxide, ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum zinc oxide), FTO (fluorine-doped tin oxide) It can also be used as an electrode formed on any surface of an n-type GaN-based semiconductor and a p-type GaN-based semiconductor. Each of the lower electrode 13 and the upper electrode 14 has a surface layer of Ag (silver), Au (gold), Sn (tin), In (indium), Bi (so that it can be easily connected to an external electrode. It is preferable to provide a layer made of bismuth), Cu (copper), Zn (zinc), or the like. The upper electrode 14 may be composed of a full-surface electrode that covers substantially the entire upper surface of the second conductivity type layer 1222 and a pad electrode formed on a part of the full-surface electrode. What is necessary is just to provide the surface layer which consists of the said material in a pad electrode. The connection between the lower electrode 13 and the upper electrode 14 and the external electrode can be performed using a bonding wire made of Au or the like, or using a conductive bonding material such as solder, a eutectic alloy, or a conductive paste. You can also. In a preferred embodiment, the upper electrode 14 is composed of a light-transmitting full-surface electrode made of a conductive oxide and a pad electrode formed on a part thereof, and the light-emitting diode element 10 is flip-chip mounted. In flip-chip mounting, the lower electrode 13 and the upper electrode 14 are generally connected to an external electrode using a conductive bonding material.

次に、図１に示すＧａＮ系発光ダイオード素子の製造方法の一例について説明する。 Next, an example of a manufacturing method of the GaN-based light emitting diode element shown in FIG. 1 will be described.

（基板の加工）
鏡面研磨された結晶成長面を有する、直径２インチのＣ面サファイア基板（片面研磨基板）を準備し、その結晶成長面側の表面に、フォトレジスト膜を、ライン幅２．５μｍ、スペース幅５μｍのライン・アンド・スペース・パターンに形成する。ライン方向（ストライプ状にパターニングするフォトレジスト膜の長手方向）は、サファイアの＜１１−２０＞方向とする。この方向は、Ｃ面サファイア基板上にエピタキシャル成長するＧａＮ系半導体結晶（Ｃ軸配向結晶）のＡ面に平行である。次に、この基板を反応性イオンエッチング装置のエッチングチャンバ内に装填し、基板の結晶成長面の、フォトレジスト膜で保護されていない部分を、エッチングとデポジションが同時に生じる条件を用いてエッチング処理する。より具体的には、エッチングガスとしてトリフルオロメタンを用い、チャンバ内圧力を１．５〜６．０Ｐａとし、ＩＣＰ（誘導結合プラズマ）電力を１５０〜６００Ｗとし、バイアス電圧を３００Ｗ〜５００Ｗとする。エッチング時間は１５分〜４０分とする。この処理によって、サファイア基板表面（フォトレジスト膜で保護していない部分）に、高さが０．３μｍ〜０．５μｍの円錐状凸部を１個／μｍ２〜７０個／μｍ２の密度で有する凹凸を形成することができる。凹凸の形状やサイズは、ＩＣＰ電力、バイアス電圧、チャンバ内圧力、エッチング時間を変化させることにより、変更することができる。処理後、基板を反応性イオンエッチング装置から取り出し、フォトレジスト膜を除去するとともに、有機洗浄を行う。 (Board processing)
A C-plane sapphire substrate (single-side polished substrate) having a mirror-polished crystal growth surface and having a diameter of 2 inches is prepared. To form a line and space pattern. The line direction (longitudinal direction of the photoresist film patterned in a stripe shape) is the <11-20> direction of sapphire. This direction is parallel to the A plane of the GaN-based semiconductor crystal (C-axis oriented crystal) that is epitaxially grown on the C-plane sapphire substrate. Next, this substrate is loaded into the etching chamber of a reactive ion etching apparatus, and the portion of the crystal growth surface of the substrate that is not protected by the photoresist film is etched using conditions that cause etching and deposition simultaneously. To do. More specifically, trifluoromethane is used as the etching gas, the pressure in the chamber is 1.5 to 6.0 Pa, the ICP (inductively coupled plasma) power is 150 to 600 W, and the bias voltage is 300 W to 500 W. The etching time is 15 minutes to 40 minutes. By this treatment, conical convex portions having a height of 0.3 μm to 0.5 μm are formed on the surface of the sapphire substrate (the portion not protected by the photoresist film) at a density of 1 piece / μm 2 to 70 pieces / μm 2 . The unevenness can be formed. The shape and size of the unevenness can be changed by changing the ICP power, the bias voltage, the pressure in the chamber, and the etching time. After the treatment, the substrate is taken out from the reactive ion etching apparatus, the photoresist film is removed, and organic cleaning is performed.

（ＧａＮ系半導体の形成）
結晶成長面を部分的に加工して凹凸を形成した上記基板の上に、ＭＯＶＰＥ（有機金属化合物気相成長）法を用いて、ＬＥＤ構造を備えたＧａＮ系半導体を形成する。より具体的には、まず、ＭＯＶＰＥ装置内に装着した基板を、水素気流中１１００℃に加熱してクリーニング処理する。次に、基板温度を下げて５００℃〜６５０℃とし、ＴＭＧ（トリメチルガリウム）、ＴＭＡ（トリメチルアルミニウム）、アンモニアを原料に用いて、Ａｌ（アルミニウム）の組成比がＧａ（ガリウム）の組成比よりも大きいＡｌＧａＮバッファ層を、約３０ｎｍの厚さに形成する。バッファ層形成後、アンモニアを基板上に供給しながら基板温度を１０００℃に上げ、続いて、ＴＭＧとアンモニアを原料に用いて、ＧａＮを約４μｍの厚さに形成する。このとき、基板上に供給するＴＭＧとアンモニアの供給量の比率は、ＧａＮ結晶のラテラル成長速度が十分に大きくなる比率に調節する。また、原料のキャリアガスには、水素ガスと窒素ガスを用いる。図２に、このようにして形成されるＧａＮ結晶の成長の様子を模式的に示す。図２（ａ）は、ＧａＮ結晶を成長させる前のサファイア基板２１の断面図であり、前工程で用いたストライプ状にパターニングしたフォトレジスト膜の長手方向に直交する断面を示している。この断面を見ると、基板２１の結晶成長面には、凹凸が形成された第１領域２１Ａと、凹凸が形成されていない第２領域２１Ｂとが、交互に並んでいる。図２（ｂ）は成長初期の状態を示しており、ＧａＮ結晶２２が結晶成長面の第２領域上のみに形成されている（バッファ層の図示は省略している。図２（ｃ）（ｄ）も同じ。）。図２（ｃ）は成長を続けたところで、ＧａＮ結晶２２は、図２（ｂ）に示す状態から、更に縦方向およびラテラル方向に成長している。図２（ｄ）は図２（ｃ）の状態から更に成長を続けたところであり、ラテラル成長によって、隣接する２つの第２領域上から成長したＧａＮ結晶どうしがつながり、平坦な上面を有する層状のＧａＮ結晶２２がサファイア基板２１の結晶成長面全体を覆った状態が達成されている。 (Formation of GaN-based semiconductors)
A GaN-based semiconductor having an LED structure is formed on the substrate on which the crystal growth surface is partially processed to form irregularities by using the MOVPE (organometallic compound vapor phase epitaxy) method. More specifically, first, the substrate mounted in the MOVPE apparatus is cleaned by heating to 1100 ° C. in a hydrogen stream. Next, the substrate temperature is lowered to 500 ° C. to 650 ° C., TMG (trimethylgallium), TMA (trimethylaluminum), and ammonia are used as raw materials, and the composition ratio of Al (aluminum) is higher than the composition ratio of Ga (gallium). A larger AlGaN buffer layer is formed to a thickness of about 30 nm. After the buffer layer is formed, the substrate temperature is raised to 1000 ° C. while supplying ammonia onto the substrate, and then GaN is formed to a thickness of about 4 μm using TMG and ammonia as raw materials. At this time, the ratio of the supply amount of TMG and ammonia supplied onto the substrate is adjusted to a ratio at which the lateral growth rate of the GaN crystal is sufficiently increased. Further, hydrogen gas and nitrogen gas are used as the raw material carrier gas. FIG. 2 schematically shows how the GaN crystal thus formed grows. FIG. 2A is a cross-sectional view of the sapphire substrate 21 before the GaN crystal is grown, and shows a cross section orthogonal to the longitudinal direction of the photoresist film patterned in the stripe shape used in the previous step. Looking at this cross section, the first region 21A in which irregularities are formed and the second region 21B in which irregularities are not formed are alternately arranged on the crystal growth surface of the substrate 21. FIG. 2B shows the initial growth state, and the GaN crystal 22 is formed only on the second region of the crystal growth surface (the buffer layer is not shown. FIG. 2C). The same applies to d). In FIG. 2 (c), where the growth has continued, the GaN crystal 22 has further grown in the vertical and lateral directions from the state shown in FIG. 2 (b). FIG. 2D shows a state where the growth has further continued from the state of FIG. 2C, and the GaN crystals grown from the two adjacent second regions are connected by lateral growth, and a layered structure having a flat upper surface is obtained. A state in which the GaN crystal 22 covers the entire crystal growth surface of the sapphire substrate 21 is achieved.

上記のようにして成長させたアンドープＧａＮ層の上に、ＳｉドープＧａＮからなるｎ型コンタクト層、アンドープＧａＮ障壁層とアンドープＩｎＧａＮ井戸層とからなる多重量子井戸構造の活性層、ＭｇドープＡｌＧａＮからなるｐ型クラッド層、ＭｇドープＡｌＧａＮからなるｐ型コンタクト層を、順次形成して積層し、基板とＧａＮ系半導体からなるウェハを得る。 On the undoped GaN layer grown as described above, an n-type contact layer composed of Si-doped GaN, an active layer having a multiple quantum well structure composed of an undoped GaN barrier layer and an undoped InGaN well layer, and Mg-doped AlGaN A p-type cladding layer and a p-type contact layer made of Mg-doped AlGaN are sequentially formed and laminated to obtain a wafer made of a substrate and a GaN-based semiconductor.

（電極形成等）
上記ウェハに対して上部電極および下部電極を形成する。上部電極は、ＩＴＯ膜からなる全面電極と、その上の一部に形成したパッド電極とから構成する。下部電極は、ドライエッチングにより一部露出させたｎ型コンタクト層上に形成する。電極形成後、サファイア基板の下面（非研磨面）を研削および研磨して、基板の厚さを１００μｍまで減じたうえ、公知のスクライビング法を用いてウェハを分断し、チップ状の発光ダイオード素子を得る。 (Electrode formation, etc.)
An upper electrode and a lower electrode are formed on the wafer. The upper electrode is composed of a full-surface electrode made of an ITO film and a pad electrode formed on a part thereon. The lower electrode is formed on the n-type contact layer partially exposed by dry etching. After forming the electrode, the lower surface (non-polished surface) of the sapphire substrate is ground and polished to reduce the thickness of the substrate to 100 μm, and the wafer is divided using a known scribing method to obtain a chip-like light emitting diode element. obtain.

上記説明した製造方法では、基板表面に凹凸を形成するために、反応性イオンエッチング装置を用いて、エッチングとデポジションが同時に生じるように基板をエッチング処理しているが、この反応性イオンエッチング装置をプラズマエッチング装置に置き換えることも可能である。このような、ドライエッチング装置を用いてエッチングとデポジションが同時に生じるように基板をエッチング処理する方法では、エッチングガスおよび／または被加工物（基板）が、微細な粒子状のランダムエッチングマスクの原料となるものであるが、基板表面の凹凸加工の方法はこの方法に限定されるものではなく、ランダムエッチングマスクを予め形成したうえで、ドライエッチング処理する方法も採用可能である。その場合のランダムエッチングマスクの一例として、基板表面に蒸着法にてＡｕ薄膜（膜厚約５ｎｍ）を形成した後、基板温度を１８０℃程度に上昇させることにより薄膜をなしていたＡｕを凝集せしめて微粒子状としたものが挙げられる（特許文献３）。また、ランダムエッチングマスクは、粒子状物を堆積したものに限定されるものではなく、例えば、ブロックコポリマーを溶解した溶液を塗布してマスク材料層を形成した後、該マスク材料層をアニール処理して該ブロックコポリマーを相分離したものなどであってもよい（特許文献２）。これらのランダムエッチングマスクを用いる場合には、基板表面のうち、凹凸の形成を予定しない領域を保護膜で被覆したうえでランダムエッチングマスクの形成を行い、ドライエッチングによる加工を行う。この保護膜は、ランダムエッチングマスクを形成する工程およびその後のドライエッチング加工工程において、該保護膜で被覆した基板表面が変形して非鏡面となることを防止し得るものであればよい。 In the manufacturing method described above, in order to form irregularities on the substrate surface, a reactive ion etching apparatus is used to etch the substrate so that etching and deposition occur simultaneously. This reactive ion etching apparatus It is also possible to replace with a plasma etching apparatus. In such a method of etching a substrate so that etching and deposition occur at the same time using a dry etching apparatus, the etching gas and / or the workpiece (substrate) is a raw material for a random etching mask with fine particles. However, the method of processing the unevenness of the substrate surface is not limited to this method, and a method of dry etching treatment after forming a random etching mask in advance can also be adopted. As an example of a random etching mask in that case, after forming an Au thin film (film thickness of about 5 nm) on the substrate surface by vapor deposition, the substrate temperature is raised to about 180 ° C. to agglomerate the Au that had formed the thin film. And fine particles (Patent Document 3). In addition, the random etching mask is not limited to the one in which the particulate matter is deposited. For example, after the mask material layer is formed by applying a solution in which the block copolymer is dissolved, the mask material layer is annealed. The block copolymer may be phase-separated (Patent Document 2). In the case of using these random etching masks, a region of the substrate surface where the unevenness is not planned is covered with a protective film, the random etching mask is formed, and processing by dry etching is performed. The protective film may be any film that can prevent the surface of the substrate covered with the protective film from deforming into a non-mirror surface in the process of forming the random etching mask and the subsequent dry etching process.

本発明は上記に明示的に記載した実施形態に限定されるものではなく、発明の趣旨を逸脱しない範囲で種々の変形が可能である。 The present invention is not limited to the embodiments explicitly described above, and various modifications can be made without departing from the spirit of the invention.

本発明の実施形態に係るＧａＮ系発光ダイオード素子の構造を示す断面図である。It is sectional drawing which shows the structure of the GaN-type light emitting diode element which concerns on embodiment of this invention. 本発明の実施形態に係るＧａＮ系発光ダイオード素子の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the GaN-type light emitting diode element which concerns on embodiment of this invention.

符号の説明Explanation of symbols

１０ ＧａＮ系発光ダイオード素子
１１ 基板
１２ ＧａＮ系半導体
１３ 下部電極
１４ 上部電極 10 GaN-based light-emitting diode element 11 Substrate 12 GaN-based semiconductor 13 Lower electrode 14 Upper electrode

Claims (9)

基板と、該基板上に形成されたＧａＮ系半導体とを有し、
前記基板の表面には光を散乱可能な凹凸が形成された領域が部分的に設けられており、
前記ＧａＮ系半導体は、前記基板の表面の前記凹凸が形成されていない領域上から前記凹凸が形成された領域上にラテラル成長したＧａＮ系半導体結晶膜を含んでいる、
ＧａＮ系発光ダイオード素子。 A substrate and a GaN-based semiconductor formed on the substrate;
The surface of the substrate is partially provided with a region where unevenness capable of scattering light is formed,
The GaN-based semiconductor includes a GaN-based semiconductor crystal film laterally grown on a region where the irregularities are formed from a region where the irregularities are not formed on the surface of the substrate.
GaN-based light emitting diode element. 前記凹凸がランダムエッチングマスクを用いたエッチング処理によって形成された凹凸である、請求項１に記載のＧａＮ系発光ダイオード素子。 The GaN-based light emitting diode element according to claim 1, wherein the unevenness is an unevenness formed by an etching process using a random etching mask. 前記凹凸に含まれる凸部が錐体状である、請求項１または２に記載のＧａＮ系発光ダイオード素子。 The GaN-based light-emitting diode element according to claim 1, wherein the convex portion included in the concave and convex portions has a cone shape. 前記凹凸の高低差が０．１μｍ〜３μｍである請求項１〜３のいずれかに記載のＧａＮ系発光ダイオード素子。 The GaN-based light-emitting diode element according to any one of claims 1 to 3, wherein a height difference of the unevenness is 0.1 µm to 3 µm. 鏡面研磨された表面を有する基板の前記表面の一部をエッチング処理して光を散乱可能な凹凸を形成する工程と、ＧａＮ系半導体結晶膜を前記基板の表面の前記凹凸が形成されていない領域上から前記凹凸が形成された領域上にラテラル成長させる工程と、を有するＧａＮ系発光ダイオード素子の製造方法。 A step of etching a part of the surface of the substrate having a mirror-polished surface to form light unevenness, and a region where the unevenness of the surface of the substrate is not formed in the GaN-based semiconductor crystal film And a step of laterally growing on the region where the irregularities are formed from above. 前記エッチング処理が、ランダムエッチングマスクを用いたエッチング処理である、請求項５に記載の製造方法。 The manufacturing method according to claim 5, wherein the etching process is an etching process using a random etching mask. 前記エッチング処理が、ドライエッチング装置を用いてエッチングとデポジションが同時に生じるように行うエッチング処理である、請求項６に記載の製造方法。 The manufacturing method according to claim 6, wherein the etching process is an etching process performed so that etching and deposition occur simultaneously using a dry etching apparatus. 前記凹凸に含まれる凸部が錐体状である、請求項５〜７のいずれかに記載の製造方法。 The manufacturing method in any one of Claims 5-7 whose convex part contained in the said unevenness | corrugation is cone shape. 前記凹凸の高低差が０．１μｍ〜３μｍである請求項５〜８のいずれかに記載の製造方法。 The manufacturing method according to any one of claims 5 to 8, wherein a height difference of the unevenness is 0.1 µm to 3 µm.
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