JP2008235938A - Semiconductor image pick-up device and its manufacturing method - Google Patents

Semiconductor image pick-up device and its manufacturing method Download PDF

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JP2008235938A
JP2008235938A JP2008145039A JP2008145039A JP2008235938A JP 2008235938 A JP2008235938 A JP 2008235938A JP 2008145039 A JP2008145039 A JP 2008145039A JP 2008145039 A JP2008145039 A JP 2008145039A JP 2008235938 A JP2008235938 A JP 2008235938A
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opening width
film
imaging device
optical waveguide
semiconductor imaging
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Tetsuya Komoguchi
徹哉 菰口
Yoshitetsu Toumiya
祥哲 東宮
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Sony Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To improve light condensing efficiency of the semiconductor image pick-up device, by improving embedding properties of a transparent film that forms an optical waveguide unit of a semiconductor image pick-up device when an aspect ratio becomes higher as the semiconductor image pick-up device becomes to have more multilayer interconnections and more pixels. <P>SOLUTION: The semiconductor image pick-up device 100 includes: a silicon substrate 11; wirings 19A and 19B connected to the silicon substrate 11; an interlayer insulating film 21 which is formed on the silicon substrate 11 having a photodiode 15 so as to insulate the wirings 19A and the like; and a multistage opening-width optical waveguide unit 22 provided on a part other than the wirings 19A and 19B above the photodiode 15, which penetrates through the interlayer insulating film 21 from its uppermost part to the surface of the photodiode 15. The optical waveguide unit 22 has a multistage opening-width structure in which an opening width w1 at its uppermost part is larger than that w2 at its lowermost part. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、カラーフィルタ上のオンチップレンズから取り込んだ光を半導体撮像素子に導く光導波路構造を有する固体撮像素子や電界効果型の撮像素子に適用して好適な半導体撮像装置及びその製造方法に関する。詳しくは、半導体撮像素子上の導電性の膜を除く絶縁性の膜を貫く部分であって、当該絶縁性の膜最上部から半導体撮像素子表面へ至る部分に、最上部が第１開口幅とされ、最下部が第１開口幅に比べて狭くなされた第２開口幅を有するプラズマＳＩＮ膜から成る多段開口幅状の光導波路部を備え、導電性の膜の一部が光導波路部の第１開口幅で規定される領域下の絶縁性の膜にまで入り込んでおり、多層配線化及びその多画素化に伴いアスペクト比が高くなった場合に、この光導波路部を成す透明膜の埋め込み性が改善され、集光効率を向上できるようにしたものである。   The present invention relates to a semiconductor imaging device suitable for application to a solid-state imaging device having an optical waveguide structure that guides light taken from an on-chip lens on a color filter to a semiconductor imaging device, or a field effect imaging device, and a manufacturing method thereof. . Specifically, a portion that penetrates the insulating film excluding the conductive film on the semiconductor image sensor, the top portion of the insulating film from the top to the surface of the semiconductor image sensor has a first opening width. A multistage aperture width-shaped optical waveguide portion made of a plasma SIN film having a second aperture width whose lowermost portion is narrower than the first aperture width, and a part of the conductive film is a first portion of the optical waveguide portion. When the aspect ratio increases as a result of the multilayer wiring and the increase in the number of pixels, the transparent film forming the optical waveguide portion is embedded in the insulating film below the region defined by one opening width. Is improved so that the light collection efficiency can be improved.

近年、学校、家庭や放送局などにおいてビデオカメラ及びデジタルスチルカメラが使用される場合が多くなってきた。この種のカメラで不可欠なのが半導体撮像装置である。半導体撮像装置の中で光導波路構造を有する固体撮像素子や電界効果型の撮像素子は、光電変換素子としてのＣＣＤ（Ｃharge Ｃoupled Ｄevice：電荷結合素子）撮像素子を二次元状に配置し、光導波路によって光を電荷結合素子へ導くようにしたものである。ここで、ＣＣＤ撮像素子とは、フォトダイオードやＭＯＳキャパシタなどからなる単位素子を規則正しく並べた構造の半導体デバイスをいう。半導体撮像装置は半導体基板表面に蓄積されたある電荷のひとかたまりをＭＯＳキャパシタの電極の並びに沿って移動する機能を有している。   In recent years, video cameras and digital still cameras are often used in schools, homes, broadcasting stations, and the like. A semiconductor imaging device is indispensable for this type of camera. 2. Description of the Related Art Among solid-state imaging devices and field-effect imaging devices that have an optical waveguide structure in a semiconductor imaging device, a CCD (Charge Coupled Device) imaging device as a photoelectric conversion device is two-dimensionally arranged to form an optical waveguide. In this way, light is guided to the charge coupled device. Here, the CCD image pickup device refers to a semiconductor device having a structure in which unit elements such as photodiodes and MOS capacitors are regularly arranged. The semiconductor imaging device has a function of moving a group of charges accumulated on the surface of the semiconductor substrate along the arrangement of the electrodes of the MOS capacitor.

図１０は従来例に係る単一配線構造の半導体撮像装置１０の１画素の構造例を示す断面図である。
図１０に示す半導体撮像装置１０はシリコン基板１１を有しており、フィールド絶縁膜１２及びゲート絶縁膜１３によって素子分離されている。各々の画素を画定するためである。シリコン基板１１にはフォトダイオード１５が設けられている。 FIG. 10 is a cross-sectional view showing a structural example of one pixel of a semiconductor imaging device 10 having a single wiring structure according to a conventional example.
A semiconductor imaging device 10 shown in FIG. 10 has a silicon substrate 11 and is separated by a field insulating film 12 and a gate insulating film 13. This is to define each pixel. A photodiode 15 is provided on the silicon substrate 11.

フォトダイオード１５のゲート絶縁膜１３上には選択的にＳｉＮ膜１６が設けられている。ＳｉＮ膜１６の左隣りであって、ゲート絶縁膜１３上には転送ゲート１７が設けられ、フォトダイオード１５で検出された信号電荷を垂直レジスタ等へ転送するようになされる。   A SiN film 16 is selectively provided on the gate insulating film 13 of the photodiode 15. A transfer gate 17 is provided on the gate insulating film 13 adjacent to the left side of the SiN film 16 so as to transfer the signal charge detected by the photodiode 15 to a vertical register or the like.

このシリコン基板１１には導電性プラグ８や配線９等が設けられている。導電性プラグ８の一方は例えば、ゲート絶縁膜１３を貫いてシリコン基板１１に接合される。導電性プラグ８の他方は配線９に接続される。フォトダイオード１５を含むシリコン基板１１上には層間絶縁膜１が設けられ、転送ゲート１７、導電性プラグ８、配線９を絶縁するようになされる。   The silicon substrate 11 is provided with conductive plugs 8, wirings 9 and the like. For example, one of the conductive plugs 8 is bonded to the silicon substrate 11 through the gate insulating film 13. The other side of the conductive plug 8 is connected to the wiring 9. An interlayer insulating film 1 is provided on the silicon substrate 11 including the photodiode 15 so as to insulate the transfer gate 17, the conductive plug 8, and the wiring 9.

このフォトダイオード１５上の配線９を除く層間絶縁膜１を貫く部分であって、当該層間絶縁膜１の最上部からフォトダイオード表面へ至る部分には単一開口幅状の光導波路部２が設けられ、当該半導体撮像装置１０で受けた光をフォトダイオード１５へ導くようになされる。光導波路部２は透明性の膜から構成される。透明性の膜は高密度プラズマＣＶＤ法によって堆積され形成される。   A portion that penetrates the interlayer insulating film 1 excluding the wiring 9 on the photodiode 15 and that extends from the top of the interlayer insulating film 1 to the surface of the photodiode is provided with an optical waveguide portion 2 having a single opening width. Then, the light received by the semiconductor imaging device 10 is guided to the photodiode 15. The optical waveguide portion 2 is composed of a transparent film. The transparent film is deposited and formed by a high density plasma CVD method.

光導波路部２の開口幅は上部から下部にかけて一律にｗ０である。光導波路部２を含むシリコン基板１１上にはパッシベーション膜２３が光導波路部２上及び層間絶縁膜１上を覆うように設けられている。パッシベーション膜２３上には更に平坦化用の膜２４が設けられている。   The opening width of the optical waveguide part 2 is uniformly w0 from the upper part to the lower part. A passivation film 23 is provided on the silicon substrate 11 including the optical waveguide portion 2 so as to cover the optical waveguide portion 2 and the interlayer insulating film 1. A planarization film 24 is further provided on the passivation film 23.

平坦化用の膜２４上にはカラーフィルタ２５が設けられている。カラーフィルタ２５上にはオンチップレンズ２６が設けられ、当該半導体撮像装置１０で受けた光を光導波路部２の方へ集光（結像）するようになされる。上述の光導波路部２はオンチップレンズ２６とフォトダイオード１５とを光学的に接続し、集光効率を上げるようになされる。   A color filter 25 is provided on the planarizing film 24. An on-chip lens 26 is provided on the color filter 25, and the light received by the semiconductor imaging device 10 is condensed (imaged) toward the optical waveguide portion 2. The above-described optical waveguide unit 2 optically connects the on-chip lens 26 and the photodiode 15 to increase the light collection efficiency.

図１１Ａ及びＢは問題点を説明するための半導体撮像装置１０’の構造例及びその形成例を示す断面図である。図１１Ａに示す多層配線構造では導電性プラグ１８Ａが第１層目の配線１９Ａに接続され、この配線１９Ａが導電性プラグ１８Ｂに接続される。導電性プラグ１８Ｂには第２層目の配線１９Ｂが接続されている。配線１９Ａ，１９Ｂ等の多層構造化は電界効果型の撮像装置等においてフォトダイオード１５の多画素化に寄与する（特許文献１参照）。   FIGS. 11A and 11B are cross-sectional views showing a structural example and a formation example of the semiconductor imaging device 10 ′ for explaining the problem. In the multilayer wiring structure shown in FIG. 11A, the conductive plug 18A is connected to the first layer wiring 19A, and this wiring 19A is connected to the conductive plug 18B. A second layer wiring 19B is connected to the conductive plug 18B. The multilayer structure such as the wirings 19A and 19B contributes to the increase in the number of pixels of the photodiode 15 in a field effect type imaging device or the like (see Patent Document 1).

特開２０００−１５０８４５号公報JP 2000-150845 A

ところで、図１０に示した単一配線構造の半導体撮像装置１０の製造方法をそのまま図１１Ａに示したような多層配線構造を有する半導体撮像装置１０’の製造に適用すると、次のような問題が生ずる。   By the way, if the manufacturing method of the semiconductor imaging device 10 having the single wiring structure shown in FIG. 10 is applied to the manufacturing of the semiconductor imaging device 10 ′ having the multilayer wiring structure as shown in FIG. Arise.

（１）光導波路部２を構成するための開口部（光導波路用の開口部）６は、多層配線構造上その開口深さが深くなるため、アスペクト比が高くなる。更にはフォトダイオード１５の多画素化に向けて、画素面積が小さくなり、それに伴い光導波路部２の開口面積も縮小される。そのため、開口部６のアスペクト比が益々高くなる。   (1) Since the opening depth (opening portion for optical waveguide) 6 for constituting the optical waveguide portion 2 is deep in the multilayer wiring structure, the aspect ratio becomes high. Furthermore, the pixel area is reduced toward the increase in the number of pixels of the photodiode 15, and the opening area of the optical waveguide portion 2 is also reduced accordingly. Therefore, the aspect ratio of the opening 6 becomes higher.

（２）図１１Ｂにおいて、アスペクト比が高い単一開口幅状の開口部６に、図１０に示した半導体撮像装置１０の製造方法をそのまま適用して、高密度プラズマＣＶＤ法により、コア材となる透明性の膜３１を堆積した場合に鬆５が発生するおそれがある。鬆５は堆積初期の段階で透明性の膜３１が開口部６の底部及びその側壁部に堆積するが、ある程度の透明性の膜３１がこれらの部位に堆積すると、徐々に開口上部で透明性の膜３１が庇状に堆積成長することによって、透明性の膜３１が開口部内に未充填のまま開口上部を塞いでしまうことにより発生する。従って、光導波路用の開口部６に透明性の膜３１をＣＶＤ法等により埋め込む際の埋め込み性が悪くなる。これにより、光導波路部２の集光性の悪化やばらつきが懸念され、電界効果型の撮像装置等の信頼性の低下につながる。   (2) In FIG. 11B, the manufacturing method of the semiconductor imaging device 10 shown in FIG. 10 is applied as it is to the opening 6 having a single opening width shape with a high aspect ratio, and the core material is formed by high-density plasma CVD. When the transparent film 31 is deposited, the void 5 may be generated. In the void 5, the transparent film 31 is deposited on the bottom of the opening 6 and the side wall thereof at the initial stage of deposition. When a certain degree of the transparent film 31 is deposited on these portions, the transparency is gradually increased in the upper part of the opening. The film 31 is deposited and grown in a bowl shape, and the transparent film 31 closes the upper part of the opening without filling the opening. Accordingly, the embedding property when the transparent film 31 is embedded in the opening 6 for the optical waveguide by the CVD method or the like is deteriorated. As a result, there is a concern about deterioration and dispersion of the light condensing property of the optical waveguide portion 2, leading to a decrease in reliability of a field effect type imaging device or the like.

そこで、この発明はこのような従来の課題を解決したものであって、多層配線化及び多画素化に伴い光導波路用の開口部のアスペクト比が高くなった場合に、この光導波路部を成す透明膜の埋め込み性が改善されることにより集光効率を向上できるようにした半導体撮像装置及びその製造方法を提供することを目的とする。   Therefore, the present invention solves such a conventional problem, and this optical waveguide portion is formed when the aspect ratio of the opening portion for the optical waveguide becomes high with the increase in the number of layers and the number of pixels. It is an object of the present invention to provide a semiconductor imaging device and a method for manufacturing the same that can improve light collection efficiency by improving the embedding property of a transparent film.

上述した課題は、半導体撮像素子を有する所定の基板と、この基板に接続された導電性の膜と、この導電性の膜を絶縁するために半導体撮像素子を含む基板上に設けられた絶縁性の膜と、半導体撮像素子上の導電性の膜を除く絶縁性の膜を貫く部分であって、当該絶縁性の膜最上部から半導体撮像素子表面へ至る部分に設けられ、最上部が第１開口幅となされ、最下部が第１開口幅に比べて狭くなされた第２開口幅を有するプラズマＳＩＮ膜から構成された多段開口幅状の光導波路部とを備え、導電性の膜の一部が光導波路部の第１開口幅で規定される領域下の絶縁性の膜にまで入り込んでいる半導体撮像装置によって解決される。   The above-described problem is that a predetermined substrate having a semiconductor imaging device, a conductive film connected to the substrate, and an insulating property provided on the substrate including the semiconductor imaging device to insulate the conductive film. And a portion that penetrates the insulating film excluding the conductive film on the semiconductor imaging device, and is provided in a portion that extends from the top of the insulating film to the surface of the semiconductor imaging device. A multi-stage opening width-shaped optical waveguide portion formed of a plasma SIN film having a second opening width that has an opening width and a lowermost portion that is narrower than the first opening width. Is solved by a semiconductor imaging device that penetrates into an insulating film below the region defined by the first opening width of the optical waveguide portion.

本発明に係る半導体撮像装置によれば、半導体撮像素子上の導電性の膜を除く絶縁性の膜を貫く部分であって、当該絶縁性の膜最上部から半導体撮像素子表面へ至る部分に、最上部が第１開口幅となされ、最下部が第１開口幅に比べて狭くなされた第２開口幅を有するプラズマＳＩＮ膜から構成された多段開口幅状の光導波路部を備えているので、半導体撮像素子上の光導波路部で最上部の開口幅に比べて最下部の開口幅を狭くなされた集光構造を採ることができる。   According to the semiconductor imaging device according to the present invention, the portion that penetrates the insulating film excluding the conductive film on the semiconductor imaging device, the portion from the top of the insulating film to the surface of the semiconductor imaging device, Since the uppermost portion has a first opening width and the lowermost portion includes a multistage opening width-shaped optical waveguide portion formed of a plasma SIN film having a second opening width that is narrower than the first opening width, It is possible to adopt a condensing structure in which the lowermost opening width is narrower than the uppermost opening width in the optical waveguide portion on the semiconductor imaging device.

従って、光導波路部の形成時に、特に、多段開口幅状の開口部への原料ガス＋堆積物（ラジカル）の供給が促進され、Ｐ−ＳＩＮ膜の埋め込み性を向上できるようになり、半導体撮像装置の多層配線化及びその多画素化に伴い、深さ対開口幅の比であるアスペクト比が高くなった場合でも、単一開口幅状の光導波路部に比べて集光効率を向上させることができる。これにより、多段開口幅状の光導波路部を備えた高信頼度の半導体撮像装置を提供できる。   Therefore, when forming the optical waveguide portion, in particular, the supply of the source gas and the deposit (radical) to the opening portion having a multi-stage opening width is promoted, and the embedding property of the P-SIN film can be improved. Even when the aspect ratio, which is the ratio of depth to aperture width, increases with the increase in the number of devices and the number of pixels, the light collection efficiency is improved compared to the optical waveguide section with a single aperture width. Can do. Thereby, a highly reliable semiconductor imaging device including an optical waveguide portion having a multistage aperture width can be provided.

本発明に係る半導体撮像装置の製造方法は、所望の基板に半導体撮像素子を形成する工程と、半導体撮像素子を形成した基板上に導電性の膜及び絶縁性の膜を形成する工程と、半導体撮像素子上の導電性の膜を除く絶縁性の膜を貫く部分であって、当該絶縁性の膜最上部から半導体撮像素子表面へ至る部分に、最上部を第１開口幅とし、最下部を第１開口幅に比べて狭くなされる第２開口幅を有するプラズマＳＩＮ膜から成る多段開口幅状の光導波路部を形成する工程とを有し、基板上に導電性の膜を形成する際に、光導波路部の第１開口幅で規定される領域下の絶縁性の膜にまで導電性の膜の一部を入り込むようになされるものである。   A method of manufacturing a semiconductor imaging device according to the present invention includes a step of forming a semiconductor imaging element on a desired substrate, a step of forming a conductive film and an insulating film on the substrate on which the semiconductor imaging element is formed, and a semiconductor A portion that penetrates the insulating film excluding the conductive film on the image sensor, and has a first opening width at the top from the top of the insulating film to the surface of the semiconductor image sensor, and the bottom at the bottom. Forming a multistage opening width-shaped optical waveguide portion made of a plasma SIN film having a second opening width that is narrower than the first opening width, and forming a conductive film on the substrate. The conductive film is partially inserted into the insulating film below the region defined by the first opening width of the optical waveguide portion.

本発明に係る半導体撮像装置の製造方法によれば、特に、多段開口幅状の開口部への原料ガス＋堆積物（ラジカル）の供給が促進され、Ｐ−ＳＩＮ膜の埋め込み性を向上できるようになり、半導体撮像装置の多層配線化及びその多画素化に伴い、深さ対開口幅の比であるアスペクト比が高くなった場合でも、単一開口幅状の光導波路部に比べて透明性の膜を多段開口幅状の開口部等に確実かつ再現性良く埋め込むことができる。従って、半導体撮像素子上で最上部の開口幅に比べて最下部の開口幅を狭くなされた集光構造を有する光導波路部を形成することができる。これにより、多段開口幅状の光導波路部を備えた高信頼度の半導体撮像装置を再現性良く製造することができる。   According to the method of manufacturing a semiconductor imaging device according to the present invention, in particular, the supply of the source gas + the deposit (radical) to the opening having the multi-stage opening width is promoted, and the embedding property of the P-SIN film can be improved. Even when the aspect ratio, which is the ratio of depth to aperture width, increases with the increase in the number of multi-layer wiring and the number of pixels in a semiconductor imaging device, it is more transparent than the optical waveguide section with a single aperture width. This film can be securely and reproducibly embedded in an opening having a multistage opening width. Therefore, it is possible to form an optical waveguide portion having a condensing structure in which the lowermost opening width is narrower than the uppermost opening width on the semiconductor imaging device. As a result, a highly reliable semiconductor imaging device including an optical waveguide portion having a multistage aperture width can be manufactured with high reproducibility.

以上説明したように、本発明に係る半導体撮像装置によれば、半導体撮像素子上の導電性の膜を除く絶縁性の膜を貫く部分であって、当該絶縁性の膜最上部から半導体撮像素子表面へ至る部分に、最上部が第１開口幅とされ、最下部が第１開口幅に比べて狭くなされた第２開口幅を有するプラズマＳＩＮ膜から構成された多段開口幅状の光導波路部を備え、配線の一部が光導波路部の第１開口幅で規定される領域下の層間絶縁膜にまで入り込んでいるものである。   As described above, according to the semiconductor imaging device according to the present invention, the portion that penetrates the insulating film excluding the conductive film on the semiconductor imaging element, from the top of the insulating film to the semiconductor imaging element. An optical waveguide portion having a multi-stage opening width formed of a plasma SIN film having a second opening width in which the uppermost portion has a first opening width and the lowermost portion is narrower than the first opening width in a portion reaching the surface And part of the wiring penetrates into the interlayer insulating film below the region defined by the first opening width of the optical waveguide portion.

この構成によって、光導波路部の形成時に、特に、多段開口幅状の開口部への原料ガス＋堆積物（ラジカル）の供給が促進され、Ｐ−ＳＩＮ膜の埋め込み性を向上できるようになり、半導体撮像素子上の光導波路部で最上部の開口幅に比べて最下部の開口幅を狭くなされた集光構造を採ることができる。従って、半導体撮像装置の多層配線化及びその多画素化に伴い、深さ対開口幅の比であるアスペクト比が高くなった場合でも、単一開口幅状の光導波路部に比べて集光効率を向上させることができる。これにより、多段開口幅状の光導波路部を備えた高信頼度の半導体撮像装置を提供できる。   With this configuration, when forming the optical waveguide portion, in particular, the supply of the source gas + deposit (radical) to the opening portion having a multi-stage opening width is promoted, and the embedding property of the P-SIN film can be improved. It is possible to adopt a condensing structure in which the lowermost opening width is narrower than the uppermost opening width in the optical waveguide portion on the semiconductor imaging device. Therefore, even when the aspect ratio, which is the ratio of depth to aperture width, increases with the increase in the number of multilayered wiring and the number of pixels in a semiconductor imaging device, the light collection efficiency is higher than that of a single aperture width optical waveguide section. Can be improved. Thereby, a highly reliable semiconductor imaging device including an optical waveguide portion having a multistage aperture width can be provided.

本発明に係る半導体撮像装置の製造方法によれば、半導体撮像素子を形成した基板上に導電性の膜及び絶縁性の膜を形成し、その後、半導体撮像素子上の導電性の膜を除く絶縁性の膜を貫く部分であって、当該絶縁性の膜最上部から半導体撮像素子表面へ至る部分に最上部を第１開口幅とし、最下部を第１開口幅に比べて狭くなされる第２開口幅を有するプラズマＳＩＮ膜から構成された多段開口幅状の光導波路部を形成し、導電性の膜の一部が光導波路部の第１開口幅ｗ１で規定される領域下に入り込むようになされる。   According to the method for manufacturing a semiconductor imaging device according to the present invention, the conductive film and the insulating film are formed on the substrate on which the semiconductor imaging element is formed, and then the insulating film is removed except for the conductive film on the semiconductor imaging element. A second portion in which the uppermost portion is a first opening width and the lowermost portion is narrower than the first opening width in a portion that penetrates the insulating film and extends from the uppermost portion of the insulating film to the surface of the semiconductor imaging device. An optical waveguide portion having a multistage opening width formed from a plasma SIN film having an opening width is formed, and a part of the conductive film enters below the region defined by the first opening width w1 of the optical waveguide portion. Made.

この構成によって、光導波路部の形成時に、特に、多段開口幅状の開口部への原料ガス＋堆積物（ラジカル）の供給が促進され、Ｐ−ＳＩＮ膜の埋め込み性を向上できるようになり、半導体撮像装置の多層配線化及びその多画素化に伴い、深さ対開口幅の比であるアスペクト比が高くなった場合でも、単一開口幅状の光導波路部に比べて透明性の膜を多段開口幅状の開口部等に確実かつ再現性良く埋め込むことができる。従って、半導体撮像素子上で最上部の開口幅に比べて最下部の開口幅を狭くなされた集光構造を有する光導波路部を形成することができる。これにより、多段開口幅状の光導波路部を備えた高信頼度の半導体撮像装置を再現性良く特に、多段開口幅状の開口部への原料ガス＋堆積物（ラジカル）の供給が促進され、Ｐ−ＳＩＮ膜の埋め込み性を向上できるようになり製造することができる。   With this configuration, when forming the optical waveguide portion, in particular, the supply of the source gas + deposit (radical) to the opening portion having a multi-stage opening width is promoted, and the embedding property of the P-SIN film can be improved. Even when the aspect ratio, which is the ratio of depth to aperture width, increases with the increase in the number of wiring layers and the number of pixels in a semiconductor imaging device, a transparent film is formed compared to a single-wavelength-width optical waveguide section. It can be reliably and reproducibly embedded in an opening having a multi-stage opening width. Therefore, it is possible to form an optical waveguide portion having a condensing structure in which the lowermost opening width is narrower than the uppermost opening width on the semiconductor imaging device. As a result, a highly reliable semiconductor imaging device provided with an optical waveguide portion having a multi-stage opening width is provided with good reproducibility, in particular, the supply of source gas + deposits (radicals) to the multi-stage opening width opening is promoted, The embedding property of the P-SIN film can be improved and can be manufactured.

続いて、この発明に係る半導体撮像装置及びその製造方法の一実施の形態について、図面を参照しながら説明をする。
（１）半導体撮像装置
図１は本発明に係る実施形態としての半導体撮像装置１００の構造例を示す断面図である。
この実施形態では半導体撮像素子上の導電性の膜を除く絶縁性の膜を貫く部分であって、当該絶縁性の膜最上部から半導体撮像素子表面へ至る部分に設けられ、最上部が第１開口幅となされ、最下部が第１開口幅に比べて狭くなされた第２開口幅を有する多段開口幅状の光導波路部を備え、導電性の膜の一部が光導波路部の第１開口幅で規定される領域下の絶縁性の膜にまで入り込んでいる。この構造によって多層配線化及び多画素化に伴い深さ対開口幅の比であるアスペクト比が高くなった場合でも、単一開口幅状の光導波路部に比べて集光効率を向上できるようにすると共に、最上部の開口幅に比べて最下部の開口幅を狭くなされた集光構造の光導波路部を再現性良く形成できるようにしたものである。 Subsequently, an embodiment of a semiconductor imaging device and a manufacturing method thereof according to the present invention will be described with reference to the drawings.
(1) Semiconductor Imaging Device FIG. 1 is a cross-sectional view showing a structural example of a semiconductor imaging device 100 as an embodiment according to the present invention.
In this embodiment, it is a portion that penetrates the insulating film excluding the conductive film on the semiconductor imaging device, and is provided in the portion that extends from the top of the insulating film to the surface of the semiconductor imaging device, the top being the first. A multistage opening width-shaped optical waveguide portion having a second opening width that has an opening width and a lowermost portion that is narrower than the first opening width, and a part of the conductive film is the first opening of the optical waveguide portion. It penetrates into the insulating film below the region defined by the width. With this structure, even when the aspect ratio, which is the ratio of depth to aperture width, increases as the number of layers increases and the number of pixels increases, the light collection efficiency can be improved compared to the optical waveguide section with a single aperture width. In addition, an optical waveguide portion having a condensing structure in which the opening width of the lowermost portion is narrower than the opening width of the uppermost portion can be formed with good reproducibility.

図１に示す半導体撮像装置１００はカラー用の固体撮像装置（ＣＣＤ）や電界効果型の撮像装置（ＣＭＯＳセンサ）の構造に適用して極めて好適である。半導体撮像装置１００は所定の基板の一例となるシリコン基板１１を有しており、フィールド絶縁膜（素子分離絶縁膜）１２及び膜厚数ｎｍ程度のゲート絶縁膜１３によって素子分離されている。各々の画素を画定するためである。シリコン基板１１にはｐ型又はｎ型のＳｉ基板が使用される。ｎ型のＳｉ基板を使用する場合は当該基板内にｐ型の半導体埋め込み層（ｐ−ＷＥＬＬ）１４が形成される。   The semiconductor imaging device 100 shown in FIG. 1 is extremely suitable when applied to the structure of a color solid-state imaging device (CCD) or a field effect imaging device (CMOS sensor). The semiconductor imaging device 100 has a silicon substrate 11 as an example of a predetermined substrate, and is isolated by a field insulating film (element isolation insulating film) 12 and a gate insulating film 13 having a film thickness of about several nm. This is to define each pixel. As the silicon substrate 11, a p-type or n-type Si substrate is used. When an n-type Si substrate is used, a p-type semiconductor buried layer (p-WELL) 14 is formed in the substrate.

このシリコン基板１１には半導体撮像素子の一例となるフォトダイオード１５が設けられている。フォトダイオード１５はフィールド絶縁膜１２によって素子分離された、ｐ型のＳｉ基板又はｐ−ＷＥＬＬ１４内に設けられたｎ型の不純物領域１５Ａと、この不純物領域１５Ａ内に設けられたｐ型の不純物領域１５Ｂから成るｐｎ接合構造によって形成される。ｎ型のＳｉ基板を使用する場合、フォトダイオード１５はｐｎｐｎ接合構造によって形成される。   The silicon substrate 11 is provided with a photodiode 15 as an example of a semiconductor imaging device. The photodiode 15 includes a p-type Si substrate or an n-type impurity region 15A provided in the p-WELL 14 and a p-type impurity region provided in the impurity region 15A. It is formed by a pn junction structure consisting of 15B. When an n-type Si substrate is used, the photodiode 15 is formed by a pnpn junction structure.

フォトダイオード１５のゲート絶縁膜１３上には選択的にＳｉＮ膜１６が設けられている。このＳｉＮ膜１６は光導波路用の開口部を形成する際のエッチングストッパ膜として使用され、それがゲート絶縁膜１３上に選択的に残留したものである。ＳｉＮ膜１６の左隣りであって、ゲート絶縁膜１３上には転送ゲート１７が設けられ、ｎ型の不純物領域１５Ａに蓄積された信号電荷を垂直レジスタ等へ転送するようになされる。   A SiN film 16 is selectively provided on the gate insulating film 13 of the photodiode 15. This SiN film 16 is used as an etching stopper film when forming an opening for an optical waveguide, and it selectively remains on the gate insulating film 13. A transfer gate 17 is provided on the gate insulating film 13 on the left side of the SiN film 16 so as to transfer the signal charge accumulated in the n-type impurity region 15A to a vertical register or the like.

このシリコン基板１１には導電性の膜の一例となる導電性プラグ（ビアホール）１８Ａ、１８Ｂや配線１９Ａ，１９Ｂ等が設けられている。導電性プラグ１８Ａの一方は例えば、ゲート絶縁膜１３を貫いて開口された図示しないコンタクトホールを介してシリコン基板１１に接合される。導電性プラグ１８Ａの他方は、第１層目の配線１９Ａに接続される。   The silicon substrate 11 is provided with conductive plugs (via holes) 18A and 18B, wirings 19A and 19B, which are examples of conductive films. One of the conductive plugs 18A is bonded to the silicon substrate 11 through a contact hole (not shown) opened through the gate insulating film 13, for example. The other of the conductive plugs 18A is connected to the first layer wiring 19A.

第１層目の配線１９Ａは他の導電性プラグ１８Ｂを介して第２層目の配線１９Ｂに接続される（多層配線構造）。多層配線は例えば、電界効果型の撮像装置において、１画素毎に設けられるアンプやリセット用のトランジスタの信号線や電源線に使用される。アンプやリセット用のトランジスタは信号電荷のＳ／Ｎ比の改善に使用される。１画素に３乃至５個のトランジスタが使用される。   The first layer wiring 19A is connected to the second layer wiring 19B via another conductive plug 18B (multilayer wiring structure). For example, the multilayer wiring is used for a signal line or a power supply line of an amplifier or a reset transistor provided for each pixel in a field effect imaging device. Amplifiers and reset transistors are used to improve the signal charge S / N ratio. Three to five transistors are used for one pixel.

導電性プラグ１８Ａ，１８Ｂにはタングステンや、不純物イオンを含有した多結晶シリコンが使用され、第１及び第２層目の配線１９Ａ，１９Ｂ等には銅や、タングステン、アルミニウムなどの金属材料や上述の多結晶シリコンが使用される。導電性プラグ１８Ａ，１８Ｂや第１及び第２層目の配線１９Ａ，１９Ｂ等の抵抗率を下げるためである。   The conductive plugs 18A and 18B are made of tungsten or polycrystalline silicon containing impurity ions, and the first and second wirings 19A and 19B are made of a metal material such as copper, tungsten or aluminum, or the above-mentioned. Polycrystalline silicon is used. This is to reduce the resistivity of the conductive plugs 18A and 18B and the first and second layer wirings 19A and 19B.

フォトダイオード１５を含むシリコン基板１１上には絶縁性の膜の一例となる層間絶縁膜（クラッド部）２１が設けられ、転送ゲート１７、導電性プラグ１８、第１及び第２層目の配線１９Ａ，１９Ｂを絶縁するようになされる。層間絶縁膜２１にはＳｉＯ2膜やＢＰＳＧ膜等が使用される。   An interlayer insulating film (cladding portion) 21 as an example of an insulating film is provided on the silicon substrate 11 including the photodiode 15, and includes a transfer gate 17, a conductive plug 18, and first and second layer wirings 19A. , 19B are insulated. For the interlayer insulating film 21, a SiO2 film, a BPSG film, or the like is used.

このフォトダイオード１５上の第１及び第２層目の配線１９Ａ，１９Ｂ等を除く層間絶縁膜２１を貫く部分であって、当該層間絶縁膜２１の最上部からフォトダイオード表面（ゲート絶縁膜１３上）へ至る部分には多段開口幅状の光導波路部２２が設けられ、当該半導体撮像装置１００で受けた光をフォトダイオード１５へ導くようになされる。光導波路部２２は透明性の膜から構成される。   A portion that penetrates the interlayer insulating film 21 excluding the first and second-layer wirings 19A and 19B on the photodiode 15 and from the top of the interlayer insulating film 21 to the surface of the photodiode (on the gate insulating film 13). ) Is provided with an optical waveguide portion 22 having a multistage aperture width, and guides light received by the semiconductor imaging device 100 to the photodiode 15. The optical waveguide portion 22 is made of a transparent film.

透明性の膜には層間絶縁膜２１に比べて屈折率が高い材料が使用される。この例で層間絶縁膜２１の屈折率は１．４程度であり、光導波路部２２の屈折率は２．０程度である。透明性の膜には例えばナイトライド系のＰ−ＳＩＮ膜が使用される。Ｐ−ＳＩＮ膜は高密度プラズマＣＶＤ法によって堆積され形成される。   A material having a higher refractive index than that of the interlayer insulating film 21 is used for the transparent film. In this example, the refractive index of the interlayer insulating film 21 is about 1.4, and the refractive index of the optical waveguide portion 22 is about 2.0. For example, a nitride-based P-SIN film is used as the transparent film. The P-SIN film is deposited and formed by a high density plasma CVD method.

光導波路部２２のコア材となる透明性の膜は、クラッド部となる層間絶縁膜１に比べて屈折率が高いことを利用して、透明性の膜と層間絶縁膜１の界面で定まる臨界角より大きい入射角を持つ入射光を全反射させること（スネルの法則）により、フォトダイオード１５への集光効率を高めるようになされる。   A transparent film serving as a core material of the optical waveguide portion 22 has a criticality determined by an interface between the transparent film and the interlayer insulating film 1 by utilizing a higher refractive index than the interlayer insulating film 1 serving as a cladding portion. By condensing incident light having an incident angle larger than the angle (Snell's law), the light collection efficiency to the photodiode 15 is increased.

光導波路部２２は当該光導波路部２２の最上部の開口幅をｗ１とし、その最下部の開口幅をｗ２としたとき、開口幅ｗ１に比べて開口幅ｗ２を狭くなされている。多段開口幅状の構造を採るためである。このような構造を採ると、光導波路部２２の開口上部の受光面積が大きく保たれ、開口下部のアスペクト比を従来構造に比べて低減される。つまり、高密度プラズマＣＶＤ法によってＰ−ＳＩＮ膜を堆積形成する際に、多段開口幅状の開口部への原料ガス＋堆積物（ラジカル）の供給が促進され、Ｐ−ＳＩＮ膜の埋め込み性が向上するようになる。光導波路部２２はＰ−ＳＩＮ膜が堆積された後に、ＣＭＰ（Ｃhemical Ｍechanical Ｐolishing）法やエッチバック法により、グローバル平坦化処理されて構成される。   The optical waveguide portion 22 has an opening width w2 narrower than the opening width w1 when the uppermost opening width of the optical waveguide portion 22 is w1 and the lowermost opening width is w2. This is because a multi-stage opening width structure is adopted. When such a structure is adopted, the light receiving area at the upper part of the opening of the optical waveguide part 22 is kept large, and the aspect ratio of the lower part of the opening is reduced as compared with the conventional structure. That is, when the P-SIN film is deposited by high-density plasma CVD, the supply of the source gas + deposit (radical) to the opening having a multistage opening width is promoted, and the embedding property of the P-SIN film is improved. To improve. The optical waveguide portion 22 is configured by performing a global planarization process by a CMP (Chemical Mechanical Polishing) method or an etch back method after a P-SIN film is deposited.

この例では光導波路部２２を含むシリコン基板１１上には保護用の膜の一例となるパッシベーション膜２３が光導波路部２２上及び層間絶縁膜２１上を覆うように設けられている。パッシベーション膜２３上には更に平坦化用の膜２４が設けられている。平坦化用の膜２４上にはカラーフィルタ２５が設けられている。カラーフィルタ２５には原色系で赤（Ｒ）色、緑（Ｇ）色及び青（Ｂ）色のフィルタが使用され、補色系では、マゼンタ（Ｍｇ）色、シアン（Ｃｙ）色、グリーン（Ｇ）色、イエロー（Ｙｃ）色のフィルタが使用される。カラー用の撮像信号を得るためである。   In this example, a passivation film 23, which is an example of a protective film, is provided on the silicon substrate 11 including the optical waveguide portion 22 so as to cover the optical waveguide portion 22 and the interlayer insulating film 21. A planarization film 24 is further provided on the passivation film 23. A color filter 25 is provided on the planarizing film 24. As the color filter 25, red (R), green (G) and blue (B) filters are used as primary colors, and magenta (Mg), cyan (Cy) and green (G) are used as complementary colors. ) And yellow (Yc) color filters are used. This is to obtain a color imaging signal.

カラーフィルタ２５上には集光用の光学素子の一例となるオンチップレンズ２６が設けられ、当該半導体撮像装置１００で受けた光を光導波路部２２の方へ集光（結像）するようになされる。この光導波路部２２は当該光導波路部２２の最上部の開口径に比べて最下部の開口径を狭くなされた段付き円錐状を成すように構成してもよい。オンチップレンズ２６を球面状に形成される場合である。オンチップレンズ２６は球面状に限られることはなく、蒲鉾状であってもよい。   An on-chip lens 26, which is an example of a condensing optical element, is provided on the color filter 25, so that the light received by the semiconductor imaging device 100 is condensed (imaged) toward the optical waveguide portion 22. Made. The optical waveguide portion 22 may be configured to have a stepped conical shape in which the lowermost opening diameter is narrower than the uppermost opening diameter of the optical waveguide portion 22. This is a case where the on-chip lens 26 is formed in a spherical shape. The on-chip lens 26 is not limited to a spherical shape, and may be a bowl shape.

この例で光導波路部２２の開口形状は従来構造の単一開口形状と異なり、段差を伴って形成される。この例ではオンチップレンズ２６の曲率を調整することによって、光の焦点を光導波路部２２の中心（光軸）、つまり、開口径の小さい下部の中心へ合わせ込むようになされる。段差部での入射光の拡散を抑制してフォトダイオード１５へ集光するためである。   In this example, the opening shape of the optical waveguide portion 22 is different from the single opening shape of the conventional structure, and is formed with a step. In this example, by adjusting the curvature of the on-chip lens 26, the focal point of light is adjusted to the center (optical axis) of the optical waveguide portion 22, that is, the lower center having a small aperture diameter. This is for suppressing the diffusion of incident light at the stepped portion and condensing it to the photodiode 15.

このように、本発明に係る実施形態としての半導体撮像装置１００によれば、フォトダイオード１５上の第１及び第２層目の配線１９Ａ，１９Ｂを除く層間絶縁膜２１を貫く部分であって、当該層間絶縁膜２１の最上部からフォトダイオード１５表面へ至る部分に多段開口幅状の光導波路部２２を備えているので、フォトダイオード１５上の光導波路部２２で最上部の開口幅ｗ１に比べて最下部の開口幅ｗ２を狭くなされた集光構造を採ることができる。しかも、配線１９Ａの一部が光導波路部２２の第１開口幅ｗ１で規定される領域下の層間絶縁膜２１にまで入り込んでいる。   As described above, according to the semiconductor imaging device 100 according to the embodiment of the present invention, the portion penetrating the interlayer insulating film 21 excluding the first and second wirings 19A and 19B on the photodiode 15, Since the optical waveguide portion 22 having a multi-stage opening width is provided in the portion extending from the uppermost portion of the interlayer insulating film 21 to the surface of the photodiode 15, the optical waveguide portion 22 on the photodiode 15 is compared with the uppermost opening width w 1. Thus, it is possible to adopt a condensing structure in which the opening width w2 at the bottom is narrowed. In addition, a part of the wiring 19 </ b> A enters the interlayer insulating film 21 below the region defined by the first opening width w <b> 1 of the optical waveguide portion 22.

従って、半導体撮像装置１００の多層配線化及びその多画素化に伴い、アスペクト比が高くなった場合でも、単一開口幅状の光導波路部に比べて集光効率を向上させることができる。これにより、多段開口幅状の光導波路部２２を備えた高信頼度の固体撮像装置や電界効果型の撮像装置等を提供できる。   Therefore, even when the aspect ratio increases with the increase in the number of multilayer wiring and the number of pixels in the semiconductor imaging device 100, the light collection efficiency can be improved as compared with the optical waveguide portion having a single aperture width. Thereby, a highly reliable solid-state imaging device, a field effect type imaging device, etc. provided with the optical waveguide part 22 of multistage opening width shape can be provided.

（２）半導体撮像装置の製造方法
図２Ａ及びＢ〜図９は半導体撮像装置の形成例（その１〜８）を示す断面図である。この例では図１に示した多段開口幅状の光導波路部２２を有する半導体撮像装置１００を形成する場合を想定し、二段階エッチングにより光導波路部２２を開口する場合を例に挙げる。半導体撮像装置１００についてはカラー用の固体撮像装置や電界効果型の撮像装置が対象となる。 (2) Manufacturing Method of Semiconductor Imaging Device FIGS. 2A and B to FIG. 9 are cross-sectional views showing examples (Nos. 1 to 8) of forming a semiconductor imaging device. In this example, it is assumed that the semiconductor imaging device 100 having the optical waveguide portion 22 having the multi-stage opening width shown in FIG. 1 is formed, and an example in which the optical waveguide portion 22 is opened by two-stage etching will be described. The semiconductor imaging device 100 is a solid-state imaging device for color or a field effect imaging device.

これを前提にして、図２Ａに示すフィールド絶縁膜１２及びゲート絶縁膜１３により画定されたｎ型のシリコン基板１１にフォトダイオード１５、エッチングストッパ用のＳｉＮ膜１６及び転送ゲート１７を形成する。まず、ゲート絶縁膜１３上の所定の位置に転送ゲート１７を形成する。このとき、ゲート絶縁膜１３上の全面に所定の膜厚の多結晶シリコン膜を堆積し、これを選択的にパターニングすることにより転送ゲート１７を形成する。   On the premise of this, a photodiode 15, an SiN film 16 for an etching stopper, and a transfer gate 17 are formed on an n-type silicon substrate 11 defined by the field insulating film 12 and the gate insulating film 13 shown in FIG. 2A. First, the transfer gate 17 is formed at a predetermined position on the gate insulating film 13. At this time, a polycrystalline silicon film having a predetermined thickness is deposited on the entire surface of the gate insulating film 13 and selectively patterned to form the transfer gate 17.

フォトダイオード１５は従来法と同様にして、ｐ−ＷＥＬＬ１４内にｎ型の不純物を注入し又は熱拡散してｎ型の不純物領域１５Ａを形成する。その後、この不純物領域１５Ａ内にｐ型の不純物を注入し又は熱拡散してｐ型の不純物領域１５Ｂを形成する。これにより、ｐｎｐｎ接合構造のフォトダイオード１５が形成される。   In the photodiode 15, as in the conventional method, an n-type impurity region 15A is formed by injecting or thermally diffusing an n-type impurity into the p-WELL 14. Thereafter, a p-type impurity is implanted into the impurity region 15A or thermally diffused to form a p-type impurity region 15B. As a result, a photodiode 15 having a pnpn junction structure is formed.

フォトダイオード１５のゲート絶縁膜１３上に選択的に絶縁性の膜としてＳｉＮ膜１６を形成する。このとき、転送ゲート１７上の全面に所定の膜厚のシリコン窒化膜を堆積し、これを選択的にパターニングすることによりエッチングストッパ用のＳｉＮ膜１６を形成する。   A SiN film 16 is selectively formed as an insulating film on the gate insulating film 13 of the photodiode 15. At this time, a silicon nitride film having a predetermined thickness is deposited on the entire surface of the transfer gate 17 and selectively patterned to form an SiN film 16 for an etching stopper.

その後、フォトダイオード１５を形成したシリコン基板１１上に、図２Ｂに示す導電性プラグ１８Ａ、層間絶縁膜２１Ａ及び配線１９Ａ（多層配線）を形成する。このとき、シリコン基板１１の全面に所定の膜厚のＳｉＯ２膜等の層間絶縁膜２１Ａを堆積し、これを選択的に開口してシリコン基板１１に至るコンタクトホールを形成した後に、タングステンなどの金属材料や不純物イオンを含有した多結晶シリコン等の導電材料を埋め込むことにより導電性プラグ１８Ａを形成する。   Thereafter, the conductive plug 18A, the interlayer insulating film 21A, and the wiring 19A (multilayer wiring) shown in FIG. 2B are formed on the silicon substrate 11 on which the photodiode 15 is formed. At this time, an interlayer insulating film 21A such as a SiO2 film having a predetermined film thickness is deposited on the entire surface of the silicon substrate 11, and after selectively opening the contact hole reaching the silicon substrate 11, a metal such as tungsten is formed. A conductive plug 18A is formed by embedding a conductive material such as polycrystalline silicon containing material and impurity ions.

そして、導電性プラグ１８Ａを形成した後に、そのシリコン基板１１の全面に、銅やアルミニウムなどの金属材料や不純物イオンを含有した多結晶シリコン等を堆積し、これを選択的に除去して配線１９Ａを形成する。これにより、第１層目の配線１９Ａが形成される。   After the conductive plug 18A is formed, a metal material such as copper or aluminum or polycrystalline silicon containing impurity ions is deposited on the entire surface of the silicon substrate 11, and this is selectively removed to wire 19A. Form. As a result, the first layer wiring 19A is formed.

その後、シリコン基板１１上に、図３に示す導電性プラグ１８Ｂ、配線１９Ｂ及び層間絶縁膜２１Ｂを形成する。多層配線構造とするためである。例えば、従来法と同様にして第１層目の配線１９Ａを絶縁するように所定の膜厚のＳｉＯ2膜等の層間絶縁膜２１Ｂを形成する。その後、層間絶縁膜２１Ｂを選択的に開口してビアホールを形成した後に、タングステンなどの金属材料や不純物イオンを含有した多結晶シリコン等の導電材料を埋め込むことにより導電性プラグ１８Ｂを形成する。   Thereafter, the conductive plug 18B, the wiring 19B, and the interlayer insulating film 21B shown in FIG. 3 are formed on the silicon substrate 11. This is to provide a multilayer wiring structure. For example, an interlayer insulating film 21B such as a SiO2 film having a predetermined thickness is formed so as to insulate the first layer wiring 19A as in the conventional method. After that, after the interlayer insulating film 21B is selectively opened to form a via hole, a conductive plug 18B is formed by embedding a metal material such as tungsten or a conductive material such as polycrystalline silicon containing impurity ions.

そして、導電材料を平坦化した後に、シリコン基板１１の全面に、銅やアルミニウムなどの金属材料等を堆積し、これを選択的に除去して配線１９Ｂを形成する。これにより、第２層目の配線１９Ｂが形成される。第２層目の配線１９Ｂは従来法と同様にして、層間絶縁膜２１Ｃにより絶縁される。このとき、層間絶縁膜２１Ｃの最上層をＣＭＰ法等により平坦化するとよい。   Then, after planarizing the conductive material, a metal material such as copper or aluminum is deposited on the entire surface of the silicon substrate 11, and this is selectively removed to form the wiring 19B. As a result, the second layer wiring 19B is formed. The second layer wiring 19B is insulated by the interlayer insulating film 21C in the same manner as in the conventional method. At this time, the uppermost layer of the interlayer insulating film 21C may be planarized by a CMP method or the like.

その後、図４において、第１開口幅ｗ１を有したレジスト膜２７をシリコン基板１１上に形成する。このレジスト膜２７はフォトダイオード１５上の第２層目の配線１９Ｂを除く層間絶縁膜２１Ｃを貫き、層間絶縁膜２１Ｂを掘り込むためである。   Thereafter, in FIG. 4, a resist film 27 having a first opening width w <b> 1 is formed on the silicon substrate 11. This resist film 27 penetrates the interlayer insulating film 21C excluding the second layer wiring 19B on the photodiode 15, and digs into the interlayer insulating film 21B.

この例では二段階エッチングにより光導波路部２２を開口するに当たり、レジスト膜２７は所定のレジスト液を平坦化されたシリコン基板１１の全面に塗布し、図示しないレチクル（乾板）をマスクにして縮小露光し、未露光部分のレジスト液を除去することによりパターニングする。レチクルには光導波路開口用の第１開口幅ｗ１を有したマスクパターンが形成されたものが使用される。   In this example, when opening the optical waveguide portion 22 by two-step etching, a resist film 27 is applied on the entire surface of the flattened silicon substrate 11 and reduced exposure is performed using a reticle (dry plate) (not shown) as a mask. Then, patterning is performed by removing the resist solution in the unexposed portions. As the reticle, one having a mask pattern having a first opening width w1 for opening an optical waveguide is used.

この二段階エッチングでレチクルは２枚使用するが、一方のマスクパターンは光導波路出口側の開口径（第２開口幅ｗ２）を成す寸法であり、他方のマスクパターンは光導波路入口側の開口径（第１開口幅ｗ１）を成す寸法であり、開口面積が大きく（ｗ１＞ｗ２）なされている。つまり、開口面積をデバイス構造上の制約内で大きく設定するようになされる。第１のエッチングで開口面積の大きなマスクパターンを使用してデバイス構造の制約範囲内で可能な深さまでエッチングを進行させるためである。   In this two-step etching, two reticles are used. One mask pattern has a size that forms an opening diameter on the exit side of the optical waveguide (second opening width w2), and the other mask pattern has an opening diameter on the entrance side of the optical waveguide. It is the dimension which comprises (1st opening width w1), and the opening area is large (w1> w2). That is, the opening area is set large within the constraints on the device structure. This is because the first etching uses a mask pattern having a large opening area to advance the etching to a depth that is possible within the constraint range of the device structure.

そして、図５において、レジスト膜２７をマスクにして層間絶縁膜２１Ｃ，２１Ｂをドライエッチング（第１のエッチング）により選択的に除去して第１開口幅ｗ１の開口部２８Ａを形成する。このとき、層間絶縁膜２１Ｃ，２１Ｂのエッチングレートを考慮して所定時間だけエッチング処理を実行し、第１層目の配線１９Ａに接触しない範囲で可能な限り層間絶縁膜２１Ｂを深く開口する。その後、レジスト膜２７を除去する。   In FIG. 5, the interlayer insulating films 21C and 21B are selectively removed by dry etching (first etching) using the resist film 27 as a mask to form an opening 28A having a first opening width w1. At this time, the etching process is performed for a predetermined time in consideration of the etching rate of the interlayer insulating films 21C and 21B, and the interlayer insulating film 21B is opened as deeply as possible without contacting the first-layer wiring 19A. Thereafter, the resist film 27 is removed.

その後、図６において、フォトダイオード１５上の第１層目の配線１９Ａを除く層間絶縁膜２１Ｂ，２１Ａを貫く部分であって、第２開口幅ｗ２を有したレジスト膜２９を形成する。当該第１開口幅ｗ１の開口部２８Ａからフォトダイオード１５表面へ至る部分へ多段開口幅状の光導波路部２２を形成するためである。   Thereafter, in FIG. 6, a resist film 29 having a second opening width w2 is formed at a portion that penetrates the interlayer insulating films 21B and 21A excluding the first-layer wiring 19A on the photodiode 15. This is because the optical waveguide portion 22 having a multi-stage opening width is formed in a portion from the opening portion 28A having the first opening width w1 to the surface of the photodiode 15.

レジスト膜２９は所定のレジスト液を平坦化されたシリコン基板１１の全面に塗布し、図示しないレチクル（乾板）をマスクにして縮小露光し、未露光部分のレジスト液を除去することによりパターニングする。レチクルには光導波路開口用の第２開口幅ｗ２を有したマスクパターンが形成されている。この例でレジスト膜２９の第２開口幅ｗ２は第１開口幅ｗ１よりも狭くされる。   The resist film 29 is patterned by applying a predetermined resist solution to the entire surface of the flattened silicon substrate 11, performing reduction exposure using a reticle (dry plate) (not shown) as a mask, and removing the resist solution in the unexposed portions. A mask pattern having a second opening width w2 for opening the optical waveguide is formed on the reticle. In this example, the second opening width w2 of the resist film 29 is made narrower than the first opening width w1.

そして、図７において、レジスト膜２９をマスクにして開口部２８Ａ内の層間絶縁膜２１Ｂをドライエッチング（第２のエッチング）により選択的に除去し、更に、層間絶縁膜２１Ａを貫き、当該開口部２８Ａ内でフォトダイオード表面（ゲート絶縁膜）を露出する第２開口幅ｗ２の開口部２８Ｂを形成する。このとき、予めゲート絶縁膜１３上に形成した置いたＳｉＮ膜１６をストッパにして層間絶縁膜２１Ａを開口する。   Then, in FIG. 7, using the resist film 29 as a mask, the interlayer insulating film 21B in the opening 28A is selectively removed by dry etching (second etching), and further, penetrates the interlayer insulating film 21A and opens the opening. An opening 28B having a second opening width w2 exposing the photodiode surface (gate insulating film) is formed in 28A. At this time, the interlayer insulating film 21A is opened using the SiN film 16 previously formed on the gate insulating film 13 as a stopper.

エッチングはＳｉＮ膜１６を検出して止める。その後、レジスト膜２９を除去し、更に、ダウンフロープラズマ処理法を利用したドライエッチングによりＳｉＮ膜１６を除去する。ダウンフロープラズマ処理法によれば、化学反応を利用するので、高選択比によってＳｉＮ膜１６を除去することができる。ｐ型の不純物領域１５Ｂ上のゲート絶縁膜１３を保護するためである。これにより、多段開口幅状の開口部２８が形成される。   Etching is stopped by detecting the SiN film 16. Thereafter, the resist film 29 is removed, and the SiN film 16 is further removed by dry etching using a downflow plasma processing method. According to the down flow plasma processing method, since a chemical reaction is used, the SiN film 16 can be removed with a high selectivity. This is for protecting the gate insulating film 13 on the p-type impurity region 15B. Thereby, the opening part 28 of multistage opening width shape is formed.

その後、図８において、多段開口幅状の開口部２８内に透明性の膜３１を埋め込む。透明性の膜３１には、層間絶縁膜２１Ａ，２１Ｂ，２１Ｃに比べて屈折率が高い材料が使用される。透明性の膜３１には例えばＰ−ＳＩＮ膜が使用される。Ｐ−ＳＩＮ膜は高密度プラズマＣＶＤ法によって堆積し形成するようになされる。このＰ−ＳＩＮ膜の堆積の際に、多段開口幅状の開口部への原料ガス＋堆積物（ラジカル）の供給が促進されるので、Ｐ−ＳＩＮ膜の埋め込み性が向上する。その後、ＣＭＰ法やエッチバック法によりグローバル平坦化処理を施す。   Thereafter, in FIG. 8, a transparent film 31 is embedded in the opening 28 having a multistage opening width. For the transparent film 31, a material having a higher refractive index than the interlayer insulating films 21A, 21B, and 21C is used. For example, a P-SIN film is used as the transparent film 31. The P-SIN film is deposited and formed by a high density plasma CVD method. When the P-SIN film is deposited, the supply of the source gas + the deposit (radical) to the opening having the multi-stage opening width is promoted, so that the embedding property of the P-SIN film is improved. Thereafter, a global planarization process is performed by a CMP method or an etch back method.

そして、図８に示した平坦化処理後のシリコン基板１１上に、従来法と同様にして図９に示す保護用の膜の一例となるパッシベーション膜２３、平坦化用の膜２４及びカラーフィルタ２５を順次積層し形成する。その後、カラーフィルタ２５上に集光用の光学素子の一例となるオンチップレンズ２６を形成する。オンチップレンズ２６は球面状に形成される。これにより、図１に示した多段開口幅状の光導波路部２２を有する半導体撮像装置１００が完成する。   Then, on the silicon substrate 11 after the flattening process shown in FIG. 8, a passivation film 23, a flattening film 24, and a color filter 25 which are examples of the protective film shown in FIG. Are sequentially stacked. Thereafter, an on-chip lens 26 as an example of a condensing optical element is formed on the color filter 25. The on-chip lens 26 is formed in a spherical shape. Thereby, the semiconductor imaging device 100 having the multi-stage opening width-shaped optical waveguide portion 22 shown in FIG. 1 is completed.

このように、本発明に係る半導体撮像装置の製造方法によれば、半導体撮像装置１００の多層配線化及びその多画素化に伴い、深さ対開口幅の比であるアスペクト比が高くなった場合でも、開口部２８Ａの開口面積を大きくすることにより、当該開口部２８Ａのアスペクト比を実行的に低減させることができ、単一開口幅状の光導波路部２２に比べて、透明性の膜３１を多段開口幅状の開口部２８等に確実かつ再現性良く埋め込むことができる。ＣＶＤ法等による透明性の膜３１の埋め込み性が向上する。   As described above, according to the method for manufacturing a semiconductor imaging device according to the present invention, the aspect ratio, which is the ratio of the depth to the opening width, increases as the semiconductor imaging device 100 is formed with multi-layer wiring and the number of pixels. However, by increasing the opening area of the opening portion 28A, the aspect ratio of the opening portion 28A can be reduced effectively, and the transparent film 31 can be compared with the optical waveguide portion 22 having a single opening width. Can be reliably and reproducibly embedded in the opening 28 having a multistage opening width. The embedding property of the transparent film 31 by the CVD method or the like is improved.

従って、フォトダイオード１５上で最上部の開口幅ｗ１に比べて最下部の開口幅ｗ２を狭くなされた集光構造を有する光導波路部２２を形成することができる。この多段開口幅状の光導波路部２２の集光構造はアスペクト比が高くなるほど効果が大きい。これにより、多段開口幅状の光導波路部２２を備えた高信頼度の固体撮像装置や電界効果型の撮像装置等を再現性良く製造することができる。   Therefore, it is possible to form the optical waveguide portion 22 having a condensing structure in which the lowermost opening width w2 is made narrower on the photodiode 15 than the uppermost opening width w1. The condensing structure of the optical waveguide portion 22 having the multi-stage aperture width is more effective as the aspect ratio becomes higher. As a result, a highly reliable solid-state imaging device, a field effect imaging device, and the like including the optical waveguide portion 22 having a multistage aperture width can be manufactured with high reproducibility.

この発明はカラーフィルタ上のオンチップレンズから取り込んだ光を半導体撮像素子に導く光導波路構造を有する固体撮像素子や電界効果型の撮像素子に適用して極めて好適である。   The present invention is extremely suitable when applied to a solid-state image sensor having a light guide structure for guiding light taken from an on-chip lens on a color filter to a semiconductor image sensor, or a field effect type image sensor.

本発明に係る実施形態としての半導体撮像装置１００の構造例を示す断面図である。It is sectional drawing which shows the structural example of the semiconductor imaging device 100 as embodiment which concerns on this invention. Ａ及びＢは半導体撮像装置の形成例（その１）を示す断面図である。A and B are cross-sectional views illustrating a first example of forming a semiconductor imaging device. 半導体撮像装置１００の形成例（その２）を示す断面図である。FIG. 10 is a cross-sectional view illustrating a formation example (No. 2) of the semiconductor imaging device 100; 半導体撮像装置１００の形成例（その３）を示す断面図である。FIG. 10 is a cross-sectional view showing a formation example (No. 3) of the semiconductor imaging device 100; 半導体撮像装置１００の形成例（その４）を示す断面図である。FIG. 10 is a cross-sectional view showing a formation example (No. 4) of the semiconductor imaging device 100; 半導体撮像装置１００の形成例（その５）を示す断面図である。FIG. 11 is a cross-sectional view illustrating a fifth example of forming the semiconductor imaging device 100. 半導体撮像装置１００の形成例（その６）を示す断面図である。FIG. 11 is a cross-sectional view showing a formation example (No. 6) of the semiconductor imaging device 100; 半導体撮像装置１００の形成例（その７）を示す断面図である。FIG. 11 is a cross-sectional view illustrating a seventh example of forming the semiconductor imaging device 100. 半導体撮像装置１００の形成例（その８）を示す断面図である。FIG. 11 is a cross-sectional view illustrating a formation example (No. 8) of the semiconductor imaging device 100; 従来例に係る半導体撮像装置１０の構造例を示す断面図である。It is sectional drawing which shows the structural example of the semiconductor imaging device 10 which concerns on a prior art example. Ａ及びＢは問題点を説明するため半導体撮像装置１０’の構造例及びその形成例を示す断面図である。A and B are cross-sectional views illustrating a structural example and a formation example of the semiconductor imaging device 10 ′ for explaining the problem.

符号の説明Explanation of symbols

１１・・・シリコン基板（基板）、１２・・・フィールド絶縁膜（絶縁性の膜）、１３・・・ゲート絶縁膜（絶縁性の膜）、１４・・・ｐ−ＷＥＬＬ（半導体埋め込み層）、１５・・・フォトダイオード、１５Ａ・・・ｎ型の不純物領域、１５Ｂ・・・ｐ型の不純物領域、１６・・・ストッパ用のＳｉＮ膜、１７・・・転送ゲート、１８，１８Ａ，１８Ｂ，１８Ｃ・・・導電性プラグ（導電性の膜）、１９，１９Ａ，１９Ｂ，１９Ｃ・・・配線（導電性の膜）、２１・・・層間絶縁膜（絶縁性の膜）、２２・・・光導波路部、２３・・・パッシベーション膜（保護用の膜）、２４・・・平坦化用の膜、２５・・・カラーフィルタ、２６・・・オンチップレンズ（集光用の光学素子）、３１・・・透明性の膜、１００・・・半導体撮像装置   DESCRIPTION OF SYMBOLS 11 ... Silicon substrate (substrate), 12 ... Field insulating film (insulating film), 13 ... Gate insulating film (insulating film), 14 ... p-WELL (semiconductor embedded layer) 15 ... photodiode, 15A ... n-type impurity region, 15B ... p-type impurity region, 16 ... SiN film for stopper, 17 ... transfer gate, 18, 18A, 18B , 18C ... conductive plug (conductive film), 19, 19A, 19B, 19C ... wiring (conductive film), 21 ... interlayer insulating film (insulating film), 22 ... Optical waveguide part, 23 ... Passivation film (protective film), 24 ... Flattening film, 25 ... Color filter, 26 ... On-chip lens (Condensing optical element) 31 ... Transparent film, 100 ... Semiconductor imaging device

Claims (12)

半導体撮像素子を有する所定の基板と、
前記基板に接続された導電性の膜と、
前記導電性の膜を絶縁するために前記半導体撮像素子を含む基板上に設けられた絶縁性の膜と、
前記半導体撮像素子上の導電性の膜を除く前記絶縁性の膜を貫く部分であって、当該絶縁性の膜最上部から半導体撮像素子表面へ至る部分に設けられ、最上部が第１開口幅となされ、最下部が前記第１開口幅に比べて狭くなされた第２開口幅を有するプラズマＳＩＮ膜から構成された多段開口幅状の光導波路部とを備え、
前記導電性の膜の一部が前記光導波路部の第１開口幅で規定される領域下の前記絶縁性の膜にまで入り込んでいる半導体撮像装置。 A predetermined substrate having a semiconductor imaging device;
A conductive film connected to the substrate;
An insulating film provided on a substrate including the semiconductor imaging device to insulate the conductive film;
A portion penetrating the insulating film excluding the conductive film on the semiconductor imaging device, the portion extending from the top of the insulating film to the surface of the semiconductor imaging device, the top being the first opening width An optical waveguide portion having a multi-stage opening width formed of a plasma SIN film having a second opening width that is narrower than the first opening width at the bottom.
A semiconductor imaging device in which a part of the conductive film penetrates into the insulating film below a region defined by the first opening width of the optical waveguide portion. 前記光導波路部の第１開口幅で規定される領域の高さの位置する絶縁性の膜内に前記導電性の膜の一部が設けられる請求項１に記載の半導体撮像装置。   The semiconductor imaging device according to claim 1, wherein a part of the conductive film is provided in an insulating film positioned at a height of a region defined by the first opening width of the optical waveguide portion. 前記光導波路部の第１開口幅で規定される領域の底部が前記基板に対して水平に設けられる請求項２に記載の半導体撮像装置。   The semiconductor imaging device according to claim 2, wherein a bottom portion of a region defined by the first opening width of the optical waveguide portion is provided horizontally with respect to the substrate. 前記光導波路部は、
透明性の膜から構成される請求項３に記載の半導体撮像装置。 The optical waveguide portion is
The semiconductor imaging device according to claim 3, comprising a transparent film. 前記光導波路部を含む前記基板上を覆うように設けられた保護用の膜と、
前記保護用の膜上に設けられた平坦化用の膜と、
前記平坦化用の膜上に設けられたカラーフィルタと、
前記カラーフィルタ上に設けられた集光用の光学素子とを備える請求項１に記載の半導体撮像装置。 A protective film provided to cover the substrate including the optical waveguide portion;
A planarizing film provided on the protective film;
A color filter provided on the planarizing film;
The semiconductor imaging device according to claim 1, further comprising a condensing optical element provided on the color filter. 前記光導波路部は、
前記プラズマＳＩＮ膜が堆積された後、ＣＭＰ（Ｃhemical Ｍechanical Ｐolishing）法で平坦化処理されて構成される請求項１に記載の半導体撮像装置。 The optical waveguide portion is
The semiconductor imaging device according to claim 1, wherein after the plasma SIN film is deposited, a planarization process is performed by a CMP (Chemical Mechanical Polishing) method. 所望の基板に半導体撮像素子を形成する工程と、
前記半導体撮像素子を形成した基板上に導電性の膜及び絶縁性の膜を形成する工程と、
前記半導体撮像素子上の導電性の膜を除く絶縁性の膜を貫く部分であって、当該絶縁性の膜最上部から半導体撮像素子表面へ至る部分に、最上部を第１開口幅とし、最下部を前記第１開口幅に比べて狭くなされる第２開口幅を有するプラズマＳＩＮ膜から成る多段開口幅状の光導波路部を形成する工程とを有し、
前記基板上に導電性の膜を形成する際に、前記光導波路部の第１開口幅で規定される領域下の前記絶縁性の膜にまで前記導電性の膜の一部を入り込むようになされる半導体撮像装置の製造方法。 Forming a semiconductor image sensor on a desired substrate;
Forming a conductive film and an insulating film on a substrate on which the semiconductor imaging element is formed;
A portion that penetrates the insulating film excluding the conductive film on the semiconductor image pickup device and has a first opening width at a portion extending from the uppermost portion of the insulating film to the surface of the semiconductor image pickup device. Forming a multistage opening width-shaped optical waveguide portion made of a plasma SIN film having a second opening width whose lower portion is narrower than the first opening width;
When forming the conductive film on the substrate, a part of the conductive film is inserted into the insulating film below the region defined by the first opening width of the optical waveguide portion. A method for manufacturing a semiconductor imaging device. 前記光導波路部を形成する際に、
当該光導波路部の最上部の開口幅をｗ１とし、その最下部の開口幅をｗ２としたとき、前記開口幅ｗ１に比べて前記開口幅ｗ２を狭く（ｗ１＞ｗ２）なるような多段開口幅状の開口部を形成する工程を有し、
前記多段開口幅状の開口部を形成する際に、
前記半導体撮像素子上の導電性の膜を除く絶縁性の膜を選択的に除去して第１開口幅の開口部を形成する工程と、
前記開口部内の絶縁性の膜を選択的に除去して前記半導体撮像素子表面を露出する第２開口幅の開口部を形成する工程とを含む請求項７に記載の半導体撮像装置の製造方法。 When forming the optical waveguide portion,
A multistage opening width in which the opening width w2 is narrower (w1> w2) than the opening width w1, where w1 is the uppermost opening width of the optical waveguide portion and w2 is the lowermost opening width. Having a step of forming a shaped opening,
When forming the multi-stage opening width-shaped opening,
Selectively removing an insulating film excluding a conductive film on the semiconductor imaging element to form an opening having a first opening width;
The method of manufacturing a semiconductor imaging device according to claim 7, further comprising: selectively removing an insulating film in the opening to form an opening having a second opening width that exposes the surface of the semiconductor imaging element. 前記光導波路部の第１開口幅で規定される領域の高さの位置する絶縁性の膜内に前記導電性の膜の一部を形成する工程を有する請求項８に記載の半導体撮像装置の製造方法。   The semiconductor imaging device according to claim 8, further comprising a step of forming a part of the conductive film in an insulating film positioned at a height of a region defined by the first opening width of the optical waveguide portion. Production method. 前記光導波路部の第１開口幅で規定される領域の底部が前記基板に対して水平に形成する工程を有する請求項９に記載の半導体撮像装置の製造方法。   The method for manufacturing a semiconductor imaging device according to claim 9, further comprising a step of forming a bottom portion of a region defined by the first opening width of the optical waveguide portion horizontally with respect to the substrate. 前記多段開口幅状の開口部内に透明性の膜を埋め込む請求項７に記載の半導体撮像装置の製造方法。   The method of manufacturing a semiconductor imaging device according to claim 7, wherein a transparent film is embedded in the multi-stage opening width-shaped opening. 前記多段開口幅状の開口部内に透明性の膜を埋め込んだ後に、
前記開口部内の透明性の膜を含む前記基板上を覆うように保護用の膜を形成する工程と、
前記保護用の膜上に平坦化用の膜を形成する工程と、
前記平坦化用の膜上にカラーフィルタを形成する工程と、
前記カラーフィルタ上に集光用の光学素子を形成する工程とを含む請求項１１に記載の半導体撮像装置の製造方法。 After embedding a transparent film in the multi-stage opening width opening,
Forming a protective film so as to cover the substrate including the transparent film in the opening;
Forming a flattening film on the protective film;
Forming a color filter on the planarizing film;
The method of manufacturing a semiconductor imaging device according to claim 11, further comprising: forming a condensing optical element on the color filter.
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