JP2008205515A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP2008205515A
JP2008205515A JP2008140724A JP2008140724A JP2008205515A JP 2008205515 A JP2008205515 A JP 2008205515A JP 2008140724 A JP2008140724 A JP 2008140724A JP 2008140724 A JP2008140724 A JP 2008140724A JP 2008205515 A JP2008205515 A JP 2008205515A
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plate thickness
insulating substrate
semiconductor device
resin
manufacturing
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Japanese (ja)
Inventor
Haruo Hyodo
治雄 兵藤
Takayuki Tani
孝行 谷
Takao Shibuya
隆生 渋谷
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a small package having a reduced mounting area and to provide a manufacturing method of a semiconductor device capable of improving handlability in manufacturing. <P>SOLUTION: This manufacturing method of a semiconductor device includes a step of preparing an insulating substrate having a locally thin first plate thickness and a second plate thickness thicker than the first plate thickness; a step of fixing a plurality of semiconductor chips on a portion of the first plate thickness; a step of electrically connecting the electrodes of the semiconductor chips to an internal electrode formed on a portion having the second plate thickness; a step of coating the upper part of the insulating substrate with an insulating resin and sealing the semiconductor chips with a common resin layer; and a step of cutting the insulating substrate and the insulating resin so that the semiconductor chips can be separated into individual chips. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は半導体装置に関し、特にパッケージ外形を縮小して実装面積を低減でき、更には製造に伴う材料の無駄を削減できる半導体装置の製造方法に関する。   The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that can reduce the package area by reducing the package outer shape and further reduce the waste of materials associated with the manufacturing.

半導体装置の製造においては、ウェハからダイシングして分離した半導体チップをリードフレームに固着し、金型と樹脂注入によるトランスファーモールドによってリードフレーム上に固着された半導体チップを封止し、封止された半導体チップを個々の半導体装置毎に分離するという工程が行われている。このリードフレームには短冊状あるいはフープ状のフレームが用いられており、いずれにしろ１回の封止工程で複数個の半導体装置が同時に封止されている。   In the manufacture of a semiconductor device, a semiconductor chip diced and separated from a wafer is fixed to a lead frame, and the semiconductor chip fixed on the lead frame is sealed by a transfer mold using a mold and resin injection. A process of separating a semiconductor chip for each individual semiconductor device is performed. A strip-like or hoop-like frame is used for the lead frame, and in any case, a plurality of semiconductor devices are simultaneously sealed in one sealing step.

図８は、トランスファーモールド工程の状況を示す図である。トランスファーモールド工程では、ダイボンド、ワイヤボンドにより半導体チップ１が固着されたリードフレーム２を、上下金型３Ａ、３Ｂで形成したキャビティ４の内部に設置し、キャビティ４内にエポキシ樹脂を注入することにより、半導体チップ１の封止が行われる。このようなトランスファーモールド工程の後、リードフレーム２を各半導体チップ１毎に切断して、個別の半導体装置が製造される（例えば特開平０５−１２９４７３号）。   FIG. 8 is a diagram showing the situation of the transfer molding process. In the transfer molding process, the lead frame 2 to which the semiconductor chip 1 is fixed by die bonding or wire bonding is placed inside the cavity 4 formed by the upper and lower molds 3A and 3B, and epoxy resin is injected into the cavity 4 The semiconductor chip 1 is sealed. After such a transfer molding process, the lead frame 2 is cut for each semiconductor chip 1 to manufacture individual semiconductor devices (for example, Japanese Patent Laid-Open No. 05-129473).

この時、図９に示すように、金型３の表面には多数個のキャビティ４ａ〜４ｄと、樹脂を注入するための樹脂源５と、ランナー６、及びランナー６から各キャビティ４ａ〜４ｄに樹脂を流し込むためのゲート７とが設けられている。これらは全て金型３表面に設けた溝である。短冊状のリードフレームであれば、１本のリードフレームに例えば１０個の半導体チップ１が搭載されており、１本のリードフレームに対応して、１０個のキャビティ４と１０本のゲート７、及び１本のランナー６が設けられる。そして、金型３表面には例えばリードフレーム２０本分のキャビティ４が設けられる。   At this time, as shown in FIG. 9, a large number of cavities 4a to 4d, a resin source 5 for injecting resin, the runner 6, and the runner 6 to the cavities 4a to 4d on the surface of the mold 3. A gate 7 for pouring resin is provided. These are all grooves provided on the surface of the mold 3. In the case of a strip-like lead frame, for example, ten semiconductor chips 1 are mounted on one lead frame, and corresponding to one lead frame, ten cavities 4 and ten gates 7, And one runner 6 is provided. For example, a cavity 4 for 20 lead frames is provided on the surface of the mold 3.

図１０は、上記のトランスファーモールドによって製造した半導体装置を示す図である。トランジスタ等の素子が形成された半導体チップ１がリードフレームのアイランド８上に半田等のろう材９によって固着実装され、半導体チップ１の電極パッドとリード１０とがワイヤ１１で接続され、半導体チップ１の周辺部分が上記キャビティの形状に合致した樹脂１２で被覆され、樹脂１２の外部にリード端子１０の先端部分が導出されたものである。
特開平０５−１２９４７３号 FIG. 10 is a view showing a semiconductor device manufactured by the transfer mold described above. The semiconductor chip 1 on which elements such as transistors are formed is fixedly mounted on the island 8 of the lead frame by a soldering material 9 such as solder, and the electrode pads of the semiconductor chip 1 and the leads 10 are connected by wires 11. The peripheral portion of the lead terminal 10 is covered with the resin 12 matching the shape of the cavity, and the leading end portion of the lead terminal 10 is led out of the resin 12.
JP 05-129473 A

従来のパッケージでは、外部接続用のリード端子１０を樹脂１２から突出させるので、リード端子１０の先端部までの距離を実装面積として考慮しなくてはならず、樹脂１２の外形寸法より実装面積の方が遥かに大きくなるという欠点がある。   In the conventional package, since the lead terminal 10 for external connection protrudes from the resin 12, the distance to the tip of the lead terminal 10 must be taken into consideration as the mounting area. The disadvantage is that it is much larger.

また、トランスファーモールド技術では、圧力をかけ続けた状態で硬化させることから、ランナー６とゲート７においても樹脂が硬化し、このランナー６等に残った樹脂は廃棄処分となる。そのため、上記のリードフレームを用いた手法では、製造すべき半導体装置個々にゲート７を設けるので、樹脂の利用効率が悪く、樹脂の量に対して製造できる半導体装置の個数が少ないという欠点があった。   In the transfer mold technique, the resin is cured at the runner 6 and the gate 7 because the resin is cured while pressure is continuously applied, and the resin remaining on the runner 6 and the like is disposed of. For this reason, the above-described method using the lead frame has the disadvantage that the use efficiency of the resin is poor and the number of semiconductor devices that can be manufactured is small with respect to the amount of resin because the gate 7 is provided for each semiconductor device to be manufactured. It was.

上記に鑑み、本発明に係る半導体装置の製造方法は、局所的に薄い第１の板厚と、前記第１の板厚よりも厚い第２の板厚とを持つ絶縁基板を準備する工程と、前記第１の板厚の箇所に、多数個の半導体チップを固着する工程と、前記半導体チップの電極と、前記第２の板厚を持つ箇所に形成した内部電極とを電気的に接続する工程と、前記絶縁基板の上部を絶縁樹脂で被覆し、前記多数個の半導体チップを共通の樹脂層で封止する工程と、前記絶縁基板と前記絶縁樹脂とを、前記半導体チップの各々を分離するように切断する工程と、を具備することを特徴とする。   In view of the above, a method of manufacturing a semiconductor device according to the present invention includes a step of preparing an insulating substrate having a locally thin first plate thickness and a second plate thickness that is thicker than the first plate thickness. The step of fixing a large number of semiconductor chips to the first plate thickness portion is electrically connected to the electrode of the semiconductor chip and the internal electrode formed at the second plate thickness portion. Separating each of the semiconductor chips from a step, a step of covering an upper portion of the insulating substrate with an insulating resin, and sealing the plurality of semiconductor chips with a common resin layer; and the insulating substrate and the insulating resin And a step of cutting as described above.

本発明によれば、リードフレームを用いた半導体装置よりも更に小型化できるパッケージ構造を提供できる利点を有する。このとき、リード端子が突出しない構造であるので、実装したときの占有面積を低減し、高密度実装を実現できる。   The present invention has an advantage of providing a package structure that can be further reduced in size as compared with a semiconductor device using a lead frame. At this time, since the lead terminal does not protrude, the occupied area when mounted can be reduced, and high-density mounting can be realized.

更に、多数個の半導体チップ２２を連続した樹脂層２３で一括モールドするので、装置１個あたりに消費する樹脂の量を節約でき、無駄を少なくすることができる。   Furthermore, since a large number of semiconductor chips 22 are collectively molded with the continuous resin layer 23, the amount of resin consumed per device can be saved and waste can be reduced.

加えて、第１の絶縁基板２１ａと第２の絶縁基板２１ｂとで板厚の差を作ることにより、装置外形の高さ（ｔ３）を抑えて小型パッケージを実現でき、製造上の大判基板３２の取り扱いを容易にし、ワイヤボンドのボンダビリティを改善できる利点を有する。   In addition, by making a difference in plate thickness between the first insulating substrate 21a and the second insulating substrate 21b, a small package can be realized while suppressing the height (t3) of the outer shape of the device, and a large substrate 32 in manufacturing. This makes it easy to handle and improves the bondability of wire bonds.

以下に本発明の実施の形態を詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail.

図１（Ａ）は本発明の半導体装置を示す断面図、図１（Ｂ）はその平面図、図２（Ａ）は装置を上方から見たときの斜視図、図２（Ｂ）は装置を下方から見たときの斜視図である。   1A is a cross-sectional view showing a semiconductor device of the present invention, FIG. 1B is a plan view thereof, FIG. 2A is a perspective view of the device viewed from above, and FIG. It is a perspective view when seeing from below.

図１、図２を参照して、この半導体装置は、第１と第２の絶縁基板２１ａ、２１ｂを貼着した絶縁基板２１と、第１の絶縁基板２１ａ上に固着した、トランジスタ素子などを形成した半導体チップ２２と、半導体チップ２２を含めて全体を封止する樹脂層２３とを有する。   Referring to FIGS. 1 and 2, this semiconductor device includes an insulating substrate 21 having first and second insulating substrates 21a and 21b attached thereto, and a transistor element fixed on the first insulating substrate 21a. The formed semiconductor chip 22 and the resin layer 23 that seals the whole including the semiconductor chip 22 are included.

第１の絶縁基板２１ａは板厚（図１：ｔ１）が５０〜２００μのセラミックやガラスエポキシ等からなる基板であり、その表面には金メッキ層によってアイランド部２４ａが形成されており、裏面には同じく金メッキ層によって外部電極２５ａが形成されている。第１の絶縁基板２１ａにはこれを貫通するスルーホール２６ａが設けられており、該スルーホール２６ａの内部がタングステン、Ａｇ−Ｐｄ等の導電材料によって埋設されてアイランド部２４と外部電極２５ａとが電気的に接続されている。   The first insulating substrate 21a is a substrate made of ceramic, glass epoxy, or the like having a plate thickness (FIG. 1: t1) of 50 to 200 μm, and an island portion 24a is formed on the front surface by a gold plating layer, and on the back surface. Similarly, an external electrode 25a is formed by a gold plating layer. The first insulating substrate 21a is provided with a through hole 26a penetrating through the first insulating substrate 21a. The inside of the through hole 26a is buried with a conductive material such as tungsten or Ag-Pd so that the island portion 24 and the external electrode 25a are connected. Electrically connected.

第２の絶縁基板１１ｂは板厚（図１：ｔ２）が１００〜２５０μのセラミックやガラスエポキシ等からなる基板であり、半導体チップ２２を搭載すべき領域を除いた大きさを有し、第１の絶縁基板２１ａに接着され一体化している。第２の絶縁基板２１ｂの表面には金メッキ層によって内部電極２４ｂ、２４ｃが形成されている。その下部の第１の絶縁基板２１ａと第２の絶縁基板２１ｂにはこれらを貫通するスルーホール２６ｂ、２６ｃが設けられ、該スルーホール２６ｂ、２６ｃの内部がタングステン、Ａｇ−Ｐｄ等の導電材料によって埋設されて内部電極２４ｂ、２４ｃと第１の絶縁基板２１ａの裏面に設けた外部電極２５ｂ、２５ｃとが電気的に接続されている。   The second insulating substrate 11b is a substrate made of ceramic, glass epoxy, or the like having a plate thickness (FIG. 1: t2) of 100 to 250 μm, and has a size excluding the region where the semiconductor chip 22 is to be mounted. The insulating substrate 21a is bonded and integrated. Internal electrodes 24b and 24c are formed by a gold plating layer on the surface of the second insulating substrate 21b. The first insulating substrate 21a and the second insulating substrate 21b in the lower part thereof are provided with through holes 26b and 26c penetrating therethrough, and the insides of the through holes 26b and 26c are made of a conductive material such as tungsten or Ag-Pd. The embedded internal electrodes 24b and 24c and the external electrodes 25b and 25c provided on the back surface of the first insulating substrate 21a are electrically connected.

半導体チップ２２は第１の絶縁基板２１ａのアイランド部２４ａにＡｇペーストなどの接着剤２７でダイボンドされており、半導体チップ２２表面の電極パッド２８と第２の絶縁基板２１ｂ表面に形成した内部電極２４ｂ、２４ｃとが金ワイヤ２９によって各々ワイヤボンドされている。この結果、外部電極２５ａがコレクタ電極となり、外部電極２５ｂ、２５ｃがベースとエミッタの電極となる。そして、ダイボンド、ワイヤボンドが成された絶縁基板２１の上を、エポキシ系の絶縁樹脂層２３が被覆して半導体チップ２２を封止し、且つ略直方体のパッケージ形状を形成している。   The semiconductor chip 22 is die-bonded to the island portion 24a of the first insulating substrate 21a with an adhesive 27 such as an Ag paste, and the electrode pads 28 on the surface of the semiconductor chip 22 and the internal electrodes 24b formed on the surface of the second insulating substrate 21b. , 24c are wire-bonded to each other by a gold wire 29. As a result, the external electrode 25a becomes a collector electrode, and the external electrodes 25b and 25c become base and emitter electrodes. The insulating substrate 21 on which die bonding and wire bonding are formed is covered with an epoxy insulating resin layer 23 to seal the semiconductor chip 22 and form a substantially rectangular parallelepiped package shape.

パッケージ外形のうち、少なくとも４つの側面２３ａ〜２３ｄは金型表面によらず切断面によって構成されている。第１の絶縁基板２１ａの外周端面３０及び第２の絶縁基板２１ｂの外周端面３２は樹脂層２３表面に露出しており、樹脂層２３の側面２３ａ、２３ｂ、２３ｃ、２３ｄと連続する同一平面を成している。これらは、樹脂層２３と各絶縁基板２１ａ、２１ｂとが、同時に切断工程、例えばダイシングブレードによって切断されることによって同一平面が得られる。尚、図示したとおり、第２の絶縁基板２１ｂの外周端面３１の一つは樹脂層２３に埋没している。   Of the package outer shape, at least four side surfaces 23a to 23d are constituted by cut surfaces regardless of the mold surface. The outer peripheral end surface 30 of the first insulating substrate 21a and the outer peripheral end surface 32 of the second insulating substrate 21b are exposed on the surface of the resin layer 23, and are on the same plane continuous with the side surfaces 23a, 23b, 23c, 23d of the resin layer 23. It is made. These are obtained by cutting the resin layer 23 and the respective insulating substrates 21a and 21b at the same time by a cutting process, for example, a dicing blade. As shown in the drawing, one of the outer peripheral end faces 31 of the second insulating substrate 21 b is buried in the resin layer 23.

而して、本発明の半導体装置は、外部電極２５ａ、２５ｂ、２５ｃがパッケージの外形寸法より突出しない構造であるので、リードフレームを用いた半導体装置よりも更に小型化でき、更には実装したときの占有面積を低減し、高密度実装を実現できるものである。   Thus, the semiconductor device according to the present invention has a structure in which the external electrodes 25a, 25b, and 25c do not protrude from the outer dimensions of the package, so that the semiconductor device can be further reduced in size and further mounted when mounted. It is possible to realize a high-density mounting by reducing the area occupied by the substrate.

更に、絶縁基板２１の表面に形成したアイランド部２４ａと内部電極２４ｂ、２４ｃの金メッキ層は、樹脂層２３の側面２３ａ〜２３ｄには達せず、絶縁基板２１の全周にわたって、その端から３０〜７０μの距離だけ後退されている。また、第１の絶縁基板２１ａの裏面に形成した外部電極２５ａ、２５ｂ、２５ｃも、第１の絶縁基板２１ａの外周端面３０から後退されている。この構成は、２つの利点を生む。   Furthermore, the gold plating layer of the island portion 24a and the internal electrodes 24b and 24c formed on the surface of the insulating substrate 21 does not reach the side surfaces 23a to 23d of the resin layer 23, and is 30 to 30 mm from the end over the entire circumference of the insulating substrate 21. It is retracted by a distance of 70μ. The external electrodes 25a, 25b, 25c formed on the back surface of the first insulating substrate 21a are also retracted from the outer peripheral end surface 30 of the first insulating substrate 21a. This configuration produces two advantages.

利点の１つは、側面２３ａ、２３ｂ、２３ｃ、２３ｄをダイシングブレードで切断したときに得られる。即ち、導電材料として優れた性質を持つ金メッキ層は、同時に優れた延性を持つ素材である。そのため、金メッキ層をダイシングブレードで切断すると、ブレードによって金メッキ層が引き延ばされてバリが生じ、これが外観不良となるのである。ダイシングブレードに接触させないことで、この様な事故を防止できる。   One advantage is obtained when the side surfaces 23a, 23b, 23c, 23d are cut with a dicing blade. That is, a gold plating layer having excellent properties as a conductive material is a material having excellent ductility at the same time. For this reason, when the gold plating layer is cut with a dicing blade, the gold plating layer is stretched by the blade to generate burrs, which causes poor appearance. Such an accident can be prevented by not contacting the dicing blade.

利点の２つは、上記の半導体装置をプリント基板上に実装したときに得られる。即ち、上記の半導体装置を実装するときは、プリント基板上に形成した導電パターンに第１の絶縁基板２１ａの外部電極２５ａ、２５ｂ、２５ｃを位置あわせして設置し、両者をはんだ付けすることによって固着するのであるが、金は半田に対して塗れ性が極めて高いという特質を持つ。そのため、パッケージの側面２３ａ〜２３ｄに金メッキ層が露出して半田と接触すると、半田が絶縁基板２１と樹脂層２３との界面に進入して、樹脂剥がれや電気的短絡という事故を引き起こすのである。パッケージの側面に金メッキ層を露出させないことで、この様な事故を防止できる。   Two of the advantages are obtained when the semiconductor device is mounted on a printed circuit board. That is, when mounting the semiconductor device described above, the external electrodes 25a, 25b, 25c of the first insulating substrate 21a are aligned and placed on the conductive pattern formed on the printed circuit board, and both are soldered. Although it adheres, gold has the property that it is very wettable with solder. Therefore, when the gold plating layer is exposed on the side surfaces 23a to 23d of the package and comes into contact with the solder, the solder enters the interface between the insulating substrate 21 and the resin layer 23, causing an accident such as resin peeling or electrical short circuit. Such an accident can be prevented by not exposing the gold plating layer on the side surface of the package.

本発明の半導体装置は、パッケージ外形の側面２３ａ〜２３ｂが切断面によって構成されている。即ち、絶縁基板２１を支持基板として半導体チップ２２を搭載し、モールドしてからこれらを切断する。そのため、１枚の大判の絶縁基板から切断して上記の半導体装置を得ることになる。   In the semiconductor device of the present invention, side surfaces 23a to 23b of the package outer shape are constituted by cut surfaces. That is, the semiconductor chip 22 is mounted using the insulating substrate 21 as a support substrate, molded, and then cut. Therefore, the semiconductor device is obtained by cutting from one large insulating substrate.

而して、本発明の骨子は、半導体チップ２１を搭載する箇所の絶縁基板２１の板厚が薄く、その他に板厚が厚い部分を具備することにある。上記の例は、２枚の基板を張り合わせることで板厚の差を実現している。即ち、半導体チップ２２を搭載する部分を第１の絶縁基板２１ａの板厚ｔ１で構成し、内部電極２４ｂ、２４ｃが位置する箇所では第１と第２の絶縁基板２１ａ、２１ｂの板厚の和（ｔ１＋ｔ２）で構成している。この様な板厚の差は、上記の大判の絶縁基板を用いて製造する上で機械的強度を保つため、及び半導体装置を小型化する上で重要な要素である。   Thus, the gist of the present invention is that the insulating substrate 21 at the place where the semiconductor chip 21 is mounted has a thin plate thickness and has a thick plate portion. In the above example, the difference in plate thickness is realized by bonding two substrates together. That is, the portion on which the semiconductor chip 22 is mounted is configured by the plate thickness t1 of the first insulating substrate 21a, and the sum of the plate thicknesses of the first and second insulating substrates 21a and 21b at the positions where the internal electrodes 24b and 24c are located. (T1 + t2). Such a difference in plate thickness is an important factor in maintaining the mechanical strength in manufacturing using the above-described large-sized insulating substrate and in reducing the size of the semiconductor device.

即ち、半導体チップ２２を搭載する箇所を部分的に薄くすることにより、半導体装置の全体高さ（図１のｔ３）を低く抑えることが可能である。この時、薄い板厚ｔ１として、この基板を製造ラインで流す際に取り扱いが可能な機械的強度を保つ厚みよりは薄い板厚としておく。具体的には、板厚を５０〜２００μとする。前記大判の絶縁基板全体をこの板厚にすると、基板が割れやすくなって製造上の取り扱いが困難となる。   That is, it is possible to keep the overall height of the semiconductor device (t3 in FIG. 1) low by partially thinning the portion where the semiconductor chip 22 is mounted. At this time, the thin plate thickness t1 is set to be thinner than the thickness that maintains the mechanical strength that can be handled when the substrate is flowed on the production line. Specifically, the plate thickness is set to 50 to 200 μm. If the entire large-sized insulating substrate is made to have this thickness, the substrate is easily cracked, making it difficult to handle in manufacturing.

この取り扱いの困難さに対して、半導体チップ２２を搭載する箇所を除いて板厚を厚くする（ｔ１＋ｔ２）ことにより、全体的な機械的強度を強化する。具体的には、第１の絶縁基板２１ａの板厚と同じか或いはそれ以上の板厚を持つ第２の絶縁基板２１ｂを貼着して全体の板厚を１５０μ以上、例えば３００μまでとする。従って、前記大判の絶縁基板としては厚い板厚（ｔ１＋ｔ２）を有し局所的に薄い板厚（ｔ１）を持つだけにとどまるので、製造を行う上では十分な機械的強度を持たせることが可能になるのである。尚、樹脂層２３でモールドした後は、樹脂層２３が機械的強度を保つ。   In response to this difficulty in handling, the overall mechanical strength is enhanced by increasing the thickness (t1 + t2) except for the portion where the semiconductor chip 22 is mounted. Specifically, a second insulating substrate 21b having a thickness equal to or greater than the thickness of the first insulating substrate 21a is pasted so that the total thickness is 150 μm or more, for example, 300 μm. Therefore, since the large-sized insulating substrate has a thick plate thickness (t1 + t2) and has only a thin plate thickness (t1) locally, it can have sufficient mechanical strength for manufacturing. It becomes. In addition, after molding with the resin layer 23, the resin layer 23 maintains mechanical strength.

更に、板厚を厚くする箇所として、内部電極２４ｂ、２４ｃを設けた箇所を厚くすることにより、半導体チップ２２上の電極パッド２８と内部電極２４ｂ、２４ｃとの高さを近似させることができる。これによって、ワイヤボンド工程においてワイヤのボンダビリティを改善し、ワイヤ２９の「たれ」などによる半導体チップ２３との接触事故などを避けることができる。   Furthermore, the height of the electrode pad 28 on the semiconductor chip 22 and the internal electrodes 24b, 24c can be approximated by thickening the location where the internal electrodes 24b, 24c are provided as the location where the plate thickness is increased. As a result, the bondability of the wire can be improved in the wire bonding process, and an accident of contact with the semiconductor chip 23 due to “sag” of the wire 29 can be avoided.

以下に、上述した半導体装置の製造方法を説明する。   Hereinafter, a method for manufacturing the above-described semiconductor device will be described.

第１工程：図３、及び図４（Ａ）（Ｂ）参照
まずは図３に示したような、例えば装置１００個分に相当する大判基板３２を準備する。この基板３２は、第１と第２の絶縁基板２１ａ、２１ｂを貼着したものである。第２の絶縁基板２１ｂには、半導体チップ複数個分、例えば４個分毎に相当する貫通穴３３が規則的に多数個設けられており、貫通穴３３の内部に第１の絶縁基板２１ａが露出する。従って、貫通穴３３の部分では板厚が薄い（ｔ１）のに対し、その他の領域では厚い板厚（ｔ１＋ｔ２）を具備する。 First Step: See FIGS. 3 and 4A and 4B First, a large substrate 32 corresponding to, for example, 100 devices as shown in FIG. 3 is prepared. The substrate 32 is obtained by adhering the first and second insulating substrates 21a and 21b. The second insulating substrate 21b is regularly provided with a plurality of through holes 33 corresponding to a plurality of semiconductor chips, for example, every four chips, and the first insulating substrate 21a is provided inside the through holes 33. Exposed. Accordingly, the thickness of the through hole 33 is thin (t1), while the other region has a thick thickness (t1 + t2).

図４に大判基板３２の拡大平面図と断面図を示した。第２の絶縁基板２１ｂの貫通穴３３に露出した第１の絶縁基板２１ａの表面には、金メッキ層によりアイランド２４ａが形成されている。第２の絶縁基板２１ｂの表面には金メッキ層により内部電極２４ｂ、２４ｃが描画されている。第１の絶縁基板２１ａの裏面には外部電極２５に対応する金メッキパターンが描画されている。同図において、ライン３４’で囲んだ領域が１つの半導体装置として後に切り出されることになる。   FIG. 4 shows an enlarged plan view and a cross-sectional view of the large format substrate 32. An island 24a is formed of a gold plating layer on the surface of the first insulating substrate 21a exposed in the through hole 33 of the second insulating substrate 21b. Internal electrodes 24b and 24c are drawn on the surface of the second insulating substrate 21b by a gold plating layer. A gold plating pattern corresponding to the external electrode 25 is drawn on the back surface of the first insulating substrate 21a. In the figure, the region surrounded by the line 34 'is cut out later as one semiconductor device.

第２工程：図５（Ａ）及び図５（Ｂ）参照
斯かる状態の大判基板３２に対して、貫通穴３３内部のアイランド部２４ａに半導体チップ２２をダイボンドし、チップ２２上に形成したボンディングパッド２８と内部電極２４ｂ、２４ｃとをボンディングワイヤ２９でワイヤボンドする。同じくダイシングライン３４で囲んだ領域が１つの半導体装置として後に切り出されることになる。 Second Step: See FIG. 5A and FIG. 5B With respect to the large-sized substrate 32 in such a state, the semiconductor chip 22 is die-bonded to the island portion 24a inside the through hole 33, and the bonding is formed on the chip 22 The pad 28 and the internal electrodes 24 b and 24 c are wire-bonded with a bonding wire 29. Similarly, a region surrounded by the dicing line 34 is cut out later as one semiconductor device.

第３工程：図６参照
ダイボンドした半導体チップ２２の全部を被覆するように、大判基板３２の上に樹脂層２３を形成してモールドする。モールドは、樹脂をポッティングによって供給して硬化させるか、或いは大判基板３２一枚に対して１つのキャビティを有する上下金型によってモールドする。この樹脂層２３は半導体チップ２２を個別に被覆するものではなく、複数の半導体チップ２２を連続した樹脂で一括して被覆する。例えば一枚の大判基板３２に１００個の半導体チップ２２を搭載した場合は、１００個全てのチップを一括して被覆する。ポッティングであれば無駄になる樹脂の量は極めて少ない。また、金型を用いたトランスファーモールドであっても、装置１００個分に１本のゲートを設ければよいので、無駄にする量は少ない。 Third Step: See FIG. 6 A resin layer 23 is formed on the large substrate 32 and molded so as to cover the entire die-bonded semiconductor chip 22. The mold is supplied with resin by potting and cured, or is molded by an upper and lower mold having one cavity for each large-sized substrate 32. The resin layer 23 does not individually cover the semiconductor chips 22 but covers a plurality of semiconductor chips 22 together with a continuous resin. For example, when 100 semiconductor chips 22 are mounted on one large-sized substrate 32, all 100 chips are covered together. If potting, the amount of resin that is wasted is very small. Further, even in the case of transfer molding using a mold, only one gate needs to be provided for 100 devices, so the amount of waste is small.

第４工程：同じく図６を参照して、幅が１００〜３００μのダイシングブレード３５により、ダイシングライン３４に沿って樹脂層２３と第１と第２の絶縁基板２１ａ、２１ｂを同時に切断し、個々の半導体装置に分離する。個々の半導体装置の側面２３ａ〜２３ｂは本工程のダイシングによって形成されており、切断面には第１と第２の絶縁基板２１ａ、２１ｂの外周端面３０、３１が露出し且つ樹脂層２３と同一平面を形成する。   Fourth step: Referring also to FIG. 6, the resin layer 23 and the first and second insulating substrates 21a and 21b are simultaneously cut along the dicing line 34 by a dicing blade 35 having a width of 100 to 300 μm. The semiconductor device is separated. The side surfaces 23 a to 23 b of the individual semiconductor devices are formed by dicing in this step. The outer peripheral end surfaces 30 and 31 of the first and second insulating substrates 21 a and 21 b are exposed on the cut surfaces and are the same as the resin layer 23. Form a plane.

以上の方法によって製造された半導体装置は、以下のメリットを有する。   The semiconductor device manufactured by the above method has the following merits.

多数個の素子をまとめて樹脂でパッケージングするので、個々にパッケージングする場合に比べて、無駄にする樹脂材料を少なくでき。材料費の低減につながる。   Since a large number of elements are packaged together with resin, it is possible to reduce the amount of resin material that is wasted compared to the case of individual packaging. It leads to reduction of material cost.

モールド金型とリードフレームとの位置合わせ精度がプラス・マイナス５０μ程度であるのに対して、ダイシング装置の位置あわせ精度はプラス・マイナス１０μ程度と精度が高い。従って樹脂外形をダイシングで形成することにより、従来より外形寸法の小さなパッケージを得ることができる。   The alignment accuracy between the mold die and the lead frame is about plus / minus 50 μm, whereas the alignment accuracy of the dicing apparatus is as high as about plus / minus 10 μm. Therefore, by forming the resin outer shape by dicing, a package having a smaller outer size than the conventional one can be obtained.

大判基板３２全体が比較的厚い板厚（ｔ１＋ｔ２）を有し、アイランド部２４ａの板厚（ｔ１）だけを薄くしたので、製造工程において大判基板３２の割れ、欠け等を防止し、その取り扱いを容易にするほか、半導体チップ２２の搭載箇所が凹んでいるので、装置の高さ（ｔ３）を低く抑えて小型パッケージを製造できる利点を有する。本願発明者は、本願手法によって、縦×横×高さが、１．０ｍｍ×０．５ｍｍ×０．５ｍｍの小型パッケージトランジスタを実現することができた。   Since the entire large-sized substrate 32 has a relatively thick plate thickness (t1 + t2) and only the plate thickness (t1) of the island portion 24a is thinned, the large-sized substrate 32 is prevented from being cracked or chipped in the manufacturing process and handled. In addition to facilitating, since the mounting location of the semiconductor chip 22 is recessed, there is an advantage that a small package can be manufactured while keeping the height (t3) of the device low. The inventor of the present application was able to realize a small package transistor having a length × width × height of 1.0 mm × 0.5 mm × 0.5 mm by the method of the present application.

尚、上記の実施の形態では、薄い板厚と厚い板厚とを２枚の基板を用いて構成したが、例えば１枚の基板で貫通穴３３に相当する箇所に有底孔を設けて板厚の差を形成したような基板を用いてもよい。   In the above-described embodiment, the thin plate thickness and the thick plate thickness are configured by using two substrates. For example, a plate with a bottomed hole provided at a location corresponding to the through hole 33 on one substrate is provided. You may use the board | substrate which formed the difference of thickness.

また、図７に示したように、半導体チップ２２個々に貫通穴３３を設け、半導体チップ２２の周囲全体が厚い板厚（ｔ１＋ｔ２）を持つように切断しても良い。同じ箇所には同じ符号を伏して説明を省略する。   Further, as shown in FIG. 7, a through hole 33 may be provided for each semiconductor chip 22 and the entire periphery of the semiconductor chip 22 may be cut so as to have a thick plate thickness (t1 + t2). The same reference numerals are given to the same parts, and the description is omitted.

以上に説明したように、本発明によれば、リードフレームを用いた半導体装置よりも更に小型化できるパッケージ構造を提供できる利点を有する。このとき、リード端子が突出しない構造であるので、実装したときの占有面積を低減し、高密度実装を実現できる。   As described above, according to the present invention, there is an advantage that it is possible to provide a package structure that can be further reduced in size as compared with a semiconductor device using a lead frame. At this time, since the lead terminal does not protrude, the occupied area when mounted can be reduced, and high-density mounting can be realized.

更に、多数個の半導体チップ２２を連続した樹脂層２３で一括モールドするので、装置１個あたりに消費する樹脂の量を節約でき、無駄を少なくすることができる。   Furthermore, since a large number of semiconductor chips 22 are collectively molded with the continuous resin layer 23, the amount of resin consumed per device can be saved and waste can be reduced.

加えて、第１の絶縁基板２１ａと第２の絶縁基板２１ｂとで板厚の差を作ることにより、装置外形の高さ（ｔ３）を抑えて小型パッケージを実現でき、製造上の大判基板３２の取り扱いを容易にし、ワイヤボンドのボンダビリティを改善できる利点を有する。   In addition, by making a difference in plate thickness between the first insulating substrate 21a and the second insulating substrate 21b, a small package can be realized while suppressing the height (t3) of the outer shape of the device, and a large substrate 32 in manufacturing. This makes it easy to handle and improves the bondability of wire bonds.

本発明の半導体装置を示す（Ａ）ＡＡ線断面図、（Ｂ）平面図である。It is (A) AA sectional view taken on the line and (B) top view showing a semiconductor device of the present invention. 本発明の半導体装置を示す斜視図である。It is a perspective view which shows the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明する斜視図である。It is a perspective view explaining the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明する（Ａ）平面図、（Ｂ）断面図である。It is (A) top view and (B) sectional drawing explaining the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明する（Ａ）平面図、（Ｂ）断面図である。It is (A) top view and (B) sectional drawing explaining the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明する斜視図である。It is a perspective view explaining the manufacturing method of the semiconductor device of this invention. 本発明の他の実施の形態を示す（Ａ）断面図、（Ｂ）平面図である。It is (A) sectional drawing and (B) top view which show other embodiment of this invention. 従来例を説明する断面図である。It is sectional drawing explaining a prior art example. 従来例を説明する平面図である。It is a top view explaining a prior art example. 従来例を説明する断面図である。It is sectional drawing explaining a prior art example.

符号の説明Explanation of symbols

２１ａ 第１の絶縁基板
２１ｂ 第２の絶縁基板
２２ 半導体チップ
２３ 樹脂層
２４ａ アイランド部
２４ｂ 内部電極
２４ｃ 内部電極
２５ 外部電極
２９ ワイヤ 21a First insulating substrate 21b Second insulating substrate 22 Semiconductor chip 23 Resin layer 24a Island portion 24b Internal electrode 24c Internal electrode 25 External electrode 29 Wire

Claims (3)

局所的に薄い第１の板厚と、前記第１の板厚よりも厚い第２の板厚とを持つ絶縁基板を準備する工程と、
前記第１の板厚の箇所に、多数個の半導体チップを固着する工程と、
前記半導体チップの電極と、前記第２の板厚を持つ箇所に形成した内部電極とを電気的に接続する工程と、
前記絶縁基板の上部を絶縁樹脂で被覆し、前記多数個の半導体チップを共通の樹脂層で封止する工程と、
前記絶縁基板と前記絶縁樹脂とを、前記半導体チップの各々を分離するように切断する工程と、を具備することを特徴とする半導体装置の製造方法。 Providing an insulating substrate having a locally thin first plate thickness and a second plate thickness greater than the first plate thickness;
Fixing a large number of semiconductor chips to the first plate thickness portion;
Electrically connecting an electrode of the semiconductor chip and an internal electrode formed at a location having the second plate thickness;
Coating the upper part of the insulating substrate with an insulating resin, and sealing the multiple semiconductor chips with a common resin layer;
And a step of cutting the insulating substrate and the insulating resin so as to separate each of the semiconductor chips. 前記絶縁基板は第１と第２との２枚の絶縁基板が貼着されており、前記第１の板厚は前記第１の絶縁基板の板厚であり、前記第２の板厚は前記第１と第２の絶縁基板の板厚の和であることを特徴とする請求項１記載の半導体装置の製造方法。   The insulating substrate has two first and second insulating substrates attached thereto, the first plate thickness being the plate thickness of the first insulating substrate, and the second plate thickness being 2. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness is the sum of the thicknesses of the first and second insulating substrates. 前記半導体チップの各々を分離するように切断する工程が、ダイシングブレードによる切断であることを特徴とする請求項１又は２のいずれかに記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the step of cutting the semiconductor chips so as to separate each of them is cutting by a dicing blade.
JP2008140724A 2008-05-29 2008-05-29 Manufacturing method of semiconductor device Pending JP2008205515A (en)

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JPH08335596A (en) * 1995-06-09 1996-12-17 Sony Corp Manufacture of semiconductor package
JPH0936151A (en) * 1995-07-20 1997-02-07 Japan Aviation Electron Ind Ltd Small resin-potted integrated circuit device and its manufacture
JPH0997929A (en) * 1995-09-29 1997-04-08 Rohm Co Ltd Chip type led, led array and manufacture thereof
JPH09321345A (en) * 1996-05-28 1997-12-12 Sanken Electric Co Ltd Manufacture of surface mount light emitting semiconductor device
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0195747A (en) * 1987-10-05 1989-04-13 Masutomi Gyogyo Kk Method for processing tuna
JPH0661417A (en) * 1992-06-10 1994-03-04 Origin Electric Co Ltd Semiconductor device, electronic circuit device, and method and device for manufacturing them
JPH065926A (en) * 1992-06-18 1994-01-14 Rohm Co Ltd Chip type light emitting diode
JPH08264841A (en) * 1995-03-23 1996-10-11 Matsushita Electron Corp Surface mount led
JPH08335596A (en) * 1995-06-09 1996-12-17 Sony Corp Manufacture of semiconductor package
JPH0936151A (en) * 1995-07-20 1997-02-07 Japan Aviation Electron Ind Ltd Small resin-potted integrated circuit device and its manufacture
JPH0997929A (en) * 1995-09-29 1997-04-08 Rohm Co Ltd Chip type led, led array and manufacture thereof
JPH09321345A (en) * 1996-05-28 1997-12-12 Sanken Electric Co Ltd Manufacture of surface mount light emitting semiconductor device
JPH10150119A (en) * 1996-11-19 1998-06-02 Toshiba Corp Manufacture of semiconductor device

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