JP2008205290A - Component built-in substrate and manufacturing method thereof - Google Patents

Component built-in substrate and manufacturing method thereof Download PDF

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Publication number
JP2008205290A
JP2008205290A JP2007041070A JP2007041070A JP2008205290A JP 2008205290 A JP2008205290 A JP 2008205290A JP 2007041070 A JP2007041070 A JP 2007041070A JP 2007041070 A JP2007041070 A JP 2007041070A JP 2008205290 A JP2008205290 A JP 2008205290A
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Prior art keywords
substrate
electronic component
component
insulating layer
electronic
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Japanese (ja)
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Yoshikatsu Ishizuki
義克 石月
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Fujitsu Ltd
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a component built-in substrate whose curvature can be suppressed even when the substrate is a thin type, and a manufacturing method thereof. <P>SOLUTION: On one surface of the substrate 1, an electronic component 6 such as a bare chip is mounted facedown. The electronic component 6 is composed of a circuit portion 4 where a semiconductor integrated circuit is formed and a connection terminal 5 formed on the circuit portion 4. On the other surface of the substrate 1, an electronic component 11 such as a bare chip is mounted facedown. The electronic component 11 is composed of a circuit portion 9 where a semiconductor integrated circuit is formed and a connection terminal 10 formed on the circuit portion 9. The electronic component 6 and electronic component 11 have mutually matching structures. Further, the electronic components 6 and 11 are disposed plane symmetrically with respect to the substrate 1. Wirings 15 etc., are also disposed plane symmetrically with respect to the substrate 1. Namely, a structure disposed above the substrate 1 and a structure disposed below it are plane symmetrical with each other. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、電子部品を内蔵した部品内蔵基板及びその製造方法に関する。   The present invention relates to a component-embedded substrate that incorporates an electronic component and a manufacturing method thereof.

電子機器に対する小型化、高性能化及び低価格化等の要求に伴い、近年、プリント配線板の微細化及び多層化、並びにプリント配線板内での電子部品の高密度化が急速に進められている。また、半導体チップ等の電子部品を内蔵した多層配線基板の開発も行われている。例えば、ベアチップを内蔵した多層配線基板が開発されている。このような多層配線基板は部品内蔵基板とよばれる。そして、部品内蔵基板にも微細化の一環として薄型化の要請がある。   In recent years, with the demands for downsizing, high performance, and low prices for electronic devices, miniaturization and multilayering of printed wiring boards and high density of electronic components in printed wiring boards have been promoted rapidly. Yes. In addition, development of multilayer wiring boards incorporating electronic components such as semiconductor chips is also underway. For example, a multilayer wiring board incorporating a bare chip has been developed. Such a multilayer wiring board is called a component built-in board. There is also a demand for thinning the component-embedded substrate as part of miniaturization.

しかしながら、従来の部品内蔵基板では、薄型化が進められると、部品内蔵基板自体に反りが生じるようになってきた。このような反りが生じると、部品内蔵基板に半導体チップを搭載することが困難になり、また、部品内蔵基板をマザーボードに２次実装することも困難となる。   However, in the conventional component-embedded substrate, when the thickness is reduced, the component-embedded substrate is warped. When such warpage occurs, it becomes difficult to mount the semiconductor chip on the component built-in substrate, and it becomes difficult to secondary-mount the component built-in substrate on the motherboard.

特開２００４−２６６２０５号公報JP 2004-266205 A 特開２００４−３６３４２５号公報JP 2004-363425 A 特開平１０−３１３１７６号公報JP 10-313176 A

本発明は、薄型になっても反りを抑制することができる部品内蔵基板及びその製造方法を提供することを目的とする。   An object of the present invention is to provide a component-embedded substrate that can suppress warpage even when it is thin, and a method for manufacturing the same.

本願発明者は、従来技術の問題点を解明すべく検討を行ったところ、従来の部品内蔵基板内では、ベース板（基板）の片面上にベアチップがフェースダウンで実装されており、基板の上下の構造が非対称になっていることが反りの一因であることを見出した。つまり、従来の部品内蔵基板では、構造の非対称性によって、基板の上方と下方との間で弾性係数及び熱膨張係数等が相違しており、このような相違によって反りが生じているのである。また、ベアチップが設けられている側に多くの配線が設けられていることも反りの一因である。   The inventor of the present application has studied to solve the problems of the prior art. In the conventional component built-in substrate, the bare chip is mounted face down on one side of the base plate (substrate), and It has been found that the asymmetric structure is a cause of warping. In other words, in the conventional component-embedded substrate, due to the asymmetry of the structure, the elastic coefficient, the thermal expansion coefficient, and the like are different between the upper side and the lower side of the substrate. Further, the fact that many wirings are provided on the side where the bare chip is provided is one factor of warpage.

そして、本願発明者等は、このような知見に基づいて鋭意検討を重ねた結果、以下に示す発明の諸態様に想到した。   As a result of intensive studies based on such knowledge, the inventors of the present application have come up with the following aspects of the invention.

本発明に係る部品内蔵基板には、絶縁層と、前記絶縁層の一方の面側に配置された第１の電子部品と、前記絶縁層の他方の面側に配置された第２の電子部品と、が設けられている。   The component-embedded substrate according to the present invention includes an insulating layer, a first electronic component disposed on one surface side of the insulating layer, and a second electronic component disposed on the other surface side of the insulating layer. And are provided.

本発明に係る部品内蔵基板の製造方法では、絶縁層の一方の面側に第１の電子部品を配置し、その後、前記絶縁層の他方の面側に第２の電子部品を配置する。   In the method for manufacturing a component-embedded substrate according to the present invention, the first electronic component is disposed on one surface side of the insulating layer, and then the second electronic component is disposed on the other surface side of the insulating layer.

本発明によれば、絶縁層の両側に電子部品が配置されているため、一方の電子部品側で応力が生じたとしても、他方の電子部品側でも応力が生じ、両応力が互いに相殺されるため、反りを抑制することができる。   According to the present invention, since the electronic components are arranged on both sides of the insulating layer, even if stress is generated on one electronic component side, the stress is also generated on the other electronic component side, and the two stresses cancel each other. Therefore, warpage can be suppressed.

以下、本発明の実施形態について、添付の図面を参照して具体的に説明する。図１は、本発明の実施形態に係る部品内蔵基板の構造を示す断面図である。   Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing the structure of a component-embedded substrate according to an embodiment of the present invention.

本実施形態では、図１に示すように、ガラスエポキシ基板等の絶縁性の基板１（絶縁層）の内部に複数のビア２（接続手段）が形成され、基板１の両面に導体層３が形成されている。導体層３の一部がビア２に接続されている。また、基板１の一方の面上にベアチップ等の電子部品６がフェースダウンで実装されている。電子部品６は、例えば半導体集積回路が形成された回路部４、及びこの回路部４上に形成された接続端子５から構成されている。また、基板１の他方の面上にベアチップ等の電子部品１１がフェースダウンで実装されている。電子部品１１は、例えば半導体集積回路が形成された回路部９、及びこの回路部９上に形成された接続端子１０から構成されている。そして、基板１と回路部４との間の隙間にアンダーフィル材７が充填され、基板１と回路部９との間の隙間にアンダーフィル材１２が充填されている。   In this embodiment, as shown in FIG. 1, a plurality of vias 2 (connecting means) are formed inside an insulating substrate 1 (insulating layer) such as a glass epoxy substrate, and conductor layers 3 are formed on both surfaces of the substrate 1. Is formed. A part of the conductor layer 3 is connected to the via 2. An electronic component 6 such as a bare chip is mounted face down on one surface of the substrate 1. The electronic component 6 includes, for example, a circuit unit 4 in which a semiconductor integrated circuit is formed and a connection terminal 5 formed on the circuit unit 4. An electronic component 11 such as a bare chip is mounted face down on the other surface of the substrate 1. The electronic component 11 includes, for example, a circuit unit 9 in which a semiconductor integrated circuit is formed, and a connection terminal 10 formed on the circuit unit 9. The underfill material 7 is filled in the gap between the substrate 1 and the circuit portion 4, and the underfill material 12 is filled in the gap between the substrate 1 and the circuit portion 9.

また、電子部品６を覆うようにしてプリプレグ８が基板１に接合されており、電子部品１１を覆うようにしてプリプレグ１３が基板１に接合されている。プリプレグ８及び１３の内部には、一部の導電層３まで達するビア１４が形成されている。そして、複数の配線１５、プリプレグ１６及びビア７を備えた引き回し配線層１８がプリプレグ８及び１３上に設けられている。配線１５の一部がビア１４に接続されている。そして、引き回し配線層１８上に複数のランド１９が形成され、ランド１９上にバンプ２０が形成されている。ランド１９は、最上層のビア１７に接続されている。   The prepreg 8 is bonded to the substrate 1 so as to cover the electronic component 6, and the prepreg 13 is bonded to the substrate 1 so as to cover the electronic component 11. Vias 14 reaching part of the conductive layer 3 are formed inside the prepregs 8 and 13. A lead wiring layer 18 including a plurality of wirings 15, prepregs 16 and vias 7 is provided on the prepregs 8 and 13. A part of the wiring 15 is connected to the via 14. A plurality of lands 19 are formed on the routing wiring layer 18, and bumps 20 are formed on the lands 19. The land 19 is connected to the uppermost via 17.

なお、本実施形態では、電子部品６の構造と電子部品１１の構造とが互いに一致している。また、電子部品６及び１１は、基板１を基準として互いに面対称に配置されている。更に、プリプレグ８及び１６、ビア１４及び１７、並びに配線１５等も基板１を基準として互いに面対称に配置されている。つまり、基板１の上方に位置する構造体と、下方に位置する構造体とが、互いに面対称となっている。   In the present embodiment, the structure of the electronic component 6 and the structure of the electronic component 11 match each other. In addition, the electronic components 6 and 11 are arranged in plane symmetry with respect to the substrate 1. Further, the prepregs 8 and 16, the vias 14 and 17, the wiring 15, and the like are also arranged in plane symmetry with respect to the substrate 1. That is, the structure located above the substrate 1 and the structure located below are plane-symmetric with each other.

このような部品内蔵基板では、基板１の上方と下方との間で弾性係数及び熱膨張係数等がほぼ一致しており、部品内蔵基板自体が薄いものであったとしても、極めて反りが生じにくい。従って、この部品内蔵基板に容易に半導体チップ等の外付け電子部品を搭載することが可能であり、また、この部品内蔵基板をマザーボードに２次実装することも容易である。更に、基板１の上方及び下方に電子部品が設けられているため、電子部品の実装密度を向上させることができる。   In such a component-embedded substrate, the elastic coefficient and thermal expansion coefficient, etc., are substantially the same between the upper and lower portions of the substrate 1, and even if the component-embedded substrate itself is thin, it is extremely difficult to warp. . Therefore, it is possible to easily mount an external electronic component such as a semiconductor chip on this component built-in substrate, and it is also easy to secondary-mount this component built-in substrate on the motherboard. Furthermore, since electronic components are provided above and below the substrate 1, the mounting density of the electronic components can be improved.

次に、上述のような部品内蔵基板を製造する方法について説明する。図２Ａ乃至図２Ｆは、本発明の実施形態に係る部品内蔵基板の製造方法を工程順に示す断面図である。   Next, a method for manufacturing the component-embedded substrate as described above will be described. 2A to 2F are cross-sectional views illustrating a method of manufacturing a component-embedded substrate according to an embodiment of the present invention in the order of steps.

先ず、図２Ａに示すように、ガラスエポキシ基板等の絶縁性の基板１の内部に複数のビア２を形成し、基板１の両面に導体層３を形成する。なお、ビア２及び導体層３が形成された基板１を準備してもよい。   First, as shown in FIG. 2A, a plurality of vias 2 are formed inside an insulating substrate 1 such as a glass epoxy substrate, and a conductor layer 3 is formed on both surfaces of the substrate 1. In addition, you may prepare the board | substrate 1 with which the via | veer 2 and the conductor layer 3 were formed.

次に、図２Ｂに示すように、回路部４及び接続端子５を備えた電子部品６を、基板１の一方の面上にフェースダウンで実装する。この時、接続端子５を一部の導体層３に接触させる。次いで、回路部４と基板１との間の隙間にアンダーフィル材７を充填する。なお、アンダーフィル材７を先に基板１上に設けておき、これを接続端子５が貫通するようにして電子部品６を実装してもよい。   Next, as illustrated in FIG. 2B, the electronic component 6 including the circuit unit 4 and the connection terminal 5 is mounted face down on one surface of the substrate 1. At this time, the connection terminal 5 is brought into contact with a part of the conductor layer 3. Next, the underfill material 7 is filled in the gap between the circuit unit 4 and the substrate 1. Alternatively, the underfill material 7 may be provided on the substrate 1 first, and the electronic component 6 may be mounted so that the connection terminal 5 penetrates the underfill material 7.

その後、図２Ｃに示すように、電子部品６を覆うようにしてプリプレグ８を基板１に接合する。つまり、プリプレグ８を電子部品６側から基板１に貼り付ける。   Thereafter, as shown in FIG. 2C, the prepreg 8 is bonded to the substrate 1 so as to cover the electronic component 6. That is, the prepreg 8 is attached to the substrate 1 from the electronic component 6 side.

続いて、図２Ｄに示すように、基板１の表裏を反転させ、回路部９及び接続端子１０を備えた電子部品１１を、基板１の電子部品６が実装されていない方の面上にフェースダウンで実装する。この時、接続端子１０を一部の導体層３に接触させる。次に、回路部９と基板１との間の隙間にアンダーフィル材１２を充填する。なお、アンダーフィル材１２を先に基板１上に設けておき、これを接続端子１０が貫通するようにして電子部品１１を実装してもよい。   Subsequently, as shown in FIG. 2D, the front and back of the substrate 1 are reversed, and the electronic component 11 including the circuit portion 9 and the connection terminal 10 is placed on the surface of the substrate 1 on which the electronic component 6 is not mounted. Implement down. At this time, the connection terminal 10 is brought into contact with a part of the conductor layer 3. Next, the underfill material 12 is filled in the gap between the circuit portion 9 and the substrate 1. Alternatively, the underfill material 12 may be provided on the substrate 1 first, and the electronic component 11 may be mounted so that the connection terminal 10 penetrates the underfill material 12.

次いで、図２Ｅに示すように、電子部品１１を覆うようにしてプリプレグ１３を基板１に接合する。つまり、プリプレグ１３を電子部品１１側から基板１に貼り付ける。   Next, as shown in FIG. 2E, the prepreg 13 is bonded to the substrate 1 so as to cover the electronic component 11. That is, the prepreg 13 is attached to the substrate 1 from the electronic component 11 side.

その後、図２Ｆに示すように、プリプレグ８及び１３上に、複数の配線１５、プリプレグ１６及びビア１７を備えた引き回し配線層１８を形成する。そして、各引き回し配線層１８上に複数のランド１９を形成し、ランド１９上にバンプ２０を形成する。この時、ランド１９は、最上層のビア１７に接続する。このようにして、部品内蔵基板を完成させる。   Thereafter, as shown in FIG. 2F, a lead wiring layer 18 including a plurality of wirings 15, prepregs 16, and vias 17 is formed on the prepregs 8 and 13. Then, a plurality of lands 19 are formed on each routing wiring layer 18, and bumps 20 are formed on the lands 19. At this time, the land 19 is connected to the uppermost via 17. In this way, the component built-in substrate is completed.

なお、上述の実施形態では、電子部品６及び１１がフェースアップで実装されているが、フェースダウンで実装されていてもよい。また、基板１の上方の構造体と下方の構造体とが互いに完全な面対称となっている必要はなく、反りが許容される範囲内にあれば、電子部品６の位置と電子部品１１の位置とが互いにずれていてもよい。更に、電子部品６の構造と電子部品１１の構造との間に相違があってもよい。また、電子部品６及び１１の双方が動作する必要はなく、部品内蔵基板に要求される機能によっては、一方がダミーの電子部品であってもよい。即ち、一方を電圧が供給されない電子部品としてもよい。また、電子部品はベアチップである必要はない。電子部品には、接続端子を備えているもの等が含まれるが、抵抗膜又は半導体膜等のような単なる膜は電子部品には含まれない。更に、ビア２の代わりに側面に導電膜が形成されたスルーホールが接続手段として設けられていてもよい。   In the above-described embodiment, the electronic components 6 and 11 are mounted face-up, but may be mounted face-down. Further, it is not necessary for the upper structure and the lower structure of the substrate 1 to be completely plane-symmetric with each other, and if the warpage is within an allowable range, the position of the electronic component 6 and the electronic component 11 The positions may be shifted from each other. Furthermore, there may be a difference between the structure of the electronic component 6 and the structure of the electronic component 11. Further, it is not necessary for both the electronic components 6 and 11 to operate, and one of them may be a dummy electronic component depending on the function required for the component-embedded substrate. That is, one of them may be an electronic component to which no voltage is supplied. Also, the electronic component need not be a bare chip. Electronic parts include those provided with connection terminals, but simple films such as resistive films or semiconductor films are not included in electronic parts. Further, instead of the via 2, a through hole having a conductive film formed on the side surface may be provided as a connection means.

以下、本発明の諸態様を付記としてまとめて記載する。   Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

（付記１）
絶縁層と、
前記絶縁層の一方の面側に配置された第１の電子部品と、
前記絶縁層の他方の面側に配置された第２の電子部品と、
を有することを特徴とする部品内蔵基板。 (Appendix 1)
An insulating layer;
A first electronic component disposed on one surface side of the insulating layer;
A second electronic component disposed on the other surface side of the insulating layer;
A component-embedded substrate comprising:

（付記２）
前記絶縁層の一方の面上に形成された第１の導電層と、
前記絶縁層の他方の面上に形成された第２の導電層と、
前記絶縁層の内部に形成され、前記第１の導電層と前記第２の導電層とを接続する接続手段と、
を有し、
前記第１の電子部品は、前記第１の導電層に接続され、
前記第２の電子部品は、前記第２の導電層に接続されていることを特徴とする付記１に記載の部品内蔵基板。 (Appendix 2)
A first conductive layer formed on one surface of the insulating layer;
A second conductive layer formed on the other surface of the insulating layer;
A connection means formed inside the insulating layer and connecting the first conductive layer and the second conductive layer;
Have
The first electronic component is connected to the first conductive layer;
The component built-in substrate according to appendix 1, wherein the second electronic component is connected to the second conductive layer.

（付記３）
前記第１の電子部品と前記第２の電子部品とは、前記絶縁層を基準として互いに面対称に配置されていることを特徴とする付記１又は２に記載の部品内蔵基板。 (Appendix 3)
The component built-in substrate according to appendix 1 or 2, wherein the first electronic component and the second electronic component are arranged symmetrically with respect to each other with respect to the insulating layer.

（付記４）
前記第１の電子部品及び前記第２の電子部品は、互いに同一の構造を有することを特徴とする付記１乃至３のいずれか１項に記載の部品内蔵基板。 (Appendix 4)
The component-embedded substrate according to any one of appendices 1 to 3, wherein the first electronic component and the second electronic component have the same structure.

（付記５）
前記第１及び第２の電子部品の一方のみに電圧が供給されることを特徴とする付記１乃至４のいずれか１項に記載の部品内蔵基板。 (Appendix 5)
The component built-in board according to any one of appendices 1 to 4, wherein a voltage is supplied to only one of the first and second electronic components.

（付記６）
絶縁層の一方の面側に第１の電子部品を配置する工程と、
前記絶縁層の他方の面側に第２の電子部品を配置する工程と、
を有することを特徴とする部品内蔵基板の製造方法。 (Appendix 6)
Disposing a first electronic component on one surface side of the insulating layer;
Disposing a second electronic component on the other surface side of the insulating layer;
A method of manufacturing a component-embedded substrate, comprising:

（付記７）
前記第１及び第２の電子部品を配置する前に、
前記絶縁層の一方の面上に第１の導電層が形成されており、
前記絶縁層の他方の面上に第２の導電層が形成されており、
前記第１の導電層と前記第２の導電層とを接続する接続手段が前記絶縁層の内部に形成されており、
前記第１の電子部品を配置する工程は、前記第１の電子部品を前記第１の導電層に接続する工程を有し、
前記第２の電子部品を配置する工程は、前記第２の電子部品を前記第２の導電層に接続する工程を有することを特徴とする付記６に記載の部品内蔵基板の製造方法。 (Appendix 7)
Before placing the first and second electronic components,
A first conductive layer is formed on one surface of the insulating layer;
A second conductive layer is formed on the other surface of the insulating layer;
Connection means for connecting the first conductive layer and the second conductive layer is formed inside the insulating layer,
Placing the first electronic component comprises connecting the first electronic component to the first conductive layer;
The method for manufacturing a component-embedded board according to appendix 6, wherein the step of arranging the second electronic component includes a step of connecting the second electronic component to the second conductive layer.

（付記８）
前記第１の電子部品と前記第２の電子部品とを、前記絶縁層を基準として互いに面対称に配置することを特徴とする付記６又は７に記載の部品内蔵基板の製造方法。 (Appendix 8)
8. The method for manufacturing a component-embedded board according to appendix 6 or 7, wherein the first electronic component and the second electronic component are arranged in plane symmetry with respect to the insulating layer.

（付記９）
前記第１の電子部品及び前記第２の電子部品として、互いに同一の構造を有するものを用いることを特徴とする付記６乃至８のいずれか１項に記載の部品内蔵基板の製造方法。 (Appendix 9)
9. The method for manufacturing a component-embedded board according to any one of appendices 6 to 8, wherein the first electronic component and the second electronic component have the same structure.

（付記１０）
前記第１及び第２の電子部品の一方のみに電圧が供給されることを特徴とする付記６乃至９のいずれか１項に記載の部品内蔵基板の製造方法。 (Appendix 10)
10. The method for manufacturing a component-embedded board according to any one of appendices 6 to 9, wherein a voltage is supplied to only one of the first and second electronic components.

本発明の実施形態に係る部品内蔵基板の構造を示す断面図である。It is sectional drawing which shows the structure of the component built-in board | substrate which concerns on embodiment of this invention. 本発明の実施形態に係る部品内蔵基板の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the component built-in board which concerns on embodiment of this invention. 図２Ａに引き続き、部品内蔵基板の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of a component built-in board following FIG. 2A. 図２Ｂに引き続き、部品内蔵基板の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of a component built-in board following FIG. 2B. 図２Ｃに引き続き、部品内蔵基板の製造方法を示す断面図である。FIG. 2D is a cross-sectional view illustrating a method for manufacturing the component-embedded substrate, following FIG. 2C. 図２Ｄに引き続き、部品内蔵基板の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of a component built-in board following FIG. 2D. 図２Ｅに引き続き、部品内蔵基板の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of a component built-in board following FIG. 2E.

符号の説明Explanation of symbols

１：基板
２：ビア
３：導電層
４、９：回路部
５、１０：接続端子
６、１１：電子部品
７、１２：アンダーフィル材
８、１３：プリプレグ
１４：ビア
１５：配線
１６：プリプレグ
１７：ビア
１８：引き回し配線層
１９：ランド
２０：バンプ 1: Substrate 2: Via 3: Conductive layer 4, 9: Circuit portion 5, 10: Connection terminal 6, 11: Electronic component 7, 12: Underfill material 8, 13: Prepreg 14: Via 15: Wiring 16: Prepreg 17 : Via 18: Leading wiring layer 19: Land 20: Bump

Claims (6)

絶縁層と、
前記絶縁層の一方の面側に配置された第１の電子部品と、
前記絶縁層の他方の面側に配置された第２の電子部品と、
を有することを特徴とする部品内蔵基板。 An insulating layer;
A first electronic component disposed on one surface side of the insulating layer;
A second electronic component disposed on the other surface side of the insulating layer;
A component-embedded substrate comprising: 前記絶縁層の一方の面上に形成された第１の導電層と、
前記絶縁層の他方の面上に形成された第２の導電層と、
前記絶縁層の内部に形成され、前記第１の導電層と前記第２の導電層とを接続する接続手段と、
を有し、
前記第１の電子部品は、前記第１の導電層に接続され、
前記第２の電子部品は、前記第２の導電層に接続されていることを特徴とする請求項１に記載の部品内蔵基板。 A first conductive layer formed on one surface of the insulating layer;
A second conductive layer formed on the other surface of the insulating layer;
A connection means formed inside the insulating layer and connecting the first conductive layer and the second conductive layer;
Have
The first electronic component is connected to the first conductive layer;
The component-embedded substrate according to claim 1, wherein the second electronic component is connected to the second conductive layer. 前記第１の電子部品と前記第２の電子部品とは、前記絶縁層を基準として互いに面対称に配置されていることを特徴とする請求項１又は２に記載の部品内蔵基板。   3. The component-embedded substrate according to claim 1, wherein the first electronic component and the second electronic component are disposed symmetrically with respect to each other with respect to the insulating layer. 前記第１の電子部品及び前記第２の電子部品は、互いに同一の構造を有することを特徴とする請求項１乃至３のいずれか１項に記載の部品内蔵基板。   4. The component-embedded substrate according to claim 1, wherein the first electronic component and the second electronic component have the same structure. 5. 前記第１及び第２の電子部品の一方のみに電圧が供給されることを特徴とする請求項１乃至４のいずれか１項に記載の部品内蔵基板。   5. The component built-in substrate according to claim 1, wherein a voltage is supplied to only one of the first and second electronic components. 絶縁層の一方の面側に第１の電子部品を配置する工程と、
前記絶縁層の他方の面側に第２の電子部品を配置する工程と、
を有することを特徴とする部品内蔵基板の製造方法。 Disposing a first electronic component on one surface side of the insulating layer;
Disposing a second electronic component on the other surface side of the insulating layer;
A method of manufacturing a component-embedded substrate, comprising:
JP2007041070A 2007-02-21 2007-02-21 Component built-in substrate and manufacturing method thereof Withdrawn JP2008205290A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010141098A (en) * 2008-12-11 2010-06-24 Shinko Electric Ind Co Ltd Substrate with built-in electronic components and method of manufacturing the same
JP2011082471A (en) * 2009-10-12 2011-04-21 Samsung Electro-Mechanics Co Ltd Electronic-component housing type printed board and method for manufacturing the same
JP2014072405A (en) * 2012-09-28 2014-04-21 Dainippon Printing Co Ltd Wiring board with components incorporated therein and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010141098A (en) * 2008-12-11 2010-06-24 Shinko Electric Ind Co Ltd Substrate with built-in electronic components and method of manufacturing the same
US8559184B2 (en) 2008-12-11 2013-10-15 Shinko Electric Industries Co., Ltd. Electronic component built-in substrate and method of manufacturing the same
JP2011082471A (en) * 2009-10-12 2011-04-21 Samsung Electro-Mechanics Co Ltd Electronic-component housing type printed board and method for manufacturing the same
JP2014072405A (en) * 2012-09-28 2014-04-21 Dainippon Printing Co Ltd Wiring board with components incorporated therein and manufacturing method thereof

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