JP2008205238A - 半導体装置、半導体ウエハ構造、及び半導体装置の製造方法 - Google Patents
半導体装置、半導体ウエハ構造、及び半導体装置の製造方法 Download PDFInfo
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- JP2008205238A JP2008205238A JP2007040324A JP2007040324A JP2008205238A JP 2008205238 A JP2008205238 A JP 2008205238A JP 2007040324 A JP2007040324 A JP 2007040324A JP 2007040324 A JP2007040324 A JP 2007040324A JP 2008205238 A JP2008205238 A JP 2008205238A
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Abstract
【解決手段】シリコン基板10と、シリコン基板10の上方に形成された層間絶縁膜40と、層間絶縁膜40の上に形成され、主導電膜43bと、該主導電膜43bよりも硬い表面導電膜43dとを順に形成してなる導電性パッド43pと、層間絶縁膜40の上に形成され、導電性パッド43pが露出する窓51aを備えたパッシベーション膜51とを有し、導電性パッド43pの上面に、表面導電膜43dよりなる凸パターンPが形成された半導体装置による。
【選択図】図14
Description
図2〜図11は、本例に係る半導体ウエハ構造の製造途中の断面図である。このうち、図2〜図7では、シリコン基板1に画定された回路領域Iとパッド領域IIとを併記してある。また、図8〜図11では、パッド領域IIを拡大して示している。
図17及び図18は、第2例に係る半導体ウエハ構造の製造途中の断面図である。この半導体ウエハ構造は次のようにして製造される。
図20及び図21は、第3例に係る半導体ウエハ構造の製造途中の断面図である。この半導体ウエハ構造は次のようにして製造される。
図22〜図24は、第4例に係る半導体ウエハ構造の製造途中の断面図である。
図25〜図27は、第5例に係る半導体ウエハ構造の製造途中の断面図である。
図28は、第6例に係る半導体ウエハ構造と半導体装置のパッド領域IIの拡大平面図である。
図30は、第7例に係る半導体ウエハ構造と半導体装置のパッド領域IIの拡大平面図である。
図31は、第8例に係る半導体ウエハ構造と半導体装置のパッド領域IIの拡大平面図である。
前記半導体基板の上方に形成された層間絶縁膜と、
前記層間絶縁膜の上に形成され、主導電膜と、該主導電膜よりも硬い表面導電膜とを順に形成してなる導電性パッドと、
前記層間絶縁膜の上に形成され、前記導電性パッドが露出する窓を備えたパッシベーション膜とを有し、
前記導電性パッドの上面に、前記表面導電膜よりなる凸パターンが形成されたことを特徴とする半導体装置。
前記凸パターンは、前記多角形の少なくとも一辺に対して斜めに延在する複数の帯状であることを特徴とする付記1に記載の半導体装置。
前記半導体基板の上方に形成された層間絶縁膜と、
前記チップ領域内の前記層間絶縁膜の上に形成され、主導電膜と、該主導電膜よりも硬い表面導電膜とを順に形成してなる導電性パッドと、
前記層間絶縁膜の上に形成され、前記導電性パッドが露出する窓を備えたパッシベーション膜とを有し、
前記導電性パッドの上面に、前記表面導電膜よりなる凸パターンが形成されたことを特徴とする半導体ウエハ構造。
前記凸パターンは、前記多角形の少なくとも一辺に対して斜めに延在する複数の帯状であることを特徴とする付記11に記載の半導体ウエハ構造。
前記層間絶縁膜の上に、導電性積層膜として、主導電膜と、該主導電膜よりも硬い表面導電膜とを順に形成する工程と、
前記導電性積層膜をパターニングして導電性パッドとする工程と、
前記導電性パッドの上に窓を備えたパッシベーション膜を前記層間絶縁膜の上に形成する工程と、
前記導電性パッドの上にレジストパターンを形成する工程と、
前記レジストパターンをマスクにして前記表面導電膜を選択的にエッチングすることにより、前記表面導電膜よりなる凸パターンを前記導電性パッドの上面に形成する工程と、
前記レジストパターンを除去する工程と、
前記レジストパターンを除去した後に、前記導電性パッドに導電性の探針を当接させて、前記半導体基板に形成された回路の電気的な試験を行う工程と、
を有することを特徴とする半導体装置の製造方法。
該主導電膜よりも硬い中間導電膜と、該中間導電膜よりも軟らかい緩衝導電膜とを順に形成し、該緩衝導電膜の上に前記表面導電膜を形成することを特徴とする付記16に記載の半導体装置の製造方法。
前記凸パターンを形成する工程において、前記貴金属含有導電膜をエッチングストッパとして使用しながら前記表面導電膜をエッチングすることを特徴とする付記16に記載の半導体装置の製造方法。
前記電気的な試験を行う工程において、前記探針の侵入方向を前記凸パターンの延在方向の垂直方向とすることを特徴とする付記15に記載の半導体装置の製造方法。
Claims (10)
- 半導体基板と、
前記半導体基板の上方に形成された層間絶縁膜と、
前記層間絶縁膜の上に形成され、主導電膜と、該主導電膜よりも硬い表面導電膜とを順に形成してなる導電性パッドと、
前記層間絶縁膜の上に形成され、前記導電性パッドが露出する窓を備えたパッシベーション膜とを有し、
前記導電性パッドの上面に、前記表面導電膜よりなる凸パターンが形成されたことを特徴とする半導体装置。 - 前記表面導電膜が選択的に除去され、除去されずに残存する該表面導電膜により前記凸パターンが構成されることを特徴とする請求項1に記載の半導体装置。
- 前記主導電膜と表面導電膜との間に、該主導電膜よりも硬い中間導電膜と、該中間導電膜よりも軟らかい緩衝導電膜とが順に形成されたことを特徴とする請求項2に記載の半導体装置。
- 前記主導電膜と前記表面導電膜との間に貴金属含有導電膜が形成されたことを特徴とする請求項2に記載の半導体装置。
- 前記表面導電膜に複数の溝と凸部とが形成され、該凸部によって前記凸パターンが構成されることを特徴とする請求項1に記載の半導体装置。
- 前記導電性パッドに、ボンディングワイヤ又は外部接続端子が接合されたことを特徴とする請求項1に記載の半導体装置。
- チップ領域が画定された半導体基板と、
前記半導体基板の上方に形成された層間絶縁膜と、
前記チップ領域内の前記層間絶縁膜の上に形成され、主導電膜と、該主導電膜よりも硬い表面導電膜とを順に形成してなる導電性パッドと、
前記層間絶縁膜の上に形成され、前記導電性パッドが露出する窓を備えたパッシベーション膜とを有し、
前記導電性パッドの上面に、前記表面導電膜よりなる凸パターンが形成されたことを特徴とする半導体ウエハ構造。 - 前記窓の平面形状は多角形であり、
前記凸パターンは、前記多角形の少なくとも一辺に対して斜めに延在する複数の帯状であることを特徴とする請求項7に記載の半導体ウエハ構造。 - 前記半導体基板の上方に層間絶縁膜を形成する工程と、
前記層間絶縁膜の上に、導電性積層膜として、主導電膜と、該主導電膜よりも硬い表面導電膜とを順に形成する工程と、
前記導電性積層膜をパターニングして導電性パッドとする工程と、
前記導電性パッドの上に窓を備えたパッシベーション膜を前記層間絶縁膜の上に形成する工程と、
前記導電性パッドの上にレジストパターンを形成する工程と、
前記レジストパターンをマスクにして前記表面導電膜を選択的にエッチングすることにより、前記表面導電膜よりなる凸パターンを前記導電性パッドの上面に形成する工程と、
前記レジストパターンを除去する工程と、
前記レジストパターンを除去した後に、前記導電性パッドに導電性の探針を当接させて、前記半導体基板に形成された回路の電気的な試験を行う工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記凸パターンを形成する工程において、該凸パターンを帯状に複数形成し、
前記電気的な試験を行う工程において、前記探針の侵入方向を前記凸パターンの延在方向の垂直方向とすることを特徴とする請求項9に記載の半導体装置の製造方法。
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JP2012089703A (ja) * | 2010-10-20 | 2012-05-10 | Lapis Semiconductor Co Ltd | 半導体素子の製造方法及び半導体素子 |
WO2014014058A1 (ja) * | 2012-07-20 | 2014-01-23 | 株式会社村田製作所 | 電子部品及びその製造方法 |
JP2016141149A (ja) * | 2015-02-05 | 2016-08-08 | キヤノン株式会社 | 液体吐出ヘッド用基板の製造方法、及び該製造方法で製造された液体吐出ヘッド用基板 |
JP2018182196A (ja) * | 2017-04-19 | 2018-11-15 | トヨタ自動車株式会社 | 半導体装置 |
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