JP2008192938A5 - - Google Patents
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- Publication number
- JP2008192938A5 JP2008192938A5 JP2007027413A JP2007027413A JP2008192938A5 JP 2008192938 A5 JP2008192938 A5 JP 2008192938A5 JP 2007027413 A JP2007027413 A JP 2007027413A JP 2007027413 A JP2007027413 A JP 2007027413A JP 2008192938 A5 JP2008192938 A5 JP 2008192938A5
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- layer
- board according
- hole
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Claims (12)
前記絶縁層に積層され、かつ少なくとも一部が前記貫通孔を介して露出する導体層と、
前記導体層に接続され、かつ前記貫通孔の内面を覆う下地層と、
前記下地層を覆うように、少なくとも一部が前記貫通孔に形成されたビア導体と、
を備えた配線基板であって、
前記導体層と前記下地層との間には、前記導体層の金属材料と前記下地層の金属材料との金属結晶が形成されていることを特徴とする、配線基板。 An insulating layer having a through hole;
A conductor layer laminated on the insulating layer and exposed at least partially through the through hole;
An underlayer connected to the conductor layer and covering the inner surface of the through hole;
Via conductors at least partially formed in the through holes so as to cover the foundation layer;
A wiring board comprising:
A wiring substrate, wherein a metal crystal of the metal material of the conductor layer and the metal material of the base layer is formed between the conductor layer and the base layer.
前記下地層は、銅、ニッケル、クロム、チタン、タングステンおよびモリブデンのうちの少なくとも一つの金属材料を含んでいる、請求項１に記載の配線基板。 The conductor layer includes at least one metal material of copper, silver, gold, aluminum, nickel, chromium,
The wiring board according to claim 1, wherein the underlayer includes at least one metal material of copper, nickel, chromium, titanium, tungsten, and molybdenum.
前記ビア導体は、銅、銀、金、アルミニウム、ニッケルおよびクロムのうちの少なくとも一つである、請求項５に記載の配線基板。 The underlayer includes at least one metal material of copper, nickel, chromium, titanium, tungsten and molybdenum;
The wiring board according to claim 5, wherein the via conductor is at least one of copper, silver, gold, aluminum, nickel, and chromium.
前記下地層は、銅、ニッケル、クロム、チタン、タングステンおよびモリブデンのうちの少なくとも１つの金属材料を含んでいる、請求項９に記載の配線基板。 The insulating layer includes at least one of polyimide resin, acrylic resin, epoxy resin, cyanate resin, urethane resin, Teflon (registered trademark) resin, silicon resin, polyphenylene ether resin, bismaleimide triazine resin, and polyparaphenylene benzoxazole. Contains insulating material,
The wiring substrate according to claim 9, wherein the base layer includes at least one metal material of copper, nickel, chromium, titanium, tungsten, and molybdenum.
前記配線基板に実装された半導体素子と、
を備えていることを特徴とする、実装構造体。 The wiring board according to any one of claims 1 to 10,
A semiconductor element mounted on the wiring board;
A mounting structure characterized by comprising:
前記導体層における前記貫通孔から露出する露出面および前記貫通孔の内面を覆うように下地層を形成する第２工程と、
前記下地層を覆うようにビア導体を形成する第３工程と、
を含む配線基板の製造方法であって、
前記第２工程は、前記露出面における十点平均粗さＲｚを１μｍ以下に維持した状態で行なわれることを特徴とする、配線基板の製造方法。 A first step of forming a through hole so that a part of the conductor layer is exposed with respect to the insulating layer on which the conductor layer is formed;
A second step of forming a base layer so as to cover an exposed surface exposed from the through hole in the conductor layer and an inner surface of the through hole;
A third step of forming a via conductor so as to cover the underlayer;
A method of manufacturing a wiring board including:
The method of manufacturing a wiring board, wherein the second step is performed in a state where the ten-point average roughness Rz on the exposed surface is maintained at 1 μm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007027413A JP2008192938A (en) | 2007-02-06 | 2007-02-06 | Wiring board, package structure, and manufacturing method of wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007027413A JP2008192938A (en) | 2007-02-06 | 2007-02-06 | Wiring board, package structure, and manufacturing method of wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2008192938A JP2008192938A (en) | 2008-08-21 |
| JP2008192938A5 true JP2008192938A5 (en) | 2009-09-03 |
Family
ID=39752729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007027413A Pending JP2008192938A (en) | 2007-02-06 | 2007-02-06 | Wiring board, package structure, and manufacturing method of wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2008192938A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010157590A (en) * | 2008-12-26 | 2010-07-15 | Fujifilm Corp | Method for producing multilayer wiring substrate |
| WO2024071007A1 (en) * | 2022-09-30 | 2024-04-04 | 京セラ株式会社 | Wiring board and circuit structure obtained using same |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10190224A (en) * | 1996-12-27 | 1998-07-21 | Ibiden Co Ltd | Multilayer printed wiring board and its manufacture |
| JP4049554B2 (en) * | 2001-06-26 | 2008-02-20 | イビデン株式会社 | Multilayer printed wiring board and method for producing multilayer printed wiring board |
| JP2003229668A (en) * | 2002-12-16 | 2003-08-15 | Toshiba Corp | Method of manufacturing multilayered wiring board |
| JP2004288748A (en) * | 2003-03-19 | 2004-10-14 | Sumitomo Bakelite Co Ltd | Method of manufacturing wiring board |
| JP2006303171A (en) * | 2005-04-20 | 2006-11-02 | Teijin Ltd | Substrate for flexible printed circuit |
| JP4701842B2 (en) * | 2005-06-02 | 2011-06-15 | 凸版印刷株式会社 | Manufacturing method of semiconductor device substrate |
-
2007
- 2007-02-06 JP JP2007027413A patent/JP2008192938A/en active Pending
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