JP2008181939A - Production process of substrate for power module and substrate for power module and power module - Google Patents

Production process of substrate for power module and substrate for power module and power module Download PDF

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JP2008181939A
JP2008181939A JP2007012517A JP2007012517A JP2008181939A JP 2008181939 A JP2008181939 A JP 2008181939A JP 2007012517 A JP2007012517 A JP 2007012517A JP 2007012517 A JP2007012517 A JP 2007012517A JP 2008181939 A JP2008181939 A JP 2008181939A
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power module
circuit layer
brazing material
outer peripheral
module substrate
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JP4702293B2 (en
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Shinsuke Aoki
慎介 青木
Toshiyuki Nagase
敏之 長瀬
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Mitsubishi Materials Corp
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Mitsubishi Materials Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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Abstract

<P>PROBLEM TO BE SOLVED: To control a molten brazing material not to ride on the surface to which a semiconductor chip is bonded along the side face of a circuit layer when the circuit layer is brazed to the surface of a ceramic board. <P>SOLUTION: A brazing material layer 20 interposed between a laminate 14a of a ceramic board 11 and a circuit layer 12 has an outer circumferential part 20a where the outer circumferential edge of the circuit layer 12 is arranged on the surface, and an inside part 20b surrounded by the outer circumferential part 20a in the laminate 14a. The inside part 20b is formed of a brazing material of ultrafine particle powder having a diameter of 0.1 μm or less, and the outer circumferential part 20a is formed of a brazing material having a particle size larger than that of the brazing material of the inside part 20b, or of a brazing material foil. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

この発明は、大電流、高電圧を制御する半導体装置に用いられるパワーモジュール用基板の製造方法およびパワーモジュール用基板並びにパワーモジュールに関するものである。   The present invention relates to a power module substrate manufacturing method, a power module substrate, and a power module used in a semiconductor device that controls a large current and a high voltage.

この種のパワーモジュールは一般に、セラミックス板の表面に回路層がろう付けされたパワーモジュール用基板と、回路層の表面にはんだ接合された半導体チップとを備えている。このうちパワーモジュール用基板は、セラミックス板の表面にろう材箔と回路層とをこの順に配置して積層体とした後に、この積層体を積層方向に加圧した状態で加熱しろう材箔を溶融させて、セラミックス板の表面に回路層をろう付けすることにより形成されている。そして、このろう付けには、例えば下記特許文献１に示されるように、回路層の平面視形状と略同形同大で、かつ全体が同一の材質からなるろう材箔が用いられている。
実公平８−１０２０２号公報 This type of power module generally includes a power module substrate having a circuit layer brazed to the surface of a ceramic plate, and a semiconductor chip soldered to the surface of the circuit layer. Of these, the power module substrate is formed by arranging a brazing material foil and a circuit layer in this order on the surface of the ceramic plate to form a laminate, and then heating the brazing material foil in a state of being pressed in the laminating direction. It is formed by melting and brazing the circuit layer on the surface of the ceramic plate. For this brazing, for example, as shown in Patent Document 1 below, a brazing material foil that is substantially the same shape and size as the planar view of the circuit layer and is entirely made of the same material is used.
No. 8-10202

しかしながら、前記従来のパワーモジュール用基板の製造方法では、ろう材箔を溶融させるのに前記積層体を加熱炉内に置いて加熱すると、ろう材箔はまず、その外周縁部に加熱炉内の熱が伝わって溶融し始め、その後徐々に沿面方向の内方に向けて熱が伝導し溶融が進んでいくので、ろう材箔の沿面方向における中央部を溶融させるまで加熱しようとすると、その前に、ろう材箔の外周縁部を構成していた既に溶融したろう材が、回路層とセラミックス板との間からしみ出し、さらにその表面張力で凝集することによって、回路層の側面を伝って半導体チップがはんだ接合される表面に乗り上がるおそれがあった。
このようにして回路層の表面に乗り上げたろう材は視認することができ、外観品質を低減させるおそれがある。特に、Ｓｉを含有する例えばＡｌ−Ｓｉ系のろう材箔を用いて、純Ａｌ若しくはＡｌ合金からなる回路層をセラミックス板にろう付する場合には、溶融後に硬化したろう材は、回路層よりも硬い上にパワーモジュールを使用する過程における熱サイクルでさらに加工硬化させられることによって、回路層に対してその表面および側面から大きな外力が作用して、回路層とセラミックス板との接合界面に大きな応力が作用し、回路層がセラミックス板の表面から剥離し易くなり、パワーモジュールの熱サイクル寿命を低下させるおそれがある。さらに、上記と同様の材質からなるろう材箔および回路層を用いた場合において、回路層の表面のうちろう材が乗り上げた部分にワイヤボンディングが施されると、ろう材は前記のように回路層と比べて硬いので、この部分とワイヤボンディングとの接合部における熱サイクル寿命を低下させるおそれもある。 However, in the conventional method for manufacturing a power module substrate, when the laminated body is heated in a heating furnace to melt the brazing material foil, the brazing material foil is first placed on the outer peripheral edge of the heating furnace. Heat is transmitted and begins to melt, and then heat gradually conducts toward the inside of the creeping direction, and melting progresses.Therefore, when trying to heat until the center part in the creeping direction of the brazing foil is melted, In addition, the already melted brazing material constituting the outer peripheral edge of the brazing material foil oozes out between the circuit layer and the ceramic plate, and further aggregates by the surface tension, thereby being transmitted along the side surface of the circuit layer. There is a possibility that the semiconductor chip may run on the surface to be soldered.
In this way, the brazing material riding on the surface of the circuit layer can be visually recognized, and the appearance quality may be reduced. In particular, when a circuit layer made of pure Al or an Al alloy is brazed to a ceramic plate using, for example, an Al-Si brazing foil containing Si, the brazing material cured after melting is more difficult than the circuit layer. In addition to being hard, it is further hardened by heat cycle in the process of using the power module, so that a large external force acts on the circuit layer from its surface and side surface, resulting in a large interface at the interface between the circuit layer and the ceramic plate. The stress acts, the circuit layer is easily peeled off from the surface of the ceramic plate, and the thermal cycle life of the power module may be reduced. Further, in the case where the brazing material foil and the circuit layer made of the same material as described above are used, when wire bonding is applied to the portion of the surface of the circuit layer where the brazing material has run over, the brazing material becomes a circuit as described above. Since it is harder than the layer, the thermal cycle life at the joint between this part and wire bonding may be reduced.

本発明はこのような事情を考慮してなされたもので、セラミックス板の表面に回路層をろう付けする際に、溶融したろう材が回路層の側面を伝って、半導体チップが接合される表面に乗り上がるのを抑制することができるパワーモジュール用基板の製造方法およびパワーモジュール用基板並びにパワーモジュールを提供することを目的とする。   The present invention has been made in view of such circumstances, and when brazing the circuit layer to the surface of the ceramic plate, the surface to which the semiconductor chip is joined by the molten brazing material traveling along the side surface of the circuit layer An object of the present invention is to provide a power module substrate manufacturing method, a power module substrate, and a power module that can suppress the boarding.

このような課題を解決して、前記目的を達成するために、本発明のパワーモジュール用基板の製造方法は、セラミックス板の表面にろう材層と回路層とをこの順に配置して積層体とした後に、この積層体を積層方向に加圧した状態で加熱してろう材層を溶融させることにより、セラミックス板の表面に回路層がろう付けされてなり、この回路層の表面に半導体チップがはんだ接合されるパワーモジュール用基板を形成するパワーモジュール用基板の製造方法であって、前記ろう材層は、前記積層体において、表面に前記回路層の外周縁部が配置される外周部分と、この外周部分に囲まれた内側部分とを備え、前記内側部分は、直径０．１μｍ以下の超微粒子粉末のろう材により形成され、前記外周部分は、内側部分のろう材よりも粒径が大きいろう材又はろう材箔により形成されていることを特徴とする。   In order to solve such problems and achieve the above-mentioned object, a method for manufacturing a power module substrate according to the present invention includes a laminated body in which a brazing filler metal layer and a circuit layer are arranged in this order on the surface of a ceramic plate. After that, the laminated body is heated while being pressed in the laminating direction to melt the brazing material layer, whereby the circuit layer is brazed to the surface of the ceramic plate, and the semiconductor chip is formed on the surface of the circuit layer. A power module substrate manufacturing method for forming a power module substrate to be soldered, wherein the brazing material layer has an outer peripheral portion on the surface of which the outer peripheral edge portion of the circuit layer is disposed, An inner portion surrounded by the outer peripheral portion, and the inner portion is formed of a brazing material made of ultrafine powder having a diameter of 0.1 μm or less, and the outer peripheral portion has a particle size larger than that of the inner portion. Characterized in that it is formed by a brazing material or brazing material foil.

この発明では、ろう材層の内側部分が超微粒子粉末により形成されているので、外周部分よりも融点が低くなる。逆に言えば、内側部分よりも外周部分の方が融点が高くなるのであり、前記積層体を加熱したときに、まず、ろう材層の前記内側部分を溶融させて、その後、前記外周部分を溶融させることが可能になる。したがって、ろう材層の前記内側部分が溶融し、この溶融したろう材がろう材層の外周縁に向けて拡がるように流れようとしても、その流れを、ろう材層の前記外周部分でせき止めることができる。
また、加熱してセラミックス板と回路層とをろう付けする過程において、内側部分がまず溶融し、次いで外周部分が溶融するという二段階の溶融過程を経るので、ろう材層の前記外周部分が溶融する時点を、前記従来のように全体がほぼ同時に溶融する場合と比べて遅らせることが可能になり、この外周部分が溶融状態となっている時間を短縮することができる。
以上より、セラミックス板の表面に回路層をろう付けする際に、溶融したろう材が回路層の側面を伝って、半導体チップが接合される表面に乗り上がるのを抑制することができる。 In this invention, since the inner part of the brazing material layer is formed of the ultrafine powder, the melting point is lower than that of the outer peripheral part. In other words, the melting point is higher in the outer peripheral part than in the inner part, and when the laminate is heated, the inner part of the brazing material layer is first melted, and then the outer peripheral part is It can be melted. Therefore, even if the inner part of the brazing material layer is melted and the molten brazing material tries to flow so as to spread toward the outer peripheral edge of the brazing material layer, the flow is stopped at the outer peripheral part of the brazing material layer. Can do.
In addition, in the process of brazing the ceramic plate and the circuit layer by heating, the outer part of the brazing material layer is melted because the inner part melts first and then the outer part melts. It is possible to delay the point of time compared to the case where the whole melts almost simultaneously as in the conventional case, and the time during which the outer peripheral portion is in a molten state can be shortened.
As described above, when the circuit layer is brazed to the surface of the ceramic plate, it is possible to suppress the molten brazing material from traveling onto the surface to which the semiconductor chip is bonded along the side surface of the circuit layer.

ここで、前記外周部分は前記内側部分より厚く形成されるとよく、内側部分が溶融状態となった後に外部にしみ出すことを確実に阻止することができる。   Here, the outer peripheral portion may be formed thicker than the inner portion, and the outer portion can be reliably prevented from oozing out after being melted.

また、本発明のパワーモジュール用基板は、セラミックス板の表面に回路層がろう付けされてなり、この回路層の表面に半導体チップがはんだ接合されるパワーモジュール用基板であって、本発明のパワーモジュール用基板の製造方法により形成されたことを特徴とする。
さらに、本発明のパワーモジュールは、セラミックス板の表面に回路層がろう付けされたパワーモジュール用基板と、回路層の表面にはんだ接合された半導体チップとを備えたパワーモジュールであって、前記パワーモジュール用基板は、本発明のパワーモジュール用基板の製造方法により形成されたことを特徴とする。 The power module substrate of the present invention is a power module substrate in which a circuit layer is brazed to the surface of a ceramic plate, and a semiconductor chip is soldered to the surface of the circuit layer. It is formed by a method for manufacturing a module substrate.
Furthermore, the power module of the present invention is a power module comprising a power module substrate having a circuit layer brazed to the surface of a ceramic plate, and a semiconductor chip solder-bonded to the surface of the circuit layer. The module substrate is formed by the method for manufacturing a power module substrate of the present invention.

この発明に係るパワーモジュール用基板の製造方法およびパワーモジュール用基板並びにパワーモジュールによれば、セラミックス板の表面に回路層をろう付けする際に、超微粒子粉末のろう材によって形成される内側部分よりも外側部分を後に溶融させて、ろう材が外方へ流れ出るのを融点の高い外周部分でせき止めることができ、ろう材が回路層の側面を伝って、半導体チップが接合される表面に乗り上がるのを抑制することができる。   According to the method for manufacturing a power module substrate, the power module substrate, and the power module according to the present invention, when the circuit layer is brazed to the surface of the ceramic plate, the inner portion formed by the brazing material of the ultrafine powder. However, the outer part can be melted later, and the brazing material can be prevented from flowing outward at the outer peripheral part having a high melting point, and the brazing material runs along the side surface of the circuit layer and rides on the surface to which the semiconductor chip is bonded. Can be suppressed.

以下、図面を参照し、この発明の実施の形態について説明する。図１はこの発明の一実施形態に係るパワーモジュール用基板を適用したパワーモジュールを示す全体図である。
このパワーモジュール１０は、セラミックス板１１の表面に回路層１２がろう付けされたパワーモジュール用基板１４と、回路層１２の表面にはんだ層１７を介してはんだ接合された半導体チップ１５とを備えている。 Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an overall view showing a power module to which a power module substrate according to an embodiment of the present invention is applied.
This power module 10 includes a power module substrate 14 having a circuit layer 12 brazed to the surface of a ceramic plate 11 and a semiconductor chip 15 soldered to the surface of the circuit layer 12 via a solder layer 17. Yes.

図示の例では、パワーモジュール用基板１４には、回路層１２と同じ材質からなる金属層１８が、セラミックス板１１の裏面にろう付けされて備えられている。さらに、パワーモジュール１０には、冷却器１６が、金属層１８の裏面にろう付けや拡散接合、はんだ付け等により接合されて備えられている。
なお、セラミックス板１１は、例えばＡｌＮ、Ａｌ２Ｏ３、Ｓｉ３Ｎ４若しくはＳｉＣ等で形成され、回路層１２および金属層１８はそれぞれ、例えば純Ａｌ若しくはＡｌ合金で形成され、冷却器１６は、純Ａｌ、純Ｃｕ、Ａｌ合金若しくはＣｕ合金で形成され、はんだ層１７は、例えばＳｎ−Ａｇ−Ｃｕ系若しくはＺｎ−Ａｌ系のはんだ材とされる。
さらに、セラミックス板１１と回路層１２および金属層１８とは、後述する特殊構造を有するＡｌ系のろう材層２０を用いてろう付けされている。 In the illustrated example, the power module substrate 14 is provided with a metal layer 18 made of the same material as the circuit layer 12 by being brazed to the back surface of the ceramic plate 11. Further, the power module 10 is provided with a cooler 16 joined to the back surface of the metal layer 18 by brazing, diffusion bonding, soldering, or the like.
The ceramic plate 11 is made of, for example, AlN, Al 2 O 3 , Si 3 N 4, or SiC, and the circuit layer 12 and the metal layer 18 are made of, for example, pure Al or Al alloy, and the cooler 16 is The solder layer 17 is made of, for example, a Sn—Ag—Cu-based or Zn—Al-based solder material.
Further, the ceramic plate 11, the circuit layer 12, and the metal layer 18 are brazed using an Al-based brazing material layer 20 having a special structure described later.

ここで、本実施形態では、回路層１２および金属層１８はそれぞれ、純Ａｌ若しくはＡｌ合金からなる母材を打ち抜いたり、あるいは鋳造により形成されており、回路層１２および金属層１８の各外表面のうち、セラミックス板１１の表裏面から立上がる側面はそれぞれ、セラミックス板１１の表裏面に対して略垂直に延在している。   Here, in the present embodiment, each of the circuit layer 12 and the metal layer 18 is formed by stamping or casting a base material made of pure Al or an Al alloy, and each outer surface of the circuit layer 12 and the metal layer 18. Among these, the side surfaces rising from the front and back surfaces of the ceramic plate 11 respectively extend substantially perpendicular to the front and back surfaces of the ceramic plate 11.

次に、以上のように構成されたパワーモジュール用基板１４の製造方法について説明する。
まず、図２に示されるように、セラミックス板１１の表面に、ろう材層２０と回路層１２とをこの順に配置するとともに、セラミックス板１１の裏面に、ろう材層２０と金属層１８とをこの順に配置して図２に示すような積層体１４ａを形成する。そして、この積層体１４ａを、加熱炉内に置いて積層方向に加圧した状態で加熱し、ろう材層２０を溶融させることによって、セラミックス板１１の表面に回路層１２をろう付けするとともに、セラミックス板１１の裏面に金属層１８をろう付けし、パワーモジュール用基板１４を形成する。 Next, a method for manufacturing the power module substrate 14 configured as described above will be described.
First, as shown in FIG. 2, the brazing material layer 20 and the circuit layer 12 are arranged in this order on the surface of the ceramic plate 11, and the brazing material layer 20 and the metal layer 18 are arranged on the back surface of the ceramic plate 11. Arranged in this order to form a laminate 14a as shown in FIG. Then, the laminated body 14a is placed in a heating furnace and heated while being pressed in the laminating direction, and the brazing material layer 20 is melted to braze the circuit layer 12 to the surface of the ceramic plate 11, A metal layer 18 is brazed to the back surface of the ceramic plate 11 to form a power module substrate 14.

ここで、本実施形態では、ろう材層２０は、材料としては、例えば、Ａｌ−Ｓｉ系、Ａｌ−Ｓｉ−Ｍｇ系、Ａｌ−Ｓｉ−Ｃｕ−Ｍｇ系、Ａｌ−Ｆｅ−Ｎｉ系、Ａｌ−Ｓｉ−Ｆｅ―Ｎｉ系、Ａｌ−Ｓｉ−Ｍｇ−Ｆｅ系、Ａｌ−Ｓｉ−Ｃｕ系、Ａｌ−Ｓｉ−Ｆｅ系、およびＡｌ−Ｓｉ−Ｍｇ−Ｆｅ−Ｍｎ系等の中から選ばれるが、図３及び図４に示されるように、積層体１４ａにおいて、表面に回路層１２の外周縁部が配置される外周部分２０ａと、この外周部分２０ａに囲まれた内側部分２０ｂとを備えている。   Here, in this embodiment, the brazing filler metal layer 20 is made of, for example, Al—Si, Al—Si—Mg, Al—Si—Cu—Mg, Al—Fe—Ni, Al— It is selected from Si-Fe-Ni, Al-Si-Mg-Fe, Al-Si-Cu, Al-Si-Fe, Al-Si-Mg-Fe-Mn, etc. As shown in FIG. 3 and FIG. 4, the laminated body 14 a includes an outer peripheral portion 20 a on the surface of which the outer peripheral edge portion of the circuit layer 12 is disposed, and an inner portion 20 b surrounded by the outer peripheral portion 20 a.

そして、外周部分２０ａは枠状のろう材箔によって構成され、内側部分２０ｂは、直径が０．１μｍ以下、好ましくは１０ｎｍ以上３０ｎｍ以下の超微粒子の粉末からなるろう材によって構成されている。この場合、内側部分２０ｂのろう材は、セラミックス板１１に外周部分２０ａの枠状のろう材箔を載せ、その枠の中に超微粒子の粉末のまま埋めるか、超微粒子の粉末をペースト状にして塗ることにより供給される。   The outer peripheral portion 20a is made of a frame-shaped brazing material foil, and the inner portion 20b is made of a brazing material made of ultrafine powder having a diameter of 0.1 μm or less, preferably 10 nm or more and 30 nm or less. In this case, the brazing material of the inner portion 20b is obtained by placing the frame-shaped brazing material foil of the outer peripheral portion 20a on the ceramic plate 11, and filling the frame with the ultrafine powder as it is, or making the ultrafine powder into a paste. Supplied by painting.

このときのろう材層２０の厚さは、内側部分２０ｂのろう材の厚さとしては１０μｍ以上３０μｍ以下とされ、外周部分２０ａのろう材箔の厚さは、内側部分２０ｂのろう材の厚さの１．５倍以上２倍以下の範囲となるように厚く形成される。例えば、内側部分２０ｂのろう材の厚さを１０μｍとした場合には、外周部分２０ａのろう材箔の厚さは１５μｍ以上２０μｍ以下とし、内側部分２０ｂのろう材の厚さを３０μｍとした場合には、外周部分２０ａのろう材箔の厚さは４５μｍ以上６０μｍ以下とされる。   At this time, the thickness of the brazing filler metal layer 20 is 10 μm or more and 30 μm or less as the thickness of the brazing filler metal of the inner portion 20b, and the thickness of the brazing filler metal foil of the outer peripheral portion 20a is the thickness of the brazing filler metal of the inner portion 20b. It is formed thick so as to be in the range of 1.5 to 2 times the thickness. For example, when the thickness of the brazing material of the inner portion 20b is 10 μm, the thickness of the brazing material foil of the outer peripheral portion 20a is 15 μm or more and 20 μm or less, and the thickness of the brazing material of the inner portion 20b is 30 μm. In this case, the thickness of the brazing material foil of the outer peripheral portion 20a is set to 45 μm or more and 60 μm or less.

また、図示の例では、外周部分２０ａは、回路層１２の裏面の外周縁に沿ってその全周にわたって延在し、その沿面方向における内側に内側部分２０ｂが配置されている。なお、前記沿面方向は、積層体１４ａの積層方向に直交する方向のことをいう。さらに、内側部分２０ｂの外周縁は、外周部分２０ａの内周縁と同形同大とされており、内側部分２０ｂの外周縁と、外周部分２０ａの内周縁との間には略隙間のない状態となっている。   In the illustrated example, the outer peripheral portion 20a extends over the entire periphery along the outer peripheral edge of the back surface of the circuit layer 12, and the inner portion 20b is disposed on the inner side in the creeping direction. The creeping direction means a direction orthogonal to the stacking direction of the stacked body 14a. Further, the outer peripheral edge of the inner portion 20b is the same shape and size as the inner peripheral edge of the outer peripheral portion 20a, and there is substantially no gap between the outer peripheral edge of the inner portion 20b and the inner peripheral edge of the outer peripheral portion 20a. It has become.

以上のようにして回路層１２とセラミックス板１１との間に、ろう材箔からなる外周部分２０ａと、超微粒子粉末のろう材からなる内側部分２０ｂとに分けたろう材層２０が配置されるが、図示の例では、金属層１８とセラミックス板１１との間に配置されたろう材層２０も、回路層１２とセラミックス板１１との間に配置されたろう材層２０と同様に、外周部分２０ａと内側部分２０ｂとを備えている。なお、本実施形態では、ろう材層２０は、回路層１２の裏面の、セラミックス板１１の表面への投影面における略全域に配置されるとともに、金属層１８の裏面の、セラミックス板１１の裏面への投影面における略全域にも配置されている。   As described above, between the circuit layer 12 and the ceramic plate 11, the brazing material layer 20 divided into the outer peripheral portion 20a made of the brazing material foil and the inner portion 20b made of the brazing material of ultrafine powder is disposed. In the illustrated example, the brazing filler metal layer 20 disposed between the metal layer 18 and the ceramic plate 11 is similar to the brazing filler metal layer 20 disposed between the circuit layer 12 and the ceramic plate 11. And an inner portion 20b. In the present embodiment, the brazing filler metal layer 20 is disposed on substantially the entire area of the back surface of the circuit layer 12 on the projection surface onto the surface of the ceramic plate 11, and the back surface of the ceramic plate 11 on the back surface of the metal layer 18. It is also arranged over substantially the entire area on the projection plane.

そして、このろう材層２０を介在させた積層体１４ａを加圧しながら加熱してろう材層２０を溶融させるのであるが、このろう材層２０に用いられている外周部分２０ａのろう材箔と内側部分２０ｂの超微粒子粉末のろう材とでは液相温度が異なり、内側部分２０ｂを超微粒子粉末にしたことにより、外周部分２０ａの液相温度に比べて、内側部分２０ｂの液相温度の方が、１０℃以上３０℃以下低くなっている。この融点降下は粒径が小さくなるほど大きくなり、Ａｌ−Ｓｉ系ろう材の場合は、粒径１μｍ以下でその傾向が現れ、
特に３０ｎｍ以下の粒径の場合に顕著になる。 And the laminated body 14a with the brazing material layer 20 interposed between them is heated to melt the brazing material layer 20, and the brazing material foil of the outer peripheral portion 20a used for the brazing material layer 20 and The liquid phase temperature is different from that of the brazing material of the ultrafine particle powder of the inner part 20b, and the liquid phase temperature of the inner part 20b is compared with the liquid phase temperature of the outer peripheral part 20a because the inner part 20b is made of ultrafine powder. However, it is 10 degrees C or more and 30 degrees C or less low. This melting point drop becomes larger as the particle size becomes smaller. In the case of an Al—Si brazing material, the tendency appears when the particle size is 1 μm or less,
This is particularly noticeable when the particle diameter is 30 nm or less.

したがって、このようなろう材層２０を用いて積層体１４ａを加熱する際、まず、内側部分２０ｂが溶融するまで加熱した後に、その温度を内側部分２０ｂが全て液相状態になるまで保持し、その後、外周部分２０ａが溶融するまでさらに加熱し、その温度になったのと略同時に、あるいはその温度に、内側部分２０ｂの液相温度で保持した時間よりも短い時間保持した後に、つまり外周部分２０ａが液相状態になったのと略同時にこの加熱を停止して徐冷し、パワーモジュール用基板１４を形成するのである。
なお、このろう付け時の積層体１４ａへの加圧は、例えば接合面に２２５KＰａ以上２６５KＰａ以下の圧力を作用させる程度とされる。 Therefore, when heating the laminated body 14a using such a brazing material layer 20, first, the inner part 20b is heated until it melts, and then the temperature is maintained until all the inner part 20b is in a liquid phase state. Thereafter, further heating until the outer peripheral portion 20a is melted, and at the same time as the temperature is reached, or after being held at that temperature for a time shorter than the time held at the liquid phase temperature of the inner portion 20b, that is, the outer peripheral portion. This heating is stopped and gradually cooled to form the power module substrate 14 at approximately the same time as 20a is in the liquid phase state.
The pressure applied to the laminated body 14a at the time of brazing is such that, for example, a pressure of 225 KPa or more and 265 KPa or less is applied to the bonding surface.

このように製造される本実施形態のパワーモジュール用基板によれば、ろう材層２０の内側部分２０ｂを超微粒子粉末により形成したことにより、外周部分２０ａのろう材箔に比べて液相温度が低くなり、積層体１４ａを加熱したときに、まず、内側部分２０ｂを溶融させて、その後、外周部分２０ａを溶融させることが可能になる。したがって、ろう材層２０の内側部分２０ｂが溶融し、この溶融したろう材がろう材層２０の外周縁に向けて拡がるように流れようとしても、その流れを、ろう材層２０の外周部分２０ａでせき止めることができる。また、加熱してセラミックス板１１と回路層１２とをろう付けする過程において、ろう材層２０の外周部分２０ａが溶融する時点を、全体を箔からなるろう材層を用いるのと比べて遅らせることが可能になり、この外周部分２０ａが溶融状態となっている時間を短縮することができる。
以上より、セラミックス板１１の表面に回路層１２をろう付けする際に、溶融したろう材が回路層１２の側面を伝って、半導体チップ１５が接合される表面に乗り上がるのを抑制することができる。 According to the power module substrate of the present embodiment manufactured in this way, the liquid phase temperature is higher than that of the brazing filler metal foil of the outer peripheral portion 20a because the inner portion 20b of the brazing filler metal layer 20 is formed of ultrafine powder. When the stacked body 14a is heated, the inner portion 20b can be melted first, and then the outer peripheral portion 20a can be melted. Therefore, even if the inner portion 20 b of the brazing filler metal layer 20 is melted and the molten brazing filler metal flows toward the outer peripheral edge of the brazing filler metal layer 20, the flow is changed to the outer peripheral portion 20 a of the brazing filler metal layer 20. You can stop it. Further, in the process of brazing the ceramic plate 11 and the circuit layer 12 by heating, the time when the outer peripheral portion 20a of the brazing filler metal layer 20 is melted is delayed as compared with the case of using the brazing filler metal layer. The time during which the outer peripheral portion 20a is in the molten state can be shortened.
As described above, when the circuit layer 12 is brazed to the surface of the ceramic plate 11, it is possible to suppress the molten brazing material from traveling on the side surface of the circuit layer 12 and climbing onto the surface to which the semiconductor chip 15 is bonded. it can.

この場合、内側部分２０ｂの超微粒子粉末は、外周部分２０ａとの液相温度の差が１０℃以上３０℃以下低くなるように微粒子化したものであれば、前記の作用効果が確実に奏効されることになる。すなわち、両液相温度の差が１０℃より小さいと、ろう付け時の加熱温度を加熱炉内の全域にわたってばらつき少なく均一にしなければ、外周部分２０ａが内側部分２０ｂと略同時に溶融し始めたり、あるいは外周部分２０ａが溶融した後に、内側部分２０ｂが溶融したりするおそれがある。また、両液相温度の差が３０℃より大きいと、ろう材層２０において、内側部分２０ｂを溶融させた後、外周部分２０ａを溶融させるまでに、この内側部分２０ｂのろう材を熱により変質させたり、あるいは外周部分２０ａおよび内側部分２０ｂの各組成が互いに大きく異なったことに起因して、ろう付け時に互いが反応し合い例えばろう付けの接合強度を低下させる等し、さらには、加熱炉の温度制御が困難になる等のおそれがある。   In this case, if the ultrafine particle powder of the inner portion 20b is finely divided so that the difference in liquid phase temperature from the outer peripheral portion 20a is lower by 10 ° C. or more and 30 ° C. or less, the above-mentioned effects are surely achieved. Will be. That is, if the difference between the liquid phase temperatures is less than 10 ° C., the outer peripheral portion 20a starts to melt almost simultaneously with the inner portion 20b unless the heating temperature during brazing is made uniform with little variation over the entire area in the heating furnace, Alternatively, after the outer peripheral portion 20a is melted, the inner portion 20b may be melted. Also, if the difference between the two liquid phase temperatures is greater than 30 ° C., after the inner portion 20b is melted in the brazing filler metal layer 20, the brazing filler in the inner portion 20b is altered by heat before the outer peripheral portion 20a is melted. Or because the compositions of the outer peripheral portion 20a and the inner portion 20b are greatly different from each other, they react with each other at the time of brazing, for example, the bonding strength of the brazing is reduced. It may be difficult to control the temperature.

ここで、この製造方法についての具体的な実施例について説明する。
まず、材質については、回路層１２および金属層１８を純度９９．９８ｗｔ％の純Ａｌ、セラミックス板１１をＡｌＮによりそれぞれ形成した。そして、ろう材層２０としてＡｌ−Ｓｉ系のろう材（Ａｌが９２．５ｗｔ％、Ｓｉが７．５ｗｔ％、固相温度が５７７℃、液相温度が６１５℃）を採用し、外周部分２０ａはその箔を使用し、内側部分２０ｂは１μｍ以下の超微粒子粉末として使用した。 Here, specific examples of the manufacturing method will be described.
First, regarding the materials, the circuit layer 12 and the metal layer 18 were formed of pure Al having a purity of 99.98 wt%, and the ceramic plate 11 was formed of AlN. The brazing filler metal layer 20 is made of an Al—Si brazing material (Al is 92.5 wt%, Si is 7.5 wt%, the solid phase temperature is 577 ° C., the liquid phase temperature is 615 ° C.), and the outer peripheral portion 20a. Used the foil, and the inner portion 20b was used as an ultrafine powder of 1 μm or less.

この内側部分に使用される超微粒子粉末のろう材を製造する方法としては、例えば特開平６−１７２８２０号公報に開示された熱プラズマ法による技術を用いた。
すなわち、２個のプラズマトーチからプラズマフレームを重畳させるようにして生成させ、その片方のプラズマトーチ（第１トーチ）のみに、ＡｌxＳｉy（x＝９２．５，y＝１００−x）となるようにとＡｌとＳｉを秤量・混合した粉末原料を供給し、他方のプラズマトーチ（第２トーチ）には原料を供給しない状態とし、超微粒子粉末を得る。そのときの実施条件は例えば以下の通りである。 As a method for producing a brazing material of ultrafine powder used for this inner portion, for example, a technique by a thermal plasma method disclosed in Japanese Patent Laid-Open No. 6-172820 was used.
That is, a plasma flame is generated from two plasma torches so as to overlap each other, and only one of the plasma torches (first torch) has AlxSiy (x = 92.5, y = 100−x). A powder raw material obtained by weighing, mixing Al, and Si is supplied, and the raw material is not supplied to the other plasma torch (second torch) to obtain ultrafine powder. The implementation conditions at that time are as follows, for example.

反応容器内圧 ： ０．０７ＭＰａ
反応容器雰囲気： Ａｒガス雰囲気
トーチ個数 ： ２
トーチ対向角度： 約８０度（２つのプラズマフレームが高温部で重畳）
第１トーチ作動条件
電流： ２００Ａ
電圧： ６０Ｖ
ガス： Ａｒ＝０．１３３ｌ／ｓ
Ｎ2＝０．１１６ｌ／ｓ
原料供給速度：０．１８ｇ／ｓ
第２トーチ作動条件
電流： ２５０Ａ
電圧： ４０Ｖ
ガス：Ａｒ＝０．１６６ｌ／ｓ
Ｎ2＝０．０５０ｌ／ｓ
原料供給せず。 Reaction vessel internal pressure: 0.07 MPa
Reaction vessel atmosphere: Ar gas atmosphere torch Number: 2
Torch facing angle: Approx. 80 degrees (Two plasma flames overlap at high temperature)
First torch operating condition Current: 200A
Voltage: 60V
Gas: Ar = 0.133 l / s
N 2 = 0.116 l / s
Raw material supply rate: 0.18 g / s
Second torch operating condition Current: 250A
Voltage: 40V
Gas: Ar = 0.166 l / s
N 2 = 0.050 l / s
Without supplying raw materials.

また、各層の厚さについては、回路層１２および金属層１８を約０．４ｍｍ、ろう材層２０については外周部分２０ａを約３５μｍ、内側部分２０ｂを約２０μｍとし、セラミックス板１１を約０．６３５ｍｍとした。なお、外周部分２０ａの外周縁の縦および横の寸法をそれぞれ約２８ｍｍおよび約７０ｍｍとし、この外周縁と内周縁との距離は約５ｍｍとした。そして、平面視四角形とされたろう材層２０の内側部分２０ｂは、縦および横の寸法をそれぞれ約１８ｍｍおよび約６０ｍｍとした。
そして、積層体１４ａを接合面に２００KＰａの圧力を作用させた状態として真空状態の加熱炉内に置いて、この加熱炉内を約５５０℃になるまで１０℃／ｍｉｎで加熱する。その後、約５５０℃の温度を約９０分間保持した後に、さらに約６４５℃になるまで１０℃／ｍｉｎで加熱し、そして、約６４５℃の温度を約４０分間保持した後に徐冷して、パワーモジュール用基板１４を形成した。
このように製造されたパワーモジュール用基板１４は、回路層１２の側面及び表面へのろう材のしみ出しは生じなかった。 The thickness of each layer is about 0.4 mm for the circuit layer 12 and the metal layer 18, about 35 μm for the outer peripheral portion 20 a for the brazing filler metal layer 20, about 20 μm for the inner portion 20 b, and about 0.1 mm for the ceramic plate 11. It was set to 635 mm. The vertical and horizontal dimensions of the outer peripheral edge of the outer peripheral portion 20a were about 28 mm and about 70 mm, respectively, and the distance between the outer peripheral edge and the inner peripheral edge was about 5 mm. And the inner part 20b of the brazing filler metal layer 20 made into a square in plan view has a vertical and horizontal dimension of about 18 mm and about 60 mm, respectively.
Then, the laminated body 14a is placed in a vacuum heating furnace with a pressure of 200 KPa acting on the joint surface, and the inside of the heating furnace is heated at 10 ° C./min until it reaches about 550 ° C. After that, after holding the temperature of about 550 ° C. for about 90 minutes, further heating at 10 ° C./min until reaching about 645 ° C., holding the temperature of about 645 ° C. for about 40 minutes, and then gradually cooling to power A module substrate 14 was formed.
In the power module substrate 14 manufactured in this way, no seepage of the brazing material to the side surface and the surface of the circuit layer 12 occurred.

なお、本発明は前記実施の形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲において種々の変更を加えることが可能である。
例えば、前記実施形態では、パワーモジュール用基板１４として金属層１８を備えた構成を示したが、この金属層１８を設けなくてもよい。
また、ろう材層２０の内側部分２０ｂは超微粒子粉末により構成されるが、外周部分２０ａは箔でなくても粉末状等の形態であってもよい。その場合、外周部分２０ａは内側部分２０ｂの超微粒子よりも粒径が大きいものが用いられ、しみ出しを抑制するためには、３０ｎｍ以上の粒径である必要があるとともに、前記した溶融時期を内側部分２０ｂに対して遅らせるために、内側部分２０ｂの超微粒子粉末に対して例えば、１５ｎｍ以上１００ｎｍ以下の粒径差のものであることが好ましい。また、外周部分２０ａおよび内側部分２０ｂを形成する各材質は、前記実施形態で示したものに限られるものではない。さらに、外周部分２０ａは、内側部分２０ｂを形成する材質よりも液相温度が高い材質で形成されていてもよい。 The present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.
For example, in the above-described embodiment, the configuration in which the metal layer 18 is provided as the power module substrate 14 is shown, but the metal layer 18 may not be provided.
Moreover, although the inner part 20b of the brazing filler metal layer 20 is comprised by ultrafine particle powder, the outer peripheral part 20a may not be foil but may be a powder form. In that case, the outer peripheral portion 20a is used having a particle size larger than the ultrafine particles of the inner portion 20b. In order to suppress the seepage, the outer peripheral portion 20a needs to have a particle size of 30 nm or more, and the melting time described above is used. In order to delay with respect to the inner part 20b, it is preferable that the particle size difference is, for example, 15 nm or more and 100 nm or less with respect to the ultrafine particle powder of the inner part 20b. Moreover, each material which forms the outer peripheral part 20a and the inner part 20b is not restricted to what was shown by the said embodiment. Furthermore, the outer peripheral portion 20a may be formed of a material having a higher liquidus temperature than the material forming the inner portion 20b.

さらに、前記実施形態では、ろう材層２０の外周部分２０ａとして、回路層１２の裏面の外周縁に沿ってその全周にわたって延在した構成を示したが、これに代えて、例えば図４に示されるように、周方向に複数に分割された外周部分２０ａを採用してもよい。
また、前記実施形態では、ろう材層２０として、内側部分２０ｂの外周縁と、外周部分２０ａの内周縁との間に略隙間のない構成を示したが、これに代えて、例えば約５０μｍ程度であれば隙間を設けてもよい。さらに、図４に示したように、分割された外周部分２０ａでは、その周方向に隙間のない状態でセラミックス板１１に配置してもよいし、あるいは約５０μｍ程度であればこの周方向に隙間を設けてもよい。また、外周部分２０ａおよび内側部分２０ｂの平面視形状は前記実施形態のものに限られるものではない。 Furthermore, in the said embodiment, although the structure extended over the perimeter along the outer periphery of the back surface of the circuit layer 12 was shown as the outer peripheral part 20a of the brazing material layer 20, it replaces with this, for example in FIG. As shown, an outer peripheral portion 20a divided into a plurality in the circumferential direction may be employed.
In the above embodiment, the brazing material layer 20 has a configuration without a substantial gap between the outer peripheral edge of the inner portion 20b and the inner peripheral edge of the outer peripheral portion 20a. Instead, for example, about 50 μm. If so, a gap may be provided. Further, as shown in FIG. 4, the divided outer peripheral portion 20a may be arranged on the ceramic plate 11 without any gap in the circumferential direction, or the gap in the circumferential direction is about 50 μm. May be provided. Moreover, the planar view shape of the outer peripheral part 20a and the inner part 20b is not restricted to the thing of the said embodiment.

この発明の一実施形態に係るパワーモジュール用基板を適用したパワーモジュールを示す全体図である。1 is an overall view showing a power module to which a power module substrate according to an embodiment of the present invention is applied. この発明の一実施形態に係るパワーモジュール用基板を製造する途中の積層体の断面側面図である。It is a cross-sectional side view of the laminated body in the middle of manufacturing the board | substrate for power modules which concerns on one Embodiment of this invention. 図２の積層体に用いられているろう材層を示す平面図である。It is a top view which shows the brazing material layer used for the laminated body of FIG. 図３のろう材層の縦断面図である。It is a longitudinal cross-sectional view of the brazing filler metal layer of FIG. この発明の他の実施形態に係るパワーモジュール用基板の製造方法で用いられるろう材層の平面図である。It is a top view of the brazing material layer used with the manufacturing method of the board | substrate for power modules which concerns on other embodiment of this invention.

符号の説明Explanation of symbols

１０ パワーモジュール １１ セラミックス板 １２ 回路層 １４ パワーモジュール用基板 １４ａ 積層体 １５ 半導体チップ ２０ ろう材層 ２０ａ 外周部分 ２０ｂ 内側部分   DESCRIPTION OF SYMBOLS 10 Power module 11 Ceramic board 12 Circuit layer 14 Power module substrate 14a Laminate 15 Semiconductor chip 20 Brazing material layer 20a Outer peripheral part 20b Inner part

Claims (4)

セラミックス板の表面にろう材層と回路層とをこの順に配置して積層体とした後に、この積層体を積層方向に加圧した状態で加熱してろう材層を溶融させることにより、セラミックス板の表面に回路層がろう付けされてなり、この回路層の表面に半導体チップがはんだ接合されるパワーモジュール用基板を形成するパワーモジュール用基板の製造方法であって、
前記ろう材層は、前記積層体において、表面に前記回路層の外周縁部が配置される外周部分と、この外周部分に囲まれた内側部分とを備え、前記内側部分は、直径０．１μｍ以下の超微粒子粉末のろう材により形成され、前記外周部分は、内側部分のろう材よりも粒径が大きいろう材又はろう材箔により形成されていることを特徴とするパワーモジュール用基板の製造方法。 A ceramic plate is obtained by arranging a brazing filler metal layer and a circuit layer in this order on the surface of the ceramic plate to form a laminated body, and then heating the laminated body in a pressed state in the laminating direction to melt the brazing filler metal layer. A power module substrate is formed by brazing a circuit layer on the surface of the power module, and forming a power module substrate on which the semiconductor chip is soldered to the surface of the circuit layer,
The brazing material layer includes an outer peripheral portion on the surface of which the outer peripheral edge portion of the circuit layer is disposed, and an inner portion surrounded by the outer peripheral portion, and the inner portion has a diameter of 0.1 μm. Production of a power module substrate, characterized in that the outer peripheral portion is formed of a brazing material or brazing material foil having a larger particle size than the brazing material of the inner portion. Method. 請求項１記載のパワーモジュール用基板の製造方法であって、
前記外周部分は前記内側部分よりも厚く形成されていることを特徴とするパワーモジュール用基板の製造方法。 A method for manufacturing a power module substrate according to claim 1,
The method of manufacturing a power module substrate, wherein the outer peripheral portion is formed thicker than the inner portion. セラミックス板の表面に回路層がろう付けされてなり、この回路層の表面に半導体チップがはんだ接合されるパワーモジュール用基板であって、
請求項１または２に記載のパワーモジュール用基板の製造方法により形成されたことを特徴とするパワーモジュール用基板。 A power module substrate in which a circuit layer is brazed to the surface of a ceramic plate, and a semiconductor chip is soldered to the surface of the circuit layer,
A power module substrate formed by the method for manufacturing a power module substrate according to claim 1. セラミックス板の表面に回路層がろう付けされたパワーモジュール用基板と、回路層の表面にはんだ接合された半導体チップとを備えたパワーモジュールであって、
前記パワーモジュール用基板は、請求項１または２に記載のパワーモジュール用基板の製造方法により形成されたことを特徴とするパワーモジュール。 A power module including a power module substrate having a circuit layer brazed to the surface of a ceramic plate, and a semiconductor chip soldered to the surface of the circuit layer,
The power module substrate is formed by the method for manufacturing a power module substrate according to claim 1 or 2.
JP2007012517A 2007-01-23 2007-01-23 Power module substrate manufacturing method, power module substrate, and power module Expired - Fee Related JP4702293B2 (en)

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