JP2008178261A - Power converter - Google Patents

Power converter Download PDF

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JP2008178261A
JP2008178261A JP2007010927A JP2007010927A JP2008178261A JP 2008178261 A JP2008178261 A JP 2008178261A JP 2007010927 A JP2007010927 A JP 2007010927A JP 2007010927 A JP2007010927 A JP 2007010927A JP 2008178261 A JP2008178261 A JP 2008178261A
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terminal
control device
emitter
gate
connection terminal
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Hidenobu Kusumoto
英伸 楠本
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Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
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Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To obtain a power converter that prevents breakage of each semiconductor device of a power converter, when a plurality of the semiconductor devices are connected to each main circuit bus-bar in parallel so as to control each semiconductor device by a single controller. <P>SOLUTION: A common-mode current countermeasure component 18 is connected to a wiring 14 between a gate connection terminal G01 of a controller 5 and a connection point G00 and a wiring 16 in between an emitter connection terminal E01 and a connection point E00, and a common-mode current countermeasure component 19 is connected to a wiring 15, between a gate connection terminal G02 of the controller 5 and the connection point G00 and a wiring 17, between an emitter connection terminal E02 and the connection point E00. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

この発明は、主回路母線に対して複数の半導体素子を並列接続した電力変換装置に関するものである。   The present invention relates to a power conversion device in which a plurality of semiconductor elements are connected in parallel to a main circuit bus.

図６は従来の電力変換装置の回路構成図を示し、同一の制御装置により並列接続した複数の半導体素子を駆動する回路が示されている。又、図７は図６の電力変換装置の要部の配線構造図である。図において、１，２は電力変換装置の主回路母線、３，４は主回路母線１，２に並列に接続された半導体素子であるＩＧＢＴ、５はＩＧＢＴ３，４をそれぞれオン・オフさせるゲート信号を発生する制御装置、Ｃ１，Ｃ２はＩＧＢＴ３，４のコレクタ端子、Ｇ１，Ｇ２はＩＧＢＴ３，４のゲート端子、Ｅ１１，Ｅ１２，Ｅ２１，Ｅ２２はＩＧＢＴ３，４のエミッタ端子、６，７は一端がコレクタ端子Ｃ１，Ｃ２にそれぞれ接続された配線、８，９は一端がＩＧＢＴ３，４のエミッタ端子Ｅ１１、Ｅ２１にそれぞれ接続された配線、ＣＯは主回路母線１と配線６，７との接続点、ＥＯは主回路母線２と配線８，９との接続点、Ｇ０１は配線１０を介してゲート端子Ｇ１と接続された制御装置５のゲート接続端子、Ｅ０１は配線１１を介してエミッタ端子Ｅ１２と接続された制御装置５のエミッタ接続端子、Ｇ０２は配線１２を介してゲート端子Ｇ２と接続された制御装置５のゲート接続端子、Ｅ０２は配線１３を介してエミッタ端子Ｅ２２と接続された制御装置５のエミッタ接続端子であり、ゲート接続端子Ｇ０１，Ｇ０２は制御装置５内において配線１４，１５を介して接続点Ｇ００に接続され、エミッタ接続端子Ｅ０１，Ｅ０２は制御装置５内において配線１６，１７を介して接続点Ｅ００と接続される。   FIG. 6 shows a circuit configuration diagram of a conventional power converter, and shows a circuit for driving a plurality of semiconductor elements connected in parallel by the same controller. FIG. 7 is a wiring structure diagram of the main part of the power conversion device of FIG. In the figure, 1 and 2 are main circuit buses of the power converter, 3 and 4 are semiconductor elements connected in parallel to the main circuit buses 1 and 2, and 5 is a gate signal for turning on and off the IGBTs 3 and 4, respectively. C1, C2 are IGBT 3 and 4 collector terminals, G1 and G2 are IGBT 3 and 4 gate terminals, E11, E12, E21 and E22 are IGBT 3 and 4 emitter terminals, and 6 and 7 are collectors at one end. Wirings connected to the terminals C1 and C2, 8 and 9 are connected to the emitter terminals E11 and E21 of the IGBTs 3 and 4, respectively, CO is a connection point between the main circuit bus 1 and the wirings 6 and 7, EO Is a connection point between the main circuit bus 2 and the wirings 8 and 9, G01 is a gate connection terminal of the control device 5 connected to the gate terminal G1 through the wiring 10, and E01 is an emitter through the wiring 11. The emitter connection terminal of the control device 5 connected to the data terminal E12, G02 is connected to the gate connection terminal of the control device 5 connected to the gate terminal G2 via the wiring 12, and E02 is connected to the emitter terminal E22 via the wiring 13. The gate connection terminals G01 and G02 are connected to the connection point G00 through the wirings 14 and 15 in the control device 5, and the emitter connection terminals E01 and E02 are connected to the connection point G00 in the control device 5. It is connected to the connection point E00 through 16 and 17.

上記構成において、配線１１，１３が制御装置５内において配線１６，１７を介して接続点Ｇ００で接続されているので、エミッタ端子Ｅ１２とＥ２２が短絡され、ＩＧＢＴ３よりＩＧＢＴ４が先にターンオフすると、エミッタ端子Ｅ２１と接続点ＥＯとの間、即ち配線９のインピーダンスによりエミッタ端子Ｅ１２から接続点Ｅ００を介してエミッタ端子Ｅ２２に電流が流れ、ＩＧＢＴ３，４を破損する。即ち、図６のエミッタ端子Ｅ１２からエミッタ端子Ｅ２２に破線に示すように電流ｉ１が流れると、この電流ｉ１は接続点ＣＯ，ＥＯ間に流れる主回路電流とほぼ同じ大きさの電流となる。しかしながら、エミッタ端子Ｅ１２〜Ｅ２２間の配線１１，１３は本来ゲート信号用の電流が流れることを想定して設計されており、細くて電流容量が少ない線材が使用されている。このため、エミッタ端子Ｅ１２〜Ｅ２２間に主回路電流と同等の電流が流れると、発熱により溶断するおそれがあった。   In the above configuration, since the wirings 11 and 13 are connected at the connection point G00 via the wirings 16 and 17 in the control device 5, the emitter terminals E12 and E22 are short-circuited, and when the IGBT 4 is turned off earlier than the IGBT 3, the emitter Current flows from the emitter terminal E12 to the emitter terminal E22 through the connection point E00 between the terminal E21 and the connection point EO, that is, due to the impedance of the wiring 9, and the IGBTs 3 and 4 are damaged. That is, when a current i1 flows from the emitter terminal E12 to the emitter terminal E22 in FIG. 6 as indicated by a broken line, the current i1 becomes substantially the same as the main circuit current flowing between the connection points CO and EO. However, the wirings 11 and 13 between the emitter terminals E12 to E22 are originally designed on the assumption that a current for a gate signal flows, and a thin wire material having a small current capacity is used. For this reason, when a current equivalent to the main circuit current flows between the emitter terminals E12 to E22, there is a risk of fusing due to heat generation.

なお、この出願の発明に関連する先行技術文献情報としては、次のものがある。
特開平９−２６１９４８号公報 特開２０００−９１８９７号公報 The prior art document information related to the invention of this application includes the following.
Japanese Patent Laid-Open No. 9-261948 JP 2000-91897 A

上記したように、エミッタ端子Ｅ１２〜Ｅ２２間に電流が流れると、配線が溶断し、ＩＧＢＴ３，４を破損するおそれがあった。   As described above, when a current flows between the emitter terminals E12 to E22, the wiring may melt and damage the IGBTs 3 and 4.

この発明は上記のような課題を解決するために成されたものであり、複数の半導体素子を主回路母線に並列接続し、この各半導体素子を１つの制御装置により制御する場合に、各半導体素子の破損を防止することができる電力変換装置を得ることを目的とする。   The present invention has been made in order to solve the above-described problems. When a plurality of semiconductor elements are connected in parallel to a main circuit bus and each semiconductor element is controlled by one control device, each semiconductor element is controlled. It is an object of the present invention to obtain a power conversion device that can prevent element breakage.

この発明の請求項１に係る電力変換装置は、主回路母線に並列接続された複数の半導体素子の各ゲート端子に制御装置のゲート接続端子をそれぞれ接続するとともに、各半導体素子のエミッタ端子に制御装置のエミッタ接続端子をそれぞれ接続し、かつ制御装置の各ゲート接続端子間及び各エミッタ接続端子間を制御装置内の接続点においてそれぞれ接続し、制御装置からのゲート信号により各半導体素子をオンオフ制御させる電力変換装置において、制御装置の一方のゲート接続端子とその接続点間の配線及び一方のエミッタ接続端子とその接続点間の配線にコモンモード電流対策部品を接続するとともに、制御装置の他方のゲート接続端子とその接続点間の配線及び他方のエミッタ接続端子とその接続点間の配線にコモンモード電流対策部品を接続したものである。   According to a first aspect of the present invention, there is provided a power conversion device in which a gate connection terminal of a control device is connected to each gate terminal of a plurality of semiconductor elements connected in parallel to a main circuit bus, and control is performed on an emitter terminal of each semiconductor element. Connect each emitter connection terminal of the device, and connect each gate connection terminal and each emitter connection terminal of the control device at the connection point in the control device, and control each semiconductor element on / off by the gate signal from the control device In the power converter to be connected, the common mode current countermeasure component is connected to the wiring between one gate connection terminal of the control device and the connection point and the wiring between the one emitter connection terminal and the connection point, and the other of the control device. Common mode current countermeasures for the wiring between the gate connection terminal and its connection point and the wiring between the other emitter connection terminal and its connection point Which are connected the goods.

請求項２に係る電力変換装置は、主回路母線に並列接続された複数の半導体素子の各ゲート端子に制御装置のゲート接続端子をそれぞれ接続するとともに、各半導体素子のエミッタ端子に制御装置のエミッタ接続端子をそれぞれ接続し、かつ制御装置の各ゲート接続端子間及び各エミッタ接続端子間を制御装置内の接続点においてそれぞれ接続し、制御装置からのゲート信号により各半導体素子をオンオフ制御させる電力変換装置において、一方の半導体素子のゲート端子と制御装置の一方のゲート接続端子とを接続する配線及び一方の半導体素子のエミッタ端子と制御装置の一方のエミッタ接続端子とを接続する配線にコモンモード電流対策部品を接続するとともに、他方の半導体素子のゲート端子と制御装置の他方のゲート接続端子とを接続する配線及び他方の半導体素子のミッタ端子と制御装置の他方のエミッタ接続端子とを接続する配線にコモンモード電流対策部品を接続したものである。   The power conversion device according to claim 2 connects the gate connection terminal of the control device to each gate terminal of the plurality of semiconductor elements connected in parallel to the main circuit bus, and also connects the emitter of the control device to the emitter terminal of each semiconductor device. Power conversion that connects each connection terminal, connects each gate connection terminal and each emitter connection terminal of the control device at a connection point in the control device, and controls each semiconductor element on / off by a gate signal from the control device In the device, a common mode current is applied to a wiring connecting the gate terminal of one semiconductor element and one gate connection terminal of the control device, and to a wiring connecting the emitter terminal of one semiconductor element and one emitter connection terminal of the control device. Connect the countermeasure parts and connect the gate terminal of the other semiconductor element to the other gate connection terminal of the control device. The wiring connecting the other of the emitter connecting terminal emitter terminal and the control device of the wire and the other semiconductor elements continue to which are connected a common mode current suppression components.

請求項３に係る電力変換装置は、主回路母線に並列接続された複数の半導体素子の各ゲート端子に制御装置のゲート接続端子をそれぞれ接続するとともに、各半導体素子のエミッタ端子に制御装置のエミッタ接続端子をそれぞれ接続し、かつ制御装置の各ゲート接続端子間及び各エミッタ接続端子間を制御装置内の接続点においてそれぞれ接続し、制御装置からのゲート信号により各半導体素子をオンオフ制御させる電力変換装置において、各半導体素子のエミッタ端子間にコンデンサを接続したものである。   According to a third aspect of the present invention, there is provided a power converter including: a gate connection terminal of a control device connected to each gate terminal of a plurality of semiconductor elements connected in parallel to a main circuit bus; and an emitter of the control device connected to an emitter terminal of each semiconductor element. Power conversion that connects each connection terminal, connects each gate connection terminal and each emitter connection terminal of the control device at a connection point in the control device, and controls each semiconductor element on / off by a gate signal from the control device In the apparatus, a capacitor is connected between the emitter terminals of each semiconductor element.

請求項４に係る電力変換装置は、主回路母線に並列接続された複数の半導体素子の各ゲート端子に制御装置のゲート接続端子をそれぞれ接続するとともに、各半導体素子のエミッタ端子に制御装置のエミッタ接続端子をそれぞれ接続し、かつ制御装置の各ゲート接続端子間及び各エミッタ接続端子間を制御装置内の接続点においてそれぞれ接続し、制御装置からのゲート信号により各半導体素子をオンオフ制御させる電力変換装置において、各半導体素子のエミッタ端子と主回路母線間の配線を短くしたものである。   According to a fourth aspect of the present invention, there is provided a power conversion device in which a gate connection terminal of a control device is connected to each gate terminal of a plurality of semiconductor elements connected in parallel to a main circuit bus, and an emitter of the control device is connected to an emitter terminal of each semiconductor device. Power conversion that connects each connection terminal, connects each gate connection terminal and each emitter connection terminal of the control device at a connection point in the control device, and controls each semiconductor element on / off by a gate signal from the control device In the apparatus, the wiring between the emitter terminal of each semiconductor element and the main circuit bus is shortened.

請求項５に係る電力変換装置は、主回路母線に並列接続された複数の半導体素子の各ゲート端子に制御装置のゲート接続端子をそれぞれ接続するとともに、各半導体素子のエミッタ端子に制御装置のエミッタ接続端子をそれぞれ接続し、かつ制御装置の各ゲート接続端子間及び各エミッタ接続端子間を制御装置内の接続点においてそれぞれ接続し、制御装置からのゲート信号により各半導体素子をオンオフ制御させる電力変換装置において、各半導体素子のエミッタ端子と主回路母線間の配線を短くするとともに、各半導体素子のコレクタ端子と主回路母線間の配線を短くしたものである。   According to a fifth aspect of the present invention, there is provided a power conversion device in which a gate connection terminal of a control device is connected to each gate terminal of a plurality of semiconductor elements connected in parallel to a main circuit bus, and an emitter of the control device is connected to an emitter terminal of each semiconductor device. Power conversion that connects each connection terminal, connects each gate connection terminal and each emitter connection terminal of the control device at a connection point in the control device, and controls each semiconductor element on / off by a gate signal from the control device In the apparatus, the wiring between the emitter terminal of each semiconductor element and the main circuit bus is shortened, and the wiring between the collector terminal of each semiconductor element and the main circuit bus is shortened.

以上のようにこの発明の請求項１によれば、制御装置の一方のゲート接続端子とその接続点間の配線及び一方のエミッタ接続端子とその接続点間の配線にコモンモード電流対策部品を接続するとともに、制御装置の他方のゲート接続端子とその接続点間の配線及び他方のエミッタ接続端子とその接続点間の配線にコモンモード電流対策部品を接続しており、コモンモード電流対策部品を接続したことにより、エミッタ接続端子の接続点を通って流れ、半導体素子の破損原因となる電流が抑制され、半導体素子の破損を回避することができる。   As described above, according to the first aspect of the present invention, the common mode current countermeasure component is connected to the wiring between one gate connection terminal and its connection point of the control device and the wiring between one emitter connection terminal and its connection point. In addition, the common mode current countermeasure component is connected to the wiring between the other gate connection terminal of the control device and its connection point and the wiring between the other emitter connection terminal and its connection point, and the common mode current countermeasure component is connected. As a result, the current that flows through the connection point of the emitter connection terminal and causes damage to the semiconductor element is suppressed, and damage to the semiconductor element can be avoided.

又、請求項２によれば、一方の半導体素子のゲート端子と制御装置の一方のゲート接続端子とを接続する配線及び一方の半導体素子のエミッタ端子と制御装置の一方のエミッタ接続端子とを接続する配線にコモンモード電流対策部品を接続するとともに、他方の半導体素子のゲート端子と制御装置の他方のゲート接続端子とを接続する配線及び他方の半導体素子のエミッタ端子と制御装置の他方のエミッタ接続端子とを接続する配線にコモンモード電流対策部品を接続しており、コモンモード電流対策部品を接続したことにより、エミッタ接続端子の接続点を通って流れ、半導体素子の破損原因となる電流が抑制され、半導体素子の破損を回避することができる。   According to the second aspect of the present invention, the wiring for connecting the gate terminal of one semiconductor element and one gate connection terminal of the control device, and the emitter terminal of one semiconductor element and one emitter connection terminal of the control device are connected. A common mode current countermeasure component is connected to the wiring to be connected, the wiring connecting the gate terminal of the other semiconductor element and the other gate connection terminal of the control device, and the emitter terminal of the other semiconductor element and the other emitter connection of the control device A common mode current countermeasure component is connected to the wiring connecting the terminal. By connecting the common mode current countermeasure component, the current that flows through the connection point of the emitter connection terminal and causes damage to the semiconductor element is suppressed. Thus, damage to the semiconductor element can be avoided.

請求項３によれば、各半導体素子のエミッタ端子間にコンデンサを接続しており、エミッタ接続端子の接続点を通ってエミッタ端子間に流れる電流はコンデンサに吸収されて抑制され、半導体素子の破損を回避することができる。   According to the third aspect of the present invention, the capacitor is connected between the emitter terminals of each semiconductor element, and the current flowing between the emitter terminals through the connection point of the emitter connection terminal is absorbed and suppressed by the capacitor, and the semiconductor element is damaged. Can be avoided.

請求項４によれば、各半導体素子のエミッタ端子と主回路母線間の配線を短くしたので、該配線のインピーダンスが抑制され、制御装置のエミッタ接続端子の接続点を介して流れる電流も抑制され、半導体素子の破損を回避することができる。   According to claim 4, since the wiring between the emitter terminal of each semiconductor element and the main circuit bus is shortened, the impedance of the wiring is suppressed, and the current flowing through the connection point of the emitter connection terminal of the control device is also suppressed. The damage of the semiconductor element can be avoided.

請求項５によれば、各半導体素子のエミッタ端子と主回路母線間の配線を短くするとともに、各半導体素子のコレクタ端子と主回路母線間の配線を短くしたので、各半導体素子のエミッタ端子と主回路母線間の配線のインピーダンスが抑制され、制御装置のエミッタ接続端子の接続点を介して流れる電流も抑制され、半導体素子の破損を回避することができる。   According to the fifth aspect, the wiring between the emitter terminal of each semiconductor element and the main circuit bus is shortened, and the wiring between the collector terminal of each semiconductor element and the main circuit bus is shortened. The impedance of the wiring between the main circuit buses is suppressed, the current flowing through the connection point of the emitter connection terminal of the control device is also suppressed, and damage to the semiconductor element can be avoided.

実施最良形態１
以下、この発明を実施するための最良の形態を図面とともに説明する。図１はこの発明の実施最良形態１による電力変換装置の回路構成図を示し、主回路母線１，２に並列接続されたＩＧＢＴ３，４の各ゲート端子Ｇ１，Ｇ２に制御装置５のゲート接続端子Ｇ０１、Ｇ０２をそれぞれ接続するとともに、各ＩＧＢＴ３，４のエミッタ端子Ｅ１２，Ｅ２２に制御装置５のエミッタ接続端子Ｅ０１，Ｅ０２をそれぞれ接続し、制御装置５の各ゲート接続端子Ｇ０１、Ｇ０２間及び各エミッタ接続端子Ｅ０１，Ｅ０２間を制御装置５内の接続点Ｇ００，Ｅ００でそれぞれ接続し、制御装置５からのゲート信号により各ＩＧＢＴ３，４をオンオフ制御させている。 Best Embodiment 1
The best mode for carrying out the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit configuration diagram of a power conversion device according to Embodiment 1 of the present invention, in which gate terminals G1, G2 of IGBTs 3, 4 connected in parallel to main circuit buses 1, 2 are connected to gate connection terminals of a control device 5. G01 and G02 are connected to each other, and the emitter connection terminals E01 and E02 of the control device 5 are connected to the emitter terminals E12 and E22 of the IGBTs 3 and 4, respectively, and between the gate connection terminals G01 and G02 of the control device 5 and each emitter. The connection terminals E01 and E02 are connected at connection points G00 and E00 in the control device 5, respectively, and the IGBTs 3 and 4 are controlled to be turned on and off by gate signals from the control device 5.

そして、制御装置５のゲート接続端子Ｇ０１と接続点Ｇ００間の配線１４及びエミッタ接続端子Ｅ０１と接続点Ｅ００間の配線１６にコモンモード電流対策部品１８を接続するとともに、制御装置５のゲート接続端子Ｇ０２と接続点Ｇ００間の配線１５及びエミッタ接続端子Ｅ０２と接続点Ｅ００間の配線１７にコモンモード電流対策部品１９接続する。   The common mode current countermeasure component 18 is connected to the wiring 14 between the gate connection terminal G01 and the connection point G00 of the control device 5 and the wiring 16 between the emitter connection terminal E01 and the connection point E00, and the gate connection terminal of the control device 5 is connected. The common mode current countermeasure component 19 is connected to the wiring 15 between G02 and the connection point G00 and the wiring 17 between the emitter connection terminal E02 and the connection point E00.

上記構成において、コモンモード電流対策部品１８，１９は複数の配線１４と１６及び１５と１７が存在する場合、この配線に通流する電流の総和が零になるように各配線の電流を抑制する。ＩＧＢＴ３，４の破損原因となる電流ｉ１は接続点Ｅ００を介した配線１６，１７のみに通流するので、接続点Ｇ００を介した配線１４，１５と接続点Ｅ００を介した配線１６，１７にコモンモード電流対策部品１８，１９を接続すると、接続点Ｅ００を介して流れる電流ｉ１が抑制され、ＩＧＢＴ３，４の破損を回避することができる。   In the above configuration, when the plurality of wirings 14 and 16 and 15 and 17 are present, the common mode current countermeasure components 18 and 19 suppress the current of each wiring so that the sum of the currents flowing through the wirings becomes zero. . Since the current i1 that causes damage to the IGBTs 3 and 4 flows only through the wirings 16 and 17 via the connection point E00, the current i1 flows through the wirings 14 and 15 via the connection point G00 and the wirings 16 and 17 via the connection point E00. When the common mode current countermeasure components 18 and 19 are connected, the current i1 flowing through the connection point E00 is suppressed, and damage to the IGBTs 3 and 4 can be avoided.

実施最良形態２
図２はこの発明の実施最良形態２による電力変換装置の回路構成図を示し、基本的構成は実施最良形態１と同様である。そして、ＩＧＢＴ３のゲート端子Ｇ１と制御装置５のゲート接続端子Ｇ０１とを接続する配線１０及びＩＧＢＴ３のエミッタ端子Ｅ１２と制御装置５のエミッタ接続端子Ｅ０１とを接続する配線１１にコモンモード電流対策部品２０を接続するとともに、ＩＧＢＴ４のゲート端子Ｇ２と制御装置５のゲート接続端子Ｇ０２とを接続する配線１２及びＩＧＢＴ４のエミッタ端子Ｅ２２と制御装置５のエミッタ接続端子Ｅ０２とを接続する配線１３にコモンモード電流対策部品２１を接続する。 Embodiment 2
FIG. 2 is a circuit configuration diagram of a power conversion device according to the second embodiment of the present invention, and the basic configuration is the same as that of the first embodiment. The common mode current countermeasure component 20 is connected to the wiring 10 that connects the gate terminal G1 of the IGBT 3 and the gate connection terminal G01 of the control device 5 and the wiring 11 that connects the emitter terminal E12 of the IGBT 3 and the emitter connection terminal E01 of the control device 5. , And the wiring 12 connecting the gate terminal G2 of the IGBT 4 and the gate connection terminal G02 of the control device 5 and the wiring 13 connecting the emitter terminal E22 of the IGBT 4 and the emitter connection terminal E02 of the control device 5 to the common mode current. The countermeasure component 21 is connected.

上記構成において、 ＩＧＢＴ３，４の破損原因となる電流ｉ１は接続点Ｅ００を介した配線１１，１３のみに通流するので、接続点Ｇ００を介した配線１０，１２と接続点Ｅ００を介した配線１１，１３にコモンモード電流対策部品２０，２１を接続すると、接続点Ｅ００を介して流れる電流ｉ１が抑制され、ＩＧＢＴ３，４の破損を回避することができる。   In the above configuration, the current i1 that causes damage to the IGBTs 3 and 4 flows only through the wirings 11 and 13 via the connection point E00. Therefore, the wirings 10 and 12 through the connection point G00 and the wirings through the connection point E00. When common mode current countermeasure components 20 and 21 are connected to 11 and 13, the current i1 flowing through the connection point E00 is suppressed, and damage to the IGBTs 3 and 4 can be avoided.

実施最良形態３
図３は実施最良形態３による電力変換装置の回路構成図を示し、基本的構成は実施最良形態１と同様である。そして、ＩＧＢＴ３，４のエミッタ端子Ｅ１１，Ｅ２１間にコンデンサＣPを接続する。 Embodiment 3
FIG. 3 shows a circuit configuration diagram of the power conversion device according to the third embodiment, and the basic configuration is the same as that of the first embodiment. Then, a capacitor C P between the emitter terminals E11, E21 of the IGBTs 3, 4.

上記構成において、接続点Ｅ００を介して配線１１，１３に流れる電流ｉ１はコンデンサＣPに吸収され、ＩＧＢＴ３，４の破損を回避することができる。 In the above structure, a current i1 flowing through the wiring 11 and 13 via the node E00 is absorbed in the capacitor C P, it is possible to avoid damage to the IGBTs 3, 4.

実施最良形態４
図４は実施最良形態４による電力変換装置の要部の配線構造図を示し、基本的構成は実施最良形態１と同様である。そして、ＩＧＢＴ３のエミッタ端子Ｅ１１と接続点ＥＯとを接続する配線８及びＩＧＢＴ４のエミッタ端子Ｅ２１と接続点ＥＯとを接続する配線９を短くしたものである。 Embodiment 4
FIG. 4 shows a wiring structure diagram of the main part of the power conversion device according to the fourth embodiment, and the basic configuration is the same as that of the first embodiment. The wiring 8 connecting the emitter terminal E11 of the IGBT 3 and the connection point EO and the wiring 9 connecting the emitter terminal E21 of the IGBT 4 and the connection point EO are shortened.

実施最良形態４においては、上記したように、配線８，９を短くしたので、配線８，９のインピーダンスが抑制され、接続点Ｅ００を介して流れる電流ｉ１が抑制され、ＩＧＢＴ３，４の破損を回避することができる。   In the fourth embodiment, as described above, since the wirings 8 and 9 are shortened, the impedance of the wirings 8 and 9 is suppressed, the current i1 flowing through the connection point E00 is suppressed, and the IGBTs 3 and 4 are damaged. It can be avoided.

実施最良形態５
図５は実施最良形態５による電力変換装置の要部の配線構造図を示し、基本的構成は実施最良形態１と同様である。そして、ＩＧＢＴ３のエミッタ端子Ｅ１１と接続点ＥＯとを接続する配線８及びＩＧＢＴ３のコレクタ端子Ｃ１と接続点ＣＯとを接続する配線６を短くするとともに、ＩＧＢＴ４のエミッタ端子Ｅ２１と接続点ＥＯとを接続する配線９及びＩＧＢＴ４のコレクタ端子Ｃ２と接続点ＣＯとを接続する配線７を短くした。 Embodiment 5
FIG. 5 shows a wiring structure diagram of the main part of the power converter according to the fifth embodiment, and the basic configuration is the same as that of the first embodiment. The wiring 8 connecting the emitter terminal E11 of the IGBT 3 and the connection point EO and the wiring 6 connecting the collector terminal C1 of the IGBT 3 and the connection point CO are shortened, and the emitter terminal E21 of the IGBT 4 and the connection point EO are connected. The wiring 9 for connecting the collector terminal C2 of the IGBT 4 and the collector terminal C2 of the IGBT 4 to the connection point CO was shortened.

実施最良形態５においては、配線８，６，９，７を短くしたので、配線８，９のインピーダンスが抑制され、接続点Ｅ００を介して流れる電流ｉ１が抑制され、ＩＧＢＴ３，４の破損を回避することができる。   In the fifth embodiment, since the wirings 8, 6, 9, and 7 are shortened, the impedance of the wirings 8 and 9 is suppressed, the current i1 that flows through the connection point E00 is suppressed, and damage to the IGBTs 3 and 4 is avoided. can do.

この発明の実施最良形態１による電力変換装置の回路構成図である。It is a circuit block diagram of the power converter device by Embodiment 1 of this invention. 実施最良形態２による電力変換装置の回路構成図である。It is a circuit block diagram of the power converter device by Embodiment 2. FIG. 実施最良形態３による電力変換装置の回路構成図である。It is a circuit block diagram of the power converter device by Embodiment 3. 実施最良形態４による電力変換装置の要部の配線構造図である。It is a wiring structure figure of the principal part of the power converter device by Embodiment 4. 実施最良形態５による電力変換装置の要部の配線構造図である。It is a wiring structure figure of the principal part of the power converter device by Embodiment 5. 従来の電力変換装置の回路構成図である。It is a circuit block diagram of the conventional power converter device. 従来の電力変換装置の要部の配線構造図である。It is a wiring structure figure of the principal part of the conventional power converter.

符号の説明Explanation of symbols

１，２…主回路母線
３，４…ＩＧＢＴ
５…制御装置
６〜１７…配線
１８〜２１…コモンモード電流対策部品
ＣP…コンデンサ
ＣＯ，ＥＯ，Ｇ００，Ｅ００…接続点 1, 2 ... Main circuit buses 3, 4 ... IGBT
5 ... Control device 6 to 17 ... Wiring 18 to 21 ... Common mode current countermeasure component C P ... Capacitor CO, EO, G00, E00 ... Connection point

Claims (5)

主回路母線に並列接続された複数の半導体素子の各ゲート端子に制御装置のゲート接続端子をそれぞれ接続するとともに、各半導体素子のエミッタ端子に制御装置のエミッタ接続端子をそれぞれ接続し、かつ制御装置の各ゲート接続端子間及び各エミッタ接続端子間を制御装置内の接続点においてそれぞれ接続し、制御装置からのゲート信号により各半導体素子をオンオフ制御させる電力変換装置において、制御装置の一方のゲート接続端子とその接続点間の配線及び一方のエミッタ接続端子とその接続点間の配線にコモンモード電流対策部品を接続するとともに、制御装置の他方のゲート接続端子とその接続点間の配線及び他方のエミッタ接続端子とその接続点間の配線にコモンモード電流対策部品を接続したことを特徴とする電力変換装置。   The gate connection terminal of the control device is connected to each gate terminal of the plurality of semiconductor elements connected in parallel to the main circuit bus, and the emitter connection terminal of the control device is connected to the emitter terminal of each semiconductor element. In a power conversion device in which each gate connection terminal and each emitter connection terminal are connected at a connection point in the control device, and each semiconductor element is controlled to be turned on and off by a gate signal from the control device, one gate connection of the control device The common mode current countermeasure component is connected to the wiring between the terminal and its connection point and the wiring between one emitter connection terminal and its connection point, and the wiring between the other gate connection terminal of the control device and its connection point and the other A power conversion device characterized by connecting a common mode current countermeasure component to the wiring between the emitter connection terminal and the connection point. . 主回路母線に並列接続された複数の半導体素子の各ゲート端子に制御装置のゲート接続端子をそれぞれ接続するとともに、各半導体素子のエミッタ端子に制御装置のエミッタ接続端子をそれぞれ接続し、かつ制御装置の各ゲート接続端子間及び各エミッタ接続端子間を制御装置内の接続点においてそれぞれ接続し、制御装置からのゲート信号により各半導体素子をオンオフ制御させる電力変換装置において、一方の半導体素子のゲート端子と制御装置の一方のゲート接続端子とを接続する配線及び一方の半導体素子のエミッタ端子と制御装置の一方のエミッタ接続端子とを接続する配線にコモンモード電流対策部品を接続するとともに、他方の半導体素子のゲート端子と制御装置の他方のゲート接続端子とを接続する配線及び他方の半導体素子のミッタ端子と制御装置の他方のエミッタ接続端子とを接続する配線にコモンモード電流対策部品を接続したことを特徴とする電力変換装置。   The gate connection terminal of the control device is connected to each gate terminal of the plurality of semiconductor elements connected in parallel to the main circuit bus, and the emitter connection terminal of the control device is connected to the emitter terminal of each semiconductor element. In the power conversion device that connects each of the gate connection terminals and each of the emitter connection terminals at a connection point in the control device, and controls each semiconductor element on / off by a gate signal from the control device, the gate terminal of one semiconductor element The common mode current countermeasure component is connected to the wiring connecting the gate connection terminal of the control device and one emitter connection terminal of the control device and the wiring connecting the emitter terminal of one semiconductor element and the other semiconductor. Wiring for connecting the gate terminal of the element and the other gate connection terminal of the control device and the other semiconductor element Power conversion apparatus characterized by connecting the common-mode current protection component to the other of the wiring connecting the emitter connecting terminal emitter terminal and the control device. 主回路母線に並列接続された複数の半導体素子の各ゲート端子に制御装置のゲート接続端子をそれぞれ接続するとともに、各半導体素子のエミッタ端子に制御装置のエミッタ接続端子をそれぞれ接続し、かつ制御装置の各ゲート接続端子間及び各エミッタ接続端子間を制御装置内の接続点においてそれぞれ接続し、制御装置からのゲート信号により各半導体素子をオンオフ制御させる電力変換装置において、各半導体素子のエミッタ端子間にコンデンサを接続したことを特徴とする電力変換装置。   The gate connection terminal of the control device is connected to each gate terminal of the plurality of semiconductor elements connected in parallel to the main circuit bus, and the emitter connection terminal of the control device is connected to the emitter terminal of each semiconductor element. In a power conversion device in which each gate connection terminal and each emitter connection terminal are connected at a connection point in the control device, and each semiconductor element is controlled to be turned on and off by a gate signal from the control device, between the emitter terminals of each semiconductor device A power converter characterized by connecting a capacitor to the power converter. 主回路母線に並列接続された複数の半導体素子の各ゲート端子に制御装置のゲート接続端子をそれぞれ接続するとともに、各半導体素子のエミッタ端子に制御装置のエミッタ接続端子をそれぞれ接続し、かつ制御装置の各ゲート接続端子間及び各エミッタ接続端子間を制御装置内の接続点においてそれぞれ接続し、制御装置からのゲート信号により各半導体素子をオンオフ制御させる電力変換装置において、各半導体素子のエミッタ端子と主回路母線間の配線を短くしたことを特徴とする電力変換装置。   The gate connection terminal of the control device is connected to each gate terminal of the plurality of semiconductor elements connected in parallel to the main circuit bus, and the emitter connection terminal of the control device is connected to the emitter terminal of each semiconductor element. In the power conversion device that connects each gate connection terminal and each emitter connection terminal of the semiconductor device at a connection point in the control device, and controls each semiconductor device on / off by a gate signal from the control device, A power converter characterized by shortening the wiring between main circuit buses. 主回路母線に並列接続された複数の半導体素子の各ゲート端子に制御装置のゲート接続端子をそれぞれ接続するとともに、各半導体素子のエミッタ端子に制御装置のエミッタ接続端子をそれぞれ接続し、かつ制御装置の各ゲート接続端子間及び各エミッタ接続端子間を制御装置内の接続点においてそれぞれ接続し、制御装置からのゲート信号により各半導体素子をオンオフ制御させる電力変換装置において、各半導体素子のエミッタ端子と主回路母線間の配線を短くするとともに、
各半導体素子のコレクタ端子と主回路母線間の配線を短くしたことを特徴とする電力変換装置。 The gate connection terminal of the control device is connected to each gate terminal of the plurality of semiconductor elements connected in parallel to the main circuit bus, and the emitter connection terminal of the control device is connected to the emitter terminal of each semiconductor element. In the power conversion device that connects each gate connection terminal and each emitter connection terminal of the semiconductor device at a connection point in the control device, and controls each semiconductor device on / off by a gate signal from the control device, While shortening the wiring between the main circuit buses,
A power conversion device characterized in that a wiring between a collector terminal of each semiconductor element and a main circuit bus is shortened.
JP2007010927A 2007-01-22 2007-01-22 Power converter Pending JP2008178261A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018117397A (en) * 2017-01-16 2018-07-26 本田技研工業株式会社 Semiconductor circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0819246A (en) * 1994-07-04 1996-01-19 Fuji Electric Co Ltd Parallel connection circuit of semiconductor switching devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0819246A (en) * 1994-07-04 1996-01-19 Fuji Electric Co Ltd Parallel connection circuit of semiconductor switching devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018117397A (en) * 2017-01-16 2018-07-26 本田技研工業株式会社 Semiconductor circuit

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