JP2008147368A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2008147368A
JP2008147368A JP2006332034A JP2006332034A JP2008147368A JP 2008147368 A JP2008147368 A JP 2008147368A JP 2006332034 A JP2006332034 A JP 2006332034A JP 2006332034 A JP2006332034 A JP 2006332034A JP 2008147368 A JP2008147368 A JP 2008147368A
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semiconductor chip
terminal
recess
semiconductor device
semiconductor
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Yoichi Oya
洋一 大矢
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Sony Corp
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Sony Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a microdevice including a functional element having a vibrator or a movable part provided on the function surface of a MEMS (Micro Electro Mechanical System) element, a SAW (Surface Acoustic Wave) element, or an F-BAR (Thin Film Bulk Acoustic Wave Resonator) is hermetically sealed, the device which is made compact by suppressing the influence of an outgas on the functional element, and also to provide a method of manufacturing the semiconductor device. <P>SOLUTION: A first semiconductor chip 10 including a functional element 12 having a movable part of a vibrator formed on its one main surface is mounted on a second semiconductor chip 20 having a size larger than that of the first semiconductor chip 10, the first semiconductor chip 10 is inserted in a recess 38 formed in a mounting substrate 30, the second semiconductor chip 20 is mounted on the mounting substrate 30 so that the second semiconductor chip 20 closes the recess 38, and a sealing resin layer 40 is formed in a gap between the second semiconductor chip 20 and the mounting substrate 30, whereby the first semiconductor chip is accommodated to be hermetically sealed within a hollow part defined by the inner wall surface of the recess, the terminal formation surface of the second semiconductor chip, and the sealing resin layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体装置に関し、特に、ＭＥＭＳ（Micro Electro Mechanical Systems）、ＳＡＷ（Surface Acoustic Wave）素子、あるいはＦ−ＢＡＲ（Thin Film Bulk Acoustic Wave Resonators）などの機能面に可動部または振動子を持つ機能素子を有する半導体装置に関する。   The present invention relates to a semiconductor device, and in particular, has a movable part or a vibrator on a functional surface such as a micro electro mechanical system (MEMS), a surface acoustic wave (SAW) element, or a thin film bulk acoustic wave resonator (F-BAR). The present invention relates to a semiconductor device having a functional element.

近年、携帯電話やパーソナルコンピュータに代表されるモバイル機器においては、小型軽量化や多機能および高機能化が進んでおり、これらの機器を構成する部品や基板も同様に小型、薄型、軽量化や高密度実装化が進んでいる。また、半導体等のデバイスの実装に関しても、実装面積の小型化や伝達信号の高速化に伴い、モールドやセラミックパッケージによる実装から、いわゆるフリップチップ実装技術によりデバイスのベアチップを直接基板に実装し、封止する試みがとられている。   In recent years, mobile devices typified by mobile phones and personal computers have been reduced in size and weight, and have increased functionality and functionality, and the components and substrates that make up these devices have been similarly reduced in size, thickness, and weight. High-density mounting is progressing. As for the mounting of devices such as semiconductors, as the mounting area is reduced and the transmission signal speed is increased, the bare chip of the device is mounted directly on the substrate by the so-called flip chip mounting technology from the mounting by the mold or the ceramic package, and sealed. Attempts have been made to stop.

ところが、このフリップチップによるデバイスのダイレクト実装方法は、たとえば、ＭＥＭＳ（Micro Electro Mechanical Systems）、ＳＡＷ（Surface Acoustic Wave）素子あるいはＦ−ＢＡＲ（Thin Film Bulk Acoustic Wave Resonators）などの機能面に可動部または振動子を持つマイクロデバイスの場合、機能面を封止材等で覆うことができないため、セラミックや金属、あるいはガラスなどの基板を用いて気密封止するパッケージ構造がとられ、パッケージ化されたマイクロデバイスが実装基板に実装される構成となっていた。   However, this flip chip direct mounting method uses, for example, a movable part or a functional part such as a MEMS (Micro Electro Mechanical Systems), a SAW (Surface Acoustic Wave) element, or an F-BAR (Thin Film Bulk Acoustic Wave Resonators). In the case of a micro device having a vibrator, the functional surface cannot be covered with a sealing material or the like. Therefore, a package structure that hermetically seals using a substrate such as ceramic, metal, or glass is taken, and the packaged micro device The device was configured to be mounted on a mounting board.

例えば、凹部が設けられたセラミックなどの中空基板に、ＭＥＭＳなどのマイクロデバイスが設けられた半導体チップが収容され、中空基板に設けられた電極とワイヤボンディングなどで接続され、金属などからなるリッド蓋がされて樹脂封止されて、パッケージ化される。   For example, a semiconductor lid provided with a micro device such as MEMS is accommodated in a hollow substrate such as ceramic provided with a recess, and is connected to an electrode provided on the hollow substrate by wire bonding or the like, and a lid lid made of metal or the like And then sealed with resin and packaged.

上記のパッケージ構造の場合、中空基板の凹部にマイクロデバイスを実装し、封止した構造であるので、実装基板に実装するための面積は本来のマイクロデバイスの大きさよりかなり大きな面積が必要であった。   In the case of the above package structure, since the micro device is mounted and sealed in the concave portion of the hollow substrate, the area for mounting on the mounting substrate needs to be much larger than the size of the original micro device. .

特許文献１には、マイクロデバイスと他のデバイスをスタック構造で一緒にパッケージ化して小型化した構造が開示されている。
特許文献１のパッケージ構造では、ＭＥＭＳ素子が形成されている面を上にしてＭＥＭＳデバイスが実装され、その上面に他のデバイスの裏面が向き合うように実装されている。このとき、ＭＥＭＳ素子部分が中空となるように実装される必要がある。さらに、ＭＥＭＳデバイスと他のデバイスの間および各デバイスと中空基板間などがワイヤーボンドで接続され、キャップで封止されて中空構造を有するモジュール化されたパッケージが構成されている。
特開２００５−１６９５４１号公報 Patent Document 1 discloses a structure in which a micro device and another device are packaged together in a stack structure to be miniaturized.
In the package structure of Patent Document 1, the MEMS device is mounted with the surface on which the MEMS element is formed facing up, and the back surface of the other device is mounted on the upper surface thereof. At this time, it is necessary to mount so that the MEMS element portion is hollow. Further, a modular package having a hollow structure is configured in which the MEMS device and other devices and between each device and the hollow substrate are connected by wire bonds and sealed with a cap.
JP 2005-169541 A

しかし、特許文献１に記載のパッケージ構造では、ＭＥＭＳ素子の形成領域を中空にするために、ＭＥＭＳデバイス上に、封止樹脂などで他のデバイスが張り合わされているが、封止樹脂の硬化時や硬化後の加熱によって封止樹脂からのアウトガス成分の影響で、ＭＥＭＳデバイスの特性がシフトするなどの不具合が発生することがある。   However, in the package structure described in Patent Document 1, in order to make the formation region of the MEMS element hollow, another device is bonded on the MEMS device with a sealing resin or the like. In some cases, the characteristics of the MEMS device shift due to the influence of an outgas component from the sealing resin due to heating after curing.

さらに、装置の大きさの面では、マイクロデバイスや他のデバイスがフェイスアップで中空基板に実装されているため、デバイスと基板の電気的な接続はワイヤーボンドで行われており、実装面積や高さの面で小型化の弊害となっている。   Furthermore, in terms of the size of the device, since microdevices and other devices are mounted face-up on a hollow substrate, the electrical connection between the device and the substrate is made by wire bonding, which increases the mounting area and height. In this respect, it is an adverse effect of miniaturization.

また、中空基板にダイボンドされたＭＥＭＳデバイスのＭＥＭＳ素子形成面上に他のデバイスがダイボンドされているので、ダイボンド時に非常にセンシティブなＭＥＭＳデバイスの可動部分にダメージを与えてデバイスを破壊してしまう可能性があり、取り扱いに起因する工程不良が発生する恐れがある。   In addition, since other devices are die-bonded on the MEMS element forming surface of the MEMS device die-bonded to the hollow substrate, it is possible to damage the movable part of the MEMS device that is very sensitive at the time of die-bonding and destroy the device. There is a risk that process defects may occur due to handling.

本発明の目的は、ＭＥＭＳ、ＳＡＷ素子あるいはＦ−ＢＡＲなどの機能面に振動子または可動部を持つ機能素子を有するマイクロデバイスが気密封止して組み込まれてなり、機能素子へのアウトガスの影響を抑制して、小型化を実現できる半導体装置を提供することである。   An object of the present invention is that a microdevice having a functional element having a vibrator or a movable portion is incorporated in a functional surface such as a MEMS, SAW element, or F-BAR in a hermetically sealed manner, and the influence of outgas on the functional element. It is providing the semiconductor device which can suppress size and can implement | achieve size reduction.

上記の課題を解決するため、本発明の半導体装置は、一主面に可動部または振動子を有する機能素子が形成された第１半導体チップと、前記第１半導体チップよりも大きいサイズを有し、一主面が端子形成面であり、前記端子形成面上に、前記第１半導体チップが前記機能素子の形成面側から所定の間隔をもってマウントされた第２半導体チップと、前記第１半導体チップ用の凹部が形成され、前記凹部に前記第１半導体チップが挿入し、前記第２半導体チップが前記凹部を塞ぐようにして、前記第２半導体チップが前記端子形成面側から前記凹部の縁部上にマウントされた実装基板と、前記凹部の縁部において前記第２半導体チップと前記実装基板の間隙を気密封止するように形成された封止樹脂層とを有し、前記凹部の内壁面、前記第２半導体チップの前記端子形成面及び前記封止樹脂層から構成される中空部分に前記第１半導体チップが気密封止された状態で収容されている。   In order to solve the above problems, a semiconductor device of the present invention has a first semiconductor chip in which a functional element having a movable part or a vibrator is formed on one main surface, and a size larger than the first semiconductor chip. A second semiconductor chip in which one main surface is a terminal formation surface, and the first semiconductor chip is mounted on the terminal formation surface at a predetermined interval from the formation surface side of the functional element; and the first semiconductor chip A recess is formed, and the second semiconductor chip is inserted into the recess from the terminal forming surface side so that the second semiconductor chip closes the recess. A mounting substrate mounted thereon; and a sealing resin layer formed so as to hermetically seal a gap between the second semiconductor chip and the mounting substrate at an edge of the recess, and an inner wall surface of the recess The second Conductor chip the terminal formation surface and the sealing said first semiconductor chip to the hollow portion consisting of the resin layer of is accommodated in a state of being hermetically sealed.

上記の本発明の半導体装置は、一主面に可動部または振動子を有する機能素子が形成された第１半導体チップが、第１半導体チップよりも大きいサイズを有し、一主面が端子形成面であり、端子形成面上に機能素子の形成面側から所定の間隔をもって第２半導体チップ上にマウントされており、さらに第１半導体チップ用の凹部が形成された実装基板に、凹部に第１半導体チップが挿入し、第２半導体チップが凹部を塞ぐようにして、第２半導体チップが端子形成面側から凹部の縁部上にマウントされている。さらに、凹部の縁部において第２半導体チップと実装基板の間隙を気密封止するように封止樹脂層が形成されており、凹部の内壁面、第２半導体チップの端子形成面及び封止樹脂層から構成される中空部分に第１半導体チップが気密封止された状態で収容された構成となっている。   In the semiconductor device of the present invention, the first semiconductor chip in which the functional element having the movable portion or the vibrator is formed on one main surface has a size larger than that of the first semiconductor chip, and the one main surface is formed with a terminal. Mounted on the second semiconductor chip at a predetermined interval from the functional element forming surface side on the terminal forming surface, and further on the mounting substrate on which the concave portion for the first semiconductor chip is formed. One semiconductor chip is inserted, and the second semiconductor chip is mounted on the edge of the recess from the terminal forming surface side so that the second semiconductor chip closes the recess. Further, a sealing resin layer is formed so as to hermetically seal the gap between the second semiconductor chip and the mounting substrate at the edge of the recess, and the inner wall surface of the recess, the terminal formation surface of the second semiconductor chip, and the sealing resin The first semiconductor chip is housed in a hermetically sealed state in a hollow portion composed of layers.

本発明の半導体装置は、ＭＥＭＳ、ＳＡＷ素子あるいはＦ−ＢＡＲなどの機能面に振動子または可動部を持つ機能素子を有するマイクロデバイスが気密封止して組み込まれてなり、機能素子が形成された第１半導体チップには封止樹脂層が接していないので、機能素子へのアウトガスの影響を抑制して、また、第２半導体チップ自体を中空部分の蓋として用いることができるので半導体装置の小型化を実現できる。   In the semiconductor device of the present invention, a microdevice having a functional element having a vibrator or a movable part is incorporated in a functional surface such as a MEMS, SAW element, or F-BAR in a hermetically sealed manner to form a functional element. Since the sealing resin layer is not in contact with the first semiconductor chip, the influence of outgas on the functional element can be suppressed, and the second semiconductor chip itself can be used as a cover for the hollow portion, so that the semiconductor device can be made compact. Can be realized.

以下に、本発明の半導体装置の実施の形態について、図面を参照して説明する。   Embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings.

第１実施形態
図１は本実施形態に係る半導体装置の模式断面図である。本実施形態に係る半導体装置は、ＭＥＭＳ、ＳＡＷ素子あるいはＦ−ＢＡＲなどの機能素子を有する第１半導体チップと他の第２半導体チップをパッケージ化してモジュールとしたものである。 First Embodiment FIG. 1 is a schematic cross-sectional view of a semiconductor device according to this embodiment. The semiconductor device according to the present embodiment is a module obtained by packaging a first semiconductor chip having a functional element such as a MEMS, SAW element, or F-BAR and another second semiconductor chip.

例えば、一主面に可動部または振動子を有する機能素子が形成された第１半導体チップ１０が、第２半導体チップ２０上にマウントされている。   For example, the first semiconductor chip 10 in which a functional element having a movable part or a vibrator is formed on one main surface is mounted on the second semiconductor chip 20.

例えば、第１半導体チップ１０は、チップ本体１１の一主面に可動部または振動子を有する機能素子１２が形成されており、機能素子１２あるいはチップ本体１１に形成された他の電子素子などに接続して第１端子１３が形成されており、第１端子１３に接続してハンダなどからなるバンプ１４が形成されている。   For example, in the first semiconductor chip 10, a functional element 12 having a movable part or a vibrator is formed on one main surface of the chip body 11, and the functional element 12 or other electronic elements formed on the chip body 11 are used. A first terminal 13 is formed by connection, and a bump 14 made of solder or the like is formed by connection to the first terminal 13.

また、例えば、第２半導体チップ２０は、第１半導体チップ１０よりも大きいサイズを有し、チップ本体２１の活性面に電子素子が形成されており、活性面上に絶縁層２２と絶縁層２２内に埋め込まれた再配線層２３が形成され、絶縁層２２の表面が端子形成面となって、絶縁層２２の表面に露出するように、第１半導体チップに接続するための第２内周端子２４と実装基板に実装するための第２外周端子２５が再配線層２３に接続して形成されており、第２外周端子２５に接続してハンダなどからなるバンプ２６が形成されている。   Further, for example, the second semiconductor chip 20 has a size larger than that of the first semiconductor chip 10, an electronic element is formed on the active surface of the chip body 21, and the insulating layer 22 and the insulating layer 22 are formed on the active surface. A rewiring layer 23 embedded therein is formed, and a second inner periphery for connecting to the first semiconductor chip so that the surface of the insulating layer 22 becomes a terminal forming surface and is exposed on the surface of the insulating layer 22. A terminal 24 and a second outer peripheral terminal 25 for mounting on the mounting substrate are formed connected to the rewiring layer 23, and a bump 26 made of solder or the like is formed connected to the second outer peripheral terminal 25.

ここで、バンプ１４を介して第１端子１３と第２内周端子２４が接続され、バンプ１４の高さに相当する所定の間隔をもって、第１半導体チップ１０が機能素子１２の形成面側から第２半導体チップ２０の端子形成面上にマウントされている。ここで、第１端子１３と第２内周端子２４を接続するバンプ１４は、第１半導体チップ１０の第１端子１３に形成されていたものとして説明しているが、第２半導体チップ２０の第２内周端子２４に形成されていたものであってもよい。   Here, the first terminal 13 and the second inner peripheral terminal 24 are connected via the bump 14, and the first semiconductor chip 10 is formed from the side on which the functional element 12 is formed with a predetermined interval corresponding to the height of the bump 14. It is mounted on the terminal formation surface of the second semiconductor chip 20. Here, the bump 14 connecting the first terminal 13 and the second inner peripheral terminal 24 is described as being formed on the first terminal 13 of the first semiconductor chip 10. It may be formed on the second inner peripheral terminal 24.

また、例えば、上記のように第１半導体チップ１０がマウントされた第２半導体チップ２０が、モジュール基板である実装基板３０に実装されている。   Further, for example, the second semiconductor chip 20 on which the first semiconductor chip 10 is mounted as described above is mounted on the mounting substrate 30 which is a module substrate.

例えば、実装基板３０は積層樹脂基板であり、第１樹脂基板３１と第２樹脂基板３２が積層しており、第１樹脂基板３１の表面、第１樹脂基板３１と第２樹脂基板３２の界面、第２樹脂基板３２の表面に、それぞれ配線層（３３，３４，３５）が形成され、また、第１樹脂基板３１と第２樹脂基板３２をそれぞれ貫通する貫通配線（３６，３７）が形成されて、構成されている。
また、例えば、実装基板３０には、第１半導体チップ用の凹部３８が形成されている。 For example, the mounting substrate 30 is a laminated resin substrate, in which a first resin substrate 31 and a second resin substrate 32 are laminated, and the surface of the first resin substrate 31 and the interface between the first resin substrate 31 and the second resin substrate 32. The wiring layers (33, 34, 35) are formed on the surface of the second resin substrate 32, and the through wirings (36, 37) penetrating the first resin substrate 31 and the second resin substrate 32 are formed. Has been configured.
Further, for example, a recess 38 for the first semiconductor chip is formed in the mounting substrate 30.

例えば、凹部３８に第１半導体チップ１０が挿入し、第２半導体チップ２０が凹部３８を塞ぐようにして、実装基板３０の一主面に形成された配線層３３の一部などからなる実装基板端子と第２外周端子２５とがバンプ２６を介して接続されて、第１半導体チップ１０がマウントされた第２半導体チップ２０が端子形成面側から実装基板３０の凹部３８の縁部上にマウントされている。ここで、第２外周端子２５と実装基板端子（配線層３３の一部）を接続するバンプ２６は、第２半導体チップ２０の第２外周端子２５に形成されていたものとして説明しているが、実装基板３０の実装基板端子（配線層３３の一部）に形成されていたものであってもよい。   For example, the mounting substrate formed of a part of the wiring layer 33 formed on one main surface of the mounting substrate 30 such that the first semiconductor chip 10 is inserted into the recess 38 and the second semiconductor chip 20 closes the recess 38. The terminal and the second outer peripheral terminal 25 are connected via the bump 26, and the second semiconductor chip 20 on which the first semiconductor chip 10 is mounted is mounted on the edge of the recess 38 of the mounting substrate 30 from the terminal forming surface side. Has been. Here, the bump 26 that connects the second outer peripheral terminal 25 and the mounting substrate terminal (a part of the wiring layer 33) is described as being formed on the second outer peripheral terminal 25 of the second semiconductor chip 20. Alternatively, it may be formed on the mounting board terminal (a part of the wiring layer 33) of the mounting board 30.

また、例えば、実装基板３０の凹部３８の縁部において、第２半導体チップ２０と実装基板３０の間隙を気密封止するように、封止樹脂層４０が形成されている。
上記によって、凹部３８の内壁面、第２半導体チップ２０の端子形成面及び封止樹脂層４０から構成される中空部分Ｓに、第１半導体チップ１０が気密封止された状態で収容された構成となっている。中空部分Ｓは、例えば、真空、減圧、還元雰囲気、あるいは不活性ガス雰囲気に保持されている。 For example, the sealing resin layer 40 is formed at the edge of the recess 38 of the mounting substrate 30 so as to hermetically seal the gap between the second semiconductor chip 20 and the mounting substrate 30.
By the above, the 1st semiconductor chip 10 is accommodated in the hollow part S comprised from the inner wall face of the recessed part 38, the terminal formation surface of the 2nd semiconductor chip 20, and the sealing resin layer 40 in the airtightly sealed state. It has become. The hollow portion S is held in, for example, a vacuum, a reduced pressure, a reducing atmosphere, or an inert gas atmosphere.

さらに、例えば、本実施形態においては実装基板３０がモジュール基板であって、実装基板３０の一主面に形成された配線層３５の一部などからなる実装基板端子に、他の実装基板に実装するためのバンプ５０が形成されている。   Further, for example, in the present embodiment, the mounting substrate 30 is a module substrate, and is mounted on a mounting substrate terminal formed of a part of the wiring layer 35 formed on one main surface of the mounting substrate 30 and the like on another mounting substrate. Bumps 50 are formed for this purpose.

以上のようにして、本実施形態に係る第１半導体チップと他の第２半導体チップをパッケージ化してモジュールとした半導体装置が構成されている。
例えば、バンプ５０を介して他の実装基板などにマウントされて用いることができる。 As described above, the semiconductor device is configured by packaging the first semiconductor chip according to the present embodiment and another second semiconductor chip into a module.
For example, it can be used by being mounted on another mounting substrate or the like via the bump 50.

上記の第１半導体チップ１０に形成されている機能素子１２は、例えば、ＭＥＭＳ、ＳＡＷ素子あるいはＦ−ＢＡＲなどであり、図面上は特にＭＥＭＳを示している。
本実施形態の半導体装置において、第１半導体チップ１０の機能素子１２は中空部分Ｓにおいて気密封止された構成となっており、従来技術のような中空部分Ｓを構成するための中空基板は不要であり、第１半導体チップとスタックさせる第２半導体チップを中空部分Ｓを構成する蓋として利用することにより、半導体装置として小型化や薄型化が可能である。 The functional element 12 formed in the first semiconductor chip 10 is, for example, a MEMS, a SAW element, or an F-BAR, and the MEMS is particularly shown in the drawing.
In the semiconductor device of the present embodiment, the functional element 12 of the first semiconductor chip 10 is hermetically sealed in the hollow portion S, and a hollow substrate for forming the hollow portion S as in the prior art is unnecessary. By using the second semiconductor chip to be stacked with the first semiconductor chip as a lid constituting the hollow portion S, the semiconductor device can be reduced in size and thickness.

また、機能素子を有する半導体チップ（第１半導体チップ１０）に封止樹脂が接していると、封止樹脂から放出されるアウトガスに起因して機能素子に不具合が発生しやすい不利益があるが、本実施形態においては、機能素子１２が形成された第１半導体チップ１０には封止樹脂層４０が接していないので、封止樹脂層４０から放出されるアウトガスの機能素子１２への影響を抑制することができる。   Further, when the sealing resin is in contact with the semiconductor chip having the functional element (first semiconductor chip 10), there is a disadvantage that the functional element is likely to fail due to outgas released from the sealing resin. In this embodiment, since the sealing resin layer 40 is not in contact with the first semiconductor chip 10 on which the functional element 12 is formed, the influence of the outgas released from the sealing resin layer 40 on the functional element 12 is affected. Can be suppressed.

上記のように第１半導体チップを収容する中空部分の蓋として第２半導体チップを利用することから、第２半導体チップは第１半導体チップよりも大きなサイズであることが必要である。   As described above, since the second semiconductor chip is used as a lid for the hollow portion that houses the first semiconductor chip, the second semiconductor chip needs to be larger in size than the first semiconductor chip.

次に、上記の本実施形態の半導体装置の製造方法について、図２〜６を参照して説明する。
まず、本実施形態に係る第１半導体チップ１０及び第２半導体チップ２０をそれぞれの工程で形成する。 Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.
First, the first semiconductor chip 10 and the second semiconductor chip 20 according to the present embodiment are formed in respective steps.

図２（ａ）は本実施形態に係る第１半導体チップの機能素子の形成面における平面図であり、図２（ｂ）は断面図である。
例えば、第１半導体チップ１０を構成するチップ本体１１の一主面に可動部または振動子を有する機能素子１２及び必要に応じてその他の電子素子を形成し、これらに接続して第１端子１３を形成し、さらに第１端子１３に接続してハンダなどからなるバンプ１４を形成する。以上のようにして、第１半導体チップ１０を形成する。 2A is a plan view of the functional element forming surface of the first semiconductor chip according to the present embodiment, and FIG. 2B is a cross-sectional view.
For example, a functional element 12 having a movable part or a vibrator and other electronic elements as necessary are formed on one main surface of the chip body 11 constituting the first semiconductor chip 10, and connected to these first terminals 13. And bumps 14 made of solder or the like are formed by connecting to the first terminals 13. As described above, the first semiconductor chip 10 is formed.

図３（ａ）は本実施形態に係る第２半導体チップの端子形成面側における平面図であり、図３（ｂ）は断面図である。
例えば、第１半導体チップ１０よりも大きいサイズを有するチップ本体２１の活性面に電子素子を形成し、活性面上に絶縁層２２と絶縁層２２内に埋め込まれた再配線層２３を形成する。このとき、再配線層に接続して、絶縁層２２の表面に露出するように、第２内周端子２４と第２外周端子２５を形成して、絶縁層２２の表面を端子形成面とする。次に、第２外周端子２５に接続してハンダなどからなるバンプ２６を形成する。以上のようにして、第２半導体チップ２０を形成する。
上記の絶縁層２２は、例えばポリイミドやＰＢＯ（ポリベンゾオキサゾール）などから構成されるが、上記のように中空部分Ｓの壁面となる部材であるので、熱硬化型樹脂などの放出するアウトガスが少ない種類を用いることが好ましい。 FIG. 3A is a plan view on the terminal forming surface side of the second semiconductor chip according to the present embodiment, and FIG. 3B is a cross-sectional view.
For example, an electronic element is formed on the active surface of the chip body 21 having a size larger than that of the first semiconductor chip 10, and the rewiring layer 23 embedded in the insulating layer 22 and the insulating layer 22 is formed on the active surface. At this time, the second inner peripheral terminal 24 and the second outer peripheral terminal 25 are formed so as to be connected to the rewiring layer and exposed on the surface of the insulating layer 22, and the surface of the insulating layer 22 is used as a terminal forming surface. . Next, a bump 26 made of solder or the like is formed in connection with the second outer peripheral terminal 25. As described above, the second semiconductor chip 20 is formed.
The insulating layer 22 is made of, for example, polyimide, PBO (polybenzoxazole), or the like, but is a member that becomes the wall surface of the hollow portion S as described above, so that outgas emitted from a thermosetting resin or the like is small. It is preferable to use a type.

図４〜６は本実施形態の半導体装置の製造方法の製造工程の断面図である。
上記のようにして第１半導体チップ１０及び第２半導体チップ２０を形成した後、図４（ａ）に示すように、例えば、バンプ１４及び第１端子１３と第２内周端子２４を位置合わせして第２半導体チップ２０上に第１半導体チップ１０を戴置し、リフロー処理などを行って、バンプ１４を介して第１端子１３と第２内周端子２４を接続することにより、図４（ｂ）に示すように、第１半導体チップ１０を機能素子１２の形成面側から第２半導体チップ２０の端子形成面上にマウントする。
上記のマウントにおいては、バンプ１４を介して行うことで、第１半導体チップ１０の機能素子１２形成面と第２半導体チップ２０の端子形成面の間にバンプ１４の高さに相当する所定の間隔を確保することができる。
ここで、上記のバンプ１４は予め第２半導体チップ２０の第２内周端子２４側に形成されていたものであってもよい。 4 to 6 are cross-sectional views of the manufacturing process of the semiconductor device manufacturing method of the present embodiment.
After the first semiconductor chip 10 and the second semiconductor chip 20 are formed as described above, for example, as shown in FIG. 4A, the bumps 14 and the first terminals 13 and the second inner peripheral terminals 24 are aligned. Then, by placing the first semiconductor chip 10 on the second semiconductor chip 20 and performing a reflow process or the like, the first terminal 13 and the second inner peripheral terminal 24 are connected via the bumps 14, so that FIG. As shown in (b), the first semiconductor chip 10 is mounted on the terminal formation surface of the second semiconductor chip 20 from the formation surface side of the functional element 12.
In the mount described above, a predetermined distance corresponding to the height of the bump 14 is provided between the functional element 12 formation surface of the first semiconductor chip 10 and the terminal formation surface of the second semiconductor chip 20 by performing through the bumps 14. Can be secured.
Here, the bumps 14 may be previously formed on the second inner peripheral terminal 24 side of the second semiconductor chip 20.

上記の第１半導体チップ１０の第２半導体チップ２０へのマウント工程は、第２半導体チップ２０についてウェハレベルのままで行い、第１半導体チップ１０のマウント終了後に、第２半導体チップのダイシング加工を行うようにすると取り扱いが容易となって好ましい。   The mounting process of the first semiconductor chip 10 to the second semiconductor chip 20 is performed at the wafer level with respect to the second semiconductor chip 20, and after the mounting of the first semiconductor chip 10, the second semiconductor chip is diced. This is preferable because it is easy to handle.

次に、図５（ａ）に示すように、例えば、上記のように第１半導体チップ１０がマウントされた第２半導体チップ２０を、モジュール基板である実装基板３０に実装する。   Next, as shown in FIG. 5A, for example, the second semiconductor chip 20 on which the first semiconductor chip 10 is mounted as described above is mounted on a mounting substrate 30 that is a module substrate.

上記の実装基板３０は積層樹脂基板であり、以下のようにして予め形成しておく。
まず、例えば、両面に銅箔などが貼り合わされた第１樹脂基板３１に凹部３８となるうちぬき穴を加工し、銅箔のパターン加工による配線層（３３，３４）の形成及び貫通配線３６の形成などを行う。さらに、配線層３４を介して、一方の面に銅箔などが貼り合わされた第２樹脂基板３２を第１樹脂基板３１に積層し、銅箔のパターン加工による配線層３５の形成及び貫通配線３７の形成などを行う。以上のようにして、実装基板３０を形成する。 The mounting substrate 30 is a laminated resin substrate and is formed in advance as follows.
First, for example, a hollow hole that becomes a recess 38 is processed in the first resin substrate 31 having copper foil or the like bonded to both sides, and formation of wiring layers (33, 34) and formation of through wiring 36 by patterning of the copper foil. And so on. Further, a second resin substrate 32 having a copper foil or the like bonded to one surface is laminated on the first resin substrate 31 via the wiring layer 34, the formation of the wiring layer 35 by pattern processing of the copper foil, and the through wiring 37. And so on. The mounting substrate 30 is formed as described above.

上記のようにして実装基板３０を形成した後、例えば、凹部３８に第１半導体チップ１０を挿入させ、第２半導体チップ２０が凹部３８を塞ぐようにして、実装基板３０の一主面に形成された配線層３３の一部などからなる実装基板端子バンプ２６及び第２外周端子２５を位置合わせして実装基板３０上に第２半導体チップ２０を戴置し、リフロー処理などを行って、バンプ２６を介して実装基板３０の一主面に形成された配線層３３の一部などからなる実装基板端子と第２外周端子２５とを接続することにより、図５（ｂ）に示すように、第１半導体チップ１０がマウントされた第２半導体チップ２０を端子形成面側から実装基板３０の凹部３８の縁部上にマウントする。
ここで、上記のバンプ２６は予め実装基板３０の実装基板端子側に形成されていたものであってもよい。 After forming the mounting substrate 30 as described above, for example, the first semiconductor chip 10 is inserted into the recess 38, and the second semiconductor chip 20 is formed on one main surface of the mounting substrate 30 so as to close the recess 38. The mounting substrate terminal bump 26 and the second outer peripheral terminal 25 made of a part of the wiring layer 33 and the like are aligned, the second semiconductor chip 20 is placed on the mounting substrate 30, a reflow process or the like is performed, and the bump As shown in FIG. 5B, by connecting the mounting board terminal composed of a part of the wiring layer 33 formed on one main surface of the mounting board 30 and the second outer peripheral terminal 25 via The second semiconductor chip 20 on which the first semiconductor chip 10 is mounted is mounted on the edge of the recess 38 of the mounting substrate 30 from the terminal forming surface side.
Here, the bumps 26 may be formed in advance on the mounting board terminal side of the mounting board 30.

次に、図６（ａ）に示すように、例えば、実装基板３０の凹部３８の縁部において、第２半導体チップ２０と実装基板３０の間隙を気密封止するように、封止樹脂層４０を形成する。
封止樹脂層４０の形成は、例えば液体状の樹脂を第２半導体チップ２０と実装基板３０の間隙に供給し、固化処理などを施して形成する。
液体状の樹脂は、例えば粘度を１０〜２０Ｐａ・Ｓ程度に調整することなどにより、液体状の樹脂が第２半導体チップ２０と実装基板３０の幅の狭い間隙に毛細管現象で隅までいきわたるが、凹部３８の縁までいきわたると凹部３８の存在により急激に空間が広がるので、それ以上の進入を起こさないように形成することができる。
上記によって、凹部３８の内壁面、第２半導体チップ２０の端子形成面及び封止樹脂層４０から構成される中空部分Ｓに、第１半導体チップ１０が気密封止された状態で収容された構成となっている。 Next, as shown in FIG. 6A, for example, the sealing resin layer 40 is hermetically sealed at the edge of the recess 38 of the mounting substrate 30 so that the gap between the second semiconductor chip 20 and the mounting substrate 30 is hermetically sealed. Form.
The sealing resin layer 40 is formed, for example, by supplying a liquid resin to the gap between the second semiconductor chip 20 and the mounting substrate 30 and performing a solidification process or the like.
For example, by adjusting the viscosity to about 10 to 20 Pa · S, the liquid resin spreads to the corner by capillary action in the narrow gap between the second semiconductor chip 20 and the mounting substrate 30. Since the space suddenly expands due to the presence of the recess 38 when it reaches the edge of the recess 38, it can be formed so as not to cause further entry.
By the above, the 1st semiconductor chip 10 is accommodated in the hollow part S comprised from the inner wall face of the recessed part 38, the terminal formation surface of the 2nd semiconductor chip 20, and the sealing resin layer 40 in the airtightly sealed state. It has become.

上記の封止樹脂層の形成工程は、例えば、真空、減圧、還元雰囲気、あるいは不活性ガス雰囲気下で行い、これにより中空部分Ｓを真空、減圧、還元雰囲気、あるいは不活性ガス雰囲気に保持することができる。   The sealing resin layer forming step is performed, for example, in a vacuum, reduced pressure, reducing atmosphere, or inert gas atmosphere, thereby holding the hollow portion S in a vacuum, reduced pressure, reducing atmosphere, or inert gas atmosphere. be able to.

次に、図６（ｂ）に示すように、例えば、実装基板３０の一主面に形成された配線層３５の一部などからなる実装基板端子に、他の実装基板に実装するためのバンプ５０を形成する。   Next, as shown in FIG. 6B, for example, bumps for mounting on a mounting board terminal formed of a part of the wiring layer 35 formed on one main surface of the mounting board 30 and the like on another mounting board. 50 is formed.

以上のようにして、本実施形態に係る第１半導体チップと他の第２半導体チップをパッケージ化してモジュールとした半導体装置を製造することができる。   As described above, it is possible to manufacture a semiconductor device in which the first semiconductor chip according to the present embodiment and another second semiconductor chip are packaged to form a module.

本実施形態の半導体装置の製造方法において、機能素子１２を保持するための中空部分Ｓの蓋として第２半導体チップ２０を利用することにより、小型化や薄型化を実現した半導体装置を製造できる。   In the method for manufacturing a semiconductor device according to the present embodiment, by using the second semiconductor chip 20 as a lid for the hollow portion S for holding the functional element 12, it is possible to manufacture a semiconductor device that is reduced in size and thickness.

また、機能素子を有する半導体チップに封止樹脂が接していると、封止樹脂から放出されるアウトガスに起因して機能素子に不具合が発生しやすい不利益があるが、本実施形態においては、機能素子１２が形成された第１半導体チップ１０に封止樹脂層４０が接しないように形成できるので、封止樹脂層４０から放出されるアウトガスの機能素子１２への影響を抑制することができる。   Further, when the sealing resin is in contact with the semiconductor chip having the functional element, there is a disadvantage that the functional element is likely to fail due to the outgas released from the sealing resin. Since it can form so that the sealing resin layer 40 may not contact the 1st semiconductor chip 10 in which the functional element 12 was formed, the influence on the functional element 12 of the outgas discharged | emitted from the sealing resin layer 40 can be suppressed. .

第２実施形態
図７は第２実施形態に係る半導体装置の模式断面図である。
実質的に第１実施形態と同様の構成であるが、半導体装置を構成する実装基板３０ａがモジュールを構成するための基板ではなく、他の電子部品を実装できる通常の実装基板であることが異なる。
実装基板３０ａは、第１樹脂基板３１ａと第２樹脂基板３２ａを積層して、表面や界面などに配線層（３３，３４，３５）がパターン形成され、さらに貫通配線（３６，３７）などが形成されている。
実装基板３０ａは、第１半導体チップ１０及び第２半導体チップ２０を実装した領域のほかに十分広い実装領域を有しており、ここに他の半導体チップや電子部品などを実装することができる。 Second Embodiment FIG. 7 is a schematic cross-sectional view of a semiconductor device according to a second embodiment.
The configuration is substantially the same as that of the first embodiment, except that the mounting substrate 30a configuring the semiconductor device is not a substrate for configuring a module but a normal mounting substrate on which other electronic components can be mounted. .
The mounting substrate 30a is formed by laminating a first resin substrate 31a and a second resin substrate 32a, and a wiring layer (33, 34, 35) is formed on the surface or interface, and through wiring (36, 37) is further formed. Is formed.
The mounting substrate 30a has a sufficiently wide mounting area in addition to the area where the first semiconductor chip 10 and the second semiconductor chip 20 are mounted, and other semiconductor chips and electronic components can be mounted thereon.

本実施形態の半導体装置においても、中空部分Ｓを構成する蓋として第２半導体チップを利用することにより、半導体装置として小型化や薄型化が可能であり、また、機能素子が形成された第１半導体チップには封止樹脂層が接していないので、封止樹脂層から放出されるアウトガスの機能素子１２への影響を抑制することができる。   Also in the semiconductor device of the present embodiment, by using the second semiconductor chip as a lid constituting the hollow portion S, the semiconductor device can be reduced in size and thickness, and the first in which the functional element is formed. Since the sealing resin layer is not in contact with the semiconductor chip, the influence of the outgas released from the sealing resin layer on the functional element 12 can be suppressed.

第３実施形態
図８は第３実施形態に係る半導体装置の模式断面図である。
実質的に第１実施形態と同様の構成であるが、第２半導体チップ２０に複数個（図面上２個）の第１半導体チップ（１０ａ，１０ｂ）がマウントされ、実装基板３０の凹部３８内に挿入された状態で第２半導体チップ２０が実装基板３０にマウントされ、封止樹脂で気密封止されて、形成される中空部分Ｓに第１半導体チップ（１０ａ，１０ｂ）が保持されている構成である。 Third Embodiment FIG. 8 is a schematic cross-sectional view of a semiconductor device according to a third embodiment.
Although the configuration is substantially the same as that of the first embodiment, a plurality (two in the drawing) of the first semiconductor chips (10a, 10b) are mounted on the second semiconductor chip 20, and the inside of the recess 38 of the mounting substrate 30 The second semiconductor chip 20 is mounted on the mounting substrate 30 in a state where the first semiconductor chip (10a, 10b) is held in the formed hollow portion S by being hermetically sealed with a sealing resin. It is a configuration.

複数個の第１半導体チップ（１０ａ，１０ｂ）はいずれも機能素子を有しており、たとえば両者がともにＭＥＭＳ素子などの同じ種類の機能素子を有する場合、あるいは一方がＭＥＭＳ素子を有し、他方がＳＡＷ素子を有するなど、異なる種類の機能素子を有する場合など、種々の組み合わせが可能である。
また、機能素子を有さない半導体チップを第２半導体チップ２０上にマウントしてもよい。 Each of the plurality of first semiconductor chips (10a, 10b) has a functional element. For example, when both have the same type of functional element such as a MEMS element, or one has a MEMS element and the other has Various combinations are possible, such as when having different types of functional elements, such as having a SAW element.
A semiconductor chip that does not have a functional element may be mounted on the second semiconductor chip 20.

本実施形態の半導体装置においても、中空部分Ｓを構成する蓋として第２半導体チップを利用することにより、半導体装置として小型化や薄型化が可能であり、また、機能素子が形成された第１半導体チップには封止樹脂層が接していないので、封止樹脂層から放出されるアウトガスの機能素子１２への影響を抑制することができる。   Also in the semiconductor device of the present embodiment, by using the second semiconductor chip as a lid constituting the hollow portion S, the semiconductor device can be reduced in size and thickness, and the first in which the functional element is formed. Since the sealing resin layer is not in contact with the semiconductor chip, the influence of the outgas released from the sealing resin layer on the functional element 12 can be suppressed.

第４実施形態
上記の実施形態では、図面上、機能面に振動子または可動部を持つ機能素子を有するマイクロデバイスとしてＭＥＭＳについて示しているが、これに限らず、例えば図８に示す構造のＦ−ＢＡＲや、ＳＡＷ素子などを備えたマイクロデバイスを内蔵するようにしてもよい。
図９は、Ｆ−ＢＡＲの一例の構成を示す模式断面図である。
例えば、デバイス基板６０に、所定の共振領域を構成する空隙６１を介して、下部電極６２、圧電膜６３および上部電極６４の積層体からなる弾性共振膜が形成されている。
下部電極６２および上部電極６４は、例えばＡｌ、Ｐｔ、Ａｕ、Ｃｕ、Ｗ、Ｍｏ、Ｔｉなどの導電性材料からなり、例えば０．１〜０．５μｍの膜厚で形成されている。
また、圧電膜６３は窒化アルミニウムや酸化亜鉛などの圧電材料からなり、ｃ軸に高配向した緻密な膜となっており、優れた圧電特性と弾性特性を備えた圧電膜であり、例えば１．５μｍ以下の膜厚で形成されている。
空隙６１は、下部電極６２の端部に屈曲して形成された足部により支えられており、空隙６１の高さは例えば数μｍ程度である。
下部電極６２、上部電極６４および圧電膜６３の膜厚や空隙６１の高さなどは、共振周波数に合わせて適宜調整することができる。 Fourth Embodiment In the above-described embodiment, MEMS is shown as a micro device having a functional element having a vibrator or a movable part on the functional surface in the drawing. However, the present invention is not limited to this. For example, F having the structure shown in FIG. -You may make it incorporate the microdevice provided with BAR, a SAW element, etc.
FIG. 9 is a schematic cross-sectional view illustrating an exemplary configuration of the F-BAR.
For example, an elastic resonance film made of a laminate of a lower electrode 62, a piezoelectric film 63, and an upper electrode 64 is formed on the device substrate 60 via a gap 61 that constitutes a predetermined resonance region.
The lower electrode 62 and the upper electrode 64 are made of a conductive material such as Al, Pt, Au, Cu, W, Mo, and Ti, and are formed with a film thickness of 0.1 to 0.5 μm, for example.
The piezoelectric film 63 is made of a piezoelectric material such as aluminum nitride or zinc oxide, is a dense film highly oriented in the c-axis, and has excellent piezoelectric characteristics and elastic characteristics. The film thickness is 5 μm or less.
The gap 61 is supported by a leg formed by bending at the end of the lower electrode 62, and the height of the gap 61 is, for example, about several μm.
The film thickness of the lower electrode 62, the upper electrode 64, and the piezoelectric film 63, the height of the gap 61, and the like can be appropriately adjusted according to the resonance frequency.

上記の本発明の各実施形態に係る半導体装置によれば、以下の効果を享受できる。
（１）中空構造を要求されるような部品を含む、マルチチップパッケージが可能になる。
（２）樹脂で充填することなく、チップを積層した構造を得ることができる。
（３）上記の結果、より高密度の実装が可能となり、製品の小型化が実現する。
（４）機能素子と封止樹脂の距離を取ることができ、アウトガス成分の影響を受けないパッケージが可能となる。
（５）ＭＥＭＳデバイス等の、ハンドリングによる工程不良を低減できる。
（６）総じて、コストダウンが実現する。 According to the semiconductor device according to each embodiment of the present invention, the following effects can be obtained.
(1) A multi-chip package including parts that require a hollow structure is possible.
(2) A structure in which chips are stacked can be obtained without filling with resin.
(3) As a result, higher-density mounting is possible, and the product can be downsized.
(4) The distance between the functional element and the sealing resin can be increased, and a package that is not affected by the outgas component is possible.
(5) It is possible to reduce process defects due to handling such as MEMS devices.
(6) Overall, cost reduction is realized.

本発明は上記の説明に限定されない。
例えば、ＭＥＭＳの他、ＳＡＷ素子やＦ−ＢＡＲなどの機能素子を有する半導体チップを組み込んだ半導体装置とすることも可能である。
第２半導体チップの再配線層を埋め込んでいる樹脂層中には、静電容量素子やインダクタンス、電気抵抗素子などの受動素子やトランジスタなどの能動素子が形成された半導体チップを適宜組み込むことが可能である。
また、第２半導体チップは能動素子を有するチップに限らず、ＩＰＤ（Integrated Passive Device）などの受動素子チップなどでもよい。
その他、本発明の要旨を逸脱しない範囲で、種々の変更が可能である。 The present invention is not limited to the above description.
For example, a semiconductor device incorporating a semiconductor chip having a functional element such as a SAW element or F-BAR in addition to the MEMS can be used.
A semiconductor chip in which a passive element such as a capacitance element, an inductance or an electric resistance element or an active element such as a transistor is formed can be appropriately incorporated in the resin layer in which the rewiring layer of the second semiconductor chip is embedded. It is.
The second semiconductor chip is not limited to a chip having an active element, and may be a passive element chip such as an IPD (Integrated Passive Device).
In addition, various modifications can be made without departing from the scope of the present invention.

本発明の半導体装置は、ＭＥＭＳ、ＳＡＷ素子あるいはＦ−ＢＡＲなどの機能面に可動部または振動子を持つ機能素子を有する半導体チップを組み込んだ半導体装置に適用できる。
本発明の半導体装置の製造方法は、ＭＥＭＳ、ＳＡＷ素子あるいはＦ−ＢＡＲなどの機能面に可動部または振動子を持つ機能素子を有する半導体チップを組み込んだ半導体装置の製造方法に適用できる。 The semiconductor device of the present invention can be applied to a semiconductor device in which a semiconductor chip having a functional element having a movable portion or a vibrator on a functional surface such as a MEMS, SAW element, or F-BAR is incorporated.
The method for manufacturing a semiconductor device of the present invention can be applied to a method for manufacturing a semiconductor device in which a semiconductor chip having a functional element having a movable part or a vibrator on a functional surface such as a MEMS, SAW element, or F-BAR is incorporated.

図１は本発明の第１実施形態に係る半導体装置の模式断面図である。FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the present invention. 図２（ａ）は本発明の第１実施形態に係る第１半導体チップの機能素子の形成面における平面図であり、図２（ｂ）は断面図である。2A is a plan view of the functional element forming surface of the first semiconductor chip according to the first embodiment of the present invention, and FIG. 2B is a cross-sectional view. 図３（ａ）は本発明の第１実施形態に係る第２半導体チップの端子形成面における平面図であり、図３（ｂ）は断面図である。FIG. 3A is a plan view of the terminal formation surface of the second semiconductor chip according to the first embodiment of the present invention, and FIG. 3B is a cross-sectional view. 図４（ａ）及び図４（ｂ）は本発明の第１実施形態に係る半導体装置の製造工程を示す模式断面図である。FIGS. 4A and 4B are schematic cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment of the present invention. 図５（ａ）及び図５（ｂ）は本発明の第１実施形態に係る半導体装置の製造工程を示す模式断面図である。FIGS. 5A and 5B are schematic cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment of the present invention. 図６（ａ）及び図６（ｂ）は本発明の第１実施形態に係る半導体装置の製造工程を示す模式断面図である。FIGS. 6A and 6B are schematic cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment of the present invention. 図７は本発明の第２実施形態に係る半導体装置の模式断面図である。FIG. 7 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention. 図８は本発明の第３実施形態に係る半導体装置の模式断面図である。FIG. 8 is a schematic cross-sectional view of a semiconductor device according to the third embodiment of the present invention. 図９は本発明の第４実施形態に係る半導体装置の第１半導体チップが有するＦ−ＢＡＲの模式断面図である。FIG. 9 is a schematic cross-sectional view of the F-BAR included in the first semiconductor chip of the semiconductor device according to the fourth embodiment of the present invention.

符号の説明Explanation of symbols

１０，１０ａ，１０ｂ…第１半導体チップ、１１…チップ本体、１２…機能素子、１３…第１端子、１４…バンプ、２０…第２半導体チップ、２１…チップ本体、２２…絶縁層、２３…再配線層、２４…第２内周端子、２５…第２外周端子、２６…バンプ、３０，３０ａ…実装基板、３１，３１ａ…第１樹脂基板、３２，３２ａ…第２樹脂基板、３３，３４，３５…配線層、３６，３７…貫通配線、３８…凹部、４０…封止樹脂層、５０…バンプ、Ｓ…中空部分   DESCRIPTION OF SYMBOLS 10, 10a, 10b ... 1st semiconductor chip, 11 ... Chip body, 12 ... Functional element, 13 ... 1st terminal, 14 ... Bump, 20 ... 2nd semiconductor chip, 21 ... Chip body, 22 ... Insulating layer, 23 ... Redistribution layer, 24 ... second inner peripheral terminal, 25 ... second outer peripheral terminal, 26 ... bump, 30, 30a ... mounting substrate, 31, 31a ... first resin substrate, 32, 32a ... second resin substrate, 33, 34, 35 ... wiring layer, 36, 37 ... through wiring, 38 ... recess, 40 ... sealing resin layer, 50 ... bump, S ... hollow part

Claims (7)

一主面に可動部または振動子を有する機能素子が形成された第１半導体チップと、
前記第１半導体チップよりも大きいサイズを有し、一主面が端子形成面であり、前記端子形成面上に、前記第１半導体チップが前記機能素子の形成面側から所定の間隔をもってマウントされた第２半導体チップと、
前記第１半導体チップ用の凹部が形成され、前記凹部に前記第１半導体チップが挿入し、前記第２半導体チップが前記凹部を塞ぐようにして、前記第２半導体チップが前記端子形成面側から前記凹部の縁部上にマウントされた実装基板と、
前記凹部の縁部において前記第２半導体チップと前記実装基板の間隙を気密封止するように形成された封止樹脂層と
を有し、
前記凹部の内壁面、前記第２半導体チップの前記端子形成面及び前記封止樹脂層から構成される中空部分に前記第１半導体チップが気密封止された状態で収容されている
半導体装置。 A first semiconductor chip in which a functional element having a movable part or a vibrator is formed on one main surface;
The first semiconductor chip has a size larger than the first semiconductor chip, one main surface is a terminal formation surface, and the first semiconductor chip is mounted on the terminal formation surface at a predetermined interval from the formation surface side of the functional element. A second semiconductor chip,
A recess for the first semiconductor chip is formed, the first semiconductor chip is inserted into the recess, and the second semiconductor chip closes the recess, so that the second semiconductor chip is viewed from the terminal formation surface side. A mounting substrate mounted on the edge of the recess;
A sealing resin layer formed so as to hermetically seal a gap between the second semiconductor chip and the mounting substrate at an edge of the recess,
A semiconductor device in which the first semiconductor chip is hermetically sealed in a hollow portion constituted by an inner wall surface of the recess, the terminal forming surface of the second semiconductor chip, and the sealing resin layer. 前記第１半導体チップには前記機能面において前記機能素子の外周に第１端子が形成されており、
前記第２半導体チップには前記端子形成面に第２内周端子及び第２外周端子が形成されており、
前記実装基板には前記凹部の縁部に実装基板端子が形成されており、
前記第１端子と前記第２内周端子がバンプで接続され、
前記第２内周端子と前記実装基板端子がバンプで接続されている
請求項１に記載の半導体装置。 The first semiconductor chip has a first terminal formed on an outer periphery of the functional element in the functional surface,
A second inner peripheral terminal and a second outer peripheral terminal are formed on the terminal forming surface of the second semiconductor chip;
A mounting board terminal is formed on the edge of the recess on the mounting board,
The first terminal and the second inner peripheral terminal are connected by a bump,
The semiconductor device according to claim 1, wherein the second inner peripheral terminal and the mounting board terminal are connected by a bump. 前記第２半導体チップは、チップ本体と、前記チップ本体の活性面上に形成された絶縁層と、前記チップ本体に接続し、前記絶縁層に埋め込まれて、一部が前記端子形成面で端子となる再配線層とを有する
請求項１に記載の半導体装置。 The second semiconductor chip includes a chip body, an insulating layer formed on an active surface of the chip body, and is connected to the chip body and embedded in the insulating layer. The semiconductor device according to claim 1. 前記実装基板が、他の実装基板に実装するためのバンプが形成されたモジュール基板である
請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the mounting substrate is a module substrate on which bumps for mounting on another mounting substrate are formed. 前記実装基板に他の電子部品が実装されている
請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein another electronic component is mounted on the mounting substrate. 前記機能素子がＭＥＭＳ素子、ＳＡＷ素子、またはＦ−ＢＡＲ素子である
請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the functional element is a MEMS element, a SAW element, or an F-BAR element. 前記中空部分が、真空、減圧、還元雰囲気、あるいは不活性ガス雰囲気に保持されている
請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the hollow portion is held in a vacuum, a reduced pressure, a reducing atmosphere, or an inert gas atmosphere.
JP2006332034A 2006-12-08 2006-12-08 Semiconductor device Pending JP2008147368A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2010047228A1 (en) * 2008-10-21 2012-03-22 日本電気株式会社 Wiring board and manufacturing method thereof
CN110944936A (en) * 2017-06-19 2020-03-31 芬兰国家技术研究中心股份公司 Capacitive microstructure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2010047228A1 (en) * 2008-10-21 2012-03-22 日本電気株式会社 Wiring board and manufacturing method thereof
CN110944936A (en) * 2017-06-19 2020-03-31 芬兰国家技术研究中心股份公司 Capacitive microstructure
JP2020524917A (en) * 2017-06-19 2020-08-20 テクノロギアン トゥトキムスケスクス ヴェーテーテー オイ Capacitive microstructure
US11548779B2 (en) 2017-06-19 2023-01-10 Teknologian Tutkimuskeskus Vtt Oy Capacitive micro structure

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