JP2008141737A - Charge detector - Google Patents

Charge detector Download PDF

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JP2008141737A
JP2008141737A JP2007278392A JP2007278392A JP2008141737A JP 2008141737 A JP2008141737 A JP 2008141737A JP 2007278392 A JP2007278392 A JP 2007278392A JP 2007278392 A JP2007278392 A JP 2007278392A JP 2008141737 A JP2008141737 A JP 2008141737A
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capacitor
charge
difference
photocurrent
detection device
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Toshihito Shirai
白井　　稔人
Tomoshi Sasaki
朋詩 佐々木
Masayoshi Sakai
坂井　　正善
Takayuki Hamamoto
隆之 浜本
Hisamasa Taruki
久征 樽木
Suguru Ono
英 大野
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Nippon Signal Co Ltd
Tokyo University of Science
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Nippon Signal Co Ltd
Tokyo University of Science
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a charge detector capable of surely detecting a difference of electric charge amounts with small-capacity capacitors when distributing an optical current of a light-receiving element to two capacitors synchronously with brightness/darkness of modulation light and detecting the difference of the electric charge amounts between both the capacitors. <P>SOLUTION: A control circuit 4 controls driving of a switch circuit 1 and a differential accumulation circuit 2, a photoelectric current Iin generated in a photo-diode PD that performs photoelectric conversion on the modulation light, is distributed to a capacitor CH and a capacitor CL by the switch circuit 1, and the same electric charge amount as an accumulated electric charge amount VCL of the capacitor CL is subtracted from an accumulated electric charge amount VCH of the capacitor CH by the differential accumulation circuit 2, so that the difference is remained in the capacitor CH. The operation is repeated for a predetermined time to accumulate the differential electric charge amount. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、変調光の明暗に同期して受光素子で生じる光電流に基づいて２つのコンデンサに振り分けた電荷量の差分を検出する電荷検出装置に関し、特に、小容量のコンデンサで確実に電荷量の差分を検出可能な電荷検出装置に関する。   The present invention relates to a charge detection device that detects a difference between charge amounts distributed to two capacitors based on a photocurrent generated in a light receiving element in synchronization with light and darkness of modulated light. It is related with the electric charge detection apparatus which can detect the difference of these.

物体検出方式の代表的な手法として、予め取得した背景画像データと現在の画像データとの差分から背景の変化を検出して物体を検出する背景差分法がある。背景差分法の場合、照明や太陽光等の背景に照射されている光の量や向きが変化すると、背景に変化がなくても恰も変化したかのように検出されて、誤検出する虞れがある。
かかる問題を解消するため、背景に変調光を照射し、変調光の明暗に同期してイメージセンサの受光素子に発生する光電流を２つのコンデンサに振り分けて電荷を蓄積し、その差分に基づいて背景画像データと現在の画像データとを比較することにより、背景光の変化の影響を排除して物体を検出する手法が知られている。 As a typical method of the object detection method, there is a background difference method in which an object is detected by detecting a change in the background from a difference between background image data acquired in advance and current image data. In the case of the background subtraction method, if the amount or direction of light illuminating the background, such as lighting or sunlight, changes, even if there is no change in the background, it will be detected as if it has changed, and there is a risk of false detection. There is.
In order to solve such a problem, the background is irradiated with modulated light, the photocurrent generated in the light receiving element of the image sensor in synchronization with the brightness of the modulated light is distributed to two capacitors, and electric charges are accumulated. A method for detecting an object by comparing the background image data with the current image data and eliminating the influence of a change in background light is known.

そして、変調光の明暗に同期して２つのコンデンサに振り分けた電荷の差分を読み出す従来の手法としては、例えば特許文献１に記載されたものがあり、これを図１２に示す。
図１２の従来回路では、通常はＶXFRを低電位に維持して２つのコンデンサＣ３、Ｃ４を充電し、走査時にＶXFRを高電位に切替えることにより、ＦＥＴＱ３を介して２つのコンデンサＣ３，Ｃ４の蓄積電荷の差分に応じた電圧を検出することにより、差分を読取る。
特開平１０−２８１８６８号公報 A conventional technique for reading out the difference between the charges distributed to the two capacitors in synchronism with the brightness of the modulated light is described in Patent Document 1, for example, and is shown in FIG.
In the conventional circuit shown in FIG. 12, normally, two capacitors C3 and C4 are charged while maintaining V XFR at a low potential, and V XFR is switched to a high potential during scanning, whereby two capacitors C3 and C4 are connected via FET Q3. The difference is read by detecting a voltage corresponding to the difference between the accumulated charges.
Japanese Patent Laid-Open No. 10-281868

しかしながら、上述の従来回路では、２つのコンデンサＣ３，Ｃ４に蓄積された電荷の差が少ない場合、ＦＥＴＱ３を通して読み出される電荷量が少なく、検出できない虞れがある。また、フォトダイオードＰＤによる光電流の量が大きい場合にコンデンサＣ３，Ｃ４の飽和を避けようとすれば、予め大きな容量のコンデンサにしておく必要があり、イメージセンサの回路面積が大きくなるという問題がある。   However, in the above-described conventional circuit, when the difference between the charges accumulated in the two capacitors C3 and C4 is small, there is a possibility that the amount of charge read through the FET Q3 is small and cannot be detected. Further, if it is attempted to avoid the saturation of the capacitors C3 and C4 when the amount of photocurrent generated by the photodiode PD is large, it is necessary to use a capacitor having a large capacity in advance, which increases the circuit area of the image sensor. is there.

本発明は上記問題点に着目してなされたもので、小容量のコンデンサで確実に電荷量の差分を検出可能な電荷検出装置を提供することを目的とする。   The present invention has been made paying attention to the above problems, and an object of the present invention is to provide a charge detection device capable of reliably detecting a difference in charge amount with a small-capacitance capacitor.

このため、請求項１に記載の発明の電荷検出装置は、変調した光の明暗に同期してイメージセンサ内の受光素子で生じる光電流をそれぞれ第１及び第２のコンデンサに振り分けて供給し、前記光電流に基づいて前記第１のコンデンサに蓄えられる電荷量と前記第２のコンデンサに蓄えられる電荷量の差分を蓄積する構成としたことを特徴とする。   For this reason, the charge detection device according to the first aspect of the present invention distributes and supplies the photocurrent generated in the light receiving element in the image sensor to the first and second capacitors in synchronization with the brightness of the modulated light, A difference between the charge amount stored in the first capacitor and the charge amount stored in the second capacitor is accumulated based on the photocurrent.

かかる構成では、変調光の明暗に同期してイメージセンサ内の受光素子で生じる光電流をそれぞれ第１及び第２のコンデンサに振り分けて供給することにより、第１のコンデンサに明るい時の電荷量が蓄えられ、第２のコンデンサに暗い時の電荷量が蓄えられる。そして、第１コンデンサの電荷量と第２のコンデンサ電荷量の差分を蓄積することにより、差分を増大させることができるようになる。   In such a configuration, the photocurrent generated in the light receiving element in the image sensor in synchronization with the brightness of the modulated light is distributed and supplied to the first and second capacitors, respectively, so that the first capacitor has a bright charge amount. It is stored, and the amount of charge in the dark is stored in the second capacitor. Then, the difference can be increased by accumulating the difference between the charge amount of the first capacitor and the second capacitor charge amount.

請求項２のように、前記光電流の振り分けを複数回繰返し、前記第１及び第２のコンデンサに前記光電流に基づく電荷をそれぞれ蓄積した後に、これら蓄積電荷量の差分を蓄積する構成とするとよい。
かかる構成では、１回の振り分け量が微量な場合でもこれを複数回繰返して蓄積することにより、第１及び第２のコンデンサそれぞれの蓄積電荷量が多くなり、差分の検出が容易にある。 As described in claim 2, the photocurrent distribution is repeated a plurality of times, and the charge based on the photocurrent is accumulated in the first and second capacitors, respectively, and then the difference between these accumulated charge amounts is accumulated. Good.
In such a configuration, even if the amount of distribution at one time is very small, the accumulated charge amount of each of the first and second capacitors is increased by repeatedly accumulating this several times, so that the difference can be easily detected.

具体的には、請求項３のように、前記変調光の明暗に同期してスイッチングし、前記受光素子で生じる光電流を前記第１のコンデンサと第２のコンデンサに振り分けて供給するスイッチ手段と、前記第１のコンデンサに蓄えられる電荷量から前記第２のコンデンサに蓄えられる電荷量を減算してその差分を蓄積させる差分蓄積手段と、を備え、前記変調光の明暗に同期させて前記スイッチ手段を駆動制御し、所定タイミングで前記差分蓄積手段を駆動させる構成とするとよい。
かかる構成では、スイッチ手段が変調光の明暗に同期したスイッチング動作して、受光素子で生じる光電流を第１のコンデンサと第２のコンデンサとに振り分けて供給する。また、所定タイミングで差分蓄積手段が駆動し、差分蓄積手段により第１及び第２のコンデンサにそれぞれ蓄えられた電荷量の差分を蓄積する。 Specifically, as in claim 3, switch means that switches in synchronization with the brightness of the modulated light and distributes and supplies the photocurrent generated in the light receiving element to the first capacitor and the second capacitor. Difference accumulation means for subtracting the amount of charge stored in the second capacitor from the amount of charge stored in the first capacitor and storing the difference, and synchronizing the brightness of the modulated light with the switch It is preferable to control the driving means and drive the difference accumulating means at a predetermined timing.
In such a configuration, the switching means performs a switching operation synchronized with the brightness of the modulated light, and distributes and supplies the photocurrent generated in the light receiving element to the first capacitor and the second capacitor. Further, the difference accumulation unit is driven at a predetermined timing, and the difference accumulation unit accumulates the difference between the charge amounts respectively stored in the first and second capacitors.

請求項４のように、蓄えられる電荷量の多い前記第１のコンデンサの電荷量を検出し、検出電荷量を予め定めた閾値と比較して検出電荷量が閾値以上になった時に、前記差分蓄積手段を駆動させる駆動指令を発生する比較手段を備える構成とするとよい。
かかる構成では、蓄えられる電荷量の多い第１のコンデンサの電荷量が閾値以上になった時に比較手段の駆動指令に基づいて差分蓄積手段が駆動するようになる。これにより、第１のコンデンサが飽和することを確実に回避できると共に、閾値の設定により、差分蓄積手段の動作タイミングを変更させることが可能になる。 According to a fourth aspect of the present invention, when the charge amount of the first capacitor that stores a large amount of charge is detected, the detected charge amount is compared with a predetermined threshold value, and when the detected charge amount is equal to or greater than the threshold value, It may be configured to include comparison means for generating a drive command for driving the storage means.
In such a configuration, the difference accumulating unit is driven based on the drive command of the comparing unit when the amount of charge of the first capacitor having a large amount of stored charge becomes equal to or greater than the threshold value. As a result, it is possible to reliably avoid saturation of the first capacitor, and it is possible to change the operation timing of the difference accumulating means by setting the threshold value.

請求項５のように、前記差分蓄積手段は、蓄えられる電荷量の少ない前記第２のコンデンサを基準とし、前記駆動指令に基づいてカレントミラー回路を駆動し、前記第１及び第２のコンデンサから同量の電荷量を放電させて前記第１のコンデンサに前記差分を残存させる構成であり、前記差分蓄積手段を繰返し動作させて前記第１のコンデンサに前記差分を蓄積する構成とするとよい。   The difference accumulation means drives the current mirror circuit based on the drive command based on the second capacitor with a small amount of stored charge as a reference, and from the first and second capacitors. It is preferable that the difference is left in the first capacitor by discharging the same amount of charge, and the difference is stored in the first capacitor by repeatedly operating the difference accumulation unit.

請求項６のように、前記スイッチ手段は、前記受光素子で生じる光電流を前記第１及び第２のコンデンサにそれぞれ振り分けるためのカレントミラー回路と、該カレントミラー回路で振り分けた光電流を前記変調光の明暗に同期してスイッチングし第１及び第２コンデンサにそれぞれ供給するためのスイッチ部とを備える構成とした。   The switch means includes a current mirror circuit for distributing the photocurrent generated in the light receiving element to the first and second capacitors, and the modulation of the photocurrent distributed by the current mirror circuit. And a switch unit for switching in synchronization with the brightness of light and supplying the first and second capacitors respectively.

請求項７のように、前記カレントミラー回路は、電源と前記受光素子の間に直列に接続しゲート端子が前記受光素子に接続し前記受光素子で生じる前記光電流が流れる第１ＭＯＳトランジスタと、電源と前記第１のコンデンサの間に直列に介装しゲート端子が前記第１ＭＯＳトランジスタのゲート端子に接続し前記スイッチ部のスイッチング動作に同期して変調光が明るい時の前記光電流に対応する出力電流が流れる第２ＭＯＳトランジスタと、電源と前記第２のコンデンサの間に直列に介装しゲート端子が前記第１ＭＯＳトランジスタのゲート端子に接続し前記スイッチ部のスイッチング動作に同期して変調光が暗い時の前記光電流に対応する出力電流が流れる第３ＭＯＳトランジスタと、を備える構成とした。   The current mirror circuit includes a first MOS transistor connected in series between a power source and the light receiving element, a gate terminal connected to the light receiving element, and the photocurrent generated in the light receiving element flowing therein; And a gate terminal connected in series to the gate terminal of the first MOS transistor, and an output corresponding to the photocurrent when the modulated light is bright in synchronization with the switching operation of the switch unit. A second MOS transistor through which a current flows, a power supply and the second capacitor are connected in series, and the gate terminal is connected to the gate terminal of the first MOS transistor, and the modulated light is dark in synchronization with the switching operation of the switch unit. And a third MOS transistor through which an output current corresponding to the photocurrent at the time flows.

請求項８のように、前記スイッチ部は、前記電源と前記第２ＭＯＳトランジスタの間に介装され変調光が明るい期間に駆動信号の入力で前記第２ＭＯＳトランジスタを電源に接続し駆動信号の停止で前記第２ＭＯＳトランジスタをＧＮＤに切換接続する第１切換スイッチと、前記電源と前記第３ＭＯＳトランジスタの間に介装され変調光が暗い期間に駆動信号の入力で前記第３ＭＯＳトランジスタを電源に接続し駆動信号の停止で前記第３ＭＯＳトランジスタをＧＮＤに切換接続する第２切換スイッチと、を備えて構成とするとよい。   According to another aspect of the present invention, the switch unit is interposed between the power source and the second MOS transistor and connects the second MOS transistor to the power source by inputting the driving signal during a period when the modulated light is bright, and stops the driving signal. A first changeover switch for switchingly connecting the second MOS transistor to GND, and a drive signal that is interposed between the power supply and the third MOS transistor and is input with a drive signal during a period in which the modulated light is dark. A second change-over switch that switches and connects the third MOS transistor to GND when the signal is stopped may be provided.

また、請求項９のように、前記カレントミラー回路を、前記第１ＭＯＳトランジスタのバルク端子を電源に接続し、前記第２及び第３ＭＯＳトランジスタのバルク端子を、それぞれ電圧が可変できる可変電圧源に接続する構成とすると共に、前記受光素子の電圧を予め定めた設定値に保持するよう前記受光素子の電圧変化に応じて第１ＭＯＳトランジスタのゲート端子電圧を可変制御するオペアンプを、前記スイッチ手段に設ける構成としてもよい。
かかる構成では、第１ＭＯＳトランジスタがサブスレショールド領域で動作するときの応答特性を改善できるようになる。 Further, as in claim 9, the current mirror circuit is connected to the power supply at the bulk terminal of the first MOS transistor, and the bulk terminal of the second and third MOS transistors is connected to a variable voltage source capable of varying the voltage. And an operational amplifier that variably controls the gate terminal voltage of the first MOS transistor in accordance with a change in the voltage of the light receiving element so as to hold the voltage of the light receiving element at a predetermined set value. It is good.
With such a configuration, the response characteristic when the first MOS transistor operates in the subthreshold region can be improved.

請求項１０のように、前記受光素子で生じる前記光電流にオフセット電流を付加する構成とするとよい。
かかる構成では、オフセット電流を付加することで、カレントミラー回路の応答速度を高め、動作を安定化できるようになる。 It is preferable that an offset current is added to the photocurrent generated in the light receiving element.
In such a configuration, by adding an offset current, the response speed of the current mirror circuit can be increased and the operation can be stabilized.

請求項１１のように、多数の受光素子からなるイメージセンサからの画像データに基づいて、予め取得した背景画像データと現在の画像データとの差分から物体を検出する背景差分法を利用する物体検出装置に適用するとよい。   12. Object detection using a background subtraction method for detecting an object from a difference between background image data acquired in advance and current image data based on image data from an image sensor composed of a large number of light receiving elements. It is good to apply to the device.

本発明の電荷検出装置によれば、変調光の明暗に同期させて２つのコンデンサに振り分けて蓄えた電荷量の差分を蓄積することで差分を増大する構成としたので、変調光の明るい時と暗い時の電荷量の差が僅かでも検出可能な十分な差分電荷量を得ることができ、ダイナミックレンジを拡大できる。また、第１のコンデンサに蓄えた変調光の明るい時の電荷量から第２のコンデンサに蓄えた変調光の暗い時の電荷量を減算しその差分を蓄積するので、受光素子の光電流の量が大きい場合でもコンデンサが飽和する虞れはなく、コンデンサを小さい容量にでき回路面積を小さくできる。   According to the charge detection device of the present invention, the difference is increased by accumulating the difference between the charge amounts distributed and stored in the two capacitors in synchronization with the brightness of the modulated light. A sufficient differential charge amount that can be detected even when the difference in charge amount in the dark is small, and the dynamic range can be expanded. In addition, since the amount of dark light of the modulated light stored in the second capacitor is subtracted from the amount of light of the modulated light stored in the first capacitor when it is bright, the difference is accumulated. Even when the capacitor is large, there is no possibility that the capacitor is saturated, and the capacitor can be made small in capacity and the circuit area can be reduced.

以下、本発明の実施形態を図面に基づいて説明する。
図１は、本発明に係る電荷検出装置の第１実施形態の構成を示す概略図である。
図１において、本実施形態の電荷検出装置は、変調光を含む光を光電変換する受光素子であるフォトダイオードＰＤに生じる光電流Ｉｉｎを第１のコンデンサＣＨと第２のコンデンサＣＬに振り分け供給するスイッチ手段としてのスイッチ回路１と、コンデンサＣＨに蓄えられる電荷量に相当する電圧ＶＣＨからコンデンサＣＬに蓄えられる電荷量に相当する電圧ＶＣＬを減算し、その差分をコンデンサＣＨに蓄積させる差分蓄積手段としての差分蓄積回路２と、フォトダイオードＰＤの光電流Ｉｉｎにオフセット電流Ｉｏｆｆを付加する電流源３とを備え、制御信号の入力で、制御回路４により変調光の明暗に同期したｎ−ｓｗ１，ｎ−ｓｗ２の各信号をスイッチ回路１に出力してスイッチ回路１を駆動制御し、所定タイミングで差分蓄積回路２にＶｓｅｌ，ｎ−Ｖｓｅｌの各信号及びｆｌａｇ信号を出力して差分蓄積回路２を駆動制御する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic diagram showing the configuration of a first embodiment of a charge detection device according to the present invention.
In FIG. 1, the charge detection device of this embodiment distributes and supplies a photocurrent Iin generated in a photodiode PD, which is a light receiving element that photoelectrically converts light including modulated light, to a first capacitor CH and a second capacitor CL. Switch circuit 1 as a switch means, and difference accumulation means for subtracting voltage VCL corresponding to the amount of charge stored in capacitor CL from voltage VCH corresponding to the amount of charge stored in capacitor CH and storing the difference in capacitor CH Differential storage circuit 2 and a current source 3 for adding an offset current Ioff to the photocurrent Iin of the photodiode PD, and n-sw1, n synchronized with the brightness of the modulated light by the control circuit 4 by the input of the control signal -Sw2 signals are output to the switch circuit 1 to drive and control the switch circuit 1, and the difference is accumulated at a predetermined timing. Vsel the road 2, and outputs each signal and flag signals n-Vsel controls driving of the difference storage circuit 2.

図２に、電荷検出装置の具体的回路構成を示す。
図２において、スイッチ回路１は、３つのＰＭＯＳＱ１１〜Ｑ１３で構成され、フォトダイオードＰＤで生じる光電流Ｉｉｎを第１及び第２のコンデンサＣＨ，ＣＬにそれぞれ振り分けるためのカレントミラー回路と、ＰＭＯＳＱ１４，１５で構成され、前記カレントミラー回路で振り分けた光電流を変調光の明暗に同期するｎ−ｓｗ１，ｎ−ｓｗ２の各信号によりスイッチングして第１及び第２のコンデンサＣＨ，ＣＬにそれぞれ供給するためのスイッチ部とを備えて構成される。 FIG. 2 shows a specific circuit configuration of the charge detection device.
In FIG. 2, the switch circuit 1 is composed of three PMOSs Q11 to Q13, and a current mirror circuit for distributing the photocurrent Iin generated in the photodiode PD to the first and second capacitors CH and CL, and PMOSs Q14 and 15 respectively. The photocurrents distributed by the current mirror circuit are switched by the n-sw1 and n-sw2 signals synchronized with the brightness of the modulated light and supplied to the first and second capacitors CH and CL, respectively. And a switch unit.

前記差分蓄積回路２は、一対のＰＭＯＳＱ２１とＮＭＯＳＱ２２で構成されｆｌａｇ信号の入力を制御するためのゲート回路と、４つのＮＭＯＳＱ２３〜Ｑ２６で構成され、蓄えられる電荷量の少ない第２のコンデンサＣＬを基準としてｆｌａｇ信号の入力で駆動し、第１及び第２のコンデンサＣＨ，ＣＬから同量の電荷量を放電させ第１のコンデンサＣＨに両者の電荷量の差分を残存させるためのカレントミラー回路と、ｎ−Ｖｓｅｌ信号によりｆｌａｇ信号がＮＭＯＳＱ２３とＱ２４に印加されていない時にこれらのゲート電圧を０ＶにするＮＭＯＳＱ２７とを備えて構成される。   The differential accumulation circuit 2 is composed of a pair of PMOS Q21 and NMOS Q22, and is composed of a gate circuit for controlling the input of a flag signal and four NMOSs Q23 to Q26, and is based on a second capacitor CL with a small amount of stored charge. A current mirror circuit that is driven by the input of a flag signal, discharges the same amount of charge from the first and second capacitors CH and CL, and leaves the difference between the amounts of charge in the first capacitor CH; The n-Vsel signal is configured to include an NMOS Q27 that sets the gate voltage to 0 V when the flag signal is not applied to the NMOSs Q23 and Q24.

前記電流源３は、外部からバイアス電圧ｂｉａｓが印加されて光電流Ｉｉｎに付加してオフセット電流Ｉｏｆｆを流すためのＮＭＯＳＱ３１で構成される。
更に、電荷検出装置は、各コンデンサＣＨ，ＣＬの電荷蓄積をリセットするためのＮＭＯＳＱ４１，４２と、信号線Φ１へのコンデンサＣＨの蓄積電荷量の読出しを制御するためのＰＭＯＳＱ４３，Ｑ４４と、信号線Φ２へのコンデンサＣＬの蓄積電荷量の読出しを制御するためのＰＭＯＳＱ４５，Ｑ４６と、各信号線Φ１，Φ２に読出した蓄積電荷量を外部に信号電圧として出力するために必要な、ゲート端子に所定のバイアス電圧ｂｉａｓ２（前述のバイアス電圧ｂｉａｓとは異なる）が印加されたソースフォロワのＰＭＯＳＱ４７，Ｑ４８とを備える。
尚、前記ＰＭＯＳＱ４７，Ｑ４８は、実際の２次元アレイ回路では、図３に示すように、１つの列に共通に１つ設ければよい。図中の１０は、図２に示す電荷検出回路から制御回路とＰＭＯＳＱ４７，Ｑ４８を除いた回路部分に相当する。 The current source 3 is composed of an NMOS Q31 for applying an external bias voltage bias and adding it to the photocurrent Iin to flow an offset current Ioff.
Further, the charge detection device includes NMOSs Q41 and 42 for resetting the charge accumulation of the capacitors CH and CL, PMOSs Q43 and Q44 for controlling the reading of the accumulated charge amount of the capacitor CH to the signal line Φ1, and the signal lines. PMOSs Q45 and Q46 for controlling reading of the accumulated charge amount of the capacitor CL to Φ2, and a gate terminal required to output the accumulated charge amount read to the signal lines Φ1 and Φ2 to the outside as a signal voltage. Source follower PMOSs Q47 and Q48 to which a bias voltage bias2 (which is different from the bias voltage bias described above) is applied.
In the actual two-dimensional array circuit, the PMOSs Q47 and Q48 may be provided in common in one column as shown in FIG. 10 in the figure corresponds to a circuit portion obtained by removing the control circuit and PMOSs Q47 and Q48 from the charge detection circuit shown in FIG.

次に、図２の回路の動作を図４のタイムチャートを参照して説明する。
制御回路４からのｒｓｔ信号をハイにし、ＮＭＯＳＱ４１，４２をＯＮして両コンデンサＣＨ，ＣＬの電荷をリセットし、電荷リセット後はｒｓｔ信号をローにしてＮＭＯＳＱ４１，４２をＯＦＦにする（図４中の動作ａ）。 Next, the operation of the circuit of FIG. 2 will be described with reference to the time chart of FIG.
The rst signal from the control circuit 4 is set to high, the NMOSs Q41 and 42 are turned on to reset the charges of both capacitors CH and CL, and after the charge reset, the rst signal is set to low and the NMOSs Q41 and 42 are turned off (in FIG. 4). Operation a).

電荷リセット後、変調光の明暗に同期させて、変調光が明（ハイ）の期間でｎ−ｓｗ１信号をローにし、スイッチ回路１のＰＭＯＳＱ１４をＯＮにする。これにより、この時にフォトダイオードＰＤに流れる光電流Ｉｉｎがカレントミラー回路及びＰＭＯＳＱ１４を介してコンデンサＣＨに流れ、変調光が明るい時の光電流に対応する電荷量がコンデンサＣＨに蓄えられる。一方、変調光が暗（ロー）の期間でｎ−ｓｗ２信号をローにし、スイッチ回路１のＰＭＯＳＱ１５をＯＮにする。これにより、この時にフォトダイオードＰＤに流れる光電流Ｉｉｎがカレントミラー回路及びＰＭＯＳＱ１５を介してコンデンサＣＬに流れ、変調光が暗い時の光電流に対応する電荷量がコンデンサＣＬに蓄えられる。この動作を、複数回（図４では２回）繰返し、変調光が明るい時と暗い時の各電荷量を両コンデンサＣＨ，ＣＬに振り分けて蓄積する。これにより、コンデンサＣＨの両端電圧はＶＣＨとなり、コンデンサＣＬの両端電圧はＶＣＬとなる（図４中の動作ｂ）。   After the charge reset, in synchronization with the brightness of the modulated light, the n-sw1 signal is set low during the period when the modulated light is bright (high), and the PMOS Q14 of the switch circuit 1 is turned ON. As a result, the photocurrent Iin flowing through the photodiode PD at this time flows to the capacitor CH via the current mirror circuit and the PMOS Q14, and the amount of charge corresponding to the photocurrent when the modulated light is bright is stored in the capacitor CH. On the other hand, the n-sw2 signal is set to low while the modulated light is dark (low), and the PMOS Q15 of the switch circuit 1 is turned ON. As a result, the photocurrent Iin flowing through the photodiode PD at this time flows to the capacitor CL via the current mirror circuit and the PMOS Q15, and the charge amount corresponding to the photocurrent when the modulated light is dark is stored in the capacitor CL. This operation is repeated a plurality of times (twice in FIG. 4), and the respective charge amounts when the modulated light is bright and dark are distributed and accumulated in both capacitors CH and CL. As a result, the voltage across the capacitor CH becomes VCH, and the voltage across the capacitor CL becomes VCL (operation b in FIG. 4).

次に、予め定めたタイミング（本実施形態の場合は電荷蓄積動作が２回繰返された後）で、制御回路４から互いに相補の関係にあるＶｓｅｌ信号とｎ−Ｖｓｅｌ信号に加えてｆｌａｇ信号を差分蓄積回路２に出力して、両コンデンサＣＨ，ＣＬの電荷量の差分の蓄積動作を実行する。具体的には、ハイのＶｓｅｌ信号とローのｎ−Ｖｓｅｌ信号を発生し、ＰＭＯＳＱ２１とＮＭＯＳＱ２２をＯＮしてゲート回路を開き、ＮＭＯＳＱ２７をＯＦＦにして、ｆｌａｇ信号が差分蓄積回路２のカレントミラー回路に入力できる状態にする。その後、ｆｌａｇ信号をハイにして前記カレントミラー回路を動作させる。これにより、コンデンサＣＬの電圧ＶＣＬに対応した電流ＩＬがカレントミラー回路の右側に流れ、同じ電流ＩＬがカレントミラー回路の左側に流れ、コンデンサＣＬから放電される電荷量と同じ電荷量がコンデンサＣＨから放電される。従って、コンデンサＣＨには、図４中の動作ｂでコンデンサＣＨとＣＬにそれぞれ蓄積された各電荷量の差分（ＶＣＨ−ＶＣＬ）が残存する（図４中の動作ｃ）。 Next, at a predetermined timing (in the case of this embodiment, after the charge accumulation operation is repeated twice), a flag signal is added in addition to the Vsel signal and the n-Vsel signal that are complementary to each other from the control circuit 4. Output to the difference accumulation circuit 2 to execute the accumulation operation of the difference between the charge amounts of the capacitors CH and CL. Specifically, a high Vsel signal and a low n-Vsel signal are generated, the PMOS Q21 and the NMOS Q22 are turned on to open the gate circuit, the NMOS Q27 is turned off, and the flag signal is supplied to the current mirror circuit of the differential accumulation circuit 2. Make it ready for input. Thereafter, the flag signal is set to high to operate the current mirror circuit. Accordingly, current I L corresponding to the voltage VCL of the capacitor CL flows to the right side of the current mirror circuit, the same current I L flows through the left side of the current mirror circuit, a capacitor is the same amount of charge as the amount of charge discharged from the capacitor CL It is discharged from CH. Therefore, the difference (VCH−VCL) between the respective charge amounts accumulated in the capacitors CH and CL in the operation b in FIG. 4 remains in the capacitor CH (operation c in FIG. 4).

そして、所定の時間間隔で、差分電荷量の読出し信号としてローのｎ−Ｖｓｅｌ信号をＰＭＯＳＱ４４，Ｑ４６に印加してＯＮし、コンデンサＣＨに蓄積された電荷量を信号線Φ１，Φ２から読み出す。   Then, at a predetermined time interval, a low n-Vsel signal as a differential charge amount read signal is applied to the PMOSs Q44 and Q46 to turn them on, and the charge amount accumulated in the capacitor CH is read from the signal lines Φ1 and Φ2.

かかる構成の電荷検出装置によれば、コンデンサＣＨに蓄えた変調光の明るい時の電荷量からコンデンサＣＨに蓄えた変調光の暗い時の電荷量と同じ量を放電させて差分をコンデンサＣＨに残存させるので、フォトダイオードＰＤの光電流Ｉｉｎが大きい場合でも、コンデンサＣＨ，ＣＬが飽和する虞れはなく、コンデンサＣＨ，ＣＬの容量を大きくしなくて済む。また、コンデンサＣＨに残存させる差分を蓄積して前記差分を増大するようにしたので、変調光の明るい時と暗い時の電荷量の差が僅かでも、検出可能な十分な差分電荷量を得ることができ、ダイナミックレンジを拡大できる。   According to the charge detection device having such a configuration, the same amount as the dark charge amount of the modulated light stored in the capacitor CH is discharged from the bright charge amount of the modulated light stored in the capacitor CH, and the difference remains in the capacitor CH. Therefore, even when the photocurrent Iin of the photodiode PD is large, there is no possibility that the capacitors CH and CL are saturated, and it is not necessary to increase the capacitance of the capacitors CH and CL. Further, since the difference remaining in the capacitor CH is accumulated to increase the difference, a sufficient difference charge amount that can be detected can be obtained even if the difference in the charge amount between the bright and dark modulated light is small. Can expand the dynamic range.

また、本実施形態では、電流源３のＮＭＯＳＱ３１に外部バイアス電圧ｂｉａｓを印加してＯＮ状態とし、オフセット電流ＩｏｆｆをフォトダイオードＰＤの光電流Ｉｉｎに付加することができる。オフセット電流Ｉｏｆｆを付加することにより、スイッチ回路１のカレントミラー回路を構成するＰＭＯＳＱ１１，Ｑ１２を飽和領域で動作させることができ、カレントミラー回路の動作を安定させ、応答速度を高めることができる。そして、光電流Ｉｉｎが多い場合はバイアス電圧ｂｉａｓを低くしてオフセット電流Ｉｏｆｆを小さくし、光電流Ｉｉｎが少ない場合はバイアス電圧ｂｉａｓを高くしてオフセット電流Ｉｏｆｆを多くするよう、バイアス電圧ｂｉａｓによりオフセット電流Ｉｏｆｆを調整することで、カレントミラー回路の応答速度をコントロールすることができる。光電流Ｉｉｎが十分多い場合、オフセット電流Ｉｏｆｆは付加する必要はなくＩｏｆｆ＝０とする。   In the present embodiment, the external bias voltage bias can be applied to the NMOS Q31 of the current source 3 to turn it on, and the offset current Ioff can be added to the photocurrent Iin of the photodiode PD. By adding the offset current Ioff, the PMOSs Q11 and Q12 constituting the current mirror circuit of the switch circuit 1 can be operated in the saturation region, and the operation of the current mirror circuit can be stabilized and the response speed can be increased. When the photocurrent Iin is large, the bias voltage bias is lowered to decrease the offset current Ioff, and when the photocurrent Iin is small, the bias voltage bias is increased to increase the offset current Ioff. The response speed of the current mirror circuit can be controlled by adjusting the current Ioff. When the photocurrent Iin is sufficiently large, it is not necessary to add the offset current Ioff, and Ioff = 0.

尚、本実施形態では、変調光が明るい時の電荷量と暗い時の電荷量の蓄積を複数回繰返した後に差分蓄積回路２を駆動する構成としたが、１回の蓄積動作毎に差分蓄積回路２を駆動させて電荷量を減算するようにしてもよい。   In this embodiment, the difference accumulation circuit 2 is driven after the accumulation of the charge amount when the modulated light is bright and the charge amount when the modulation light is dark a plurality of times, but the difference accumulation is performed for each accumulation operation. The circuit 2 may be driven to subtract the charge amount.

次に、本発明の電荷検出装置の第２実施形態を図５を参照して説明する。
図５は、本発明に係る電荷検出装置の第２実施形態の構成を示す概略図である。尚、第１実施形態と同一要素には同一符号を付して説明を省略する。
図５において、本実施形態の電荷検出装置では、図１の第１実施形態の構成に加えて、コンデンサＣＨの電荷量ＶＣＨを予め設定した閾値Ｖｔｈと比較する比較回路５を設ける構成とした。比較回路５は、コンデンサＣＨに蓄えられる電荷量に相当する電圧ＶＣＨと前記閾値Ｖｔｈを比較し、ＶＣＨ≧Ｖｔｈになった時にｆｌａｇ信号をハイとする。これにより、差分蓄積回路２が動作し、コンデンサＣＨにはコンデンサＣＬとの差分の電荷量が残存する。 Next, a second embodiment of the charge detection device of the present invention will be described with reference to FIG.
FIG. 5 is a schematic view showing the configuration of the second embodiment of the charge detection device according to the present invention. In addition, the same code | symbol is attached | subjected to the same element as 1st Embodiment, and description is abbreviate | omitted.
In FIG. 5, the charge detection device of the present embodiment is configured to include a comparison circuit 5 that compares the charge amount VCH of the capacitor CH with a preset threshold value Vth in addition to the configuration of the first embodiment of FIG. The comparison circuit 5 compares the voltage VCH corresponding to the amount of charge stored in the capacitor CH with the threshold value Vth, and sets the flag signal to high when VCH ≧ Vth. As a result, the differential accumulation circuit 2 operates, and the capacitor CH retains a difference charge amount from the capacitor CL.

かかる第２実施形態によれば、コンデンサＣＨの電荷量が閾値Ｖｔｈ以上になれば、差分蓄積回路２により電荷量の減算動作が実行されるので、蓄えられる電荷量が多いコンデンサＣＨが飽和する以前にコンデンサＣＨが放電され、フォトダイオードＰＤに生じる光電流Ｉｉｎが多い場合でも、コンデンサＣＨが飽和することを確実に防止できる。   According to the second embodiment, when the charge amount of the capacitor CH becomes equal to or higher than the threshold value Vth, the subtraction operation of the charge amount is executed by the differential accumulation circuit 2, so that the capacitor CH having a large amount of stored charge is saturated. Even when the capacitor CH is discharged and the photocurrent Iin generated in the photodiode PD is large, the capacitor CH can be reliably prevented from being saturated.

尚、比較回路５は各フォトダイオードＰＤに対応させて設ける必要はなく、複数のフォトダイオードＰＤを１グループとして各グループ毎に１つの比較回路５を設けるよう構成すれば、多数のフォトダイオードからなるイメージセンサ等の回路面積をコンパクトにできる利点がある。   The comparison circuit 5 does not need to be provided corresponding to each photodiode PD. If a plurality of photodiodes PD are provided as one group and one comparison circuit 5 is provided for each group, the comparison circuit 5 includes a large number of photodiodes. There is an advantage that the circuit area of an image sensor or the like can be made compact.

次に、本発明の電荷検出装置の第３実施形態について説明する。
第３実施形態は、図１に示す第１実施形態とスイッチ回路１の構成が異なるだけである。
図６に、第３実施形態におけるスイッチ回路１の回路図を示す。尚、第１実施形態と同一要素には同一符号を付して説明を省略する。
図６において、第３実施形態のスイッチ回路１は、フォトダイオードＰＤに生じる光電流Ｉｉｎを第１のコンデンサＣＨと第２のコンデンサＣＬに振り分けるときのみ、カレントミラー回路を電源ＶＤＤに接続する構成である。 Next, a third embodiment of the charge detection device of the present invention will be described.
The third embodiment differs from the first embodiment shown in FIG. 1 only in the configuration of the switch circuit 1.
FIG. 6 shows a circuit diagram of the switch circuit 1 in the third embodiment. In addition, the same code | symbol is attached | subjected to the same element as 1st Embodiment, and description is abbreviate | omitted.
In FIG. 6, the switch circuit 1 of the third embodiment has a configuration in which the current mirror circuit is connected to the power supply VDD only when the photocurrent Iin generated in the photodiode PD is distributed to the first capacitor CH and the second capacitor CL. is there.

第１実施形態において、前記カレントミラー回路は、電源とフォトダイオードＰＤの間に直列に接続しゲート端子がフォトダイオードＰＤに接続しフォトダイオードＰＤで生じる光電流Ｉｉｎが流れる第１ＭＯＳトランジスタであるＰＭＯＳＱ１１と、電源と第１のコンデンサＣＨの間に直列に介装しゲート端子がＰＭＯＳＱ１１のゲート端子に接続しスイッチ部のスイッチング動作に同期して変調光が明るい時の光電流Ｉｉｎに対応する出力電流が流れる第２ＭＯＳトランジスタであるＰＭＯＳＱ１２と、電源と第２のコンデンサＣＬの間に直列に介装しゲート端子がＰＭＯＳＱ１１のゲート端子に接続しスイッチ部スイッチング動作に同期して変調光が暗い時の光電流Ｉｉｎに対応する出力電流が流れる第３ＭＯＳトランジスタであるＰＭＯＳＱ１３とを備えて構成されている。第１実施形態のスイッチ回路１では、ＰＭＯＳＱ１２とコンデンサＣＨとの間にスイッチ部のＰＭＯＳＱ１４を介装し、ＰＭＯＳＱ１３とコンデンサＣＬとの間にスイッチ部のＰＭＯＳＱ１５を介装し、これらを変調光の明暗に同期してスイッチングする構成とした。   In the first embodiment, the current mirror circuit includes a PMOS Q11 that is a first MOS transistor that is connected in series between a power source and a photodiode PD, a gate terminal is connected to the photodiode PD, and a photocurrent Iin generated in the photodiode PD flows. The output current corresponding to the photocurrent Iin when the modulated light is bright in synchronization with the switching operation of the switch unit with the gate terminal connected in series between the power source and the first capacitor CH and the gate terminal connected to the gate terminal of the PMOS Q11. A photocurrent when the modulated light is dark in synchronization with the switching operation of the switch unit with the gate terminal connected to the gate terminal of the PMOS Q11 in series between the PMOS Q12 which is the second MOS transistor that flows and the power supply and the second capacitor CL. P, which is a third MOS transistor through which an output current corresponding to Iin flows. It is constituted by a OSQ13. In the switch circuit 1 of the first embodiment, the PMOS Q14 of the switch unit is interposed between the PMOS Q12 and the capacitor CH, and the PMOS Q15 of the switch unit is interposed between the PMOS Q13 and the capacitor CL. Switching is performed in synchronization with

第３実施形態では、ＰＭＯＳＱ１４，Ｑ１５の代わりに、カレントミラー回路の各ＰＭＯＳＱ１２，Ｑ１３のソース端子と定電源ラインＶＤＤとの間に、第１及び第２切換スイッチ２１，２２を設ける構成である。第１切換スイッチ２１は、駆動信号とであるｎ−ｓｗ１信号の入力でＰＭＯＳＱ１２のソース端子を電源ＶＤＤに接続し、ｎ−ｓｗ１信号の停止でＰＭＯＳＱ１２のソース端子をＧＮＤに切換接続する構成である。第２切換スイッチ２２は、駆動信号であるｎ−ｓｗ２信号の入力でＰＭＯＳＱ１３のソース端子を電源ＶＤＤに接続し、ｎ−ｓｗ２信号の停止でＰＭＯＳＱ１３のソース端子をＧＮＤに切換接続する構成である。   In the third embodiment, instead of the PMOSs Q14 and Q15, the first and second changeover switches 21 and 22 are provided between the source terminals of the PMOSs Q12 and Q13 of the current mirror circuit and the constant power supply line VDD. The first changeover switch 21 is configured to connect the source terminal of the PMOS Q12 to the power supply VDD when an n-sw1 signal as a drive signal is input, and to switch and connect the source terminal of the PMOS Q12 to GND when the n-sw1 signal is stopped. . The second changeover switch 22 has a configuration in which the source terminal of the PMOS Q13 is connected to the power supply VDD when an n-sw2 signal as a drive signal is input, and the source terminal of the PMOS Q13 is switched and connected to GND when the n-sw2 signal is stopped.

第３実施形態のスイッチ回路１の動作を説明する。尚、その他の動作は第１実施形態と同様であるので、ここではスイッチ回路１による電荷振り分け動作についてのみ説明しその他の動作の説明は省略する。
変調光が明（ハイ）の期間でｎ−ｓｗ１信号を発生して切換スイッチ２１を電源ＶＤＤ側に切換えてＰＭＯＳＱ１２を電源ＶＤＤに接続する。このとき、ｎ−ｓｗ２信号は発生しておらず切換スイッチ２２はＰＭＯＳＱ１３をＧＮＤに接続してＰＭＯＳＱ１３への電流の流れを停止する。これにより、ＰＭＯＳＱ１１とＱ１２がカレントミラーとして動作して、変調光が明るい時の光電流に対応する電荷量が第１のコンデンサＣＨに蓄えられる。変調光が暗（ロー）の期間でｎ−ｓｗ２信号を発生して切換スイッチ２２を電源ＶＤＤ側に切換えてＰＭＯＳＱ１３を電源ＶＤＤに接続する。このとき、ｎ−ｓｗ１信号は発生しておらず切換スイッチ２１はＰＭＯＳＱ１２をＧＮＤに接続してＰＭＯＳＱ１２への電流の流れを停止する。これにより、ＰＭＯＳＱ１１とＱ１３がカレントミラーとして動作して、変調光が暗い時の光電流に対応する電荷量が第２のコンデンサＣＬに蓄えられる。 The operation of the switch circuit 1 of the third embodiment will be described. Since other operations are the same as those in the first embodiment, only the charge distribution operation by the switch circuit 1 will be described here, and description of other operations will be omitted.
The n-sw1 signal is generated during the period when the modulated light is bright (high), and the changeover switch 21 is switched to the power supply VDD side to connect the PMOS Q12 to the power supply VDD. At this time, the n-sw2 signal is not generated, and the changeover switch 22 connects the PMOS Q13 to the GND to stop the current flow to the PMOS Q13. Thereby, the PMOSs Q11 and Q12 operate as a current mirror, and a charge amount corresponding to the photocurrent when the modulated light is bright is stored in the first capacitor CH. The n-sw2 signal is generated during the period when the modulated light is dark (low), and the changeover switch 22 is switched to the power supply VDD side to connect the PMOS Q13 to the power supply VDD. At this time, the n-sw1 signal is not generated, and the changeover switch 21 connects the PMOS Q12 to GND and stops the current flow to the PMOS Q12. Thereby, the PMOSs Q11 and Q13 operate as a current mirror, and a charge amount corresponding to the photocurrent when the modulated light is dark is stored in the second capacitor CL.

かかるスイッチ回路１の構成によれば、例えばＰＭＯＳＱ１３のゲート端子とフォトダイオードＰＤを結ぶラインに浮遊容量ＣＦが存在する場合、浮遊容量ＣＦにはフォトダイオードＰＤの電圧に応じた電荷が蓄積されるが、浮遊容量ＣＦから第１及び第２のコンデンサＣＨ，ＣＬへの充電経路がなく、浮遊容量ＣＦに蓄えられる電荷が第１及び第２のコンデンサＣＨ，ＣＬに充電されることがない。従って、浮遊容量ＣＦの影響を受けることがなく、変調光の明暗に応じてフォトダイオードＰＤに流れる光電流に対応する電荷量を精度良く蓄積できる。   According to the configuration of the switch circuit 1, for example, when the stray capacitance CF exists on the line connecting the gate terminal of the PMOS Q13 and the photodiode PD, charges corresponding to the voltage of the photodiode PD are accumulated in the stray capacitance CF. There is no charging path from the stray capacitance CF to the first and second capacitors CH and CL, and the charge stored in the stray capacitance CF is not charged to the first and second capacitors CH and CL. Therefore, the amount of charge corresponding to the photocurrent flowing through the photodiode PD can be accumulated with high accuracy without being affected by the stray capacitance CF and depending on the brightness of the modulated light.

次に、本発明の電荷検出装置の第４実施形態について説明する。
第４実施形態は、図６のように切換スイッチ２１,２２を設けた場合のスイッチ回路１の別の構成例である。
図７に、第４実施形態のスイッチ回路１の回路図を示す。尚、第１実施形態と同一要素には同一符号を付して説明を省略する。
図７において、本実施形態のスイッチ回路１は、図６の回路に、３つのＰＭＯＳＱ５１，Ｑ５２，Ｑ５３で構成したカレントミラー回路を新たに追加し、このカレントミラーを、ＰＭＯＳＱ１１，Ｑ１２，Ｑ１３で構成したカレントミラー回路に従続接続する構成とした。 Next, a fourth embodiment of the charge detection device of the present invention will be described.
4th Embodiment is another structural example of the switch circuit 1 at the time of providing the changeover switches 21 and 22 like FIG.
FIG. 7 shows a circuit diagram of the switch circuit 1 of the fourth embodiment. In addition, the same code | symbol is attached | subjected to the same element as 1st Embodiment, and description is abbreviate | omitted.
In FIG. 7, the switch circuit 1 of the present embodiment adds a current mirror circuit composed of three PMOSs Q51, Q52, and Q53 to the circuit of FIG. 6, and this current mirror is composed of PMOSs Q11, Q12, and Q13. The current mirror circuit is configured to be connected continuously.

図６のスイッチ回路１の場合、切換スイッチ２１，２２でＰＭＯＳＱ１２，１３のソース端子を電源ＶＤＤとＧＮＤに切換接続して電圧を変化させるので、電源接続時にソース−ゲート端子間の静電容量の影響を受けてゲート端子の電圧が不安定となり、安定するまでに時間を要し、その間待つ必要がある。第４実施形態のように、カレントミラー回路を従続接続する構成とすれば、ＰＭＯＳＱ５１，Ｑ５２，Ｑ５３で構成したカレントミラー回路については、切換スイッチ２１，２２による電圧変化の影響を受けず、電源接続後、直ちに安定して動作するようになる。また、ＰＭＯＳＱ１２，１３のチャネル長変調効果の影響を抑制する効果もある。
尚、その他の動作は第１実施形態と同様であり説明は省略する。 In the case of the switch circuit 1 in FIG. 6, the source terminals of the PMOSs Q12 and 13 are switched and connected to the power sources VDD and GND by the changeover switches 21 and 22, and the voltage is changed. Due to the influence, the voltage at the gate terminal becomes unstable, and it takes time to stabilize, and it is necessary to wait during that time. If the current mirror circuit is configured to be continuously connected as in the fourth embodiment, the current mirror circuit constituted by the PMOSs Q51, Q52, and Q53 is not affected by the voltage change caused by the changeover switches 21 and 22, and the power supply Immediately after connection, it will operate stably. In addition, there is an effect of suppressing the influence of the channel length modulation effect of the PMOSs Q12 and 13.
Other operations are the same as those in the first embodiment, and a description thereof will be omitted.

次に、本発明の電荷検出装置の第５実施形態について説明する。
第５実施形態も、図６のように切換スイッチ２１,２２を設けた場合のスイッチ回路１の別の構成例である。
図８に、第５実施形態のスイッチ回路１の回路図を示す。尚、第１実施形態と同一要素には同一符号を付して説明を省略する。
図８において、本実施形態のスイッチ回路１は、カレントミラー回路を構成するＰＭＯＳＱ１１のバルク端子を電源に接続して基板バイアスとして電源ＶＤＤを印加し、ＰＭＯＳＱ１２のバルク端子を電圧可変の可変電圧源に接続し基板バイアスとして可変電圧Ｖｃｎｔを印加する構成とする。また、ＰＭＯＳＱ１１がサブスレショールド領域で動作する時の応答性改善のためのオペアンプ２３を設ける。 Next, a fifth embodiment of the charge detection device of the present invention will be described.
The fifth embodiment is another example of the configuration of the switch circuit 1 when the changeover switches 21 and 22 are provided as shown in FIG.
FIG. 8 shows a circuit diagram of the switch circuit 1 of the fifth embodiment. In addition, the same code | symbol is attached | subjected to the same element as 1st Embodiment, and description is abbreviate | omitted.
In FIG. 8, the switch circuit 1 of the present embodiment connects the bulk terminal of the PMOS Q11 constituting the current mirror circuit to the power supply, applies the power supply VDD as a substrate bias, and uses the bulk terminal of the PMOS Q12 as a variable voltage source with variable voltage. The variable voltage Vcnt is applied as a substrate bias. In addition, an operational amplifier 23 is provided for improving the response when the PMOS Q11 operates in the subthreshold region.

前記オペアンプ２３は、フォトダイオードＰＤの電圧Ｖｐを予め定めた設定値である外部バイアス電圧Ｖｉｎｎに保持するようフォトダイオードＰＤの電圧変化に応じてＰＭＯＳＱ１１のゲート端子電圧を可変制御するものである。即ち、フォトダイオードＰＤに流れる光電流Ｉｉｎが変化するとフォトダイオードＰＤの電圧Ｖｐが変化する。オペアンプ２３は、この変化を検出して電圧Ｖｐを外部バイアス電圧Ｖｉｎｎに保持するようにＰＭＯＳＱ１１のゲート端子電圧ＶＧ（オペアンプの出力）を制御する。これにより、フォトダイオードＰＤの電圧Ｖｐは外部バイアス電圧Ｖｉｎｎに一定に維持され、オペアンプ２３の出力ＶＧはフォトダイオードＰＤに流れる光電流の変化に応じて変化し、前記光電流に応じた電圧値となる。   The operational amplifier 23 variably controls the gate terminal voltage of the PMOS Q11 in accordance with a change in the voltage of the photodiode PD so that the voltage Vp of the photodiode PD is held at an external bias voltage Vinn which is a predetermined set value. That is, when the photocurrent Iin flowing through the photodiode PD changes, the voltage Vp of the photodiode PD changes. The operational amplifier 23 detects this change and controls the gate terminal voltage VG (output of the operational amplifier) of the PMOS Q11 so that the voltage Vp is held at the external bias voltage Vinn. As a result, the voltage Vp of the photodiode PD is kept constant at the external bias voltage Vinn, and the output VG of the operational amplifier 23 changes according to the change of the photocurrent flowing through the photodiode PD, and the voltage value corresponding to the photocurrent is Become.

次に、図８のスイッチ回路１の動作を説明する。尚、その他の動作は第１実施形態と同様であり、ここではスイッチ回路の動作のみを説明し、その他の動作については説明を省略する。
変調光が明（ハイ）の期間でｎ−ｓｗ１信号を発生して切換スイッチ２１を電源ＶＤＤ側に切換えてＰＭＯＳＱ１２を電源ＶＤＤに接続し、切換スイッチ２２はＰＭＯＳＱ１３をＧＮＤに接続する。これにより、ＰＭＯＳＱ１１とＱ１２がカレントミラーとして動作し、変調光が明るい時の光電流に対応するオペアンプ２３の出力電圧ＶＧと電源ＶＤＤとの電位差に応じた電流がＰＭＯＳＱ１２に流れ、変調光が明るい時の光電流に対応する電荷量が第１のコンデンサＣＨに蓄えられる。変調光が暗（ロー）の期間ではｎ−ｓｗ２信号を発生して切換スイッチ２２を電源ＶＤＤ側に切換えてＰＭＯＳＱ１３を電源ＶＤＤに接続し、切換スイッチ２１はＰＭＯＳＱ１２をＧＮＤに接続する。これにより、ＰＭＯＳＱ１１とＱ１３がカレントミラーとして動作し、変調光が暗い時の光電流に対応するオペアンプ２３の出力電圧ＶＧと電源ＶＤＤとの電位差に応じた電流がＰＭＯＳＱ１３に流れ、変調光が暗い時の光電流に対応する電荷量が第２のコンデンサＣＬに蓄えられる。 Next, the operation of the switch circuit 1 in FIG. 8 will be described. The other operations are the same as those in the first embodiment, and only the operation of the switch circuit will be described here, and the description of the other operations will be omitted.
The n-sw1 signal is generated during the period when the modulated light is bright (high), the changeover switch 21 is switched to the power supply VDD side to connect the PMOSQ12 to the power supply VDD, and the changeover switch 22 connects the PMOSQ13 to GND. Thereby, the PMOSs Q11 and Q12 operate as a current mirror, and a current corresponding to the potential difference between the output voltage VG of the operational amplifier 23 and the power supply VDD corresponding to the photocurrent when the modulated light is bright flows to the PMOS Q12, and the modulated light is bright The charge amount corresponding to the photocurrent is stored in the first capacitor CH. During the period when the modulated light is dark (low), an n-sw2 signal is generated to switch the changeover switch 22 to the power supply VDD side to connect the PMOSQ13 to the power supply VDD, and the changeover switch 21 connects the PMOSQ12 to GND. Thereby, the PMOSs Q11 and Q13 operate as a current mirror, and a current corresponding to the potential difference between the output voltage VG of the operational amplifier 23 and the power supply VDD corresponding to the photocurrent when the modulated light is dark flows to the PMOS Q13, and the modulated light is dark The charge amount corresponding to the photocurrent is stored in the second capacitor CL.

尚、コンデンサＣＨの蓄積電荷量に対応する電圧ＶＣＨやコンデンサＣＬの蓄積電荷量に対応する電圧ＶＣＬが、電圧ＶＧより高電位になると、ＰＭＯＳＱ１２やＰＭＯＳＱ１３のソース端子をＧＮＤに接続したときに、コンデンサＣＨ，ＣＬ側からＰＭＯＳＱ１２やＰＭＯＳＱ１３を介して電荷が放電する。この放電を防止するため、ＰＭＯＳＱ１２とコンデンサＣＨとの間及びＰＭＯＳＱ１３とコンデンサＣＬとの間に、逆流防止用ダイオード２４，２５をそれぞれ設けてある。   When the voltage VCH corresponding to the amount of charge stored in the capacitor CH or the voltage VCL corresponding to the amount of charge stored in the capacitor CL becomes higher than the voltage VG, the capacitor Q2 and the PMOS Q13 are connected to GND when the source terminals of the PMOS Q12 and PMOS Q13 are connected. Electric charges are discharged from the CH and CL sides via the PMOS Q12 and the PMOS Q13. In order to prevent this discharge, backflow prevention diodes 24 and 25 are provided between the PMOS Q12 and the capacitor CH and between the PMOS Q13 and the capacitor CL, respectively.

かかる構成では、ＰＭＯＳＱ１２，１３をサブスレショールド領域で動作するよう構成すると、電流利得を可変の基板バイアス電圧Ｖｃｎｔに応じて変化させることができる。従って、フォトダイオードＰＤの検出する光量に応じて基板バイアス電圧Ｖｃｎｔを調整して電流利得を調整することで、微弱光から強い光まで広範囲の光量検出が可能である。   In such a configuration, when the PMOSs Q12 and 13 are configured to operate in the subthreshold region, the current gain can be changed according to the variable substrate bias voltage Vcnt. Therefore, by adjusting the substrate gain voltage Vcnt in accordance with the light amount detected by the photodiode PD and adjusting the current gain, it is possible to detect the light amount in a wide range from weak light to strong light.

次に、本発明の電荷検出装置を適用した物体検出装置について説明する。
図９は、物体検出装置の概略構成図を示す。
図９において、物体検出装置は、多数のフォトダイオードＰＤを備え、各フォトダイオードＰＤ毎に上述した本発明の電荷検出装置を組込んだイメージセンサ１１と、変調光源１２と、イメージセンサ１１からの画像データに基づいて予め取得した背景画像データと現在の画像データとの差分から背景差分法を用いて物体の有無を判定する画像データ処理部１３と、これらイメージセンサ１１、変調光源１２及び画像データ処理部１３を統括的に制御する制御部１４とを備えて構成される。尚、図中の背景光は、太陽光や照明光等を意味する。 Next, an object detection apparatus to which the charge detection apparatus of the present invention is applied will be described.
FIG. 9 shows a schematic configuration diagram of the object detection apparatus.
In FIG. 9, the object detection device includes a large number of photodiodes PD, and each of the photodiodes PD incorporates the above-described charge detection device of the present invention, the modulation light source 12, and the image sensor 11. An image data processing unit 13 for determining the presence or absence of an object using a background difference method from a difference between background image data acquired in advance based on image data and current image data, and these image sensor 11, modulated light source 12, and image data And a control unit 14 that comprehensively controls the processing unit 13. In addition, the background light in a figure means sunlight, illumination light, etc.

制御部１４は、変調光源１２に例えばパルス状の変調信号を出力して変調光源１２から変調光を発生させる。また、前述のようにして前記変調信号に同期させて電荷検出装置を駆動し、変調信号が明るい時と暗い時の電荷量の差分を各フォトダイオードＰＤに対応するコンデンサＣＨに蓄積させて画像データを取得する。更に、所定の時間間隔でイメージセンサ１１から画像データを画像データ処理部１３に出力させる。
画像データ処理部１３は、物体１５の存在しない予め取得した背景画像データと現状の画像データを比較して変化の有無により物体１５の存在の有無を判定する。 The control unit 14 generates a modulated light from the modulated light source 12 by outputting, for example, a pulsed modulated signal to the modulated light source 12. Further, as described above, the charge detection device is driven in synchronization with the modulation signal, and the difference in the amount of charge when the modulation signal is bright and dark is accumulated in the capacitor CH corresponding to each photodiode PD to obtain image data. To get. Further, the image data is output from the image sensor 11 to the image data processing unit 13 at a predetermined time interval.
The image data processing unit 13 compares the background image data acquired in advance without the object 15 with the current image data, and determines the presence or absence of the object 15 based on the presence or absence of the change.

本実施形態の物体検出装置の動作を図１０に基づいて詳述する。
図１０において、ｋフレームを基準フレームとし、（ｋ＋ｍ）フレームでは背景光がＢ１からＢ２に変化し、（ｋ＋ｎ）フレームでは物体１５の存在により反射率がＲ１からＲ２に変化したとする。検出対象領域に変調光源１２から、図１０に示すような例えばパルス状のＭ１、Ｍ２の２値の変調光を照射する。尚、変調光を点滅させてＭ２が０となる場合も含む。この場合、イメージセンサ１１の各フォトダイオードＰＤに入力する反射光は変調光に同期して変化する。ここで、図に示すように、ｋフレームの反射光をＲ１（Ｍ１＋Ｂ１）とＲ１（Ｍ２＋Ｂ１）とし、（ｋ＋ｍ）フレームの反射光をＲ１（Ｍ１＋Ｂ２）とＲ１（Ｍ２＋Ｂ２）とし、（ｋ＋ｎ）フレームの反射光をＲ２（Ｍ１＋Ｂ２）とＲ２（Ｍ２＋Ｂ２）とする。 The operation of the object detection apparatus of this embodiment will be described in detail with reference to FIG.
In FIG. 10, it is assumed that the k frame is a reference frame, the background light changes from B1 to B2 in the (k + m) frame, and the reflectance changes from R1 to R2 due to the presence of the object 15 in the (k + n) frame. For example, pulsed M1 and M2 binary modulated light as shown in FIG. 10 is irradiated from the modulated light source 12 to the detection target region. In addition, the case where M2 becomes 0 by blinking the modulated light is included. In this case, the reflected light input to each photodiode PD of the image sensor 11 changes in synchronization with the modulated light. Here, as shown in the figure, the reflected light of the k frame is R1 (M1 + B1) and R1 (M2 + B1), the reflected light of the (k + m) frame is R1 (M1 + B2) and R1 (M2 + B2), and the (k + n) frame is reflected. The reflected light is R2 (M1 + B2) and R2 (M2 + B2).

そして、変調光の明暗に同期させて、上述した本発明の電荷検出装置により、変調光の明るい時（Ｍ１）にフォトダイオードＰＤで生じる光電流ＩｉｎをコンデンサＣＨに、暗い時（Ｍ２）の光電流ＩｉｎをコンデンサＣＬに供給し、図１０に示すように、各コンデンサＣＨ，ＣＬそれぞれに電荷を蓄える。ここで、各フレームにおけるそれぞれのコンデンサＣＨ，ＣＬの電圧（蓄積電荷量に相当する）を、ｋフレームはＡＲ１（Ｍ１＋Ｂ１）、ＡＲ１（Ｍ２＋Ｂ１）とし、（ｋ＋ｍ）フレームはＡＲ１（Ｍ１＋Ｂ２）、ＡＲ１（Ｍ２＋Ｂ２）とし、（ｋ＋ｎ）フレームはＡＲ２（Ｍ１＋Ｂ２）、ＡＲ２（Ｍ２＋Ｂ２）とする。尚、ＡはフォトダイオードＰＤの光電変換効率等により決定される定数である。   Then, in synchronization with the brightness of the modulated light, the above-described charge detection device of the present invention causes the photocurrent Iin generated in the photodiode PD when the modulated light is bright (M1) to the capacitor CH, and the light when dark (M2). The current Iin is supplied to the capacitor CL, and charges are stored in the capacitors CH and CL as shown in FIG. Here, the voltages of the capacitors CH and CL (corresponding to the accumulated charge amount) in each frame are AR1 (M1 + B1) and AR1 (M2 + B1) in the k frame, and AR1 (M1 + B2) and AR1 (in the (k + m) frame). M2 + B2), and (k + n) frames are AR2 (M1 + B2) and AR2 (M2 + B2). A is a constant determined by the photoelectric conversion efficiency of the photodiode PD.

その後、コンデンサＣＨに蓄えた電荷量からコンデンサＣＬに蓄えた電荷量を減算して両者の差分をとる。この場合、ｋフレームと（ｋ＋ｍ）フレームの差分値は、ＡＲ１（Ｍ１−Ｍ２）となり、（ｋ＋ｎ）フレームの差分値は、ＡＲ２（Ｍ１−Ｍ２）となり、背景光Ｂ１，Ｂ２の影響を排除できることがわかる。また、（ｋ＋ｍ）フレームでは背景光が変化しているが反射率が変化しないため、変調光の明暗によるｋフレームと（ｋ＋ｍ）フレームの差分値は等しい。一方、（ｋ＋ｎ）フレームでは物体１５の存在により反射率が変化するため、変調光の明暗による差分値は、ｋフレームや（ｋ＋ｍ）フレームの差分値と比べて変化することがわかる。   Thereafter, the charge amount stored in the capacitor CL is subtracted from the charge amount stored in the capacitor CH to obtain a difference between the two. In this case, the difference value between the k frame and the (k + m) frame is AR1 (M1-M2), and the difference value between the (k + n) frames is AR2 (M1-M2), so that the influence of the background lights B1 and B2 can be eliminated. I understand. In addition, since the background light changes in the (k + m) frame, but the reflectance does not change, the difference value between the k frame and the (k + m) frame due to the brightness of the modulated light is equal. On the other hand, in the (k + n) frame, since the reflectance changes due to the presence of the object 15, it can be seen that the difference value due to the brightness of the modulated light changes compared to the difference value of the k frame or (k + m) frame.

従って、予め基準フレームの差分値を取得し、この基準フレームの差分値と逐次取得した差分値とを比較し、その差が予め定めた閾値以上であれば物体１５が存在すると判定できる。これにより、背景光の変化の影響を排除して物体の検出ができる。そして、本発明の電荷検出装置を用いて前記差分値を蓄積することで、増大した差分値で比較することができる。従って、変調光によりフォトダイオードＰＤの光電流Ｉｉｎが小さくても精度良く物体を検出することが可能となる。   Accordingly, the difference value of the reference frame is acquired in advance, the difference value of the reference frame is compared with the sequentially acquired difference value, and it can be determined that the object 15 exists if the difference is equal to or greater than a predetermined threshold value. As a result, the object can be detected while eliminating the influence of changes in the background light. Then, by storing the difference value using the charge detection device of the present invention, it is possible to compare with the increased difference value. Therefore, even if the photocurrent Iin of the photodiode PD is small due to the modulated light, the object can be detected with high accuracy.

図１０では、フレーム毎に電荷の差分蓄積動作を行う例を示したが、図１１に示すように、各フレームの途中で差分蓄積動作を行うようにしてもよい。図１１は、フレーム途中で電荷検出装置を動作させた場合の光量に応じた蓄積過程の様子を示し、上から光量が大、中、小の場合のコンデンサＣＨ、コンデンサＣＬの電荷蓄積の様子を示す。所定のリセットタイミング時にコンデンサＣＨの電荷量と閾値Ｖｔｈとの比較を行い、コンデンサＣＨの電荷量が閾値Ｖｔｈ以上の場合は減算動作を実行し、コンデンサＣＬの電荷量と同量の電荷量を両コンデンサＣＨ，ＣＬから減算する。コンデンサＣＨの電荷量が閾値Ｖｔｈ未満であればそのまま蓄積動作を継続する。   Although FIG. 10 shows an example in which the charge difference accumulation operation is performed for each frame, the difference accumulation operation may be performed in the middle of each frame as shown in FIG. FIG. 11 shows the state of the accumulation process according to the amount of light when the charge detection device is operated in the middle of the frame. The state of charge accumulation in the capacitors CH and CL when the amount of light is large, medium, and small from above is shown. Show. The charge amount of the capacitor CH is compared with the threshold value Vth at a predetermined reset timing. If the charge amount of the capacitor CH is equal to or greater than the threshold value Vth, a subtraction operation is executed, and the same charge amount as that of the capacitor CL is obtained. Subtract from capacitors CH and CL. If the charge amount of the capacitor CH is less than the threshold value Vth, the accumulation operation is continued as it is.

尚、変調光の明暗を高速で切替えることにより背景光の緩やかな変化を無視することができ、物体検出の精度をより一層向上させることができる。
また、上記の各実施形態では、フォトダイオードＰＤがＧＮＤに接続している場合の構成例を示したが、フォトダイオードＰＤが電源ＶＤＤに接続している場合でも、ＮＭＯＳトランジスタとＰＯＭＳトランジスタを逆にした相補な回路構成で、同様の効果が実現可能である。 It should be noted that a gradual change in background light can be ignored by switching the brightness of the modulated light at high speed, and the accuracy of object detection can be further improved.
In each of the above embodiments, the configuration example in which the photodiode PD is connected to the GND is shown. However, even when the photodiode PD is connected to the power supply VDD, the NMOS transistor and the POMS transistor are reversed. The same effect can be realized with the complementary circuit configuration.

本発明に係る電荷検出装置の第１実施形態を示す概略構成図1 is a schematic configuration diagram showing a first embodiment of a charge detection device according to the present invention. 同上実施形態の具体的回路図Specific circuit diagram of the embodiment 図２の回路を２次元アレイに組込んだ例を示す回路図Circuit diagram showing an example of incorporating the circuit of FIG. 2 into a two-dimensional array 図２の回路図の動作タイムチャートOperation time chart of the circuit diagram of FIG. 本発明に係る電荷検出装置の第２実施形態を示す概略構成図Schematic configuration diagram showing a second embodiment of a charge detection device according to the present invention. 本発明に係る電荷検出装置の第３実施形態の要部を示すスイッチ回路図Switch circuit diagram showing the main part of a third embodiment of the charge detection device according to the present invention 本発明に係る電荷検出装置の第４実施形態の要部を示すスイッチ回路図Switch circuit diagram showing the main part of a fourth embodiment of the charge detection device according to the present invention 本発明に係る電荷検出装置の第５実施形態の要部を示すスイッチ回路図Switch circuit diagram showing the main part of a fifth embodiment of the charge detection device according to the present invention 電荷検出装置を適用した物体検出装置の概略図Schematic diagram of an object detection device to which a charge detection device is applied 図９の物体検出装置の動作説明図Operation explanatory diagram of the object detection apparatus of FIG. フレーム途中で差分蓄積動作する場合のコンデンサの電荷蓄積過程の様子を示す図The figure which shows the mode of the electric charge accumulation process of the capacitor when differential accumulation operation is performed in the middle of the frame 従来例を示す回路図Circuit diagram showing a conventional example

符号の説明Explanation of symbols

１ スイッチ回路
２ 差分蓄積回路
３ 電流源
４ 制御回路
５ 比較回路
１１ イメージセンサ
１２ 変調光源
１３ 画像データ処理部
１４ 制御部
１５ 物体
２１，２２ 切換スイッチ
２３ オペアンプ
ＣＨ 第１のコンデンサ
ＣＬ 第２のコンデンサ
ＰＤ フォトダイオード DESCRIPTION OF SYMBOLS 1 Switch circuit 2 Difference accumulation circuit 3 Current source 4 Control circuit 5 Comparison circuit 11 Image sensor 12 Modulation light source 13 Image data processing part 14 Control part 15 Object 21, 22 Changeover switch 23 Operational amplifier CH 1st capacitor CL 2nd capacitor PD Photodiode

Claims (11)

変調した光の明暗に同期してイメージセンサ内の受光素子で生じる光電流をそれぞれ第１及び第２のコンデンサに振り分けて供給し、前記光電流に基づいて前記第１のコンデンサに蓄えられる電荷量と前記第２のコンデンサに蓄えられる電荷量の差分を蓄積する構成としたことを特徴とする電荷検出装置。   The photocurrent generated in the light receiving element in the image sensor in synchronization with the brightness of the modulated light is distributed and supplied to the first and second capacitors, respectively, and the amount of charge stored in the first capacitor based on the photocurrent And a charge detection device, wherein the difference between the charge amounts stored in the second capacitor is stored. 前記光電流の振り分けを複数回繰返し、前記第１及び第２のコンデンサに前記光電流に基づく電荷をそれぞれ蓄積した後に、これら蓄積電荷量の差分を蓄積する構成とした請求項１に記載の電荷検出装置。   2. The charge according to claim 1, wherein the photocurrent distribution is repeated a plurality of times, and the charge based on the photocurrent is accumulated in the first and second capacitors, respectively, and then the difference between the accumulated charge amounts is accumulated. Detection device. 前記変調光の明暗に同期してスイッチングし、前記受光素子で生じる光電流を前記第１のコンデンサと第２のコンデンサに振り分けて供給するスイッチ手段と、
前記第１のコンデンサに蓄えられる電荷量から前記第２のコンデンサに蓄えられる電荷量を減算してその差分を蓄積させる差分蓄積手段と、を備え、
前記変調光の明暗に同期させて前記スイッチ手段を駆動制御し、所定タイミングで前記差分蓄積手段を駆動させる構成とした請求項１又は２に記載の電荷検出装置。 Switching means that switches in synchronization with the brightness of the modulated light, and distributes and supplies the photocurrent generated in the light receiving element to the first capacitor and the second capacitor;
Difference accumulation means for subtracting the amount of charge stored in the second capacitor from the amount of charge stored in the first capacitor and storing the difference;
3. The charge detection device according to claim 1, wherein the switch unit is driven and controlled in synchronization with light and darkness of the modulated light, and the difference accumulation unit is driven at a predetermined timing. 蓄えられる電荷量の多い前記第１のコンデンサの電荷量を検出し、検出電荷量を予め定めた閾値と比較して検出電荷量が閾値以上になった時に、前記差分蓄積手段を駆動させる駆動指令を発生する比較手段を備える構成とした請求項３に記載の電荷検出装置。   A drive command for detecting the charge amount of the first capacitor having a large amount of stored charge and driving the difference accumulation means when the detected charge amount is equal to or greater than a threshold value by comparing the detected charge amount with a predetermined threshold value. The charge detection device according to claim 3, wherein the charge detection device is configured to include a comparison unit that generates a voltage. 前記差分蓄積手段は、蓄えられる電荷量の少ない前記第２のコンデンサを基準とし、前記駆動指令に基づいてカレントミラー回路を駆動し、前記第１及び第２のコンデンサから同量の電荷量を放電させて前記第１のコンデンサに前記差分を残存させる構成であり、前記差分蓄積手段を繰返し動作させて前記第１のコンデンサに前記差分を蓄積する構成とした請求項３又は４に記載の電荷検出装置。   The differential accumulation means drives the current mirror circuit based on the drive command based on the second capacitor with a small amount of stored charge, and discharges the same amount of charge from the first and second capacitors. 5. The charge detection according to claim 3, wherein the difference is caused to remain in the first capacitor, and the difference accumulation unit is repeatedly operated to accumulate the difference in the first capacitor. 6. apparatus. 前記スイッチ手段は、前記受光素子で生じる光電流を前記第１及び第２のコンデンサにそれぞれ振り分けるためのカレントミラー回路と、該カレントミラー回路で振り分けた光電流を前記変調光の明暗に同期してスイッチングし第１及び第２コンデンサにそれぞれ供給するためのスイッチ部とを備える構成とした請求項３〜５のいずれか１つに記載の電荷検出装置。   The switch means includes a current mirror circuit for distributing the photocurrent generated in the light receiving element to the first and second capacitors, and the photocurrent distributed by the current mirror circuit in synchronization with the brightness of the modulated light. 6. The charge detection device according to claim 3, further comprising: a switch unit that performs switching and supplies the first and second capacitors to each of them. 前記カレントミラー回路は、電源と前記受光素子の間に直列に接続しゲート端子が前記受光素子に接続し前記受光素子で生じる前記光電流が流れる第１ＭＯＳトランジスタと、電源と前記第１のコンデンサの間に直列に介装しゲート端子が前記第１ＭＯＳトランジスタのゲート端子に接続し前記スイッチ部のスイッチング動作に同期して変調光が明るい時の前記光電流に対応する出力電流が流れる第２ＭＯＳトランジスタと、電源と前記第２のコンデンサの間に直列に介装しゲート端子が前記第１ＭＯＳトランジスタのゲート端子に接続し前記スイッチ部のスイッチング動作に同期して変調光が暗い時の前記光電流に対応する出力電流が流れる第３ＭＯＳトランジスタと、を備える構成である請求項６に記載の電荷検出装置。   The current mirror circuit includes a first MOS transistor connected in series between a power source and the light receiving element, a gate terminal connected to the light receiving element, and the photocurrent generated in the light receiving element flowing therethrough; a power source and a first capacitor; A second MOS transistor having a gate terminal connected in series between the gate terminal of the first MOS transistor and an output current corresponding to the photocurrent when the modulated light is bright in synchronization with the switching operation of the switch unit; The gate terminal is connected in series between the power source and the second capacitor, and the gate terminal is connected to the gate terminal of the first MOS transistor, so that the photocurrent when the modulated light is dark is synchronized with the switching operation of the switch unit. The charge detection device according to claim 6, further comprising: a third MOS transistor through which an output current flows. 前記スイッチ部は、前記電源と前記第２ＭＯＳトランジスタの間に介装され変調光が明るい期間に駆動信号の入力で前記第２ＭＯＳトランジスタを電源に接続し駆動信号の停止で前記第２ＭＯＳトランジスタをＧＮＤに切換接続する第１切換スイッチと、前記電源と前記第３ＭＯＳトランジスタの間に介装され変調光が暗い期間に駆動信号の入力で前記第３ＭＯＳトランジスタを電源に接続し駆動信号の停止で前記第３ＭＯＳトランジスタをＧＮＤに切換接続する第２切換スイッチと、を備えて構成した請求項７に記載の電荷検出装置。   The switch unit is interposed between the power source and the second MOS transistor, connects the second MOS transistor to the power source when a drive signal is input during a period when the modulated light is bright, and turns the second MOS transistor to GND when the drive signal is stopped. A first changeover switch connected between the power supply and the third MOS transistor, and the third MOS transistor is connected to the power supply by input of a drive signal during a period when the modulated light is dark, and the third MOS is turned off by stopping the drive signal. The charge detection device according to claim 7, further comprising: a second changeover switch for switchingly connecting the transistor to GND. 前記カレントミラー回路を、前記第１ＭＯＳトランジスタのバルク端子を電源に接続し、前記第２及び第３ＭＯＳトランジスタのバルク端子を、それぞれ電圧が可変できる可変電圧源に接続する構成とすると共に、前記受光素子の電圧を予め定めた設定値に保持するよう前記受光素子の電圧変化に応じて第１ＭＯＳトランジスタのゲート端子電圧を可変制御するオペアンプを、前記スイッチ手段に設ける構成とした請求項７又は８に記載の電荷検出装置。   The current mirror circuit has a configuration in which a bulk terminal of the first MOS transistor is connected to a power source, and a bulk terminal of each of the second and third MOS transistors is connected to a variable voltage source capable of varying a voltage. 9. The operational amplifier for variably controlling the gate terminal voltage of the first MOS transistor in accordance with a change in voltage of the light receiving element so as to hold the voltage at a predetermined setting value is provided in the switch means. Charge detection device. 前記受光素子で生じる前記光電流にオフセット電流を付加する構成とした請求項１〜９のいずれか１つに記載の電荷検出装置。   The charge detection device according to claim 1, wherein an offset current is added to the photocurrent generated in the light receiving element. 多数の受光素子からなるイメージセンサからの画像データに基づいて、予め取得した背景画像データと現在の画像データとの差分から物体を検出する背景差分法を利用する物体検出装置に適用したことを特徴とする請求項１〜１０のいずれか１つに記載の電荷検出装置。   The present invention is applied to an object detection apparatus that uses a background difference method for detecting an object from a difference between background image data acquired in advance and current image data based on image data from an image sensor including a large number of light receiving elements. The charge detection device according to any one of claims 1 to 10.
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KR20160130938A (en) * 2014-03-06 2016-11-15 파나소닉 인텔렉츄얼 프로퍼티 코포레이션 오브 아메리카 Measurement system, measurement method and vision chip
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