JP2008124248A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2008124248A
JP2008124248A JP2006306393A JP2006306393A JP2008124248A JP 2008124248 A JP2008124248 A JP 2008124248A JP 2006306393 A JP2006306393 A JP 2006306393A JP 2006306393 A JP2006306393 A JP 2006306393A JP 2008124248 A JP2008124248 A JP 2008124248A
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Japan
Prior art keywords
organic wiring
semiconductor chip
support plate
semiconductor device
wiring substrate
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JP2006306393A
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Japanese (ja)
Inventor
Atsushi Onohara
淳 小野原
Kiyotomo Nakamura
清智 中村
Takamasa Okuma
隆正 大熊
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Toppan Inc
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Toppan Printing Co Ltd
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Priority to JP2006306393A priority Critical patent/JP2008124248A/en
Publication of JP2008124248A publication Critical patent/JP2008124248A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To correct warp generated when a semiconductor chip is subjected to flip chip mounting on an organic wiring substrate. <P>SOLUTION: A semiconductor device is manufactured, which has an organic wiring substrate with a first major surface and a second major surface, a supporting plate with a first major surface and a second major surface and a semiconductor chip. The first major surface of the organic wiring substrate and the second major surface of the supporting plate are adhered, the organic wiring substrate has a first external connection terminal and a second external connection terminal in the second major surface, the semiconductor chip is connected to the first external connection terminal, the semiconductor chip and the organic wiring substrate are adhered by means of an underfill resin layer and the first major surface of the supporting plate has a rib skeleton structure. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体チップを上面搭載した有機配線基板の下面に金属板が設けられた半導体装置に関する。また、その金属板により放熱性と剛性を向上するのに適した半導体装置に関する。   The present invention relates to a semiconductor device in which a metal plate is provided on the lower surface of an organic wiring board on which a semiconductor chip is mounted. The present invention also relates to a semiconductor device suitable for improving heat dissipation and rigidity by the metal plate.

図３により、従来の半導体装置で、半導体チップ１を有機配線基板２の上面に搭載し有機配線基板２の下面に金属板３を設置した半導体装置を説明する。図３は、金属板３を有する半導体装置であって有機配線基板２に半導体チップ１をフリップチップ実装した半導体装置を示す側面断面図である。図３に示すように、半導体チップ１の機能面に例えば半田からなるバンプ５が設置され、とそれが有機配線基板２のランドに電気的に接続されている。この接続は、例えば半導体チップ１の側のパットの上にバンプ５を設置し、また、有機配線基板２の上面にこのバンプ５に位置を合わせてランドを設ける。そして、そのランドに例えばボンディング技術を適用してバンプ５接続し、その半導体チップ１と有機配線基板２の間に樹脂を注入して、アンダーフィル樹脂層６を形成し、それにより両者を接着するものである。バンプ５に接続された有機配線基板２上のランドは、配線パターンやビア等によりボールランドと電気的に接続されている。有機配線基板２は、例えば、ポリイミドのようなフレキシブルな材質、ガラスエポキシ樹脂のようなリジッドな材質いずれも用いられている。また、ボールランドには、図示するように、半田ボール７が形成され、これを溶融することによりさらに別の基板に実装され得られるものである。さらに、半導体チップ１と有機配線基板２との空間には、半導体チップ１の機能面を大気や湿り気から遮断し化学的変質を防止し信頼性を確保するように、充填樹脂が充填されている。また、有機配線基板２の裏面には例えば銅を主とする金属板が、接着樹脂を介して接続されている。金属板を設けて得られる機能には、半導体チップ１の放熱、有機配線基板２および半導体チップ１の反り矯正などがある。   A semiconductor device in which a semiconductor chip 1 is mounted on the upper surface of an organic wiring substrate 2 and a metal plate 3 is installed on the lower surface of the organic wiring substrate 2 will be described with reference to FIG. FIG. 3 is a side cross-sectional view showing a semiconductor device having a metal plate 3 in which the semiconductor chip 1 is flip-chip mounted on the organic wiring board 2. As shown in FIG. 3, bumps 5 made of, for example, solder are provided on the functional surface of the semiconductor chip 1, and are electrically connected to the lands of the organic wiring substrate 2. For this connection, for example, bumps 5 are provided on a pad on the semiconductor chip 1 side, and lands are provided on the upper surface of the organic wiring substrate 2 so as to be aligned with the bumps 5. Then, for example, a bonding technique is applied to the land to connect the bump 5, and a resin is injected between the semiconductor chip 1 and the organic wiring substrate 2 to form an underfill resin layer 6, thereby bonding them together. Is. The land on the organic wiring board 2 connected to the bump 5 is electrically connected to the ball land by a wiring pattern, a via or the like. The organic wiring substrate 2 is made of, for example, a flexible material such as polyimide or a rigid material such as glass epoxy resin. Also, as shown in the figure, solder balls 7 are formed on the ball lands, and can be mounted on another substrate by melting them. Further, the space between the semiconductor chip 1 and the organic wiring substrate 2 is filled with a filling resin so as to block the functional surface of the semiconductor chip 1 from the atmosphere and moisture to prevent chemical deterioration and to ensure reliability. . In addition, a metal plate mainly made of copper, for example, is connected to the back surface of the organic wiring board 2 via an adhesive resin. Functions obtained by providing the metal plate include heat dissipation of the semiconductor chip 1, warpage correction of the organic wiring substrate 2 and the semiconductor chip 1, and the like.

上記のような半導体実装における金属板の機能について、有機配線基板２および半導体チップ１の反り矯正、半導体チップ１の応力緩和を目的として、特許文献１では、前記半導体チップ１と熱膨張係数が近い金属板を用いて半導体チップ１による反りを矯正している。また、半導体チップ１の放熱のため良好な熱伝導率を有する金属板を用いている。特許文献２では、裏面に電子部品と金属板を用いている。   Regarding the function of the metal plate in the semiconductor mounting as described above, in Patent Document 1, the thermal expansion coefficient is close to that of the semiconductor chip 1 for the purpose of correcting the warp of the organic wiring substrate 2 and the semiconductor chip 1 and relieving the stress of the semiconductor chip 1. The warp due to the semiconductor chip 1 is corrected using a metal plate. Further, a metal plate having good thermal conductivity is used for heat dissipation of the semiconductor chip 1. In Patent Document 2, an electronic component and a metal plate are used on the back surface.

以下に公知文献を記す。
特開２００１−１５６２４６号公報 特開平６−２０４６５４号公報 The known literature is described below.
JP 2001-156246 A JP-A-6-204654

しかし、特許文献１のように半導体チップ１と同じ大きさの金属板３を有機配線基板２に設置するのみでは、有機配線基板２上に半導体チップ１をフリップチップ実装した場合に生じる反り矯正が不十分である問題があり、また、金属板の表面が平らで放熱性が不十分である問題があった。また、特許文献２では、２つの部品を貼り付ける必要があり工数がかかり不便である問題があった。本発明は、このような従来の技術が有する課題を解決するために提案されたものであり、半導体チップ１を有機配線基板２にフリップチップ実装した場合に発生する反りを矯正し、また、半導体チップ１からの発熱を低減することができる半導体装置を得ることを課題とする。   However, if only the metal plate 3 having the same size as the semiconductor chip 1 is installed on the organic wiring board 2 as in Patent Document 1, the warp correction that occurs when the semiconductor chip 1 is flip-chip mounted on the organic wiring board 2 is corrected. There is a problem that it is insufficient, and there is a problem that the surface of the metal plate is flat and heat dissipation is insufficient. Further, in Patent Document 2, there is a problem in that two parts need to be pasted, which requires man-hours and is inconvenient. The present invention has been proposed in order to solve the above-described problems of the prior art, and corrects the warp that occurs when the semiconductor chip 1 is flip-chip mounted on the organic wiring substrate 2. An object is to obtain a semiconductor device capable of reducing heat generation from the chip 1.

本発明は、この課題を解決するために、第一主面と第二主面を備える有機配線基板と、第一主面と第二主面を備える支持板と、半導体チップとを備え、前記有機配線基板の第一主面と前記支持板の第二主面は接着され、前記有機配線基板は第二主面に第一の外部接続端子と第二の外部接続端子を備え、前記半導体チップは前記第一の外部接続端子に接続され、前記半導体チップと前記有機配線基板をアンダーフィル樹脂層で接着し、前記支持板の第一主面にリブ骨格構造を備えたことを特徴とする半導体装置である。   In order to solve this problem, the present invention includes an organic wiring board having a first main surface and a second main surface, a support plate having a first main surface and a second main surface, and a semiconductor chip, The first main surface of the organic wiring board and the second main surface of the support plate are bonded, and the organic wiring board includes a first external connection terminal and a second external connection terminal on the second main surface, and the semiconductor chip Is connected to the first external connection terminal, the semiconductor chip and the organic wiring board are bonded with an underfill resin layer, and the first main surface of the support plate has a rib skeleton structure. Device.

また、本発明は、上記支持板が金属板であり、上記支持板と上記半導体チップの熱膨張係数はいずれも上記有機配線基板の熱膨張係数よりも小さいことを特徴とする上記の半導体装置である。   Further, the present invention provides the above semiconductor device, wherein the support plate is a metal plate, and the thermal expansion coefficient of the support plate and the semiconductor chip is smaller than the thermal expansion coefficient of the organic wiring substrate. is there.

また、本発明は、上記支持板は第一主面に前記支持板の外周を囲む枠状の上記リブ骨格構造を備えることを特徴とする上記の半導体装置である。   The present invention is the above-described semiconductor device, wherein the support plate includes a frame-shaped rib skeleton structure surrounding an outer periphery of the support plate on a first main surface.

また、本発明は、上記支持板と上記有機配線基板は接着剤層を介して接着され、当該接着剤層の熱膨張係数は前記支持板よりも大きく前記有機配線基板よりも小さいことを特徴とする上記の半導体装置である。   Further, the present invention is characterized in that the support plate and the organic wiring substrate are bonded via an adhesive layer, and the thermal expansion coefficient of the adhesive layer is larger than the support plate and smaller than the organic wiring substrate. The semiconductor device described above.

また、本発明は、上記有機配線基板は厚さが０．３ｍｍ以下であることを特徴とする上記の半導体装置である。   The present invention is the above semiconductor device, wherein the organic wiring board has a thickness of 0.3 mm or less.

また、本発明は、上記支持板の大きさは上記有機配線基板の大きさの８０％以上１２０％以下であることを特徴とする上記の半導体装置である。   The present invention is the above semiconductor device, wherein the size of the support plate is 80% or more and 120% or less of the size of the organic wiring substrate.

また、本発明は、上記支持板の厚みをＴ、前記支持板の備える上記リブ骨格構造の高さをｔとすると、０．６６７Ｔ＞ｔ＞０．３３３Ｔであることを特徴とする上記の半導体装置である。   Further, the present invention is characterized in that 0.667T> t> 0.333T, where T is the thickness of the support plate and t is the height of the rib skeleton structure provided in the support plate. Device.

本発明は、半導体チップと熱膨張係数が近い金属板を用いるので、半導体チップにかかる垂直方向の応力を減らすことができ、有機配線基板の変形を抑制し、有機配線基板および半導体チップの反りを矯正し、半導体チップの応力緩和をする効果がある。また、良好な熱伝導率を有する金属板を用いるので、半導体チップの放熱性が良い効果がある。   Since the present invention uses a metal plate having a thermal expansion coefficient close to that of the semiconductor chip, the stress in the vertical direction applied to the semiconductor chip can be reduced, the deformation of the organic wiring board can be suppressed, and the warpage of the organic wiring board and the semiconductor chip can be reduced. It has the effect of correcting and relaxing the stress of the semiconductor chip. In addition, since a metal plate having good thermal conductivity is used, there is an effect that the heat dissipation of the semiconductor chip is good.

以下、本発明による半導体装置の実施形態を図面にもとづいて詳細に説明する。図１は本実施形態の半導体装置の側面断面図を示し、図２は平面図を示す。図２（ａ）は上面図であり、図２（ｂ）は裏面図である。図１は図２のＡ−Ａ’線断面図を示す。本実施形態は、図１のように、半導体チップ１の大きさの数倍の大きさの四角形の絶縁樹脂の上面に配線パターンを形成した有機配線基板２を用いる。絶縁樹脂の上面に接着剤層４を介して金属箔を積層し、この金属箔の不要部分をエッチングにより除去することによって任意の配線パターンと、それに接続する第１の外部接続端子であるランドと第２の外部接続端子であるボールランドを形成する。有機配線基板２の絶縁樹脂は、厚さが０．０４ｍｍから０．３ｍｍで可とう性を有するガラスエポキシ系樹脂やポリイミド系樹脂を用い、特に、ガラス繊維を含浸した有機樹脂を用いることが望ましい。有機配線基板２上のランドは半導体チップ１に設置したバンプ５と相対する位置に形成する。   Embodiments of a semiconductor device according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a side sectional view of the semiconductor device of this embodiment, and FIG. 2 is a plan view. 2A is a top view, and FIG. 2B is a back view. 1 shows a cross-sectional view taken along line A-A ′ of FIG. 2. In the present embodiment, as shown in FIG. 1, an organic wiring substrate 2 in which a wiring pattern is formed on the upper surface of a rectangular insulating resin having a size several times the size of the semiconductor chip 1 is used. A metal foil is laminated on the upper surface of the insulating resin via the adhesive layer 4 and an unnecessary portion of the metal foil is removed by etching, whereby an arbitrary wiring pattern and a land which is a first external connection terminal connected thereto are provided. A ball land as a second external connection terminal is formed. As the insulating resin of the organic wiring board 2, it is desirable to use a glass epoxy resin or a polyimide resin having a thickness of 0.04 mm to 0.3 mm, and particularly an organic resin impregnated with glass fibers. . The land on the organic wiring board 2 is formed at a position opposite to the bump 5 installed on the semiconductor chip 1.

半導体チップ１のバンプ５をこの有機樹脂配線基板２のランドにはんだ接続し易くするために、あらかじめはんだをランド上に設置しておく。一般的には、スクリーン印刷機に
よりはんだペーストを供給したり、電解はんだメッキを行なうことにより供給する。 In order to make it easy to solder-connect the bumps 5 of the semiconductor chip 1 to the lands of the organic resin wiring board 2, solder is previously installed on the lands. In general, the solder paste is supplied by a screen printing machine or by electrolytic solder plating.

次に、有機配線基板２の下面に、有機配線基板２の大きさと略同じ大きさの、シリコン製の半導体チップ１の熱膨張係数に近い熱膨張係数を有する銅や銅タングステンやCUB、あるいは、アルミナや窒化アルミニウムなどの金属材料から成る金属板３を厚さが５０μｍの接着剤層４で貼り付け、有機配線基板２と金属板３の複合基板を形成する。こうして金属板３を貼り付けた複合基板にすることにより有機配線基板２が補強される。なお、この金属板３の替わりに、シリコン基板あるいはセラミックス基板による支持板を用いることもできる。   Next, on the lower surface of the organic wiring board 2, copper, copper tungsten, CUB having a thermal expansion coefficient close to the thermal expansion coefficient of the silicon semiconductor chip 1 having the same size as the organic wiring board 2, or A metal plate 3 made of a metal material such as alumina or aluminum nitride is attached with an adhesive layer 4 having a thickness of 50 μm to form a composite substrate of the organic wiring substrate 2 and the metal plate 3. In this way, the organic wiring board 2 is reinforced by using the composite board to which the metal plate 3 is attached. Instead of the metal plate 3, a support plate made of a silicon substrate or a ceramic substrate can be used.

有機配線基板２の厚さが０．３ｍｍの場合には、金属板３には、厚さが0.5mmの薄層部分３ａを形成し、また、金属板３の下面に高さが０．２ｍｍから０．３ｍｍで幅が０．５ｍｍのリブ骨格構造３ｂを形成することで薄層部分３ａを補強する。リブ骨格構造３ｂは、金属板３を縦横に横切り金属板３を反らせようとする応力を支える梁状の骨格構造である。また、金属板３の外周を囲む枠状のリブ骨格構造３ｂも形成することで金属板３を補強する。有機配線基板２の厚さが０．０４ｍｍから０．３ｍｍの間の範囲で厚さが異なる場合は、その厚さに応じて金属板３の薄層部分３ａとリブ骨格構造３ｂの寸法を定める。このとき、金属板３の薄層部分３ａとリブ骨格構造３ｂの断面構造は、断面二次モーメントを大きくし、その金属板３と半導体チップ１がアンダーフィル樹脂層６で有機配線基板２の上面に接着した部分のストレスと釣り合わせ打ち消すようにシュミレーションにより計算し定めた。その結果、この金属板３の厚み、すなわち、薄層部分３ａの厚さとリブ骨格構造３ｂの高さの和ををＴとし、リブ骨格構造の高さをｔとすると、０．６６７Ｔ＞ｔ＞０．３３３Ｔであると良好な断面二次モーメントを持つ構造になる知見を得た。   When the thickness of the organic wiring board 2 is 0.3 mm, a thin layer portion 3 a having a thickness of 0.5 mm is formed on the metal plate 3, and the height is 0.2 mm on the lower surface of the metal plate 3. The thin layer portion 3a is reinforced by forming a rib skeleton structure 3b having a width of 0.3 mm and a width of 0.5 mm. The rib skeleton structure 3b is a beam-like skeleton structure that supports a stress that attempts to warp the metal plate 3 across the metal plate 3 vertically and horizontally. Moreover, the metal plate 3 is reinforced by forming a frame-like rib skeleton structure 3 b surrounding the outer periphery of the metal plate 3. When the thickness of the organic wiring board 2 is different in the range between 0.04 mm and 0.3 mm, the dimensions of the thin layer portion 3a of the metal plate 3 and the rib skeleton structure 3b are determined according to the thickness. . At this time, the cross-sectional structure of the thin layer portion 3a and the rib skeleton structure 3b of the metal plate 3 increases the secondary moment of the cross section, and the metal plate 3 and the semiconductor chip 1 are underfill resin layer 6 and the upper surface of the organic wiring substrate 2. It was calculated and determined by simulation so as to cancel out the balance with the stress of the part adhered to. As a result, assuming that the thickness of the metal plate 3, that is, the sum of the thickness of the thin layer portion 3a and the height of the rib skeleton structure 3b is T, and the height of the rib skeleton structure is t, 0.667T> t> It was found that the structure having a good moment of inertia in section was 0.333T.

このようにリブ骨格構造３ｂを設けることにより、金属板３が薄層部分３ａのみの場合にはんだリフローによる応力で有機配線基板２と金属板３の複合基板が反る問題を無くすことができる効果がある。また、リブ骨格構造３ｂと薄層部分３ａで金属板３を構成することにより、金属板３をリブ骨格構造３ｂの厚さの平板で形成した場合よりも金属板３の表面積を大きくし、金属板３の放熱効果を大きくできる効果がある。このリブ骨格構造３ｂと薄層部分３ａの形成は、金属板３から薄層部分３ａをエッチングして形成し、エッチングしなかった部分のパターンでリブ骨格構造３ｂを形成する。金属板３の替わりにシリコン基板を支持板として用いた場合もシリコン基板をエッチングすることでリブ骨格構造３ｂを有する支持板を形成することができる。また、薄層部分３ａの厚さの金属板３の下面にセラミックスのリブ骨格構造を印刷し焼結することでリブ骨格構造３ｂを有する支持板を形成することができる。   By providing the rib skeleton structure 3b as described above, the effect that the composite substrate of the organic wiring substrate 2 and the metal plate 3 is warped by the stress due to solder reflow when the metal plate 3 is only the thin layer portion 3a can be eliminated. There is. Further, by forming the metal plate 3 with the rib skeleton structure 3b and the thin layer portion 3a, the surface area of the metal plate 3 is made larger than when the metal plate 3 is formed of a flat plate having the thickness of the rib skeleton structure 3b. There is an effect that the heat dissipation effect of the plate 3 can be increased. The rib skeleton structure 3b and the thin layer portion 3a are formed by etching the thin layer portion 3a from the metal plate 3 and forming the rib skeleton structure 3b with a pattern of the portion not etched. Even when a silicon substrate is used as the support plate instead of the metal plate 3, the support plate having the rib skeleton structure 3b can be formed by etching the silicon substrate. Further, a support plate having the rib skeleton structure 3b can be formed by printing and sintering a ceramic rib skeleton structure on the lower surface of the metal plate 3 having the thickness of the thin layer portion 3a.

次に、以下の様にして、半導体チップ１のフリップチップ実装により、半導体チップ１のバンプ５を有機配線基板２のランドに接続し、半導体チップ１と有機配線基板２をアンダーフィル樹脂層６で接着した構造を形成する。先ず、半導体チップ１のバンプ５を複合基板のランド上のはんだに接触させて設置し、リフロー炉に通してはんだ接続する。このとき、複合基板の下面は、ボンディングツールのバックアップのステージに接触して加熱される。複合基板の下側に金属板３を設置したため、リフロー炉ではんだを溶融したときの内部応力を金属板３が打ち消し、複合基板に反りや撓みを生じないようにできる効果がある。次に、半導体チップ１と有機配線基板２の間の隙間に熱硬化性のエポキシ樹脂を主成分とするアンダーフィル材を注入し充填させ、アンダーフィル材を加熱・硬化させてアンダーフィル樹脂層６を形成する。   Next, the bump 5 of the semiconductor chip 1 is connected to the land of the organic wiring board 2 by flip chip mounting of the semiconductor chip 1 as follows, and the semiconductor chip 1 and the organic wiring board 2 are connected by the underfill resin layer 6. Form a bonded structure. First, the bumps 5 of the semiconductor chip 1 are placed in contact with the solder on the lands of the composite substrate, and are soldered through a reflow furnace. At this time, the lower surface of the composite substrate is heated in contact with the backup stage of the bonding tool. Since the metal plate 3 is installed on the lower side of the composite substrate, the metal plate 3 cancels the internal stress when the solder is melted in the reflow furnace, and there is an effect that the composite substrate is not warped or bent. Next, an underfill material mainly composed of a thermosetting epoxy resin is injected and filled in the gap between the semiconductor chip 1 and the organic wiring substrate 2, and the underfill material is heated and cured to form the underfill resin layer 6. Form.

この効果を最適に働かせるために、金属板３を有機配線基板２の下面に固定する接着剤層４の条件として、有機配線基板２の下面に接着剤層４で金属板３を貼り付けた構造が、有機配線基板２の上面にアンダーフィル樹脂層６で半導体チップ１が接着されている構造
と同じ挙動（反りに関していえば、反対向きの相殺応力発生）を示すようにさせ、有機配線基板２の上下面のストレスを釣り合わせ、有機配線基板２の反りを矯正する。そのため、接着剤層４の熱膨張係数は金属基板３よりも大きく有機配線基板２よりも小さい熱膨張係数にすることが望ましい。このために、接着剤層４は例えば東京レーヨン製のＴＳＡ等を用いる。また、金属板３の寸法は、有機配線基板２の大きさの８０％から１２０％の寸法にすることが望ましい。金属板３の寸法が有機配線基板２の１２０％よりも大きくなると、半導体装置の大きさが大きくなり過ぎて不都合になり、一方、金属板３の大きさが有機配線基板２の大きさの８０％よりも小さいと、有機配線基板２の反りの矯正が不十分になるからである。 In order to make this effect work optimally, as a condition of the adhesive layer 4 for fixing the metal plate 3 to the lower surface of the organic wiring substrate 2, a structure in which the metal plate 3 is attached to the lower surface of the organic wiring substrate 2 with the adhesive layer 4 However, the organic wiring board 2 is made to exhibit the same behavior as the structure in which the semiconductor chip 1 is bonded to the upper surface of the organic wiring board 2 with the underfill resin layer 6 (in terms of warping, the occurrence of a counterbalance stress in the opposite direction). The warping of the organic wiring board 2 is corrected by balancing the stresses on the upper and lower surfaces. Therefore, it is desirable that the thermal expansion coefficient of the adhesive layer 4 is larger than that of the metal substrate 3 and smaller than that of the organic wiring board 2. For this purpose, the adhesive layer 4 uses, for example, TSA manufactured by Tokyo Rayon. The size of the metal plate 3 is desirably 80% to 120% of the size of the organic wiring board 2. If the size of the metal plate 3 is larger than 120% of the organic wiring board 2, the size of the semiconductor device becomes too large, which is inconvenient. On the other hand, the size of the metal plate 3 is 80 times the size of the organic wiring board 2. This is because if it is less than%, the correction of the warpage of the organic wiring board 2 becomes insufficient.

次に、有機配線基板２のボールランド上に半田ボール７を設置し、半田ボール７のボールグリッドアレイを形成した半導体装置を製造する。   Next, a solder ball 7 is placed on the ball land of the organic wiring board 2 to manufacture a semiconductor device in which a ball grid array of the solder balls 7 is formed.

本発明の実施形態の半導体装置の側面断面図である。It is side surface sectional drawing of the semiconductor device of embodiment of this invention. 本発明の実施形態の半導体装置の平面図である。It is a top view of the semiconductor device of the embodiment of the present invention. 従来の半導体装置の側面断面図である。It is side surface sectional drawing of the conventional semiconductor device.

符号の説明Explanation of symbols

１・・・半導体チップ
２・・・有機配線基板
３・・・金属板
３ａ・・・薄層部分
３ｂ・・・リブ骨格構造
４・・・接着剤層
５・・・バンプ
６・・・アンダーフィル樹脂層
７・・・半田ボール DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip 2 ... Organic wiring board 3 ... Metal plate 3a ... Thin layer part 3b ... Rib frame structure 4 ... Adhesive layer 5 ... Bump 6 ... Under Fill resin layer 7 ... Solder balls

Claims (7)

第一主面と第二主面を備える有機配線基板と、第一主面と第二主面を備える支持板と、半導体チップとを備え、前記有機配線基板の第一主面と前記支持板の第二主面は接着され、前記有機配線基板は第二主面に第一の外部接続端子と第二の外部接続端子を備え、前記半導体チップは前記第一の外部接続端子に接続され、前記半導体チップと前記有機配線基板をアンダーフィル樹脂層で接着し、前記支持板の第一主面にリブ骨格構造を備えたことを特徴とする半導体装置。   An organic wiring substrate having a first main surface and a second main surface, a support plate having a first main surface and a second main surface, and a semiconductor chip, the first main surface of the organic wiring substrate and the support plate The second main surface is bonded, the organic wiring board is provided with a first external connection terminal and a second external connection terminal on the second main surface, the semiconductor chip is connected to the first external connection terminal, A semiconductor device, wherein the semiconductor chip and the organic wiring substrate are bonded with an underfill resin layer, and a rib skeleton structure is provided on a first main surface of the support plate. 前記支持板が金属板であり、前記支持板と前記半導体チップの熱膨張係数はいずれも前記有機配線基板の熱膨張係数よりも小さいことを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the support plate is a metal plate, and the thermal expansion coefficients of the support plate and the semiconductor chip are both smaller than the thermal expansion coefficient of the organic wiring substrate. 前記支持板は第一主面に前記支持板の外周を囲む枠状の前記リブ骨格構造を備えることを特徴とする請求項１又は２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the support plate includes a frame-shaped rib skeleton structure surrounding an outer periphery of the support plate on a first main surface. 前記支持板と前記有機配線基板は接着剤層を介して接着され、当該接着剤層の熱膨張係数は前記支持板よりも大きく前記有機配線基板よりも小さいことを特徴とする請求項１乃至３の何れか一項記載の半導体装置。   The said support plate and the said organic wiring board are adhere | attached through an adhesive bond layer, and the thermal expansion coefficient of the said adhesive bond layer is larger than the said support board, and is smaller than the said organic wiring board. The semiconductor device according to any one of the above. 前記有機配線基板は厚さが０．３ｍｍ以下であることを特徴とする請求項１乃至４の何れか一項記載の半導体装置。   The semiconductor device according to claim 1, wherein the organic wiring board has a thickness of 0.3 mm or less. 前記支持板の大きさは前記有機配線基板の大きさの８０％以上１２０％以下であることを特徴とする請求項１乃至５の何れか一項記載の半導体装置。   6. The semiconductor device according to claim 1, wherein the size of the support plate is 80% to 120% of the size of the organic wiring substrate. 前記支持板の厚みをＴ、前記支持板の備える前記リブ骨格構造の高さをｔとすると、０．６６７Ｔ＞ｔ＞０．３３３Ｔであることを特徴とする請求項１乃至６の何れか一項記載の半導体装置。
7. The thickness of the support plate is T, and the height of the rib skeleton structure provided in the support plate is t, and 0.667T>t> 0.333T. A semiconductor device according to item.
JP2006306393A 2006-11-13 2006-11-13 Semiconductor device Pending JP2008124248A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8547705B2 (en) 2009-08-20 2013-10-01 Nec Corporation Semiconductor device having power supply-side and ground-side metal reinforcing members insulated from each other

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8547705B2 (en) 2009-08-20 2013-10-01 Nec Corporation Semiconductor device having power supply-side and ground-side metal reinforcing members insulated from each other

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