JP2008073818A - Electronic component and composite electronic component - Google Patents

Electronic component and composite electronic component Download PDF

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JP2008073818A
JP2008073818A JP2006257761A JP2006257761A JP2008073818A JP 2008073818 A JP2008073818 A JP 2008073818A JP 2006257761 A JP2006257761 A JP 2006257761A JP 2006257761 A JP2006257761 A JP 2006257761A JP 2008073818 A JP2008073818 A JP 2008073818A
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electronic component
asic
rewiring layer
electrode
mems element
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Kenichi Kamisaka
健一 上坂
Yoshihiro Koshido
義弘 越戸
Hajime Yamada
一 山田
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a small electronic component comprising an MEMS element and an ASIC, which connects junction electrodes of the MEMS element and the ASIC even if they do not correspond to each other on a one-to-one basis, and avoids damage of the MEMS element caused by wire bonding, and also to provide a composite electronic component composed of the electronic component. <P>SOLUTION: The electronic component has a structure formed of the MEMS element 10 and the ASIC 30 electrically/mechanically connected to each other. Each of the MEMS element 10 and the ASIC 30 has a rectangular plate-like shape as a whole, and has the junction electrodes 26 on one main surface. The electronic component has a wire-rearranging layer 20 which has the junction electrodes 26 to be connected to the junction electrodes 26 of the MEMS element 10, on a first surface, the junction electrodes 26 to be connected to the junction electrodes 26 of the ASIC 30, on a second surface opposite to the first surface, and a wiring for conducting between the junction electrodes 26 on the first surface and the junction electrodes 26 on the second surface. The wire-rearranging layer 20 is interposed between the MEMS element 10 and the ASIC 30. The electronic component has bumps 27, which are formed on an external terminal pad 25 on the wire-rearranging layer 20 and have a height higher than that of the ASIC 30. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

この発明は、ＭＥＭＳ素子とＡＳＩＣとを備え、ＭＥＭＳ素子とＡＳＩＣとを電気的・機械的に接続してなる電子部品およびそれを備えた複合電子部品に関するものである。   The present invention relates to an electronic component that includes a MEMS element and an ASIC and is electrically and mechanically connected to the MEMS element and an ASIC, and a composite electronic component including the electronic component.

従来、電気的または機械的な力で動作する稼働部を備えるＭＥＭＳ素子は、慣性計測や圧力検出、温度計測、マイクロ流体システム、光通信、無線通信等に向けた素子として開発されている。このようなＭＥＭＳ素子はＡＳＩＣとともに用いることによって機能性の高い電子部品となる。このようなＭＥＭＳ素子とＡＳＩＣとを備えた電子部品については特許文献１，２が示されている。   2. Description of the Related Art Conventionally, a MEMS element including an operating unit that operates with an electric or mechanical force has been developed as an element for inertial measurement, pressure detection, temperature measurement, microfluidic system, optical communication, wireless communication, and the like. Such a MEMS element becomes an electronic component having high functionality when used with an ASIC. Patent documents 1 and 2 are shown about an electronic component provided with such a MEMS element and ASIC.

特許文献１には、ＭＥＭＳ素子の上面にＡＳＩＣを搭載するための凹部および接合電極を備え、その凹部にＡＳＩＣをバンプを介して接続するようにした構成が示されている。   Patent Document 1 discloses a configuration in which a concave portion and a bonding electrode for mounting an ASIC are provided on the upper surface of the MEMS element, and the ASIC is connected to the concave portion via a bump.

また特許文献２には保護ケース内にＭＥＭＳ素子とＩＣチップとを積層状態で収容した構成が示されている。
特表２００５−５２８２３５号公報 特開２００５−１６９５４１号公報 Patent Document 2 shows a configuration in which a MEMS element and an IC chip are accommodated in a protective case in a stacked state.
Special table 2005-528235 gazette JP 2005-169541 A

ところがＭＥＭＳ素子とＡＳＩＣとでは、元々要求される機能を実現するために必要な製造上のプロセスが異なり、それぞれに最適な設計および製造がなされている。そのため、ＭＥＭＳ素子・ＡＳＩＣそれぞれの小型化が進み、ＭＥＭＳ素子の接続電極とＡＳＩＣの接続電極とを１対１に対応させて接続することが困難になってきている。   However, the MEMS device and the ASIC have different manufacturing processes necessary for realizing the originally required functions, and are optimally designed and manufactured. Therefore, miniaturization of each of the MEMS element and the ASIC has progressed, and it has become difficult to connect the connection electrode of the MEMS element and the connection electrode of the ASIC in a one-to-one correspondence.

ここでＭＥＭＳジャイロとその信号を扱うＡＳＩＣとのサイズおよび構成の違いの例を図１に示す。図１においてＭＥＭＳ素子１０の上面にはＡＳＩＣの外部端子（バンプ）を接合するための接合電極１１が形成されている。また、このＭＥＭＳ素子１０上の上面には接合電極１１の周囲を除くほぼ全面にグランド電極１４が形成されている。一方、ＡＳＩＣ３０には接続電極（電極パッド）３２が形成されている。   FIG. 1 shows an example of the difference in size and configuration between the MEMS gyro and the ASIC that handles the signal. In FIG. 1, a bonding electrode 11 for bonding an external terminal (bump) of the ASIC is formed on the upper surface of the MEMS element 10. In addition, a ground electrode 14 is formed on the entire upper surface of the MEMS element 10 except for the periphery of the bonding electrode 11. On the other hand, connection electrodes (electrode pads) 32 are formed on the ASIC 30.

このようにＭＥＭＳ素子上の接合電極１１は、その周囲がグランド電極１４で囲まれているので、接合電極１１をＭＥＭＳ素子上に最小化して設けるとしても、各接合電極１１がグランド電極１４で囲まれている分、配列ピッチの縮小化には限界が生じ、小型化されたＡＳＩＣ３０に設けられている接合電極３２の電極間隔より広くなってしまう。そのため、ＭＥＭＳ素子とＡＳＩＣのそれぞれの小型化の進展に伴い、ＭＥＭＳ素子１０の接合電極１１とＡＳＩＣ３０の接合電極３２とを１対１に対応させて接続することが困難になってきている。   Thus, since the periphery of the bonding electrode 11 on the MEMS element is surrounded by the ground electrode 14, each bonding electrode 11 is surrounded by the ground electrode 14 even if the bonding electrode 11 is minimized and provided on the MEMS element. As a result, there is a limit to the reduction in the arrangement pitch, which is wider than the electrode interval of the bonding electrodes 32 provided in the miniaturized ASIC 30. Therefore, with the progress of miniaturization of the MEMS element and the ASIC, it has become difficult to connect the bonding electrode 11 of the MEMS element 10 and the bonding electrode 32 of the ASIC 30 in a one-to-one correspondence.

また、ワイヤ−ボンディングによってＭＥＭＳ素子１０とＡＳＩＣ３０とを電気的に接続する構造も考えられるが、ＭＥＭＳ素子１０がＭＥＭＳジャイロである場合、ＭＥＭＳ素子１０とＡＳＩＣ３０との電気的接続を図るために超音波を用いてワイヤ−ボンディングを行うと、超音波振動によりＭＥＭＳジャイロに内蔵されている櫛歯状電極同士が接触したり、櫛歯状電極が破壊したりするため、実質的にワイヤ−ボンディングを行うことができなかった。   In addition, a structure in which the MEMS element 10 and the ASIC 30 are electrically connected by wire bonding is conceivable. However, when the MEMS element 10 is a MEMS gyro, ultrasonic waves are used to electrically connect the MEMS element 10 and the ASIC 30. When wire bonding is performed by using the wire, the comb-like electrodes built in the MEMS gyro are brought into contact with each other or the comb-like electrodes are destroyed by ultrasonic vibration, so that the wire-bonding is substantially performed. I couldn't.

そこで、この発明の目的は、ＭＥＭＳ素子とＡＳＩＣの接合電極同士が１対１に対応しない場合でも両者を接続可能とし、ワイヤ−ボンディングによるＭＥＭＳ素子の損傷の問題を回避しつつ、ＭＥＭＳ素子とＡＳＩＣを備えたより小型の電子部品およびそれを備えた複合電子部品を提供することにある。   SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to enable a MEMS element and an ASIC to be connected to each other even when the bonding electrodes of the MEMS element and the ASIC do not correspond one-to-one, and avoid the problem of damage to the MEMS element due to wire bonding. It is an object of the present invention to provide a smaller electronic component including the above and a composite electronic component including the same.

（１）この発明の電子部品は、ＭＥＭＳ素子とＡＳＩＣとを備え、ＭＥＭＳ素子とＡＳＩＣとを電気的・機械的に接続した構造をなし、ＭＥＭＳ素子およびＡＳＩＣのそれぞれは、全体に矩形の板状をなし、一方の主面に接合電極を備え、ＭＥＭＳ素子の接合電極に接合される接合電極を第１面に備え、ＡＳＩＣの接合電極に接続される接合電極を第１面とは反対の第２面に備え、第１面の接合電極と第２面の接合電極との間を導通させる配線を備えた再配線層を有し、ＭＥＭＳ素子とＡＳＩＣとの間に再配線層を介在させた構造を特徴とするものである。   (1) An electronic component of the present invention includes a MEMS element and an ASIC, and has a structure in which the MEMS element and the ASIC are electrically and mechanically connected. Each of the MEMS element and the ASIC has a rectangular plate shape as a whole. The first electrode is provided with a bonding electrode on one main surface, the bonding electrode bonded to the bonding electrode of the MEMS element is provided on the first surface, and the bonding electrode connected to the bonding electrode of the ASIC is opposite to the first surface. A rewiring layer provided on two surfaces and provided with wiring for conducting between the bonding electrode on the first surface and the bonding electrode on the second surface, and the rewiring layer interposed between the MEMS element and the ASIC It is characterized by its structure.

（２）前記ＡＳＩＣの実装領域は前記再配線層の領域より狭く、再配線層に対するＡＳＩＣの実装領域外の再配線層の第２面にＡＳＩＣの実装高さより高い複数のバンプを備え、これらのバンプの少なくとも幾つかは再配線層の第１面または第２面の接合電極と電気的に導通している。   (2) The mounting area of the ASIC is narrower than the area of the rewiring layer, and includes a plurality of bumps higher than the mounting height of the ASIC on the second surface of the rewiring layer outside the mounting area of the ASIC with respect to the rewiring layer. At least some of the bumps are electrically connected to the bonding electrode on the first surface or the second surface of the rewiring layer.

（３）また、例えば前記再配線層の第２面にキャビティを形成し、そのキャビティの底面にＡＳＩＣを実装する。   (3) For example, a cavity is formed on the second surface of the rewiring layer, and an ASIC is mounted on the bottom surface of the cavity.

（４）また、前記キャビティの周縁部に、前記再配線層の第１面または第２面に備えた接合電極に導通する接合電極を有し、キャビティを覆う蓋を備え、該蓋の外面に、キャビティ周縁部の接合電極に導通するバンプを設ける。   (4) In addition, a peripheral electrode of the cavity has a bonding electrode that conducts to the bonding electrode provided on the first surface or the second surface of the redistribution layer, and includes a lid that covers the cavity. Bumps that are electrically connected to the bonding electrodes at the peripheral edge of the cavity are provided.

（５）また、前記蓋の内面に、前記再配線層の第１面または第２面に備えた接合電極に導通する薄膜受動素子を形成する。   (5) Further, a thin-film passive element that conducts to a bonding electrode provided on the first surface or the second surface of the rewiring layer is formed on the inner surface of the lid.

（６）また、前記蓋の外面に、当該蓋よりヤング率の小さな応力緩和層を設ける。   (6) A stress relaxation layer having a Young's modulus smaller than that of the lid is provided on the outer surface of the lid.

（７）また、前記ＡＳＩＣは樹脂により封止され、該樹脂に前記再配線層の第１面または第２面の接合電極と電気的に導通するビアを備え、該ビアにバンプを設ける。   (7) The ASIC is sealed with a resin, and the resin is provided with a via that is electrically connected to the bonding electrode on the first surface or the second surface of the rewiring layer, and the via is provided with a bump.

（８）また、前記樹脂は前記バンプおよび前記ビアに比べてヤング率が小さいものとする。   (8) The resin has a Young's modulus smaller than that of the bump and the via.

（９）また、前記再配線層に、前記第１面または第２面の接合電極に導通する薄膜受動素子を形成する。   (9) A thin-film passive element that is electrically connected to the bonding electrode on the first surface or the second surface is formed on the rewiring layer.

（１０）この発明の複合電子部品は、前記電子部品を、前記ＭＥＭＳ素子を実装面として基板に実装し、前記再配線層の第２面にワイヤーボンディング用パッドを形成し、該ワイヤーボンディング用パッドと基板上の電極との間をワイヤーボンディングして構成したことを特徴とするものである。   (10) In the composite electronic component of the present invention, the electronic component is mounted on a substrate using the MEMS element as a mounting surface, a wire bonding pad is formed on the second surface of the redistribution layer, and the wire bonding pad is formed. And the electrode on the substrate are formed by wire bonding.

（１１）また、この発明の複合電子部品は、前記電子部品を、前記バンプを介して基板に実装し、該基板に前記電子部品を覆う金属キャップを取り付けたものである。   (11) Moreover, the composite electronic component of this invention mounts the said electronic component on a board | substrate via the said bump, and attached the metal cap which covers the said electronic component to this board | substrate.

（１２）また、この発明の複合電子部品は、前記電子部品を、前記バンプを介して基板に実装し、該基板上で前記電子部品全体を樹脂封止したものである。   (12) In the composite electronic component of the present invention, the electronic component is mounted on a substrate through the bumps, and the entire electronic component is resin-sealed on the substrate.

（１３）前記基板には、前記電子部品と電気的に導通する実装電極を形成するとともに、該実装電極に受動素子を実装してもよい。   (13) A mounting electrode that is electrically connected to the electronic component may be formed on the substrate, and a passive element may be mounted on the mounting electrode.

（１４）前記基板の内部には、前記電子部品と電気的に導通する導体膜からなる受動素子を形成してもよい。   (14) A passive element made of a conductive film that is electrically connected to the electronic component may be formed inside the substrate.

（１）ＭＥＭＳ素子とＡＳＩＣとの間に再配線層を介在させて積層したことにより、ＭＥＭＳ素子の接合電極とＡＳＩＣの接合電極とを１対１に対応させて接続できるようになる。またＭＥＭＳ素子の接合電極に対してワイヤ−ボンディングを行う必要がないので、ＭＥＭＳ素子が例えばＭＥＭＳジャイロのように超音波振動によって悪影響を受ける素子である場合でもＡＳＩＣとの電気的接続が可能となる。   (1) Since the rewiring layer is interposed between the MEMS element and the ASIC and stacked, the bonding electrode of the MEMS element and the bonding electrode of the ASIC can be connected in a one-to-one correspondence. Further, since it is not necessary to perform wire bonding to the bonding electrode of the MEMS element, even when the MEMS element is an element that is adversely affected by ultrasonic vibration such as a MEMS gyro, for example, electrical connection with the ASIC is possible. .

（２）特に、再配線層に対するＡＳＩＣの実装領域外にＡＳＩＣの実装高さより高いバンプを備えることによって、これらのバンプの形成およびバンプを介しての実装基板への電子部品の実装が容易となる。   (2) In particular, by providing bumps higher than the mounting height of the ASIC outside the mounting area of the ASIC on the rewiring layer, it becomes easy to form these bumps and mount electronic components on the mounting board via the bumps. .

（３）また再配線層にキャビティを形成し、その底面にＡＳＩＣを実装することによってＡＳＩＣの実装高さに対するバンプの高さを容易に稼ぐことができる。   (3) Further, by forming a cavity in the rewiring layer and mounting the ASIC on the bottom surface, the height of the bump relative to the mounting height of the ASIC can be easily obtained.

（４）また、前記キャビティを覆う蓋を備え、その蓋の外面に再配線層の接合電極に導通するバンプを設けることによって、それ以外の特別な樹脂モールドや金属キャップ等を用いることなくＡＳＩＣの耐環境性を高めた小型の電子部品が得られる。   (4) In addition, by providing a cover that covers the cavity and providing a bump on the outer surface of the cover that is connected to the bonding electrode of the rewiring layer, there is no need to use a special resin mold or metal cap. Small electronic parts with improved environmental resistance can be obtained.

（５）前記蓋の内面に薄膜受動素子を形成することにより、限られた空間内に必要な回路を構成することができ、全体に小型化できる。   (5) By forming a thin-film passive element on the inner surface of the lid, a necessary circuit can be configured in a limited space, and the overall size can be reduced.

（６）また、前記蓋の外面に応力緩和層を設けることによって外部からの衝撃および応力が緩和されて信頼性が向上する。   (6) Further, by providing a stress relaxation layer on the outer surface of the lid, impact and stress from the outside are relaxed, and reliability is improved.

（７）前記ＡＳＩＣを樹脂により封止し、その封止樹脂にビアおよびバンプを設けることによって外部からの衝撃・応力を緩和することができ、且つ湿度に対する信頼性が向上する。   (7) By sealing the ASIC with a resin and providing vias and bumps in the sealing resin, it is possible to mitigate external impacts and stresses, and to improve the reliability with respect to humidity.

（８）上記封止樹脂をバンプおよびビアに比べてヤング率の小さなものとすることにより応力緩和効果が向上する。   (8) The stress relaxation effect is improved by making the sealing resin have a Young's modulus smaller than that of the bump and via.

（９）再配線層に薄膜受動素子を形成することにより、チップ状の受動素子を設ける場合に比べて小型化できる。   (9) By forming a thin film passive element in the rewiring layer, the size can be reduced as compared with the case where a chip-like passive element is provided.

（１０）中間に再配線層を介在させてＭＥＭＳ素子とＡＳＩＣとを積層してなる電子部品を基板に実装し、再配線層のワイヤ−ボンディング用パッドと基板上の電極との間をワイヤ−ボンディングすることによって、基板を介して電子機器の回路基板上に実装することになり、外部からの衝撃・応力がより緩和できる。   (10) An electronic component formed by stacking a MEMS element and an ASIC with a rewiring layer interposed therebetween is mounted on a substrate, and a wire between the wire-bonding pad of the rewiring layer and an electrode on the substrate By bonding, it is mounted on the circuit board of the electronic device via the substrate, and the impact and stress from the outside can be further relaxed.

（１１）前記バンプを設けた電子部品をそのバンプを介して基板に実装し、基板に金属キャップを取り付けることにより、ワイヤ−ボンディングを用いる場合より小型化でき、ワイヤ−ボンディングのできないＭＥＭＳ素子でも実装可能となる。   (11) An electronic component provided with the bump is mounted on a substrate through the bump, and a metal cap is attached to the substrate, so that the size can be reduced as compared with the case of using wire bonding, and even a MEMS element that cannot perform wire bonding is mounted. It becomes possible.

（１２）上記金属キャップに代えて樹脂封止を行っても同様である。   (12) The same applies if resin sealing is performed instead of the metal cap.

（１３）上記基板に電子部品とともに受動素子を実装することにより、受動素子の要する小型の複合電子部品が構成できる。   (13) By mounting a passive element together with an electronic component on the substrate, a small composite electronic component requiring a passive element can be configured.

（１４）上記基板の内部に受動素子を形成することにより回路基板への実装面積が削減できる。   (14) The mounting area on the circuit board can be reduced by forming passive elements inside the board.

《第１の実施形態》
図２は第１の実施形態に係る電子部品の製造工程における各段階での断面図である。また図３はその電子部品の全体の外観斜視図である。 << First Embodiment >>
FIG. 2 is a cross-sectional view at each stage in the manufacturing process of the electronic component according to the first embodiment. FIG. 3 is an external perspective view of the entire electronic component.

この電子部品の製造工程を図２中の記号に合わせて順に説明する。
（ａ）ＭＥＭＳ素子１０上に接合用の電極１１を形成する。この接合電極１１は例えば蒸着およびリフトオフによりパターニングする。この接合電極１１の膜構成は例えばＣｕ，Ｓｎ，Ａｕ，Ｔｉおよびそれらの組み合わせとする。なお、ＭＥＭＳ素子１０内部の構造は図示していない。 The manufacturing process of this electronic component will be described in order according to the symbols in FIG.
(A) An electrode 11 for bonding is formed on the MEMS element 10. The bonding electrode 11 is patterned by, for example, vapor deposition and lift-off. The film configuration of the bonding electrode 11 is, for example, Cu, Sn, Au, Ti, or a combination thereof. The structure inside the MEMS element 10 is not shown.

（ｂ）Ｓｉまたはガラスからなる再配線層２０の第１面にＭＥＭＳ素子との接合用の電極２１を形成する。この接合電極２１は例えば蒸着およびリフトオフによりパターニングする。この接合電極の膜構成は例えばＣｕ，Ｓｎ，Ａｕ，Ｔｉおよびそれらの組み合わせとする。再配線層２０には例えばＳｉやガラス等を用いる。   (B) An electrode 21 for bonding to the MEMS element is formed on the first surface of the rewiring layer 20 made of Si or glass. The bonding electrode 21 is patterned by, for example, vapor deposition and lift-off. The film configuration of the bonding electrode is, for example, Cu, Sn, Au, Ti, or a combination thereof. For example, Si or glass is used for the rewiring layer 20.

（ｃ）ＭＥＭＳ素子１０と再配線層２０に形成した接合電極同士が一致するようにアライメントし加熱・加圧により接合する。なお、接合後、再配線層２０を研磨などにより所望の厚さまで薄化してもよい。   (C) Alignment is performed so that the bonding electrodes formed on the MEMS element 10 and the rewiring layer 20 are aligned, and bonding is performed by heating and pressing. In addition, after the bonding, the rewiring layer 20 may be thinned to a desired thickness by polishing or the like.

（ｄ）再配線層２０の第２面の所定位置に接合電極２１に達するビアホール２２を形成する。再配線層２０がＳｉであればＲＩＥ（反応性イオンエッチング）、ガラスであればレーザ加工またはサンドブラスト法等により形成する。   (D) A via hole 22 reaching the bonding electrode 21 is formed at a predetermined position on the second surface of the rewiring layer 20. If the rewiring layer 20 is Si, it is formed by RIE (reactive ion etching), and if it is glass, it is formed by laser processing or sandblasting.

（ｅ）再配線層２０のビアホール２２に対してＣｕのメッキにより導電性材料を充填してビア２３を形成する。図２ではビアホール２２に導電性材料を完全に充填した例を示したが、ビア２３は次の工程で形成される配線２４と導通するように形成されていればよく、導電性材料をビアホール２２内を完全に充填することなく半分程度充填するようにしてもよい。   (E) The via 23 is formed by filling the via hole 22 of the rewiring layer 20 with a conductive material by plating with Cu. Although FIG. 2 shows an example in which the via hole 22 is completely filled with the conductive material, the via 23 may be formed so as to be electrically connected to the wiring 24 formed in the next step. You may make it fill about half, without filling the inside completely.

（ｆ）再配線層２０の上面に配線２４を形成する。
（ｇ）再配線層２０の配線２４上に外部端子用のパッド２５を形成する。 (F) The wiring 24 is formed on the upper surface of the rewiring layer 20.
(G) A pad 25 for an external terminal is formed on the wiring 24 of the rewiring layer 20.

（ｈ）再配線層２０の配線２４上に接合用の電極２６を形成する。この接合電極２６は例えば蒸着およびリフトオフによりパターニングする。この接合電極２６の膜構成は例えばＣｕ，Ｓｎ，Ａｕ，Ｔｉおよびそれらの組み合わせとする。   (H) An electrode 26 for bonding is formed on the wiring 24 of the rewiring layer 20. The bonding electrode 26 is patterned by, for example, vapor deposition and lift-off. The film configuration of the bonding electrode 26 is, for example, Cu, Sn, Au, Ti, or a combination thereof.

（ｉ）ＡＳＩＣ３０の片面に形成された配線３１上に、ＭＥＭＳ素子に接合された再配線層２０との接合用電極３２を形成する。この接合電極３２は例えば蒸着およびリフトオフによりパターニングする。この接合電極３２の膜構成は例えばＣｕ，Ｓｎ，Ａｕ，Ｔｉおよびそれらの組み合わせとする。   (I) On the wiring 31 formed on one side of the ASIC 30, the bonding electrode 32 with the rewiring layer 20 bonded to the MEMS element is formed. The bonding electrode 32 is patterned by, for example, vapor deposition and lift-off. The film configuration of the bonding electrode 32 is, for example, Cu, Sn, Au, Ti, or a combination thereof.

（ｊ）ＭＥＭＳ素子１０と接合された再配線層２０と、ＡＳＩＣ３０に形成された接合電極とが一致するようにアライメントし、加熱・加圧により接合する。また、この時、図３に示すように再配線層２０の上にチップコンデンサ等の受動素子６１を実装してもよい。さらには再配線層２０内に薄膜受動素子を形成してもよい。   (J) Alignment is performed so that the rewiring layer 20 bonded to the MEMS element 10 and the bonding electrode formed on the ASIC 30 coincide with each other, and bonding is performed by heating and pressing. At this time, a passive element 61 such as a chip capacitor may be mounted on the rewiring layer 20 as shown in FIG. Furthermore, a thin film passive element may be formed in the rewiring layer 20.

（ｋ）再配線層２０上の外部端子用パッド２５にＡＳＩＣ３０より高いバンプ２７を形成する。   (K) Bumps 27 higher than the ASIC 30 are formed on the external terminal pads 25 on the rewiring layer 20.

以上のようにしてＭＥＭＳ素子１０とＡＳＩＣ３０との間に再配線層２０を介在させた電子部品１００を構成する。この電子部品１００を回路基板上に実装する際には、再配線層２０に設けたバンプ２７を介して実装する。   As described above, the electronic component 100 in which the rewiring layer 20 is interposed between the MEMS element 10 and the ASIC 30 is configured. When the electronic component 100 is mounted on the circuit board, the electronic component 100 is mounted via the bumps 27 provided on the rewiring layer 20.

このような構成により、ＭＥＭＳ素子１０にワイヤ−ボンディングを行う必要がないのでワイヤ−ボンディングのできない、例えばＭＥＭＳジャイロ等にも適用できる。   With such a configuration, since it is not necessary to perform wire bonding to the MEMS element 10, the present invention can be applied to, for example, a MEMS gyro that cannot perform wire bonding.

《第２の実施形態》
図４は第２の実施形態に係る電子部品の製造工程における各段階での断面図である。
この電子部品の製造工程を図４中の記号に合わせて順に説明する。 << Second Embodiment >>
FIG. 4 is a cross-sectional view at each stage in the manufacturing process of the electronic component according to the second embodiment.
The manufacturing process of this electronic component will be described in order according to the symbols in FIG.

（ａ）ＭＥＭＳ素子１０上に接合用の電極１１を形成する。
（ｂ）再配線層２０の第１面にＭＥＭＳ素子との接合用の電極２１を形成する。
（ｃ）ＭＥＭＳ素子１０と再配線層２０に形成した接合電極同士が一致するようにアライメントし加熱・加圧により接合する。 (A) An electrode 11 for bonding is formed on the MEMS element 10.
(B) The electrode 21 for bonding with the MEMS element is formed on the first surface of the rewiring layer 20.
(C) Alignment is performed so that the bonding electrodes formed on the MEMS element 10 and the rewiring layer 20 are aligned, and bonding is performed by heating and pressing.

上記工程（ａ）〜（ｃ）の詳細は図２に示した工程（ａ）〜（ｃ）と同様である。但し、この第２の実施形態では再配線層２０の厚みが図２に示したものに比べて厚い。   The details of the steps (a) to (c) are the same as the steps (a) to (c) shown in FIG. However, in the second embodiment, the rewiring layer 20 is thicker than that shown in FIG.

（ｄ）再配線層２０の第２面にキャビティ２８を形成する。再配線層２０がＳｉなら異方性エッチングやＲＩＥにより形成し、ガラスであればサンドブラスト等により形成する。   (D) A cavity 28 is formed on the second surface of the rewiring layer 20. If the rewiring layer 20 is Si, it is formed by anisotropic etching or RIE, and if it is glass, it is formed by sandblasting or the like.

（ｅ）再配線層２０のキャビティ内にビアホール２２を形成する。
（ｆ）再配線層２０のビアホール２２に対してＣｕのメッキにより導電性材料を充填してビア２３を形成する。 (E) A via hole 22 is formed in the cavity of the rewiring layer 20.
(F) The via hole 22 is formed by filling the via hole 22 of the rewiring layer 20 with a conductive material by plating with Cu.

（ｇ）再配線層２０の上面に配線２４を形成する。また、再配線層２０の配線上に外部端子用のパッド２５を形成する。   (G) The wiring 24 is formed on the upper surface of the rewiring layer 20. Further, pads 25 for external terminals are formed on the wiring of the rewiring layer 20.

（ｈ）再配線層２０の配線２４上に接合用の電極２６を形成する。
（ｉ）ＡＳＩＣ３０の片面に形成された配線３１上に、ＭＥＭＳ素子に接合された再配線層２０との接合用電極３２を形成する。 (H) An electrode 26 for bonding is formed on the wiring 24 of the rewiring layer 20.
(I) On the wiring 31 formed on one side of the ASIC 30, the bonding electrode 32 with the rewiring layer 20 bonded to the MEMS element is formed.

（ｊ）ＭＥＭＳ素子１０と接合された再配線層２０と、ＡＳＩＣ３０に形成された接合電極とが一致するようにアライメントし、加熱・加圧により接合する。   (J) Alignment is performed so that the rewiring layer 20 bonded to the MEMS element 10 and the bonding electrode formed on the ASIC 30 coincide with each other, and bonding is performed by heating and pressing.

（ｋ）再配線層２０上の外部端子用パッド２５にバンプ２７を形成する。
上記工程（ｅ）〜（ｋ）の詳細は図２に示した工程（ｄ）〜（ｋ）と同様である。 (K) A bump 27 is formed on the external terminal pad 25 on the rewiring layer 20.
The details of the steps (e) to (k) are the same as the steps (d) to (k) shown in FIG.

以上に示した第２の実施形態によれば、第１の実施形態で述べた効果以外に、次のような効果を奏する。   According to the second embodiment described above, the following effects can be obtained in addition to the effects described in the first embodiment.

（１）ＡＳＩＣ３０を再配線層２０のキャビティ内に実装することによりＡＳＩＣ３０への衝撃が吸収され信頼性が向上する。   (1) By mounting the ASIC 30 in the cavity of the rewiring layer 20, the impact on the ASIC 30 is absorbed and the reliability is improved.

（２）ＡＳＩＣを搭載するためのキャビティをＭＥＭＳ素子１０の片面に形成するわけではないのでＭＥＭＳ素子の機械的強度の劣化が生じない。   (2) Since the cavity for mounting the ASIC is not formed on one side of the MEMS element 10, the mechanical strength of the MEMS element does not deteriorate.

《第３の実施形態》
図５は第３の実施形態に係る電子部品の製造工程における各段階での断面図である。また図６は完成した電子部品の断面図である。 << Third Embodiment >>
FIG. 5 is a cross-sectional view at each stage in the manufacturing process of the electronic component according to the third embodiment. FIG. 6 is a cross-sectional view of the completed electronic component.

この電子部品の製造工程を、図５中の記号に合わせて順に説明する。この電子部品の製造工程の途中までは第２の実施形態で示したものと同様であるので、図５ではその同一工程を省略して途中から示している。   The manufacturing process of this electronic component will be described in order according to the symbols in FIG. The process up to the middle of the manufacturing process of the electronic component is the same as that shown in the second embodiment, and therefore the same process is omitted in FIG.

（ａ）ＭＥＭＳ素子１０に再配線層２０を接合し、再配線層２０に形成したキャビティ内にＡＳＩＣ３０を実装した状態である。この状態は図４の（ｊ）と同様である。   (A) The rewiring layer 20 is bonded to the MEMS element 10 and the ASIC 30 is mounted in the cavity formed in the rewiring layer 20. This state is the same as (j) in FIG.

（ｂ）再配線層２０のキャビティの外側に接合電極２９を形成する。この接合電極２９は例えば蒸着およびリフトオフによりパターニングする。この接合電極２９の膜構成は例えばＣｕ，Ｓｎ，Ａｕ，Ｔｉおよびそれらの組み合わせとする。   (B) A bonding electrode 29 is formed outside the cavity of the rewiring layer 20. The bonding electrode 29 is patterned by vapor deposition and lift-off, for example. The film configuration of the bonding electrode 29 is, for example, Cu, Sn, Au, Ti, or a combination thereof.

（ｃ）蓋基板４０に接合電極４５を形成する。この接合電極４５も、例えば蒸着およびリフトオフによりパターニングする。また接合電極４５の膜構成は例えばＣｕ，Ｓｎ，Ａｕ，Ｔｉおよびそれらの組み合わせとする。この工程で蓋基板４０の裏面に接合電極４５に導通する薄膜キャパシタを形成してもよい。   (C) The bonding electrode 45 is formed on the lid substrate 40. The bonding electrode 45 is also patterned by, for example, vapor deposition and lift-off. The film configuration of the bonding electrode 45 is, for example, Cu, Sn, Au, Ti, or a combination thereof. In this step, a thin film capacitor conducting to the bonding electrode 45 may be formed on the back surface of the lid substrate 40.

（ｄ）ＭＥＭＳ素子１０と接合した再配線層２０に対して蓋基板４０を加熱・加圧により接合する。   (D) The lid substrate 40 is bonded to the rewiring layer 20 bonded to the MEMS element 10 by heating and pressing.

（ｅ）蓋基板４０にビアホール４１を形成する。蓋基板がＳｉであればＲＩＥ、ガラスであればレーザやサンドブラスト法等により形成する。   (E) A via hole 41 is formed in the lid substrate 40. If the lid substrate is Si, it is formed by RIE. If the lid substrate is glass, it is formed by a laser, a sandblast method or the like.

（ｆ）蓋基板４０のビアホール４１に導電性材料（例えばＣｕやＮｉ）をメッキすることにより充填しビア４６を形成する。   (F) A via 46 is formed by filling the via hole 41 of the lid substrate 40 by plating with a conductive material (for example, Cu or Ni).

また、ビア４６の最表層にはＡｕ等の酸化防止膜を形成してもよい。また、蓋基板４０の表面に応力緩和層としての樹脂膜４２を形成してもよい。この樹脂膜４２は蓋基板４０よりヤング率が小さいものとする。   Further, an antioxidant film such as Au may be formed on the outermost layer of the via 46. Further, a resin film 42 as a stress relaxation layer may be formed on the surface of the lid substrate 40. The resin film 42 has a Young's modulus smaller than that of the lid substrate 40.

（ｇ）蓋基板４０に形成したビア４６に外部端子としてのバンプ４３を形成する。   (G) Bumps 43 as external terminals are formed in the vias 46 formed in the lid substrate 40.

上記蓋基板４０の内面または内層に薄膜導体と薄膜誘電体層からなるキャパシタなどの薄膜受動素子を形成してもよい。   A thin film passive element such as a capacitor composed of a thin film conductor and a thin film dielectric layer may be formed on the inner surface or inner layer of the lid substrate 40.

このようにして図６に示すような電子部品１０１を構成する。図６に示す例では、蓋基板４０の内面に、接合電極４５に導通する２つの薄膜導体と、この２つの薄膜導体で挟まれる薄膜誘電体層とでキャパシタとして作用する薄膜受動素子４４を形成している。   In this way, the electronic component 101 as shown in FIG. 6 is configured. In the example shown in FIG. 6, a thin film passive element 44 that functions as a capacitor is formed on the inner surface of the lid substrate 40 by two thin film conductors connected to the bonding electrode 45 and a thin film dielectric layer sandwiched between the two thin film conductors. is doing.

《第４の実施形態》
図７は第４の実施形態に係る電子部品の製造工程における各段階での断面図、図８は完成した電子部品の斜視図である。 << Fourth Embodiment >>
FIG. 7 is a cross-sectional view at each stage in the manufacturing process of the electronic component according to the fourth embodiment, and FIG. 8 is a perspective view of the completed electronic component.

この電子部品の製造工程を、図７中の記号に合わせて順に説明する。この電子部品の製造工程の途中までは第１の実施形態で示したものと同様であるので、図７ではその同一工程を省略して途中から示している。   The manufacturing process of this electronic component will be described in order according to the symbols in FIG. Since the manufacturing process of the electronic component is the same as that shown in the first embodiment, the same process is omitted in FIG. 7 from the middle.

（ａ）ＭＥＭＳ素子１０に再配線層２０を接合し、再配線層２０上にＡＳＩＣ３０を実装した状態である。この状態は図２の（ｊ）と同様である。   (A) The rewiring layer 20 is bonded to the MEMS element 10 and the ASIC 30 is mounted on the rewiring layer 20. This state is the same as (j) in FIG.

（ｂ）再配線層２０の上部に実装したＡＳＩＣ３０の周囲をエポキシ樹脂５０で封止する。このエポキシ樹脂５０は後に述べるバンプ５３およびビア５２に比べてヤング率が小さい。
（ｃ）樹脂５０に例えばレーザやリソグラフィによりビアホール５１を形成する。 (B) The periphery of the ASIC 30 mounted on the rewiring layer 20 is sealed with an epoxy resin 50. This epoxy resin 50 has a Young's modulus smaller than bumps 53 and vias 52 described later.
(C) A via hole 51 is formed in the resin 50 by, for example, laser or lithography.

（ｄ）上記ビアホール５１内に導電性材料（例えばＣｕやＮｉ）をメッキすることにより充填しビア５２を形成する。このビア５２の最表層にはＡｕ等の酸化防止膜を形成してもよい。
（ｅ）ビア５２の最表層に外部端子としてのバンプ５３を形成する。 (D) The via hole 51 is formed by filling the via hole 51 by plating with a conductive material (for example, Cu or Ni). An antioxidant film such as Au may be formed on the outermost layer of the via 52.
(E) A bump 53 as an external terminal is formed on the outermost layer of the via 52.

これにより図８に示すような電子部品１０２を構成する。但し図８では樹脂５０内の構成を示すために、樹脂部分を仮想的に分離して表している。   Thus, an electronic component 102 as shown in FIG. 8 is configured. However, in FIG. 8, in order to show the structure in the resin 50, the resin part is virtually separated and shown.

《第５の実施形態》
図９は第５の実施形態に係る複合電子部品の製造時の各工程での断面図である。また図１０は完成した複合電子部品の斜視図である。 << Fifth Embodiment >>
FIG. 9 is a cross-sectional view at each step during the manufacture of the composite electronic component according to the fifth embodiment. FIG. 10 is a perspective view of the completed composite electronic component.

この電子部品の製造工程を、図９中の記号に合わせて順に説明する。
（ａ）第１の実施形態として示した図２の（ｊ）の段階での電子部品（図２のバンプ２７を形成する前の状態）である。 The manufacturing process of this electronic component will be described in order according to the symbols in FIG.
(A) It is the electronic component in the stage of (j) of FIG. 2 shown as 1st Embodiment (The state before forming the bump 27 of FIG. 2).

（ｂ）このように再配線層２０を介してＭＥＭＳ素子１０にＡＳＩＣ３０を積層した電子部品を、例えばダイボンダで基板（プリント基板）７０の上に実装する。この時、図１０に示すように基板７０の上にチップコンデンサ等の受動素子６２を実装してもよい。また、基板７０の内部に導体膜の形成等によって受動素子を作りこんでもよい。   (B) The electronic component in which the ASIC 30 is laminated on the MEMS element 10 in this way through the rewiring layer 20 is mounted on the substrate (printed substrate) 70 by, for example, a die bonder. At this time, a passive element 62 such as a chip capacitor may be mounted on the substrate 70 as shown in FIG. Alternatively, a passive element may be built in the substrate 70 by forming a conductor film or the like.

（ｃ）再配線層２０の電極と基板７０上の電極との間をワイヤ−６３でワイヤ−ボンディングする。この時、再配線層２０が超音波振動を吸収して（再配線層２０が超音波振動の緩衝層として作用し）、ＭＥＭＳ素子１０には超音波振動が加わらないのでＭＥＭＳ素子が例えばＭＥＭＳジャイロであっても問題は生じない。   (C) Wire-bonding between the electrode of the rewiring layer 20 and the electrode on the substrate 70 with a wire 63. At this time, the rewiring layer 20 absorbs the ultrasonic vibration (the rewiring layer 20 acts as a buffer layer for the ultrasonic vibration), and no ultrasonic vibration is applied to the MEMS element 10, so that the MEMS element is, for example, a MEMS gyro. But there is no problem.

（ｄ）基板７０の上部を金属キャップ８１で覆う。また、この金属キャップ８１に代えて樹脂で封止（樹脂モールド）してもよい。   (D) Cover the upper portion of the substrate 70 with a metal cap 81. Further, instead of the metal cap 81, sealing with resin (resin molding) may be performed.

このようにして図１０に示すような複合電子部品１１０を構成する。なお、基板７０の下面には電子機器の回路基板に実装するための電極を形成していて、回路基板に対して表面実装する。   In this way, the composite electronic component 110 as shown in FIG. 10 is configured. An electrode for mounting on the circuit board of the electronic device is formed on the lower surface of the board 70 and is surface-mounted on the circuit board.

《第６の実施形態》
図１１は第６の実施形態に係る複合電子部品の斜視図である。但しその内部を透視した状態で示している。図１１において電子部品１０２は第４の実施形態として図８に示したものと同様の電子部品である。これを基板（プリント基板）７０上に実装（マウント）する。また基板７０の上にはチップコンデンサ等の受動素子６２を実装してもよい。基板７０の上は金属キャップで覆うか樹脂８０で封止する。
このようにして電子部品１０２と基板７０とを含む複合電子部品１１１を構成する。 << Sixth Embodiment >>
FIG. 11 is a perspective view of a composite electronic component according to the sixth embodiment. However, the inside is shown in a transparent state. In FIG. 11, an electronic component 102 is the same electronic component as that shown in FIG. 8 as the fourth embodiment. This is mounted (mounted) on a substrate (printed substrate) 70. A passive element 62 such as a chip capacitor may be mounted on the substrate 70. The top of the substrate 70 is covered with a metal cap or sealed with a resin 80.
In this way, the composite electronic component 111 including the electronic component 102 and the substrate 70 is configured.

次に、ＭＥＭＳ素子とＡＳＩＣとを再配線層を介して積層した構造のその他の構成例について図１２〜図１４を参照して説明する。   Next, another configuration example of a structure in which a MEMS element and an ASIC are stacked via a rewiring layer will be described with reference to FIGS.

図１２に示す例では、先ずＭＥＭＳ素子１０、再配線層２０およびＡＳＩＣ３０をそれぞれウエハーレベルで積層し、加熱・加圧によって層間を接合し、ウエハー状態のＭＥＭＳ素子１０側からビアホールを形成し、そのビアホール内に導電性材料を充填することのよってビア９０を形成する。その後、ウエハー状態のＭＥＭＳ素子の図における下面側に樹脂膜１２を形成し、バンプ１３を形成する部分を開口し、その開口部にバンプ１３を形成する。   In the example shown in FIG. 12, the MEMS element 10, the redistribution layer 20 and the ASIC 30 are first laminated at the wafer level, the layers are bonded by heating and pressing, and a via hole is formed from the MEMS element 10 side in the wafer state. A via 90 is formed by filling the via hole with a conductive material. Thereafter, the resin film 12 is formed on the lower surface side in the drawing of the MEMS element in the wafer state, a portion where the bump 13 is formed is opened, and the bump 13 is formed in the opening.

その後、ビア９０の中心線を通る位置でウエハーを切断・ブレイクすることによって単体の電子部品を得る。このことによって電子部品の側面にビア９０が設けられた構成となり、これらのビア９０がＭＥＭＳ素子１０とＡＳＩＣ３０との間で電気的接続を行う。
再配線層２０の内部には薄膜導体層による受動素子を作りこんでもよい。 Thereafter, the wafer is cut and broken at a position passing through the center line of the via 90 to obtain a single electronic component. As a result, vias 90 are provided on the side surfaces of the electronic component, and these vias 90 provide electrical connection between the MEMS element 10 and the ASIC 30.
A passive element using a thin film conductor layer may be formed inside the redistribution layer 20.

図１３に示す例では、ＭＥＭＳ素子１０と再配線層２０とをウエハーレベルで積層し、再配線層２０の上に個別のＡＳＩＣ３０を実装する。この時、再配線層２０の上に受動素子６１を実装してもよい。この再配線層２０の上部にはＡＳＩＣ３０および受動素子６１を樹脂８０で封止する。その後、ＭＥＭＳ素子１０と再配線層２０との積層状態のウエハーを切断・ブレイクする。   In the example shown in FIG. 13, the MEMS element 10 and the rewiring layer 20 are stacked at the wafer level, and an individual ASIC 30 is mounted on the rewiring layer 20. At this time, the passive element 61 may be mounted on the rewiring layer 20. The ASIC 30 and the passive element 61 are sealed with a resin 80 on the rewiring layer 20. Thereafter, the wafer in a stacked state of the MEMS element 10 and the rewiring layer 20 is cut and broken.

図１４に示す例は、図１２で示した電子部品とともに受動素子６２を基板７０の上に実装して樹脂８０でモールドしたものである。   In the example shown in FIG. 14, the passive element 62 is mounted on the substrate 70 together with the electronic components shown in FIG.

このような構成によりＭＥＭＳ素子１０およびＡＳＩＣ３０に対する衝撃・応力が緩和できる。   With such a configuration, impact and stress on the MEMS element 10 and the ASIC 30 can be relaxed.

それぞれ小型化されたＭＥＭＳ素子およびＡＳＩＣの構造を示す図である。It is a figure which shows the structure of the MEMS element and ASIC which were each reduced in size. 第１の実施形態に係る電子部品の製造時の各工程での断面図である。It is sectional drawing in each process at the time of manufacture of the electronic component which concerns on 1st Embodiment. 同電子部品の斜視図である。It is a perspective view of the electronic component. 第２の実施形態に係る電子部品の製造時の各工程での断面図である。It is sectional drawing in each process at the time of manufacture of the electronic component which concerns on 2nd Embodiment. 第３の実施形態に係る電子部品の製造時の各工程での断面図である。It is sectional drawing in each process at the time of manufacture of the electronic component which concerns on 3rd Embodiment. 同電子部品の断面図である。It is sectional drawing of the same electronic component. 第４の実施形態に係る電子部品の製造時の各工程での断面図である。It is sectional drawing in each process at the time of manufacture of the electronic component which concerns on 4th Embodiment. 同電子部品の斜視図である。It is a perspective view of the electronic component. 第５の実施形態に係る複合電子部品の製造時の各工程での断面図である。It is sectional drawing in each process at the time of manufacture of the composite electronic component which concerns on 5th Embodiment. 同複合電子部品の斜視図である。It is a perspective view of the composite electronic component. 第６の実施形態に係る複合電子部品の斜視図である。It is a perspective view of the composite electronic component which concerns on 6th Embodiment. 他の複合電子部品の斜視図である。It is a perspective view of another composite electronic component. 他の複合電子部品の斜視図である。It is a perspective view of another composite electronic component. 他の複合電子部品の斜視図である。It is a perspective view of another composite electronic component.

符号の説明Explanation of symbols

１０−ＭＥＭＳ素子
１１−接合電極
１２−応力緩和層
１３−バンプ
１４−グランド電極
２０−再配線層
２１−接合電極
２２−ビアホール
２３−ビア
２４−配線
２５−外部端子用パッド
２６−接合電極
２７−バンプ
２８−キャビティ
２９−接合電極
３０−ＡＳＩＣ
３１−配線
３２−接合電極
４０−蓋基板
４１−ビアホール
４２−応力緩和層
４３−バンプ
４４−薄膜受動素子
４５−接合電極
４６−ビア
５０−樹脂
５１−ビアホール
５２−ビア
５３−バンプ
６１，６２−受動素子
６３−ワイヤ
７０−基板
８０−樹脂
８１−金属キャップ
９０−ビア
１００，１０１，１０２−電子部品
１１０，１１１−複合電子部品 10-MEMS element 11-Junction electrode 12-Stress relaxation layer 13-Bump 14-Ground electrode 20-Redistribution layer 21-Junction electrode 22-Via hole 23-Via 24-Wiring 25-External terminal pad 26-Junction electrode 27- Bump 28-Cavity 29-Junction electrode 30-ASIC
31-wiring 32-joint electrode 40-lid substrate 41-via hole 42-stress relaxation layer 43-bump 44-thin film passive element 45-joint electrode 46-via 50-resin 51-via hole 52-via 53-bump 61, 62- Passive element 63-Wire 70-Substrate 80-Resin 81-Metal cap 90-Via 100, 101, 102-Electronic component 110, 111-Composite electronic component

Claims (14)

ＭＥＭＳ素子とＡＳＩＣとを備え、前記ＭＥＭＳ素子と前記ＡＳＩＣとを電気的・機械的に接続してなる電子部品において、
前記ＭＥＭＳ素子および前記ＡＳＩＣのそれぞれは、全体に矩形の板状をなし、一方の主面に接合電極を備え、
前記ＭＥＭＳ素子の接合電極に接合される接合電極を第１面に備え、前記ＡＳＩＣの接合電極に接続される接合電極を第１面とは反対の第２面に備え、第１面の接合電極と第２面の接合電極との間を導通させる配線を備えた再配線層を有し、
前記ＭＥＭＳ素子と前記ＡＳＩＣとの間に前記再配線層を介在させた電子部品。 In an electronic component comprising a MEMS element and an ASIC and electrically and mechanically connecting the MEMS element and the ASIC,
Each of the MEMS element and the ASIC has a rectangular plate shape as a whole, and includes a bonding electrode on one main surface,
A bonding electrode bonded to the bonding electrode of the MEMS element is provided on the first surface, a bonding electrode connected to the bonding electrode of the ASIC is provided on the second surface opposite to the first surface, and the bonding electrode on the first surface And a rewiring layer provided with wiring for conducting between the first electrode and the bonding electrode on the second surface,
An electronic component in which the rewiring layer is interposed between the MEMS element and the ASIC. 前記ＡＳＩＣの実装領域は前記再配線層の領域より狭く、前記再配線層に対する前記ＡＳＩＣの実装領域外の前記再配線層の第２面に、前記ＡＳＩＣの実装高さより高い複数のバンプを備え、これらのバンプの少なくとも幾つかは前記再配線層の第１面または第２面の接合電極と電気的に導通している、請求項１に記載の電子部品。   The mounting area of the ASIC is narrower than the area of the rewiring layer, and the second surface of the rewiring layer outside the mounting area of the ASIC with respect to the rewiring layer includes a plurality of bumps higher than the mounting height of the ASIC, 2. The electronic component according to claim 1, wherein at least some of the bumps are electrically connected to the bonding electrode on the first surface or the second surface of the rewiring layer. 前記再配線層の前記第２面にキャビティを形成し、該キャビティの底面に前記ＡＳＩＣを実装してなる請求項２に記載の電子部品。   The electronic component according to claim 2, wherein a cavity is formed on the second surface of the rewiring layer, and the ASIC is mounted on a bottom surface of the cavity. 前記キャビティの周縁部に、前記再配線層の第１面または第２面に備えた接合電極に導通する接合電極を有し、前記キャビティを覆う蓋を備え、該蓋の外面に、前記キャビティ周縁部の接合電極に導通するバンプを設けた請求項３に記載の電子部品。   The peripheral edge of the cavity has a bonding electrode that is electrically connected to the bonding electrode provided on the first surface or the second surface of the redistribution layer, and includes a lid that covers the cavity. The electronic component according to claim 3, wherein bumps that are electrically connected to the bonding electrodes of the portions are provided. 前記蓋の内面に、前記再配線層の第１面または第２面に備えた接合電極に導通する薄膜受動素子を形成した請求項４に記載の電子部品。   The electronic component according to claim 4, wherein a thin-film passive element that is electrically connected to a bonding electrode provided on the first surface or the second surface of the rewiring layer is formed on the inner surface of the lid. 前記蓋の外面に、当該蓋よりヤング率の小さな応力緩和層を設けた請求項４または５に記載の電子部品。   The electronic component according to claim 4, wherein a stress relaxation layer having a Young's modulus smaller than that of the lid is provided on the outer surface of the lid. 前記ＡＳＩＣは樹脂により封止され、該樹脂に前記再配線層の第１面または第２面の接合電極と電気的に導通するビアを備え、該ビアにバンプを設けた請求項１に記載の電子部品。   The ASIC is sealed with a resin, and the resin includes a via electrically connected to the bonding electrode on the first surface or the second surface of the rewiring layer, and the via is provided with a bump. Electronic components. 前記樹脂は前記バンプおよび前記ビアに比べてヤング率が小さい請求項７に記載の電子部品。   The electronic component according to claim 7, wherein the resin has a Young's modulus smaller than that of the bump and the via. 前記再配線層に、前記第１面または第２面の接合電極に導通する薄膜受動素子を形成した請求項１〜８のうちいずれか１項に記載の電子部品。   The electronic component according to any one of claims 1 to 8, wherein a thin-film passive element that conducts to the bonding electrode on the first surface or the second surface is formed on the rewiring layer. 請求項１に記載の電子部品を、前記ＭＥＭＳ素子を実装面として基板に実装し、前記再配線層の第２面にワイヤーボンディング用パッドを形成し、該ワイヤーボンディング用パッドと前記基板上の電極との間をワイヤーボンディングしてなる複合電子部品。   The electronic component according to claim 1 is mounted on a substrate using the MEMS element as a mounting surface, a wire bonding pad is formed on the second surface of the redistribution layer, the wire bonding pad and an electrode on the substrate Composite electronic parts formed by wire bonding between the two. 請求項２〜９のうちいずれか１項に記載の電子部品を、前記バンプを介して基板に実装し、該基板に前記電子部品を覆う金属キャップを取り付けてなる複合電子部品。   A composite electronic component obtained by mounting the electronic component according to any one of claims 2 to 9 on a substrate via the bump, and attaching a metal cap that covers the electronic component to the substrate. 請求項２〜９のうちいずれか１項に記載の電子部品を、前記バンプを介して基板に実装し、該基板上で前記電子部品全体を樹脂封止してなる複合電子部品。   A composite electronic component obtained by mounting the electronic component according to any one of claims 2 to 9 on a substrate via the bumps and resin-sealing the entire electronic component on the substrate. 前記基板に、前記電子部品と電気的に導通する実装電極を形成するとともに、該実装電極に受動素子を実装した請求項１０〜１２のうちいずれか１項に記載の複合電子部品。   The composite electronic component according to claim 10, wherein a mounting electrode that is electrically connected to the electronic component is formed on the substrate, and a passive element is mounted on the mounting electrode. 前記基板の内部に、前記電子部品と電気的に導通する導体膜からなる受動素子を形成した請求項１０〜１３のうちいずれか１項に記載の複合電子部品。   The composite electronic component according to any one of claims 10 to 13, wherein a passive element made of a conductive film that is electrically conductive with the electronic component is formed inside the substrate.
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