JP2008047791A - Semiconductor device, its manufacturing method, and semiconductor integrated circuit device - Google Patents

Semiconductor device, its manufacturing method, and semiconductor integrated circuit device Download PDF

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JP2008047791A
JP2008047791A JP2006223881A JP2006223881A JP2008047791A JP 2008047791 A JP2008047791 A JP 2008047791A JP 2006223881 A JP2006223881 A JP 2006223881A JP 2006223881 A JP2006223881 A JP 2006223881A JP 2008047791 A JP2008047791 A JP 2008047791A
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dummy gate
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JP5092313B2 (en
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So Kurata
創 倉田
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method; and a manufacturing method which elevates a high frequency characteristic of a high dielectric strength transistor having a dummy gate, and improves its variation of manufacture for a semiconductor integrated circuit device. <P>SOLUTION: The dummy gate 5 is located on a first drain area 2 of low concentration; and a second drain area 8 of low concentration which is thinner than the first drain area 2 of low concentration, and self-matches with a main gate 4, at the place between the dummy gate 5 and an adjacent main gate 4. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は半導体装置、その製造方法、及び、半導体集積回路装置に関するものであり、特に、信号を入力する主ゲートに隣接するダミーゲートをもつ高耐圧トランジスタの高周波特性を向上するための構成に特徴のある半導体装置、その製造方法、及び、半導体集積回路装置に関するものである。   The present invention relates to a semiconductor device, a method for manufacturing the same, and a semiconductor integrated circuit device. In particular, the present invention is characterized by a configuration for improving high-frequency characteristics of a high voltage transistor having a dummy gate adjacent to a main gate for inputting a signal. The present invention relates to a semiconductor device, a manufacturing method thereof, and a semiconductor integrated circuit device.

携帯電話などの移動体通信機器の送信部分で用いられる高周波の電力増幅素子として、高耐圧のＭＯＳＦＥＴが用いられているが、このトランジスタでは良好な高周波特性のみならず、ドレイン耐圧が大きいこと、低コストでＣＭＯＳ集積回路と同一チップに集積化できることを期待されている。   A high voltage MOSFET is used as a high frequency power amplifying element used in a transmission part of a mobile communication device such as a mobile phone. This transistor has not only good high frequency characteristics but also a large drain breakdown voltage, It is expected that it can be integrated on the same chip as the CMOS integrated circuit at low cost.

従来、このような高耐圧のＭＯＳＦＥＴは、低濃度のドレイン領域をレジストによってマスクするプロセスを用いて形成していた（例えば、特許文献１参照）。   Conventionally, such a high breakdown voltage MOSFET has been formed using a process of masking a low concentration drain region with a resist (see, for example, Patent Document 1).

このような製造方法では、
ａ．ゲートに位置あわせするマスク工程が必要でゲートの微細化が困難になる、
ｂ．ゲート注入をソース・ドレイン注入と一括で行えないため工程が増える、
ｃ．低濃度のドレイン領域がシリサイド化されないように追加の工程が必要になる、
などの問題点がある。 In such a manufacturing method,
a. A mask process that aligns with the gate is necessary, making it difficult to make the gate finer.
b. Since gate injection cannot be performed at the same time as source / drain injection, the number of processes increases.
c. An additional step is required to prevent the low concentration drain region from being silicided.
There are problems such as.

一方、このような問題を解決するものとして、ダミーゲートとサイドウォールスペーサによって高濃度のソース・ドレイン注入をマスクすることが提案されている（例えば、特許文献２参照）。
この提案によって、上述のｂ及びｃの問題点を解決することができる。
特開平１１−１８６５４３号公報 特開２００４−２３５５２７号公報 On the other hand, as a solution to such a problem, it has been proposed to mask high concentration source / drain implantation by a dummy gate and a sidewall spacer (see, for example, Patent Document 2).
This proposal can solve the above-mentioned problems b and c.
Japanese Patent Laid-Open No. 11-186543 JP 2004-235527 A

しかし、上述の特許文献２の場合には、低濃度のドレイン領域をあらかじめ形成しておいて、その上にダミーゲートを配置し、且つ、主ゲートと前記低濃度ドレイン領域がオーバーラップするように位置あわせをしなければならないため、上記のａの問題点、即ち、ゲートの微細化が困難であるという問題点が依然として解決されないという問題がある。   However, in the case of the above-mentioned Patent Document 2, a low-concentration drain region is formed in advance, a dummy gate is disposed thereon, and the main gate and the low-concentration drain region overlap each other. Since the alignment has to be performed, there is a problem that the problem a described above, that is, the problem that it is difficult to miniaturize the gate is still not solved.

また、ダミーゲートが電気的にフローティングになっているため、寄生容量Ｃdgが増えてしまうおそれがあり、それによって、高周波特性が悪い、特性のばらつきが大きいなどの問題がある。 Further, since the dummy gate is electrically floating, the parasitic capacitance C dg may increase, thereby causing problems such as poor high frequency characteristics and large variations in characteristics.

したがって、本発明は、ダミーゲートを有する高耐圧トランジスタの高周波特性を向上するとともに製造バラツキを改善することを目的とする。   Accordingly, an object of the present invention is to improve high-frequency characteristics of a high voltage transistor having a dummy gate and to improve manufacturing variations.

図１は本発明の原理的構成図であり、ここで図１を参照して、本発明における課題を解決するための手段を説明する。
なお、図における符号３，６は、それぞれゲート絶縁膜及びサイドウォールである。
図１参照
上記の課題を解決するために、本発明は、半導体装置において、第１の低濃度ドレイン領域２上にダミーゲート５を有するとともに、ダミーゲート５と隣接する主ゲート４との間に第１の低濃度ドレイン領域２より浅く且つ、主ゲート４及びダミーゲート５に自己整合する第２の低濃度ドレイン領域８を有することを特徴とする。 FIG. 1 is a block diagram showing the principle of the present invention, and means for solving the problems in the present invention will be described with reference to FIG.
Reference numerals 3 and 6 in the figure denote a gate insulating film and a sidewall, respectively.
To solve the above-described problem, the present invention provides a semiconductor device having a dummy gate 5 on the first low-concentration drain region 2 and between the dummy gate 5 and the adjacent main gate 4. The second lightly doped drain region 8 is shallower than the first lightly doped drain region 2 and self-aligns with the main gate 4 and the dummy gate 5.

このような構成にすることによって、低濃度ドレイン層と主ゲート４が十分にオーバーラップしないことによる寄生抵抗の増大を回避でき、特性のばらつきも抑制できる。
また、第１の低濃度ドレイン領域２と主ゲート４に位置合わせが不要になるため、主ゲート４のゲート長を短くでき、それによって、高周波特性を改善できる。 By adopting such a configuration, it is possible to avoid an increase in parasitic resistance due to the low-concentration drain layer and the main gate 4 not sufficiently overlapping, and to suppress variation in characteristics.
Further, since it is not necessary to align the first low-concentration drain region 2 and the main gate 4, the gate length of the main gate 4 can be shortened, thereby improving the high frequency characteristics.

この場合、ダミーゲート５が、ソース領域または基板１のいずれかに接続されていることが望ましく、それによって、ダミーゲート５が電気的にフローティングにならないため、寄生容量Ｃdgが増えることがなく、高周波特性が高周波特性が向上する。 In this case, it is desirable that the dummy gate 5 is connected to either the source region or the substrate 1, and thereby the dummy gate 5 does not float electrically, so that the parasitic capacitance C dg does not increase, High frequency characteristics improve high frequency characteristics.

例えば、ダミーゲート５のソース領域または基板１のいずれかへの接続が、ダミーゲート５へのコンタクトプラグ９と上層配線層１０を用いて行われること、特に、上層配線層１０が主ゲート４を覆うように配置されていることが望ましく、それによって、主ゲート４の電界をシールドすることができる。   For example, the connection to either the source region of the dummy gate 5 or the substrate 1 is performed using the contact plug 9 and the upper wiring layer 10 to the dummy gate 5, and in particular, the upper wiring layer 10 connects the main gate 4. It is desirable to arrange so that the electric field of the main gate 4 can be shielded.

また、主ゲート４とダミーゲート５の間の間隙は、ゲート側壁に形成するサイドウォールスペーサ７によって埋め込まれていることが望ましく、それによって、高濃度のソース・ドレイン注入工程における注入イオンをマスクすることができ、工程数の低減が可能になる。   The gap between the main gate 4 and the dummy gate 5 is preferably filled with a sidewall spacer 7 formed on the gate sidewall, thereby masking implanted ions in the high concentration source / drain implantation step. And the number of processes can be reduced.

また、製造方法としては、第２の低濃度ドレイン領域８を、主ゲート４とダミーゲート５の形成後に主ゲート４とダミーゲート５に対して自己整合的にイオン注入によって形成すれば良く、それによって、位置合わせが不要になるのでゲートの微細化が可能になる。   As a manufacturing method, the second lightly doped drain region 8 may be formed by ion implantation in a self-aligned manner with respect to the main gate 4 and the dummy gate 5 after the main gate 4 and the dummy gate 5 are formed. This eliminates the need for alignment and enables gate miniaturization.

また、集積化する場合には、第１の低濃度ドレイン領域２を、第１の低濃度ドレインが第１導電型である場合、相補型電界効果型半導体装置（ＣＭＯＳ）プロセスにおける第１導電型ウエル領域の形成工程を利用して同時に形成することが望ましく、それによって、工程数の増大を抑えることができ、低コスト化が可能になる。   In the case of integration, the first low-concentration drain region 2 is used as the first conductive type in the complementary field-effect semiconductor device (CMOS) process when the first low-concentration drain is of the first conductive type. It is desirable to form well regions simultaneously using a well region forming step, whereby the increase in the number of steps can be suppressed and the cost can be reduced.

なお、このような製造工程は、ｎチャネル型素子或いはｐチャネル型素子のいずれかに対して行っても良いし、或いは、ｎチャネル型素子またはｐチャネル型素子の両方について行っても良いものである。   Such a manufacturing process may be performed for either an n-channel element or a p-channel element, or may be performed for both an n-channel element or a p-channel element. is there.

また、半導体集積回路装置を構成する場合には、上述の半導体装置を、相補型電界効果型（ＣＭＯＳ）ロジック、メモリー、及び、アナログ回路と同一基板上にモノリシックに集積化すれば良い。   In the case of configuring a semiconductor integrated circuit device, the above-described semiconductor device may be monolithically integrated on the same substrate as the complementary field effect (CMOS) logic, memory, and analog circuit.

本発明によれば、ＬＤＤ（Ｌｉｇｈｔｌｙ Ｄｏｐｅｄ Ｄｒａｉｎ）領域を主ゲートと低濃度ドレイン領域上に設けたダミーゲートに対して自己整合的に形成することによって、製造工程数を増加することなく、高耐圧トランジスタの高周波特性を向上することができるとともに、低コスト化が可能になる。   According to the present invention, an LDD (Lightly Doped Drain) region is formed in a self-aligned manner with respect to a dummy gate provided on a main gate and a lightly doped drain region, thereby increasing the number of manufacturing steps without increasing the number of manufacturing steps. The high frequency characteristics of the transistor can be improved and the cost can be reduced.

本発明は、第１の低濃度ドレイン領域上にダミーゲートを設けるともに、主ゲートとダミーゲートをマスクとしてイオン注入することによって第２の低濃度ドレイン領域、即ち、ＬＤＤ領域を自己整合的に形成したのち、サイドウォールを形成して主ゲートとダミーゲートの間隙をサイドウォールスペーサで埋め込み、次いで、主ゲート、ダミーゲート及びサイドウォールマスクとしてイオン注入することによって高濃度ソース・ドレイン領域を形成したのち、シリサイドプロセスによって主ゲート、ダミーゲート及び高濃度ソース・ドレイン領域上にシリサイド電極を形成し、次いで、コンタクトプラグ及び上層配線層を利用して主ゲートを覆うように、ダミーゲートと高濃度ソース領域を接続する接続電極を形成するものである。   In the present invention, a dummy gate is provided on the first lightly doped drain region, and a second lightly doped drain region, that is, an LDD region is formed in a self-aligned manner by ion implantation using the main gate and the dummy gate as a mask. After forming the sidewall, the gap between the main gate and the dummy gate is filled with a sidewall spacer, and then ion implantation is performed as the main gate, the dummy gate, and the sidewall mask to form the high concentration source / drain regions. A silicide electrode is formed on the main gate, the dummy gate and the high concentration source / drain region by a silicide process, and then the dummy gate and the high concentration source region are covered with the contact plug and the upper wiring layer so as to cover the main gate. The connection electrode which connects is formed.

この場合、第１の低濃度ドレイン領域のイオン注入工程をＣＭＯＳプロセスのＮウエル注入と共通の工程とし、ＬＤＤ注入を、ＣＭＯＳプロセスのＩ／Ｏ用トランジスタの注入と共通の工程とすれば、ＣＭＯＳプロセスに対してまったく追加の工程無しで高耐圧トランジスタを作製できる。   In this case, if the ion implantation step of the first low-concentration drain region is a step common to the N well implantation of the CMOS process and the LDD implantation is a step common to the implantation of the I / O transistor of the CMOS process, the CMOS A high voltage transistor can be fabricated without any additional steps to the process.

ここで、図２乃至図５を参照して、本発明の実施例１の高耐圧ＭＯＳＦＥＴの製造工程を説明する。
図２参照
まず、ｐ型不純物濃度が例えば、１．０×１０15ｃｍ-3のｐ型シリコン基板１１にシャロートレンチアイソレーション（Ｓｈａｌｌｏｗ Ｔｒｅｎｃｈ Ｉｓｏｌａｔｉｏｎ）構造の素子分離領域１２を形成したのち、Ｂをイオン注入することによってＢ濃度が例えば、１．０×１０16ｃｍ-3で深さが３５０ｎｍのｐ型ウエル領域１３を形成する。 Here, with reference to FIG. 2 thru | or FIG. 5, the manufacturing process of the high voltage | pressure-resistant MOSFET of Example 1 of this invention is demonstrated.
See Figure 2
First, an element isolation region 12 having a shallow trench isolation structure is formed on a p-type silicon substrate 11 having a p-type impurity concentration of, for example, 1.0 × 10 15 cm −3 , and then B is ion-implanted. Thus, the p-type well region 13 having a B concentration of, for example, 1.0 × 10 16 cm −3 and a depth of 350 nm is formed.

次いで、レジストパターン１４をマスクとして、ＣＭＯＳプロセスのｎ型ウエル領域を形成工程を利用してｐ型ウエル領域１３にＰをイオン注入してＰ濃度が例えば、１．０×１０16ｃｍ-3で深さが３００ｎｍのｎ型ウエル領域１５を形成する。 Next, using the resist pattern 14 as a mask, P is ion-implanted into the p-type well region 13 using a process for forming an n-type well region of a CMOS process, and the P concentration is, for example, 1.0 × 10 16 cm −3 . An n-type well region 15 having a depth of 300 nm is formed.

次いで、レジストパターン１４を除去したのち、熱酸化を行うことによって、表面に厚さが、例えば、６ｎｍのゲート絶縁膜１６を形成する。   Next, after removing the resist pattern 14, thermal oxidation is performed to form a gate insulating film 16 having a thickness of, for example, 6 nm on the surface.

図３参照
次いで、全面に多結晶シリコン膜を堆積させたのち、フォトリソグラフィー工程を利用してパターニングすることによって幅が例えば、３００ｎｍのゲート電極１７と幅が例えば、３００ｎｍのダミーゲート１８とを形成するとともに、ゲート絶縁膜１６の露出部もエッチング除去する。
なお、ゲート電極１７とダミーゲート１８との間隙は例えば、２００ｎｍとする。 See Figure 3
Next, after depositing a polycrystalline silicon film on the entire surface, patterning is performed using a photolithography process to form a gate electrode 17 having a width of, for example, 300 nm and a dummy gate 18 having a width of, for example, 300 nm, The exposed portion of the gate insulating film 16 is also removed by etching.
Note that the gap between the gate electrode 17 and the dummy gate 18 is, for example, 200 nm.

次いで、ゲート電極１７とダミーゲート１８をマスクとして、ＣＭＯＳプロセスのＩ／Ｏ用トランジスタの注入工程を利用してＰをイオン注入することによって、Ｐ濃度が例えば、１．０×１０19ｃｍ-3で深さが５０ｎｍのｎ型ＬＤＤ領域１９を形成する。 Next, using the gate electrode 17 and the dummy gate 18 as a mask, P is ion-implanted using an I / O transistor implantation process in a CMOS process, so that the P concentration is, for example, 1.0 × 10 19 cm −3. Thus, an n-type LDD region 19 having a depth of 50 nm is formed.

次いで、ＣＶＤ法を用いて全面にＳｉＯ2 膜２０を、ゲート電極１７とダミーゲート１８との間隙を完全に埋め込むように厚く堆積させる。 Next, the SiO 2 film 20 is deposited thickly on the entire surface by CVD so as to completely fill the gap between the gate electrode 17 and the dummy gate 18.

図４参照
次いで、異方性エッチングを施すことによって、ゲート電極１７とダミーゲート１８の側壁にサイドウォール２１を形成する。
この時、ゲート電極１７とダミーゲート１８との間隙はサイドウォールスペーサ２２で埋め込まれる。 See Figure 4
Next, sidewalls 21 are formed on the side walls of the gate electrode 17 and the dummy gate 18 by performing anisotropic etching.
At this time, the gap between the gate electrode 17 and the dummy gate 18 is filled with the sidewall spacer 22.

次いで、ゲート電極１７、ダミーゲート１８、サイドウォール２１、及び、サイドウォールスペーサ２２をマスクとしてイオン注入することによって、Ｐ濃度が例えば、５．０×１０20ｃｍ-3で深さが１００ｎｍのｎ+ 型ドレイン領域２３及びｎ+ 型ソース領域２４を形成する。
次いで、活性化アニール処理を行うことによって、注入した各イオンを活性化する。 Next, ion implantation is performed using the gate electrode 17, the dummy gate 18, the side wall 21, and the side wall spacer 22 as a mask, so that the P concentration is, for example, 5.0 × 10 20 cm −3 and the depth is 100 nm. A + type drain region 23 and an n + type source region 24 are formed.
Next, an activation annealing process is performed to activate the implanted ions.

次いで、全面にＣｏ膜を堆積させたのち、熱処理を行うことによってｎ+ 型ドレイン領域２３、ｎ+ 型ソース領域２４、ゲート電極１７及びダミーゲート１８の表面にＣｏシリサイド膜２５，２６を形成し、未反応のＣｏ膜をウォッシュアウトしたのち、二次熱処理を行うことによってＣｏシリサイド膜２５，２６を低抵抗相のＣｏシリサイドに変換する。 Next, after depositing a Co film on the entire surface, heat treatment is performed to form Co silicide films 25 and 26 on the surfaces of the n + -type drain region 23, the n + -type source region 24, the gate electrode 17, and the dummy gate 18. After the unreacted Co film is washed out, a secondary heat treatment is performed to convert the Co silicide films 25 and 26 into low resistance phase Co silicide.

図５参照
次いで、全面にＳｉＮ膜からなるエッチングストッパー層２７、及び、プラズマＴＥＯＳ−ＮＳＧ膜からなる層間絶縁膜２８を順次形成したのち、層間絶縁膜２８の表面を平坦化し、次いで、Ｃｏシリサイド膜２５，２６に達するコンタクトホール２９，３０を形成する。 See Figure 5
Next, an etching stopper layer 27 made of a SiN film and an interlayer insulating film 28 made of a plasma TEOS-NSG film are sequentially formed on the entire surface, and then the surface of the interlayer insulating film 28 is flattened. Contact holes 29 and 30 reaching to are formed.

次いで、例えば、ＴｉＮからなるグルー層３１を堆積した後、例えば、Ｗ層３２をＣＶＤ法により堆積してコンタクトホール内を完全に埋め込み、次いで、層間絶縁膜２８上の不要な金属層をＣＭＰで除去してプラグ３３，３４を形成する。   Next, for example, after depositing a glue layer 31 made of TiN, for example, a W layer 32 is deposited by CVD to completely fill the contact hole, and then an unnecessary metal layer on the interlayer insulating film 28 is formed by CMP. The plugs 33 and 34 are formed by removing.

次いで、全面に上層配線を形成するＣｕ膜を堆積させたのち、所定の形状にパターニングすることによって、ダミーゲート１８とｎ+ 型ソース領域２４とを接続する内部局所配線３５を形成することによって、本発明の実施例１の高耐圧ＭＯＳＦＥＴの基本構成が完成する。 Next, after depositing a Cu film that forms the upper layer wiring on the entire surface, patterning into a predetermined shape, thereby forming the internal local wiring 35 that connects the dummy gate 18 and the n + type source region 24, The basic configuration of the high voltage MOSFET of Example 1 of the present invention is completed.

このように、本発明においては、ダミーゲートを設けた場合にも、自己整合工程を用いてＬＤＤ領域を形成しているので、ｎ型ウエル領域とゲート電極が十分にオーバーラップしないことによる寄生抵抗の増大を回避でき、特性のばらつきも抑制できる。   As described above, in the present invention, even when the dummy gate is provided, the LDD region is formed by using the self-alignment process. Therefore, the parasitic resistance due to the n-type well region and the gate electrode not sufficiently overlapping. Can be avoided, and variations in characteristics can be suppressed.

また、ｎ型ウエル領域とゲート電極の位置合わせが不要になるため、ゲート電極のゲート長を短くでき、それによって、高周波特性を改善できる。   Further, since it is not necessary to align the n-type well region and the gate electrode, the gate length of the gate electrode can be shortened, thereby improving the high frequency characteristics.

さらに、ダミーゲートをｎ+ 型ソース領域に接続してダミーゲートを電気的にフローティングにしていないので、寄生容量Ｃdgが増えることがなく、高周波特性が向上する。 Furthermore, since the dummy gate is not electrically floated by connecting the dummy gate to the n + type source region, the parasitic capacitance C dg does not increase and the high frequency characteristics are improved.

特に、ダミーゲートとｎ+ 型ソース領域を接続する内部局所配線を、ゲート電極を覆うように形成していので、ゲート電極からので電界がシールドされ、それによっても、高周波特性が向上する。 In particular, the internal local wiring that connects the dummy gate and the n + -type source region is formed so as to cover the gate electrode, so that the electric field is shielded from the gate electrode, thereby improving the high-frequency characteristics.

以上、本発明の実施例を説明してきたが、本発明は実施例に記載された構成・条件等に限られるものではなく各種の変更が可能であり、例えば、上記の実施例１に記載した、不純物濃度、深さ、厚さ、ゲート長、間隙長は単なる一例であり、必要とする高耐圧特性及び高周波特性に応じて適宜設定されるものである。   The embodiments of the present invention have been described above, but the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications are possible. For example, the embodiments described in the above-described first embodiment The impurity concentration, depth, thickness, gate length, and gap length are merely examples, and are appropriately set according to the required high breakdown voltage characteristics and high frequency characteristics.

また、上記の実施例においては、ダミーゲートをｎ+ 型ソース領域に接続しているが、実施例に示したように、ｐ型シリコン基板を用いる場合には、ｐ型シリコン基板にダミーゲートを接続しても良いものである。 In the above embodiment, the dummy gate is connected to the n + type source region. However, as shown in the embodiment, when a p type silicon substrate is used, the dummy gate is formed on the p type silicon substrate. It can be connected.

また、上記の実施例の説明においては、高耐圧ＭＯＳＦＥＴをＣＭＯＳロジック、メモリー、及び、アナログ回路とモノリシックに集積化した半導体集積回路装置を念頭に説明しているが、このような高耐圧ＭＯＳＦＥＴはディスクリートデバイスとして個別に形成しても良いものである。
この場合には、各領域の不純物濃度や深さを、他の領域や工程の影響を受けることなく任意に設定することができる。 Further, in the description of the above embodiment, the semiconductor integrated circuit device in which the high voltage MOSFET is monolithically integrated with the CMOS logic, the memory, and the analog circuit is described in mind. It may be formed individually as a discrete device.
In this case, the impurity concentration and depth of each region can be arbitrarily set without being affected by other regions and processes.

また、上記の実施例においては、高耐圧ＭＯＳＦＥＴをｎチャネル型ＭＯＳＦＥＴとして説明しているが、ｐチャネル型ＭＯＳＦＥＴとして形成しても良いものであり、その場合には、上述のｎチャネル型ＭＯＳＦＥＴにおける導電型を逆にすれば良い。
さらには、ｎチャネル型高耐圧ＭＯＳＦＥＴとｐチャネル型高耐圧ＭＯＳＦＥＴを同一基板に形成しても良いものである。 In the above embodiment, the high-breakdown-voltage MOSFET is described as an n-channel MOSFET. However, the high-voltage MOSFET may be formed as a p-channel MOSFET. What is necessary is just to reverse a conductivity type.
Further, the n-channel high voltage MOSFET and the p-channel high voltage MOSFET may be formed on the same substrate.

ここで、再び図１を参照して、本発明の詳細な特徴を改めて説明する。
再び、図１参照
（付記１） 第１の低濃度ドレイン領域２上にダミーゲート５を有するとともに、前記ダミーゲート５と隣接する主ゲート４との間に前記第１の低濃度ドレイン領域２より浅く且つ前記主ゲート４及びダミーゲート５に自己整合する第２の低濃度ドレイン領域８を有することを特徴とする半導体装置。
（付記２） 上記ダミーゲート５が、ソース領域または基板１のいずれかに接続されていることを特徴とする付記１記載の半導体装置。
（付記３） 上記ダミーゲート５のソース領域または基板１のいずれかへの接続が、前記ダミーゲート５へのコンタクトプラグ９と上層配線層１０を用いて行われることを特徴とする付記１または２に記載の半導体装置。
（付記４） 上記ダミーゲート５のソース領域または基板１のいずれかへの接続が、上層配線層１０を用いて行われ、前記上層配線層１０が上記主ゲート４を覆うように配置されていることを特徴とする付記３記載の半導体装置。
（付記５） 上記主ゲート４とダミーゲート５の間の間隙が、ゲート側壁に形成するサイドウォールスペーサ７によって埋め込まれていることを特徴とする付記１乃至４のいずれか１に記載の半導体装置。
（付記６） 第１の低濃度ドレイン領域２上にダミーゲート５を有するとともに、前記ダミーゲート５と隣接する主ゲート４との間に前記第１の低濃度ドレイン領域２より浅い第２の低濃度ドレイン領域８を有する半導体装置の製造方法であって、前記第２の低濃度ドレイン領域８が、前記主ゲート４とダミーゲート５の形成後に主ゲート４とダミーゲート５に対して自己整合的にイオン注入によって形成することを特徴とする半導体装置の製造方法。
（付記７） 上記第１の低濃度ドレイン領域２を、前記第１の低濃度ドレインが第１導電型である場合、相補型電界効果型半導体装置プロセスにおける第１導電型ウエル領域の形成工程を利用して同時に形成することを特徴とする付記６記載の半導体装置の製造方法。
（付記８） 上記製造工程を、ｎチャネル型素子或いはｐチャネル型素子のいずれか、または、ｎチャネル型素子またはｐチャネル型素子の両方について行うことを特徴とする付記６または７に記載の半導体装置の製造方法。
（付記９） 付記１乃至５のいずれか１に記載の半導体装置が、相補型電界効果型ロジック、メモリー、及び、アナログ回路と同一基板上にモノリシックに集積化されていることを特徴とする半導体集積回路装置。 Here, the detailed features of the present invention will be described again with reference to FIG.
Again see Figure 1
(Supplementary Note 1) A dummy gate 5 is provided on the first low-concentration drain region 2, and the main gate is shallower than the first low-concentration drain region 2 between the dummy gate 5 and the adjacent main gate 4. 4 and a second low-concentration drain region 8 that is self-aligned with the dummy gate 5.
(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the dummy gate 5 is connected to either the source region or the substrate 1.
(Supplementary Note 3) The supplementary note 1 or 2 is characterized in that the connection of the dummy gate 5 to either the source region or the substrate 1 is performed using the contact plug 9 and the upper wiring layer 10 to the dummy gate 5. A semiconductor device according to 1.
(Supplementary Note 4) The dummy gate 5 is connected to either the source region or the substrate 1 using the upper wiring layer 10, and the upper wiring layer 10 is disposed so as to cover the main gate 4. The semiconductor device as set forth in Appendix 3, wherein
(Supplementary Note 5) The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein a gap between the main gate 4 and the dummy gate 5 is filled with a sidewall spacer 7 formed on a gate sidewall. .
(Appendix 6) A dummy gate 5 is provided on the first low-concentration drain region 2 and a second low depth shallower than the first low-concentration drain region 2 is provided between the dummy gate 5 and the adjacent main gate 4. A method of manufacturing a semiconductor device having a concentration drain region 8, wherein the second low concentration drain region 8 is self-aligned with respect to the main gate 4 and the dummy gate 5 after the formation of the main gate 4 and the dummy gate 5. A method for manufacturing a semiconductor device, characterized by being formed by ion implantation.
(Supplementary Note 7) When the first low-concentration drain region 2 is the first conductivity type when the first low-concentration drain is of the first conductivity type, the step of forming the first conductivity type well region in the complementary field effect semiconductor device process The method of manufacturing a semiconductor device according to appendix 6, wherein the semiconductor devices are simultaneously formed by using them.
(Supplementary Note 8) The semiconductor according to Supplementary Note 6 or 7, wherein the manufacturing process is performed for either an n-channel element or a p-channel element, or for both an n-channel element or a p-channel element. Device manufacturing method.
(Supplementary Note 9) A semiconductor device in which the semiconductor device according to any one of supplementary notes 1 to 5 is monolithically integrated on the same substrate as a complementary field effect logic, memory, and analog circuit. Integrated circuit device.

本発明の活用例としては、携帯電話などの移動体通信機器の送信部分で用いられる高周波の電力増幅素子が典型的なものであるが、他の用途において高耐圧と高周波特性が求められる場合にも適用されるものである。   As an application example of the present invention, a high-frequency power amplifying element used in a transmission part of a mobile communication device such as a mobile phone is typical. However, when high breakdown voltage and high-frequency characteristics are required in other applications. Is also applicable.

本発明の原理的構成の説明図である。It is explanatory drawing of the fundamental structure of this invention. 本発明の実施例１の高耐圧ＭＯＳＦＥＴの途中までの製造工程の説明図である。It is explanatory drawing of the manufacturing process to the middle of the high voltage | pressure-resistant MOSFET of Example 1 of this invention. 本発明の実施例１の高耐圧ＭＯＳＦＥＴの図２以降の途中までの製造工程の説明図である。It is explanatory drawing of the manufacturing process to the middle after FIG. 2 of the high voltage | pressure-resistant MOSFET of Example 1 of this invention. 本発明の実施例１の高耐圧ＭＯＳＦＥＴの図３以降の途中までの製造工程の説明図である。It is explanatory drawing of the manufacturing process to the middle after FIG. 3 of the high voltage | pressure-resistant MOSFET of Example 1 of this invention. 本発明の実施例１の高耐圧ＭＯＳＦＥＴの図４以降の製造工程の説明図である。It is explanatory drawing of the manufacturing process after FIG. 4 of the high voltage | pressure-resistant MOSFET of Example 1 of this invention.

符号の説明Explanation of symbols

１ 基板
２ 第１の低濃度ドレイン領域
３ ゲート絶縁膜
４ 主ゲート
５ ダミーゲート
６ サイドウォール
７ サイドウォールスペーサ
８ 第２の低濃度ドレイン領域
９ コンタクトプラグ
１０ 上層配線層
１１ ｐ型シリコン基板
１２ 素子分離領域
１３ ｐ型ウエル領域
１４ レジストパターン
１５ ｎ型ウエル領域
１６ ゲート絶縁膜
１７ ゲート電極
１８ ダミーゲート
１９ ｎ型ＬＤＤ領域
２０ ＳｉＯ2 膜
２１ サイドウォール
２２ サイドウォールスペーサ
２３ ｎ+ 型ドレイン領域
２４ ｎ+ 型ソース領域
２５ Ｃｏシリサイド膜
２６ Ｃｏシリサイド膜
２７ エッチングストッパー層
２８ 層間絶縁膜
２９ コンタクトホール
３０ コンタクトホール
３１ グルー層
３２ Ｗ層
３３ プラグ
３４ プラグ
３５ 内部局所配線 DESCRIPTION OF SYMBOLS 1 Substrate 2 First low concentration drain region 3 Gate insulating film 4 Main gate 5 Dummy gate 6 Side wall 7 Side wall spacer 8 Second low concentration drain region 9 Contact plug 10 Upper wiring layer 11 P-type silicon substrate 12 Element isolation Region 13 p-type well region 14 resist pattern 15 n-type well region 16 gate insulating film 17 gate electrode 18 dummy gate 19 n-type LDD region 20 SiO 2 film 21 side wall 22 side wall spacer 23 n + type drain region 24 n + type Source region 25 Co silicide film 26 Co silicide film 27 Etching stopper layer 28 Interlayer insulating film 29 Contact hole 30 Contact hole 31 Glue layer 32 W layer 33 Plug 34 Plug 35 Internal local wiring

Claims (5)

第１の低濃度ドレイン領域上にダミーゲートを有するとともに、前記ダミーゲートと隣接する主ゲートとの間に前記第１の低濃度ドレイン領域より浅く且つ前記主ゲート及びダミーゲートに自己整合する第２の低濃度ドレイン領域を有することを特徴とする半導体装置。 A second gate having a dummy gate on the first lightly doped drain region and being shallower than the first lightly doped drain region and self-aligned with the main gate and the dummy gate between the dummy gate and the adjacent main gate; A low-concentration drain region. 上記ダミーゲートが、ソース領域または基板のいずれかに接続されていることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the dummy gate is connected to either the source region or the substrate. 上記主ゲートとダミーゲートの間の間隙が、ゲート側壁に形成するサイドウォールスペーサによって埋め込まれていることを特徴とする請求項１または２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein a gap between the main gate and the dummy gate is filled with a side wall spacer formed on a gate side wall. 第１の低濃度ドレイン領域上にダミーゲートを有するとともに、前記ダミーゲートと隣接する主ゲートとの間に前記第１の低濃度ドレイン領域より浅い第２の低濃度ドレイン領域を有する半導体装置の製造方法であって、前記第２の低濃度ドレイン領域が、前記主ゲートとダミーゲートの形成後に主ゲートとダミーゲートに対して自己整合的にイオン注入によって形成することを特徴とする半導体装置の製造方法。 Manufacturing of a semiconductor device having a dummy gate on the first lightly doped drain region and a second lightly doped drain region shallower than the first lightly doped drain region between the dummy gate and the adjacent main gate A method of manufacturing a semiconductor device, wherein the second low-concentration drain region is formed by ion implantation in a self-aligned manner with respect to the main gate and the dummy gate after the formation of the main gate and the dummy gate. Method. 請求項１乃至３のいずれか１項に記載の半導体装置が、相補型電界効果型ロジック、メモリー、及び、アナログ回路と同一基板上にモノリシックに集積化されていることを特徴とする半導体集積回路装置。 4. The semiconductor integrated circuit according to claim 1, wherein the semiconductor device according to claim 1 is monolithically integrated on the same substrate as the complementary field effect logic, memory, and analog circuit. apparatus.
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US10923426B2 (en) 2015-11-30 2021-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Standard-cell layout structure with horn power and smart metal cut
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