JP2008041907A - Ld differential drive circuit - Google Patents

Ld differential drive circuit Download PDF

Info

Publication number
JP2008041907A
JP2008041907A JP2006213732A JP2006213732A JP2008041907A JP 2008041907 A JP2008041907 A JP 2008041907A JP 2006213732 A JP2006213732 A JP 2006213732A JP 2006213732 A JP2006213732 A JP 2006213732A JP 2008041907 A JP2008041907 A JP 2008041907A
Authority
JP
Japan
Prior art keywords
terminal
power supply
supply terminal
bias
drive circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006213732A
Other languages
Japanese (ja)
Inventor
Minoru Togashi
稔 富樫
Yotaro Umeda
洋太郎 楳田
Yusuke Otomo
祐輔 大友
Makoto Nakamura
誠 中村
Tomoaki Kawamura
智明 川村
Jun Endo
潤 遠藤
Jun Terada
純 寺田
Kazuyoshi Nishimura
和好 西村
Yuji Akatsu
祐史 赤津
Masahiro Endo
雅広 遠藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Electronics Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NTT Electronics Corp
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NTT Electronics Corp, Nippon Telegraph and Telephone Corp filed Critical NTT Electronics Corp
Priority to JP2006213732A priority Critical patent/JP2008041907A/en
Publication of JP2008041907A publication Critical patent/JP2008041907A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Semiconductor Lasers (AREA)
  • Amplifiers (AREA)
  • Optical Communication System (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the jitter of a current flowing through a laser diode. <P>SOLUTION: An LD differential drive circuit comprises an LD drive circuit 10 having differential output terminals OUT1, OUT2 oututting an LD drive current and an LD bias terminal BB outputting an LD bias current, a transmission line T1 connected between one terminal of a laser diode LD and the output terminal OUT1, a transmission line T2 connected between the other terminal of the laser diode LD and the output terminal OUT2, a bias inductor L1 connected between one terminal of the laser diode LD and an LD power supply terminal VCC2, and a bias resistor R6 connected between the other terminal of the laser diode LD and the LD bias terminal BB. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、入力するバーストデータに応じてレーザダイオード（ＬＤ）を差動駆動するＬＤ差動駆動回路に関するものである。   The present invention relates to an LD differential drive circuit that differentially drives a laser diode (LD) in accordance with input burst data.

従来のＬＤ差動駆動回路を図３に示す（例えば、非特許文献１参照）。レーザダイオードＬＤを差動駆動するＬＤ差動駆動回路は、そのレーザダイオードＬＤとＬＤ電源端子ＶＣＣ２との間に接続されるバイアス用インダクタＬ１、レーザダイオードＬＤとＬＤバイアス端子ＢＢとの間に接続されるバイアス用インダクタＬ２、伝送線路Ｔ１，Ｔ２、その伝送線路Ｔ１，Ｔ２とレーザダイオードＬＤとの間に接続される終端抵抗Ｒ４，Ｒ５、およびＬＤドライブ回路２０からなる。   A conventional LD differential drive circuit is shown in FIG. 3 (see, for example, Non-Patent Document 1). An LD differential drive circuit for differentially driving the laser diode LD is connected between a bias inductor L1 connected between the laser diode LD and the LD power supply terminal VCC2, and between the laser diode LD and the LD bias terminal BB. A bias inductor L2, transmission lines T1 and T2, termination resistors R4 and R5 connected between the transmission lines T1 and T2 and the laser diode LD, and an LD drive circuit 20.

ＬＤドライブ回路２０は、差動回路を構成するトランジスタＱ１，Ｑ２、そのトランジスタＱ１，Ｑ２のコレクタと電源端子ＶＣＣ１との間に接続される負荷抵抗（送端抵抗）Ｒ１，Ｒ２、トランジスタＱ１，Ｑ２のエミッタにコレクタが共通接続されベースが電流制御端子ＶＣＳ１に接続される電流源トランジスタＱ３、トランジスタＱ３のエミッタと接地端子ＧＮＤとの間に接続される電流安定化抵抗Ｒ３、およびレーザダイオードＬＤの出力を一定に制御するためそのレーザダイオードＬＤの後方光をモニタしてバイアス電流をフィードバックする自動光出力制御回路ＡＰＣを備える。前記したトランジスタＱ１，Ｑ２のベースはバーストデータ信号が入力する差動入力端子ＩＮ１，ＩＮ２に接続され、コレクタはバーストデータ信号が出力する差動出力端子ＯＵＴ１，ＯＵＴ２に接続されている。そして、差動出力端子ＯＵＴ１，ＯＵＴ２が前記した伝送線路Ｔ１，Ｔ２に接続され、自動光出力制御回路ＡＰＣがＬＤバイアス端子ＢＢに接続されている。   The LD drive circuit 20 includes transistors Q1 and Q2 constituting a differential circuit, load resistors (transmission resistors) R1 and R2, and transistors Q1 and Q2 connected between the collectors of the transistors Q1 and Q2 and the power supply terminal VCC1. Current collector transistor Q3 whose collector is commonly connected to its emitter and whose base is connected to current control terminal VCS1, current stabilization resistor R3 connected between the emitter of transistor Q3 and ground terminal GND, and the output of laser diode LD Is provided with an automatic light output control circuit APC for monitoring the back light of the laser diode LD and feeding back the bias current. The bases of the transistors Q1 and Q2 are connected to differential input terminals IN1 and IN2 to which burst data signals are input, and the collectors are connected to differential output terminals OUT1 and OUT2 from which burst data signals are output. The differential output terminals OUT1 and OUT2 are connected to the transmission lines T1 and T2, and the automatic light output control circuit APC is connected to the LD bias terminal BB.

このＬＤ差動駆動回路では、差動入力端子ＩＮ１，ＩＮ２に入力するバーストデータ信号が増幅されて差動出力端子ＯＵＴ１，ＯＵＴ２に出力し、レーザダイオードＬＤが差動駆動される。また、自動光出力制御回路ＡＰＣによって、レーザダイオードＬＤの後方光がモニタされ、該モニタ結果に応じたバイアス電流がＬＤバイアス端子ＢＢにフィードバックされ、レーザダイオードＬＤの出力が制御される。   In this LD differential drive circuit, burst data signals input to the differential input terminals IN1 and IN2 are amplified and output to the differential output terminals OUT1 and OUT2, and the laser diode LD is differentially driven. Further, the rear light of the laser diode LD is monitored by the automatic light output control circuit APC, and a bias current corresponding to the monitoring result is fed back to the LD bias terminal BB, thereby controlling the output of the laser diode LD.

K.Sakai, et al."1.3-μm Unlooled DFB Laser-Diode Module With a Coupled Differential Feed for 10-Gb/s Ethernet Applications" I EEE Journal of Lightwave Technology,Vol.22,No.2,2004K. Sakai, et al. "1.3-μm Unlooled DFB Laser-Diode Module With a Coupled Differential Feed for 10-Gb / s Ethernet Applications" I EEE Journal of Lightwave Technology, Vol. 22, No. 2, 2004

ところが、この従来のＬＤ差動駆動回路は、自動光出力制御回路ＡＰＣを、ＬＤバイアス端子ＢＢからバイアス用インダクタＬ２を介して接続していた関係で、そのインダクタＬ２のインダクタンスによりジッタが大きくなっていた。図４(b)にそのレーザダイオードＬＤに流れる電流波形のアイパターン特性を示す。   However, in this conventional LD differential drive circuit, the automatic optical output control circuit APC is connected from the LD bias terminal BB via the bias inductor L2, and the jitter is increased due to the inductance of the inductor L2. It was. FIG. 4B shows the eye pattern characteristics of the current waveform flowing through the laser diode LD.

本発明の目的は、レーザダイオードに流れる電流のジッタを低減にしたＬＤ差動駆動回路を提供することである。   An object of the present invention is to provide an LD differential drive circuit in which jitter of current flowing in a laser diode is reduced.

上記目的を達成するために、請求項１にかかる発明のＬＤ差動駆動回路は、ＬＤ駆動電流が出力する差動形式の第１および第２の出力端子およびＬＤバイアス電流が出力するＬＤバイアス端子を有するＬＤドライブ回路と、レーザダイオードの一方の端子と前記第１の出力端子との間に接続される第１の伝送線路と、前記レーザダイオードの他方の端子と前記第２の出力端子との間に接続される第２の伝送線路と、前記レーザダイオードの前記一方の端子とＬＤ電源端子との間に接続されるインダクタと、前記レーザダイオードの前記他方の端子と前記ＬＤバイアス端子との間に接続されるバイアス抵抗とを有することを特徴とする。
請求項２にかかる発明は、請求項１に記載のＬＤ差動駆動回路において、前記ＬＤドライブ回路が、ＬＤドライブ回路本体とＬＤバイアス回路とからなり、前記ＬＤドライブ回路本体は、第１のトランジスタと第２のトランジスタからなる第１の差動回路と、前記第１のトランジスタのコレクタ又はドレインと第１の電源端子との間に接続される第１の負荷抵抗と、前記第２のトランジスタのコレクタ又はドレインと前記第１の電源端子との間に接続される第２の負荷抵抗と、前記第１および第２のトランジスタのエミッタ又はソースと第２の電源端子に接続された電流源と、前記第１の電源端子と前記第２の電源端子との間に接続される少なくとも１０ｐＦの容量値をもつ第１の電源安定化容量とを備え、前記第１および第２のトランジスタのベース又はゲートが差動入力端子に接続され、前記第１および第２のトランジスタのコレクタ又はドレインが前記第１および第２の出力端子に接続されてなり、前記ＬＤバイアス回路が、第３のトランジスタと第４のトランジスタからなる第２の差動回路と、前記第３のトランジスタのコレクタ又はドレインと第３の電源端子との間に接続される第３の負荷抵抗と、前記第３および第４のトランジスタのエミッタ又はソースにコレクタ又はドレインが接続されベース又はゲートが自動光出力制御回路に接続されソースが第４の電源端子に接続される第５のトランジスタとを備え、前記第４のトランジスタのコレクタ又はドレインが前記ＬＤバイアス端子に接続され、前記第３および第４のトランジスタのベース又はゲートに制御信号が印加するようにしてなる、ことを特徴とする。
請求項３にかかる発明は、請求項２に記載のＬＤ差動駆動回路において、前記第１の電源端子を第５の電源端子と第６の電源端子に分離し、前記第５の電源端子を前記第１の負荷抵抗に接続すると共に前記第６の電源端子を前記第２の負荷抵抗に接続し、前記第１の電源安定化容量に代えて、前記第５の電源端子と前記第２の電源端子との間に、少なくとも１０ｐＦの容量値をもつ第２の電源安定化容量を接続し、前記第６の電源端子と前記第２の電源端子との間に、少なくとも１０ｐＦの容量値をもつ第３の電源安定化容量を接続したことを特徴とする。 To achieve the above object, an LD differential drive circuit according to a first aspect of the present invention includes differential first and second output terminals for outputting an LD drive current and an LD bias terminal for outputting an LD bias current. An LD drive circuit, a first transmission line connected between one terminal of the laser diode and the first output terminal, and the other terminal of the laser diode and the second output terminal. A second transmission line connected in between, an inductor connected between the one terminal of the laser diode and the LD power supply terminal, and between the other terminal of the laser diode and the LD bias terminal. And a bias resistor connected to.
According to a second aspect of the present invention, in the LD differential drive circuit according to the first aspect, the LD drive circuit includes an LD drive circuit main body and an LD bias circuit, and the LD drive circuit main body includes a first transistor. And a first differential circuit comprising a second transistor, a first load resistor connected between a collector or drain of the first transistor and a first power supply terminal, and A second load resistor connected between a collector or drain and the first power supply terminal; a current source connected to the emitter or source of the first and second transistors and a second power supply terminal; A first power stabilization capacitor having a capacitance value of at least 10 pF connected between the first power supply terminal and the second power supply terminal, and the first and second transistors. The base or gate of the first and second transistors is connected to the differential input terminal, the collectors or drains of the first and second transistors are connected to the first and second output terminals. A second differential circuit composed of a transistor and a fourth transistor; a third load resistor connected between a collector or drain of the third transistor and a third power supply terminal; A fourth transistor having a collector or drain connected to the emitter or source of the fourth transistor, a base or gate connected to the automatic light output control circuit, and a source connected to the fourth power supply terminal. The collector or drain of the transistor is connected to the LD bias terminal, and a control signal is applied to the base or gate of the third and fourth transistors. To way comprising, characterized in that.
According to a third aspect of the present invention, in the LD differential drive circuit according to the second aspect, the first power supply terminal is separated into a fifth power supply terminal and a sixth power supply terminal, and the fifth power supply terminal is separated. The sixth power supply terminal is connected to the second load resistance while being connected to the first load resistance, and the fifth power supply terminal and the second power supply are replaced with the first power supply stabilization capacitor. A second power stabilization capacitor having a capacitance value of at least 10 pF is connected between the power supply terminal, and a capacitance value of at least 10 pF is provided between the sixth power supply terminal and the second power supply terminal. A third power supply stabilization capacitor is connected.

本発明によれば、レーザダイオードの一端と自動光出力制御回路の出力とをインダクタではなく、バイアス抵抗を介して接続したので、レーザダイオードに流れる電流のジッタが少ないＬＤ差動駆動回路を実現することができる。また、ＬＤドライブ回路本体の電源端子間に少なくとも１０ｐＦの電源安定化容量を接続することで、そのジッタをより少なくすることができる。   According to the present invention, since one end of the laser diode and the output of the automatic light output control circuit are connected via a bias resistor instead of an inductor, an LD differential drive circuit with less jitter of current flowing through the laser diode is realized. be able to. Further, by connecting a power stabilization capacitor of at least 10 pF between the power supply terminals of the LD drive circuit main body, the jitter can be further reduced.

図１は本発明の実施例のＬＤ差動駆動回路の回路図である。本実施例のＬＤ差動駆動回路は、レーザダイオードＬＤとＬＤ電源端子ＶＣＣ２との間に接続されるバイアス用インダクタＬ１、レーザダイオードＬＤとＬＤバイアス端子ＢＢとの間に接続されるバイアス抵抗Ｒ６、伝送線路Ｔ１，Ｔ２、その伝送線路Ｔ１，Ｔ２とレーザダイオードＬＤとの間に接続される終端抵抗Ｒ４，Ｒ５、およびＬＤドライブ回路１０からなる。ＬＤドライブ回路１０の差動出力端子ＯＵＴ１，ＯＵＴ２は、伝送線路Ｔ１，Ｔ２に接続されている。また、ＬＤバイアス端子ＢＢはＬＤドライブ回路１０に接続されている。   FIG. 1 is a circuit diagram of an LD differential drive circuit according to an embodiment of the present invention. The LD differential drive circuit of this embodiment includes a bias inductor L1 connected between the laser diode LD and the LD power supply terminal VCC2, a bias resistor R6 connected between the laser diode LD and the LD bias terminal BB, It comprises transmission lines T1, T2, termination resistors R4, R5 connected between the transmission lines T1, T2 and the laser diode LD, and an LD drive circuit 10. Differential output terminals OUT1 and OUT2 of the LD drive circuit 10 are connected to transmission lines T1 and T2. The LD bias terminal BB is connected to the LD drive circuit 10.

このように、本実施例では、レーザダイオードＬＤとＬＤバイアス端子ＢＢとの間に、従来のインダクタＬ２に代えて、バイアス抵抗Ｒ６を接続している。このため、レーザダイオードＬＤを流れる電流のジッタを低減できる。図４(a)にその電流波形のアイパターン特性を示した。図４(b)のインダクタＬ１を使用した従来の場合に比べて、ジッタが大幅に低減している。   Thus, in this embodiment, the bias resistor R6 is connected between the laser diode LD and the LD bias terminal BB instead of the conventional inductor L2. For this reason, the jitter of the current flowing through the laser diode LD can be reduced. FIG. 4A shows the eye pattern characteristics of the current waveform. Compared to the conventional case using the inductor L1 of FIG. 4B, the jitter is greatly reduced.

図２は図１に示したＬＤ差動駆動回路において、ＬＤドライブ回路１０の部分を具体化した回路図である。ＬＤドライブ回路１０は、ＬＤドライブ回路本体１１とＬＤバイアス回路１２とからなる。   FIG. 2 is a circuit diagram in which the LD drive circuit 10 is embodied in the LD differential drive circuit shown in FIG. The LD drive circuit 10 includes an LD drive circuit body 11 and an LD bias circuit 12.

ＬＤドライブ回路本体１１は、差動回路を構成するトランジスタＱ１，Ｑ２、そのトランジスタＱ１，Ｑ２のコレクタと電源端子ＶＣＣ１との間に接続される負荷抵抗（送端抵抗）Ｒ１，Ｒ２、トランジスタＱ１，Ｑ２のエミッタにコレクタが共通接続されベースが電流制御端子ＶＣＳ１に接続される電流源トランジスタＱ３、トランジスタＱ３と接地端子ＧＮＤとの間に接続される電流安定化抵抗Ｒ３、電源端子ＶＣＣ１と接地端子ＧＮＤとの間に接続される電源安定化容量Ｃ１を有する。   The LD drive circuit body 11 includes transistors Q1 and Q2 constituting a differential circuit, load resistors (transmission resistors) R1 and R2, and transistors Q1 and Q2 connected between the collectors of the transistors Q1 and Q2 and the power supply terminal VCC1. A current source transistor Q3 whose collector is commonly connected to the emitter of Q2 and whose base is connected to the current control terminal VCS1, a current stabilization resistor R3 connected between the transistor Q3 and the ground terminal GND, a power supply terminal VCC1 and a ground terminal GND And a power supply stabilization capacitor C1 connected between the two.

ＬＤバイアス回路１２は、差動回路を構成するトランジスタＱ４，Ｑ５、そのトランジスタＱ４のコレクタと電源端子ＶＣＣ３との間に接続される負荷抵抗Ｒ７、トランジスタＱ４，Ｑ５のエミッタにコレクタが共通接続されベースが電流制御端子ＶＣＳ２を介して自動光出力制御回路ＡＰＣに接続される電流源トランジスタＱ６、トランジスタＱ６と接地端子ＧＮＤとの間に接続される電流安定化抵抗Ｒ８を有する。そして、トランジスタＱ５のコレクタがＬＤバイアス端子ＢＢに接続されている。   The LD bias circuit 12 includes transistors Q4 and Q5 constituting a differential circuit, a load resistor R7 connected between the collector of the transistor Q4 and the power supply terminal VCC3, and a collector commonly connected to the emitters of the transistors Q4 and Q5. Has a current source transistor Q6 connected to the automatic light output control circuit APC via the current control terminal VCS2, and a current stabilization resistor R8 connected between the transistor Q6 and the ground terminal GND. The collector of the transistor Q5 is connected to the LD bias terminal BB.

このＬＤドライブ回路１０では、電源安定化容量Ｃ１の値を少なくとも１０ｐＦ、好ましくは１００ｐＦに設定することにより、電源端子ＶＣＣ１に電源を供給するパターン配線やワイヤ配線の寄生インダクタンス成分（通常では１ｎＨ程度）による悪影響を回避できる。すなわち、このＬＤドライバ回路１０では、負荷抵抗Ｒ１，Ｒ２に４０ｍＡ以上のＬＤ駆動電流を流す必要があり、このとき、上記の寄生インダクタンスによっても、レーザダイオードＬＤに流れる電流にジッタが生じるが、上記電源安定化容量Ｃ１によって、その寄生インダクタンスによるジッタを低減できる。   In this LD drive circuit 10, by setting the value of the power stabilization capacitor C1 to at least 10 pF, preferably 100 pF, the parasitic inductance component (usually about 1 nH) of the pattern wiring and wire wiring that supplies power to the power supply terminal VCC1 The adverse effect of can be avoided. That is, in this LD driver circuit 10, it is necessary to flow an LD drive current of 40 mA or more through the load resistors R1 and R2, and at this time, the parasitic inductance described above causes jitter in the current flowing through the laser diode LD. The power supply stabilization capacitor C1 can reduce jitter due to the parasitic inductance.

自動光出力制御回路ＡＰＣの出力信号は、イネーブル時、すなわちバイアス制御端子ＩＮ３を“Ｌ”に、ＩＮ４を“Ｈ”に設定したとき、ＬＤバイアス端子ＢＢに電流として供給され、レーザダイオードＬＤの後方光のモニタ結果に応じたバイアス電流がＬＤバイアス端子ＢＢにフィードバックされる。   The output signal of the automatic light output control circuit APC is supplied as a current to the LD bias terminal BB when enabled, that is, when the bias control terminal IN3 is set to “L” and IN4 is set to “H”. A bias current corresponding to the light monitoring result is fed back to the LD bias terminal BB.

なお、以上ではトランジスタＱ１〜Ｑ６としてバイポーラトランジスタを使用した例で説明したが、ＭＯＳトランジスタを使用した場合でも同様に実施することができ、同様の作用効果を得ることができる。このようにＭＯＳトランジスタを使用する場合は、電流源安定化抵抗Ｒ３，Ｒ８は削除することができる。また、ＬＤドライブ回路本体１１の電源端子ＶＣＣ１と接地ＧＮＤ間に接続した電源安定化容量Ｃ１は、電源端子ＶＣＣ１の配線をレイアウトの関係から２系統に形成する場合には、その各系統の電源端子と接地端子間に個々に接続することが好ましい。このとき、負荷抵抗Ｒ１，Ｒ２はその各系統の電源端子にそれぞれ接続する。   In addition, although the example which used the bipolar transistor as the transistors Q1-Q6 was demonstrated above, when it uses a MOS transistor, it can implement similarly and can obtain the same effect. When the MOS transistor is used in this way, the current source stabilization resistors R3 and R8 can be eliminated. Further, the power stabilization capacitor C1 connected between the power supply terminal VCC1 of the LD drive circuit body 11 and the ground GND has a power supply terminal of each system when the wiring of the power supply terminal VCC1 is formed in two systems from the layout. It is preferable to make an individual connection between the terminal and the ground terminal. At this time, the load resistors R1 and R2 are connected to the power supply terminals of the respective systems.

本発明の実施例のＬＤ差動駆動回路の回路図である。It is a circuit diagram of the LD differential drive circuit of the Example of this invention. 図１のＬＤ差動駆動回路の具体的回路図である。FIG. 2 is a specific circuit diagram of the LD differential drive circuit of FIG. 1. 従来のＬＤ差動駆動回路の具体的回路図である。It is a specific circuit diagram of a conventional LD differential drive circuit. 本発明と従来のＬＤ差動駆動回路のレーザダイオードの電流波形のアイパターン特性図である。It is an eye pattern characteristic view of a current waveform of a laser diode of the present invention and a conventional LD differential drive circuit.

符号の説明Explanation of symbols

Ｑ１〜Ｑ６：トランジスタ、Ｒ１、Ｒ２，Ｒ７：負荷抵抗、Ｒ４，Ｒ５：終端抵抗、Ｒ６：バイアス抵抗、Ｒ３，Ｒ８：電流安定化抵抗、Ｌ１，Ｌ２：バイアス用インダクタ、ＬＤ：レーザダイオード、ＶＣＣ１，ＶＣＣ３：電源端子、ＶＣＣ２：ＬＤ電源端子、ＧＮＤ：接地端子、ＶＣＳ１，ＶＣＳ２：電流制御端子、ＩＮ１〜ＩＮ４：入力端子、ＯＵＴ１，ＯＵＴ２：出力端子、Ｔ１，Ｔ２：伝送線路、ＡＰＣ：自動光出力制御回路、ＢＢ：ＬＤバイアス端子   Q1-Q6: Transistors, R1, R2, R7: Load resistors, R4, R5: Termination resistors, R6: Bias resistors, R3, R8: Current stabilization resistors, L1, L2: Bias inductors, LD: Laser diodes, VCC1 , VCC3: power supply terminal, VCC2: LD power supply terminal, GND: ground terminal, VCS1, VCS2: current control terminal, IN1-IN4: input terminal, OUT1, OUT2: output terminal, T1, T2: transmission line, APC: automatic light Output control circuit, BB: LD bias terminal

Claims (3)

ＬＤ駆動電流が出力する差動形式の第１および第２の出力端子およびＬＤバイアス電流が出力するＬＤバイアス端子を有するＬＤドライブ回路と、レーザダイオードの一方の端子と前記第１の出力端子との間に接続される第１の伝送線路と、前記レーザダイオードの他方の端子と前記第２の出力端子との間に接続される第２の伝送線路と、前記レーザダイオードの前記一方の端子とＬＤ電源端子との間に接続されるインダクタと、前記レーザダイオードの前記他方の端子と前記ＬＤバイアス端子との間に接続されるバイアス抵抗とを有することを特徴とするＬＤ差動駆動回路。   An LD drive circuit having first and second differential output terminals for outputting an LD drive current and an LD bias terminal for outputting an LD bias current, and one terminal of a laser diode and the first output terminal A first transmission line connected in between, a second transmission line connected between the other terminal of the laser diode and the second output terminal, the one terminal of the laser diode and the LD An LD differential drive circuit comprising: an inductor connected between a power supply terminal; and a bias resistor connected between the other terminal of the laser diode and the LD bias terminal. 請求項１に記載のＬＤ差動駆動回路において、
前記ＬＤドライブ回路は、ＬＤドライブ回路本体とＬＤバイアス回路とからなり、
前記ＬＤドライブ回路本体は、第１のトランジスタと第２のトランジスタからなる第１の差動回路と、前記第１のトランジスタのコレクタ又はドレインと第１の電源端子との間に接続される第１の負荷抵抗と、前記第２のトランジスタのコレクタ又はドレインと前記第１の電源端子との間に接続される第２の負荷抵抗と、前記第１および第２のトランジスタのエミッタ又はソースと第２の電源端子に接続された電流源と、前記第１の電源端子と前記第２の電源端子との間に接続される少なくとも１０ｐＦの容量値をもつ第１の電源安定化容量とを備え、前記第１および第２のトランジスタのベース又はゲートが差動入力端子に接続され、前記第１および第２のトランジスタのコレクタ又はドレインが前記第１および第２の出力端子に接続されてなり、
前記ＬＤバイアス回路は、第３のトランジスタと第４のトランジスタからなる第２の差動回路と、前記第３のトランジスタのコレクタ又はドレインと第３の電源端子との間に接続される第３の負荷抵抗と、前記第３および第４のトランジスタのエミッタ又はソースにコレクタ又はドレインが接続されベース又はゲートが自動光出力制御回路に接続されソースが第４の電源端子に接続される第５のトランジスタとを備え、前記第４のトランジスタのコレクタ又はドレインが前記ＬＤバイアス端子に接続され、前記第３および第４のトランジスタのベース又はゲートに制御信号が印加するようにしてなる、
ことを特徴とするＬＤ差動駆動回路。 The LD differential drive circuit according to claim 1,
The LD drive circuit comprises an LD drive circuit body and an LD bias circuit,
The LD drive circuit main body is connected to a first differential circuit composed of a first transistor and a second transistor, and a first power source terminal connected between a collector or drain of the first transistor and a first power supply terminal. , A second load resistor connected between the collector or drain of the second transistor and the first power supply terminal, an emitter or source of the first and second transistors, and a second A current source connected to the power supply terminal, and a first power stabilization capacitor having a capacitance value of at least 10 pF connected between the first power supply terminal and the second power supply terminal, The bases or gates of the first and second transistors are connected to a differential input terminal, and the collectors or drains of the first and second transistors are connected to the first and second output terminals. Now,
The LD bias circuit includes a second differential circuit composed of a third transistor and a fourth transistor, a third differential circuit connected between a collector or drain of the third transistor and a third power supply terminal. A fifth resistor having a load resistor and a collector or drain connected to the emitter or source of the third and fourth transistors, a base or gate connected to the automatic light output control circuit, and a source connected to the fourth power supply terminal The collector or drain of the fourth transistor is connected to the LD bias terminal, and a control signal is applied to the base or gate of the third and fourth transistors.
LD differential drive circuit characterized by the above. 請求項２に記載のＬＤ差動駆動回路において、
前記第１の電源端子を第５の電源端子と第６の電源端子に分離し、前記第５の電源端子を前記第１の負荷抵抗に接続すると共に前記第６の電源端子を前記第２の負荷抵抗に接続し、
前記第１の電源安定化容量に代えて、前記第５の電源端子と前記第２の電源端子との間に、少なくとも１０ｐＦの容量値をもつ第２の電源安定化容量を接続し、前記第６の電源端子と前記第２の電源端子との間に、少なくとも１０ｐＦの容量値をもつ第３の電源安定化容量を接続したことを特徴とするＬＤ差動駆動回路。
The LD differential drive circuit according to claim 2,
The first power supply terminal is separated into a fifth power supply terminal and a sixth power supply terminal, the fifth power supply terminal is connected to the first load resistor, and the sixth power supply terminal is connected to the second power supply terminal. Connected to the load resistor,
Instead of the first power stabilization capacitor, a second power stabilization capacitor having a capacitance value of at least 10 pF is connected between the fifth power supply terminal and the second power supply terminal. An LD differential driving circuit, wherein a third power stabilization capacitor having a capacitance value of at least 10 pF is connected between the six power terminals and the second power terminal.
JP2006213732A 2006-08-04 2006-08-04 Ld differential drive circuit Pending JP2008041907A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006213732A JP2008041907A (en) 2006-08-04 2006-08-04 Ld differential drive circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006213732A JP2008041907A (en) 2006-08-04 2006-08-04 Ld differential drive circuit

Publications (1)

Publication Number Publication Date
JP2008041907A true JP2008041907A (en) 2008-02-21

Family

ID=39176601

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006213732A Pending JP2008041907A (en) 2006-08-04 2006-08-04 Ld differential drive circuit

Country Status (1)

Country Link
JP (1) JP2008041907A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009231362A (en) * 2008-03-19 2009-10-08 Sumitomo Electric Ind Ltd Semiconductor laser driving circuit
JP2010267924A (en) * 2009-05-18 2010-11-25 Nippon Telegr & Teleph Corp <Ntt> Laser driving circuit
JP2011146469A (en) * 2010-01-13 2011-07-28 Nippon Telegr & Teleph Corp <Ntt> Low power laser drive circuit
JP2011182108A (en) * 2010-02-26 2011-09-15 Nippon Telegr & Teleph Corp <Ntt> Burst type laser drive circuit
WO2012107994A1 (en) * 2011-02-07 2012-08-16 三菱電機株式会社 Laser diode drive circuit
WO2013031275A1 (en) * 2011-08-31 2013-03-07 住友電気工業株式会社 Drive circuit, and home-side device
JP2013526065A (en) * 2010-04-28 2013-06-20 ホーヤ コーポレイション ユーエスエイ Reduction of crosstalk in bidirectional optoelectronic devices.

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6370470A (en) * 1986-09-11 1988-03-30 Fujitsu Ltd Optical transmitter
JPH02224367A (en) * 1989-02-27 1990-09-06 Ricoh Co Ltd Semiconductor device provided with capacitor
JPH04343284A (en) * 1991-05-21 1992-11-30 Nec Corp Semiconductor laser device
JPH09191146A (en) * 1996-01-11 1997-07-22 Nec Corp Laser diode driving circuit
JP2004241505A (en) * 2003-02-04 2004-08-26 Ntt Electornics Corp E/o conversion circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6370470A (en) * 1986-09-11 1988-03-30 Fujitsu Ltd Optical transmitter
JPH02224367A (en) * 1989-02-27 1990-09-06 Ricoh Co Ltd Semiconductor device provided with capacitor
JPH04343284A (en) * 1991-05-21 1992-11-30 Nec Corp Semiconductor laser device
JPH09191146A (en) * 1996-01-11 1997-07-22 Nec Corp Laser diode driving circuit
JP2004241505A (en) * 2003-02-04 2004-08-26 Ntt Electornics Corp E/o conversion circuit

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009231362A (en) * 2008-03-19 2009-10-08 Sumitomo Electric Ind Ltd Semiconductor laser driving circuit
JP2010267924A (en) * 2009-05-18 2010-11-25 Nippon Telegr & Teleph Corp <Ntt> Laser driving circuit
JP2011146469A (en) * 2010-01-13 2011-07-28 Nippon Telegr & Teleph Corp <Ntt> Low power laser drive circuit
JP2011182108A (en) * 2010-02-26 2011-09-15 Nippon Telegr & Teleph Corp <Ntt> Burst type laser drive circuit
JP2013526065A (en) * 2010-04-28 2013-06-20 ホーヤ コーポレイション ユーエスエイ Reduction of crosstalk in bidirectional optoelectronic devices.
WO2012107994A1 (en) * 2011-02-07 2012-08-16 三菱電機株式会社 Laser diode drive circuit
JP5306547B2 (en) * 2011-02-07 2013-10-02 三菱電機株式会社 Laser diode drive circuit
CN103348544A (en) * 2011-02-07 2013-10-09 三菱电机株式会社 Laser diode drive circuit
US8831059B2 (en) 2011-02-07 2014-09-09 Mitsubishi Electric Corporation Laser diode driver circuit
WO2013031275A1 (en) * 2011-08-31 2013-03-07 住友電気工業株式会社 Drive circuit, and home-side device
JP2013051558A (en) * 2011-08-31 2013-03-14 Sumitomo Electric Ind Ltd Drive circuit and home side apparatus
US9124063B2 (en) 2011-08-31 2015-09-01 Sumitomo Electric Industries, Ltd. Drive circuit and optical network unit

Similar Documents

Publication Publication Date Title
JP2008041907A (en) Ld differential drive circuit
JP5337886B2 (en) DC coupled laser driving circuit and semiconductor laser element driving method
CN106257777B (en) Driver for high speed laser diode
JPH11251668A (en) Circuit for driving light emitting element
JP3725235B2 (en) Light emitting element driving circuit and light emitting device having the same
JP2011146902A (en) Ringing suppression circuit
CN104518751B (en) Optics receives circuit, optical receiving device and optics and sends system
JP3881079B2 (en) Semiconductor integrated circuit element
JP2013251375A (en) Optical transmission circuit and optical transmission/reception circuit module
KR101618971B1 (en) Power amplifier of the inverter form
JP4886725B2 (en) Transimpedance amplifier circuit
US7659775B2 (en) Output differential stage
JP6367984B2 (en) Driver circuit
TW202112020A (en) Gan laser diode drive fet with gate current reuse
JP2005217194A (en) Driving circuit of laser diode
JP2011155497A (en) Level shift circuit
JP2008153544A (en) Current source circuit and light-emitting element drive circuit
KR100810328B1 (en) Current driving type light source driving circuit
JP2013115241A (en) Drive circuit and optical transmission device
JP4760608B2 (en) Drive control device for output transistor
JP2008041902A (en) Ld drive circuit
JP2015019328A (en) Amplification circuit
JP3507621B2 (en) Semiconductor integrated circuit
JP2007053389A (en) Semiconductor integrated circuit device
US7525346B2 (en) Driver circuits and methods

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080911

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110111

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110118

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110901

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111012

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120605