JP2008016601A - Semiconductor element stack - Google Patents

Semiconductor element stack Download PDF

Info

Publication number
JP2008016601A
JP2008016601A JP2006185562A JP2006185562A JP2008016601A JP 2008016601 A JP2008016601 A JP 2008016601A JP 2006185562 A JP2006185562 A JP 2006185562A JP 2006185562 A JP2006185562 A JP 2006185562A JP 2008016601 A JP2008016601 A JP 2008016601A
Authority
JP
Japan
Prior art keywords
conductor
semiconductor element
element stack
conductor blocks
insulating frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006185562A
Other languages
Japanese (ja)
Inventor
Toshiyuki Yano
利行 矢野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2006185562A priority Critical patent/JP2008016601A/en
Publication of JP2008016601A publication Critical patent/JP2008016601A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element stack which retains pressure bonding force stably for a long period of time, by uniformly bonding a plurality of semiconductor chips through pressure bonding. <P>SOLUTION: The semiconductor stack 1 is constituted so that 3 pieces of conductor blocks 5A, 5B are laminated in spaces of insulating frames 2 provided with a space in an insulating board. Then a semiconductor chip 3 with molybdenum sheets attached to both surfaces thereof is pinched between neighbored conductor blocks respectively, and through-holes 8 are provided on the conductor blocks respectively in a direction orthogonal to the direction of pressure bonding. Elastic bodies 7 are arranged on the further outside of conductor blocks positioned on the outside among the conductor blocks, and the elastic bodies are bonded through pressure bonding to the internal circumferential surfaces of spaces of insulating frames to pinch the semiconductor chips between the conductor blocks by the reaction force of the pressure bonding force. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体素子スタックに関する。   The present invention relates to a semiconductor device stack.

一般に電力変換装置としてのインバータ装置にはパワー半導体を用いている。ところがパワー半導体チップを複数個圧接して通電する圧接型の半導体素子スタックでは、冷却のためのヒートシンクと共にパワー半導体チップを積層し、絶縁部材やバネなどの緩衝部材と共に圧接している。この圧接力を保持するのがフレームであり、通常は金属製のロッドで積層したパワー半導体素子の両端電極を、絶縁板を介して圧接する構造にすることが多い。このように圧縮方向に弾性的な加圧力を付加する構造を、平型半導体素子スタックと称する。   Generally, a power semiconductor is used for an inverter device as a power conversion device. However, in a pressure-contact type semiconductor element stack in which a plurality of power semiconductor chips are pressed and energized, the power semiconductor chips are stacked together with a heat sink for cooling, and are pressed together with a buffer member such as an insulating member or a spring. The frame holds this pressure contact force, and usually has a structure in which both end electrodes of a power semiconductor element laminated with metal rods are pressure-contacted via an insulating plate. Such a structure that applies elastic pressure in the compression direction is referred to as a flat semiconductor element stack.

インバータやコンバータ、サイリスタなどの電力変換装置などには、このような半導体素子スタックを半導体電力変換装置の回路構成要素として多数使用している。例えば、特開２０００−２４５１５６号公報（特許文献１）に示されているサイリスタ半導体素子スタックは、板状のフレームの一部を開放して半導体素子やヒートシンク、皿バネなどを納めてスタックを構成し、板状のフレームにはアノードリアクトルや抵抗器、コンデンサなどの部品を取り付けている。   A large number of such semiconductor element stacks are used as circuit components of a semiconductor power converter for power converters such as inverters, converters, and thyristors. For example, a thyristor semiconductor element stack disclosed in Japanese Patent Application Laid-Open No. 2000-245156 (Patent Document 1) is configured by opening a part of a plate-shaped frame and housing a semiconductor element, a heat sink, a disc spring, and the like. In addition, parts such as an anode reactor, a resistor, and a capacitor are attached to the plate-like frame.

電力変換装置に用いられているＩＧＢＴ（Insulated Gate Bipolar Transistor）やＩＥＧＴ（Injection Enhanced Gate Transistor）等の平型半導体素子は、数千ボルト、数千アンペアという大容量であり、冷却のための冷却器や通電のための導体と共に数十ｋＮという高荷重で圧接して使用する。   Flat type semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and IEGTs (Injection Enhanced Gate Transistors) used in power converters have large capacities of thousands of volts and thousands of amperes. It is used with a high load of several tens kN together with a conductor for energization.

近年、このような大容量のほかに、自動車などの小容量（数百ボルト・アンペア）のインバータには、半導体チップを実装したコンパクトな素子が適用されることが多くなってきている。   In recent years, in addition to such a large capacity, a compact element mounted with a semiconductor chip is often applied to an inverter having a small capacity (several hundred volts / ampere) such as an automobile.

半導体チップは一辺１０〜１５ｍｍ程度の四角形をしており、これを複数枚並べて均等に圧接するためには半導体チップ１枚あたり１ｋＮ以上の圧接力を必要とし、これらの荷重を付加して長期間保持する構造が半導体素子スタックには求められる。そのため、小容量半導体素子への適用はほとんどなく、実用化されていないのが現状である。   The semiconductor chip has a square shape with a side of about 10 to 15 mm. In order to arrange a plurality of semiconductor chips and press them evenly, a pressure contact force of 1 kN or more per semiconductor chip is required. A structure to be held is required for the semiconductor element stack. For this reason, there is almost no application to small-capacity semiconductor elements, and the current situation is that they have not been put into practical use.

しかし、半導体チップは電力損失による発熱をチップ両面から冷却できるため、小型化できる利点がある。またモジュールタイプの素子と比べて、通電のために半導体チップと電極とをつなぐ無数のボンディングワイヤなどが不要である利点もある。このため、小容量半導体素子スタックの実用化のためには、圧接力をいかに均等に付加して保持するかが重要なポイントとなっている。
特開２０００−２４５１５６号公報 However, the semiconductor chip has an advantage that it can be miniaturized because heat generated by power loss can be cooled from both sides of the chip. Also, compared to module type elements, there is an advantage that innumerable bonding wires and the like for connecting the semiconductor chip and the electrodes are not necessary for energization. For this reason, in order to put the small-capacity semiconductor element stack to practical use, it is an important point how to apply and maintain the pressure contact force evenly.
JP 2000-245156 A

本発明は、上記従来技術の課題に鑑みてなされたもので、複数の半導体チップを偏りなく圧接し、長期間安定して圧接力を保持することのできる半導体素子スタックを提供することを目的とする。   The present invention has been made in view of the above-described problems of the prior art, and an object thereof is to provide a semiconductor element stack that can press-contact a plurality of semiconductor chips without unevenness and can maintain a press-contact force stably for a long period of time. To do.

本発明は、絶縁板の内部に空間を設けた絶縁フレームの前記空間内において、３個の導体ブロックを積層し、隣接する前記導体ブロック間それぞれに、両面にモリブデン板を取付けた半導体チップを挟み込み、前記導体ブロックそれぞれに、圧接方向と直角な方向に貫通穴を設け、前記導体ブロックのうちの外側に位置する導体ブロックのさらに外側に弾性体を配置し、前記弾性体を前記絶縁フレームの空間の内周面に圧接させ、当該圧接力の反作用力にて前記導体ブロック間に前記半導体チップを加圧状態で挟み込んだ半導体素子スタックを特徴とする。   According to the present invention, in the space of the insulating frame provided with a space inside the insulating plate, three conductor blocks are stacked, and a semiconductor chip having a molybdenum plate attached on both sides is sandwiched between the adjacent conductor blocks. In each of the conductor blocks, a through hole is provided in a direction perpendicular to the pressure contact direction, an elastic body is disposed further outside the conductor block located outside the conductor block, and the elastic body is disposed in the space of the insulating frame. And a semiconductor element stack in which the semiconductor chip is sandwiched between the conductor blocks by a reaction force of the pressure contact force.

また本発明は、絶縁板の内部に３つの空間を並列するように設けた絶縁フレームの前記空間各々において、３個の導体ブロックを積層し、隣接する前記導体ブロック間それぞれに、両面にモリブデン板を取付けた半導体チップを挟み込み、前記導体ブロックそれぞれに、圧接方向と直角な方向に貫通穴を設け、前記導体ブロックのうちの外側に位置する導体ブロックのさらに外側に弾性体を配置し、前記弾性体を前記絶縁フレームの空間の内周面に圧接させ、当該圧接力の反作用力にて前記導体ブロック間に前記半導体チップを加圧状態で挟み込んだ半導体素子スタックを特徴とする。   The present invention also provides a structure in which three conductor blocks are stacked in each of the spaces of the insulating frame provided so that three spaces are arranged in parallel inside the insulating plate, and a molybdenum plate is provided on both sides between the adjacent conductor blocks. Sandwiching the semiconductor chip to which each of the conductor blocks is inserted, a through hole is provided in each conductor block in a direction perpendicular to the pressure contact direction, and an elastic body is disposed on the outer side of the conductor block located outside the conductor block, and the elastic block A semiconductor element stack is characterized in that a body is pressed against an inner peripheral surface of the space of the insulating frame, and the semiconductor chip is sandwiched between the conductor blocks by a reaction force of the pressing force.

本発明の半導体素子スタックによれば、１相分あるいは３相分の複数の半導体チップを偏りなく圧接し、長期間安定して圧接力を保持することができる。   According to the semiconductor element stack of the present invention, a plurality of semiconductor chips for one phase or three phases can be pressure-contacted without unevenness, and the pressure-contact force can be stably maintained for a long time.

以下、本発明の実施の形態を図に基づいて詳説する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

（第１の実施の形態）本発明の第１の実施の形態の半導体素子スタック１を、図１〜図６を用いて説明する。図１及び図２において、絶縁板の一部をくりぬいて空間３０を形成し、半導体スタッキングのための絶縁フレーム２を構成している。この絶縁フレーム２のくりぬかれた空間３０内に、ＩＧＢＴ、ＩＥＧＴ、ダイオードなどのスイッチング用半導体チップ３の表面と裏面にモリブデン（Ｍｏ）板４を設けた組体を収容し、導体ブロック５Ａと中間導体ブロック５Ｂとのそれぞれの角柱状の突起６にて挟み込み、両外の導体ブロック５Ａの外側面それぞれをコイルばね７で圧接して半導体素子スタック１が構成されている。この導体ブロック５Ａ，５Ｂの材料には、半導体チップ３の圧接と共に通電も行うため銅やアルミニウムその他導電性の材料を用いる。   (First Embodiment) A semiconductor element stack 1 according to a first embodiment of the present invention will be described with reference to FIGS. 1 and 2, a part of the insulating plate is hollowed out to form a space 30 to constitute an insulating frame 2 for semiconductor stacking. In the hollowed space 30 of the insulating frame 2, an assembly in which a molybdenum (Mo) plate 4 is provided on the front and back surfaces of the switching semiconductor chip 3 such as IGBT, IEGT, diode, etc. is accommodated, and between the conductor block 5A and the middle The semiconductor element stack 1 is formed by sandwiching the prism blocks 6 with the conductor blocks 5B and pressing the outer surfaces of the outer conductor blocks 5A with coil springs 7. As the material of the conductor blocks 5A and 5B, copper, aluminum, or other conductive material is used for conducting current as well as pressing the semiconductor chip 3.

導体ブロック５Ａ及び中間導体ブロック５Ｂには、並べて配置される半導体チップ３と半導体チップ３の境界位置に相当する部分に圧接付加方向に対して直角方向に貫通穴８を複数個設けてある。コイルばね７の片端部には、このコイルばね７と接触し、圧接力を保持するストッパ９を設けている。このストッパ９は、絶縁フレーム２の空間３０の内周に設けたばねホルダ１０Ａ，１０Ｂで保持してある。   In the conductor block 5A and the intermediate conductor block 5B, a plurality of through holes 8 are provided in the direction corresponding to the boundary position between the semiconductor chip 3 and the semiconductor chip 3 arranged side by side in a direction perpendicular to the press-contacting direction. One end of the coil spring 7 is provided with a stopper 9 that is in contact with the coil spring 7 and holds the pressure contact force. The stopper 9 is held by spring holders 10 </ b> A and 10 </ b> B provided on the inner periphery of the space 30 of the insulating frame 2.

圧接方法は、図３に示すようなスリットの入った先が開いたコップ状のストッパ９をコイルばね７の先端に取り付け、図４のようにロッド１１で押し込むと、ストッパ９の端部がばねホルダ１０Ｂの内部の小径の穴２１を通過するときはしぼんでいるが、図５のように大径の穴２２に変化する部分で広がることで、コイルばね７を圧縮した状態で保持固定する。尚、ロッド１１は、ストッパ９を図５のように押し込んだ後に取り外す。   As shown in FIG. 3, when the cup-shaped stopper 9 having an open slit is attached to the tip of the coil spring 7 and pushed by the rod 11 as shown in FIG. 4, the end of the stopper 9 becomes a spring. When passing through the small-diameter hole 21 inside the holder 10B, the coil spring 7 is held down and fixed in a compressed state by spreading at the portion that changes to the large-diameter hole 22 as shown in FIG. The rod 11 is removed after pushing the stopper 9 as shown in FIG.

図６は本実施の形態の半導体素子スタック１の回路構成を示している。この図６に示す半導体素子スタック１の回路において、両端の導体ブロック５Ａが本装置の入力側の直流電源で、中央部の中間導体ブロック５Ｂが交流出力である。このように１個の半導体素子スタック１で電力変換装置としてのインバータの１相分の回路を構成する。   FIG. 6 shows a circuit configuration of the semiconductor element stack 1 of the present embodiment. In the circuit of the semiconductor element stack 1 shown in FIG. 6, the conductor blocks 5A at both ends are DC power supplies on the input side of this apparatus, and the intermediate conductor block 5B at the center is AC output. Thus, a circuit for one phase of an inverter as a power conversion device is configured by one semiconductor element stack 1.

本実施の形態の半導体素子スタックによれば、各半導体チップ３をコイルばね７の弾性的な反発力を利用して加圧する場合、図７に示すように積層された半導体チップ３に対してコイルばね７を配置し、半導体チップ３やＭｏ板４、導体ブロック５Ａ，５Ｂの厚みの差を導体ブロック５Ａ，５Ｂに設けた複数の貫通穴８の穴と穴との間の肉厚の薄くなった導体部分がたわむことで吸収し、隣接して配置された半導体チップ３の圧接力に影響を及ぼさずに圧接することができる。   According to the semiconductor element stack of the present embodiment, when each semiconductor chip 3 is pressed using the elastic repulsive force of the coil spring 7, the coil is applied to the stacked semiconductor chips 3 as shown in FIG. The spring 7 is disposed, and the thickness difference between the holes of the plurality of through holes 8 provided in the conductor blocks 5A and 5B is reduced in thickness difference between the semiconductor chip 3, the Mo plate 4, and the conductor blocks 5A and 5B. As a result, the conductor portion is absorbed by bending and can be pressed without affecting the pressing force of the adjacent semiconductor chip 3.

このように半導体チップ３、Ｍｏ板４や導体ブロック５Ａ，５Ｂの厚みの差による半導体チップ３の圧接力の偏りを無くし、圧接力を均等に半導体チップ３に付加することができる。また半導体チップ３を個別にコイルばね７で圧接でき、またコイルばね７を押し込むためのボルトなどをスタックに取り付けておく必要がないために半導体素子スタック１の軽量化を図ることができる。さらに半導体素子スタック１のフレーム２を絶縁物で構成するので、軽量化を図ることができる。   In this way, it is possible to eliminate the uneven pressure contact force of the semiconductor chip 3 due to the difference in thickness between the semiconductor chip 3, the Mo plate 4, and the conductor blocks 5A and 5B, and to apply the pressure contact force evenly to the semiconductor chip 3. In addition, the semiconductor chip 3 can be individually press-contacted by the coil spring 7, and since it is not necessary to attach a bolt or the like for pushing the coil spring 7 to the stack, the weight of the semiconductor element stack 1 can be reduced. Furthermore, since the frame 2 of the semiconductor element stack 1 is made of an insulator, the weight can be reduced.

尚、導体ブロック５Ａ，５Ｂの複数の貫通穴８の代わりに、ハニカム状の部材や板材で接合構成しても同様の効果が得られる。   It should be noted that the same effect can be obtained even if a honeycomb-like member or plate material is used in place of the plurality of through holes 8 of the conductor blocks 5A and 5B.

また、コイルばね７は、角ばねや複数枚積層したさらばねを用いても同様の効果が得られる。そして角ばねを用いる場合、コイルばね７が丸断面であるのに対して、角ばねは角断面をしており、そのため、コイルばね７よりも大きな加圧力を得ることができる。また、さらばねも同様に少ない変位で大きな加圧力が得られる。また、コイルばね７を設ける位置は、スタック１の片端部のみに配置しても同等の効果が得られる。   Further, the coil spring 7 can obtain the same effect even when a square spring or a plurality of stacked springs are used. When the square spring is used, the coil spring 7 has a round cross section, whereas the square spring has a square cross section. Therefore, a larger pressing force than that of the coil spring 7 can be obtained. Similarly, the spring spring can obtain a large pressure with a small displacement. The same effect can be obtained even if the coil spring 7 is provided only at one end of the stack 1.

また、図８に示すようにストッパ９の形状として平板を端部が開いたコの字状に曲げたものを用いても同様の効果を得ることができる。   Further, as shown in FIG. 8, the same effect can be obtained by using a stopper 9 having a flat plate bent into a U shape with an open end.

また絶縁フレーム２の材料はＦＲＰやセラミックを用いる。金属とする場合は、コイルばね７と導体ブロック５Ａとの間に絶縁材料を挟むことで同様の効果が得られる。さらに絶縁フレーム２を特開平０８−１１１５０４号公報に記載されている絶縁バンドとしても同様の効果が得られる。   The material of the insulating frame 2 is FRP or ceramic. In the case of using a metal, the same effect can be obtained by sandwiching an insulating material between the coil spring 7 and the conductor block 5A. Further, the same effect can be obtained when the insulating frame 2 is an insulating band described in Japanese Patent Application Laid-Open No. 08-111504.

（第２の実施の形態）本発明の第２の実施の形態の半導体素子スタック１について、図９、図１０を用いて説明する。尚、本実施の形態にあって、図１、図２に示した第１の実施の形態と共通する要素については同一の符号を用いて説明する。   (Second Embodiment) A semiconductor element stack 1 according to a second embodiment of the present invention will be described with reference to FIGS. In the present embodiment, elements common to the first embodiment shown in FIGS. 1 and 2 will be described using the same reference numerals.

図１、図２に示した第１の実施の形態では、導体ブロック５Ａ，５Ｂには特に放熱用のフィンを設けてはいない。しかしながら、導体ブロック５Ａ，５Ｂは半導体チップ３が通電損失により発生する熱を冷却するヒートシンクとしても作用する。   In the first embodiment shown in FIGS. 1 and 2, the conductor blocks 5A and 5B are not particularly provided with fins for heat dissipation. However, the conductor blocks 5A and 5B also act as heat sinks for cooling the heat generated by the semiconductor chip 3 due to the conduction loss.

そこで、図９、図１０に示すように、本実施の形態の半導体素子スタック１では、導体ブロック５Ａ，５Ｂの側面に冷却フィン１２を設けることで放熱効果を高める構成にしている。   Therefore, as shown in FIGS. 9 and 10, in the semiconductor element stack 1 of the present embodiment, the heat radiation effect is enhanced by providing the cooling fins 12 on the side surfaces of the conductor blocks 5A and 5B.

これにより、本実施の形態の半導体素子スタック１では、半導体チップ３が通電損失により発生する熱を冷却するヒートシンクとしても作用する導体ブロック５Ａ，５Ｂの側面に冷却フィン１２を設けたことで、その放熱効果を高めることができ、信頼性の向上が図れる。尚、他にもこの導体ブロック５Ａ，５Ｂを水冷など冷媒による冷却を行っても同様の効果が得られる。   Thereby, in the semiconductor element stack 1 of the present embodiment, the cooling fins 12 are provided on the side surfaces of the conductor blocks 5A and 5B that also act as a heat sink for cooling the heat generated by the semiconductor chip 3 due to the conduction loss. The heat dissipation effect can be enhanced and the reliability can be improved. In addition, the same effect can be obtained by cooling the conductor blocks 5A and 5B with a coolant such as water cooling.

（第３の実施の形態）本発明の第３の実施の形態の半導体素子スタックについて、図１１を用いて説明する。尚、図１１は本実施の形態の半導体素子スタックの特徴を説明するために要部を示したものであり、本実施の形態の構造そのものは、図１及び図２に示した第１の実施の形態、図９に示した第２の実施の形態と共通である。したがって、以下、共通する要素について共通の符号を用いて説明する。   (Third Embodiment) A semiconductor element stack according to a third embodiment of the present invention will be described with reference to FIG. FIG. 11 shows a main part for explaining the characteristics of the semiconductor element stack of the present embodiment, and the structure itself of the present embodiment is the same as that of the first embodiment shown in FIGS. This is the same as the second embodiment shown in FIG. Therefore, hereinafter, common elements will be described using common reference numerals.

本実施の形態では、半導体素子スタック１の片端部に設けたコイルばね７に、雌ねじ１３Ａを設けたフランジ１３を嵌合させている。絶縁フレーム２の片端部のばねホルダ１０Ａには、コイルばね７を保持するざぐり穴１４とボルト穴１５が設けてある。そして、このざぐり穴１４とボルト穴１５の部分に絶縁フレーム２からボルト１６を挿入し、フランジ１３の雌ねじ１３Ａにねじ込むことでコイルばね７をさらに圧縮し、半導体チップ３にかかっていた圧接力を開放するようにしている。   In the present embodiment, a flange 13 provided with a female screw 13A is fitted into a coil spring 7 provided at one end of the semiconductor element stack 1. The spring holder 10 </ b> A at one end of the insulating frame 2 is provided with a counterbore 14 and a bolt hole 15 for holding the coil spring 7. Then, the bolt 16 is inserted into the counterbore 14 and the bolt hole 15 from the insulating frame 2 and screwed into the female screw 13A of the flange 13 to further compress the coil spring 7, and the pressure contact force applied to the semiconductor chip 3 is reduced. I try to open it.

本実施の形態の半導体素子スタックでは、上述した操作で半導体チップ３にかかっていた圧接力を開放することで、半導体チップ３や導体ブロック５Ａ，５Ｂなどの交換が簡単にできる。そして交換後には、ボルト１６を緩めて外すだけで所定の圧接力に戻すことができる。   In the semiconductor element stack of the present embodiment, the semiconductor chip 3 and the conductor blocks 5A and 5B can be easily replaced by releasing the pressure contact force applied to the semiconductor chip 3 by the above-described operation. And after exchange, it can return to predetermined press-contact force only by loosening and removing bolt 16.

（第４の実施の形態）本発明の第４の実施の形態の半導体素子スタックについて、図１２を用いて説明する。尚、図１２は本実施の形態の半導体素子スタックの特徴を説明するために要部を示したものであり、本実施の形態の構造そのものは、図１及び図２に示した第１の実施の形態、図９に示した第２の実施の形態と共通である。したがって、以下、共通する要素について共通の符号を用いて説明する。   (Fourth Embodiment) A semiconductor element stack according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 12 shows a main part for explaining the characteristics of the semiconductor element stack of the present embodiment. The structure of the present embodiment itself is the same as that of the first embodiment shown in FIGS. This embodiment is common to the second embodiment shown in FIG. Therefore, hereinafter, common elements will be described using common reference numerals.

本実施の形態の特徴は、図１２に示すように、中間導体ブロック５Ｂの一部を絶縁フレーム２に嵌合させた点にある。このように嵌合させることで、中間導体ブロック５Ｂの位置が決まるため、圧接時に半導体チップ３の圧接軸の中心位置決めを正確に行うことができるようになる。また、振動に対しても中間で保持されるために振動に対して揺れ難い安定した構成となる。また、図示しないが、中間導体ブロック５Ｂと絶縁フレーム２との間に隙間を設けその隙間にプラスチック系やゴム系の衝撃緩衝部材を挿入することによっても振動に対して同様の緩衝効果を得ることができる。   The feature of the present embodiment is that a part of the intermediate conductor block 5B is fitted to the insulating frame 2 as shown in FIG. By fitting in this way, the position of the intermediate conductor block 5B is determined, so that the centering of the press-contact axis of the semiconductor chip 3 can be accurately performed at the time of press-contact. Further, since it is held in the middle with respect to vibration, a stable configuration is obtained which is difficult to shake with respect to vibration. Although not shown, a similar buffering effect against vibration can also be obtained by providing a gap between the intermediate conductor block 5B and the insulating frame 2 and inserting a plastic or rubber-based shock absorbing member in the gap. Can do.

（第５の実施の形態）図１３〜図１５を用いて、本発明の第５の実施の形態について説明する。本実施の形態は、チップや導体ブロックを収納する１枚の絶縁フレーム２０の３箇所をくりぬいて３つの空間３０Ａ，３０Ｂ，３０Ｃを形成し、当該３つの空間３０Ａ，３０Ｂ，３０Ｃに３相分の半導体素子スタック１Ａ，１Ｂ，１Ｃそれぞれを収納した構成を特徴とする。これら３相分の半導体素子スタック１Ａ，１Ｂ，１Ｃそれぞれの構成は、第１の実施の形態又は第２の実施の形態と共通であり、以下、共通する要素については同一の符号を用いて説明する。   (Fifth Embodiment) A fifth embodiment of the present invention will be described with reference to FIGS. In the present embodiment, three spaces 30A, 30B, and 30C are formed by hollowing out three portions of one insulating frame 20 that accommodates chips and conductor blocks, and the three spaces 30A, 30B, and 30C are divided into three phases. The semiconductor device stacks 1A, 1B, and 1C are housed. The configuration of each of these three-phase semiconductor element stacks 1A, 1B, and 1C is the same as that of the first embodiment or the second embodiment. Hereinafter, common elements will be described using the same reference numerals. To do.

本実施の形態の場合、直流入力部のエミッタ、コレクタ電極である導体ブロック５Ａ，５Ｂは３相の導体ブロックを共通にすることで配線用の導体を不要にしている。また相間の圧接方向の位置ずれに対しては導体ブロック５Ａ，５Ｂに多数設けた貫通穴８の部分で緩衝されるため半導体チップ３に無理な力はかからなくなる。   In the case of the present embodiment, the conductor blocks 5A and 5B, which are the emitter and collector electrodes of the DC input portion, share a three-phase conductor block, thereby eliminating the need for a wiring conductor. Further, since the displacement in the pressure contact direction between the phases is buffered by the portions of the through holes 8 provided in the conductor blocks 5A and 5B, an excessive force is not applied to the semiconductor chip 3.

図示しない直流端子との接続による外力も導体ブロック５Ａの端子接続部近傍に同様の端子接続緩衝穴１７を設けることで、端子接続による力も緩衝できるようにしている。また、図１４に示すように絶縁フレーム２０の表面側にエミッタ側の導体ブロック５Ａの端部５Ａ１を伸ばして端子とし、また裏面側に同様にコレクタ側の導体ブロック５Ａの端部５Ａ２を伸ばして端子としている。これにより、両端子間の絶縁を容易にすることができる。   A similar terminal connection buffer hole 17 is provided in the vicinity of the terminal connection portion of the conductor block 5A so that an external force due to connection with a DC terminal (not shown) can also be buffered. Further, as shown in FIG. 14, the end portion 5A1 of the emitter-side conductor block 5A is extended to the front side of the insulating frame 20 to be a terminal, and the end portion 5A2 of the collector-side conductor block 5A is similarly extended to the back side. It is a terminal. Thereby, the insulation between both terminals can be made easy.

さらに、本実施の形態では、図１３、図１５に示すように、３相分の半導体チップ３それぞれに通電するための直流の入力端子や出力の交流端子との接続のための交流端子導体１８を絶縁フレーム２０に固着し、またスイッチングさせるためのゲート回路接続用導体１９なども同様に取り付けている。   Further, in the present embodiment, as shown in FIGS. 13 and 15, an AC terminal conductor 18 for connection to a DC input terminal and an output AC terminal for energizing each of the semiconductor chips 3 for three phases. Is fixed to the insulating frame 20 and a gate circuit connecting conductor 19 for switching is similarly attached.

尚、図示した本実施の形態では、導体ブロック５Ａの端部５Ａ１，５Ａ２を直流の入力としたが、これは任意の場所から引き出すこともできる。   In the illustrated embodiment, the end portions 5A1 and 5A2 of the conductor block 5A are used as direct current inputs. However, this can be drawn out from an arbitrary place.

本実施の形態によれば、３相分の半導体素子スタック１Ａ，１Ｂ，１Ｃを１枚の絶縁フレーム２０内に収容することで接続導体を共通にでき、装置がコンパクトになり軽量化できる。   According to the present embodiment, by accommodating the semiconductor element stacks 1A, 1B, and 1C for three phases in one insulating frame 20, the connection conductor can be made common, and the apparatus can be made compact and lightweight.

また、本実施の形態によれば導体ブロック５Ａ，５Ｂに入出力導体を取り付ける場合、導体を被覆絶縁しなくて接続できるようになる。また、配線の引き回しが自由に設定でき任意の場所から端子を取り出すことができる。またゲート回路などはこの絶縁フレーム２をプリント基板と同様に配線をプリントして構成することもできる。また導体を絶縁フレーム２０の内部に含浸などにより設ければ、さらに絶縁性と配線の多様化を図ることができる。   Further, according to the present embodiment, when the input / output conductors are attached to the conductor blocks 5A and 5B, the conductors can be connected without covering and insulating them. Further, the wiring can be freely set and the terminal can be taken out from an arbitrary place. A gate circuit or the like can also be configured by printing wiring on the insulating frame 2 in the same manner as a printed board. Further, if the conductor is provided inside the insulating frame 20 by impregnation or the like, it is possible to further diversify insulation and wiring.

このように絶縁フレーム２０に取り付けるものは、導体のみならず、電気回路部品なども含み、絶縁フレーム２０をプリント基板化することで軽量化することができる。   Thus, what is attached to the insulating frame 20 includes not only a conductor but also an electric circuit component, and the weight can be reduced by forming the insulating frame 20 as a printed circuit board.

本発明の第１の実施の形態の半導体素子スタックの平面図。The top view of the semiconductor element stack of the 1st Embodiment of this invention. 上記実施の形態の半導体素子スタックの側面図。The side view of the semiconductor element stack of the said embodiment. 上記実施の形態の半導体素子スタックにおけるストッパの形状を示す斜視図。The perspective view which shows the shape of the stopper in the semiconductor element stack of the said embodiment. 上記実施の形態の半導体素子スタックにおいて、圧接力を保持するストッパの挿入初期の動作を示す断面図。Sectional drawing which shows the operation | movement of the insertion initial stage of the stopper holding a press-contact force in the semiconductor element stack of the said embodiment. 上記実施の形態の半導体素子スタックにおいて、圧接力を保持するストッパの挿入完了と動作を示す断面図。Sectional drawing which shows the completion and insertion of the stopper which hold | maintains press-contact force in the semiconductor element stack of the said embodiment. 上記実施の形態の半導体素子スタックが組み込まれている電力変換装置の電気回路図。The electric circuit diagram of the power converter device in which the semiconductor element stack of the said embodiment is incorporated. 上記実施の形態の半導体素子スタックの圧接力保持状態を示す平面図。The top view which shows the press-contact force holding state of the semiconductor element stack of the said embodiment. 上記実施の形態の半導体素子スタックにおける別の形状のストッパを示す斜視図。The perspective view which shows the stopper of another shape in the semiconductor element stack of the said embodiment. 本発明の第２の実施の形態の半導体素子スタックの平面図。The top view of the semiconductor element stack of the 2nd Embodiment of this invention. 上記実施の形態の半導体素子スタックにおける導体ブロック部分の側面図。The side view of the conductor block part in the semiconductor element stack of the said embodiment. 本発明の第３の実施の形態の半導体素子スタックにおいて、コイルばねを圧縮してスタックの圧接力を開放した状態のコイルばね、フランジ、ボルト部分を示す断面図。Sectional drawing which shows a coil spring, a flange, and a bolt part of the state which compressed the coil spring and released the press-contact force of the stack in the semiconductor element stack of the 3rd Embodiment of this invention. 本発明の第４の実施の形態の半導体素子スタックにおける中間導体ブロックと絶縁フレームとの嵌合状態を示す断面図。Sectional drawing which shows the fitting state of the intermediate | middle conductor block and insulation frame in the semiconductor element stack of the 4th Embodiment of this invention. 本発明の第５の実施の形態の半導体素子スタックの平面図。The top view of the semiconductor element stack of the 5th Embodiment of this invention. 図１３におけるＡ−Ａ線断面図。AA line sectional view in FIG. 図１３におけるＢ−Ｂ線断面図。BB sectional drawing in FIG.

符号の説明Explanation of symbols

１…スタック
２，２０…絶縁フレーム
３…半導体チップ
５Ａ，５Ｂ…導体ブロック
５Ａ１，５Ａ２…延長端部
７…コイルばね
１０Ａ，１０Ｂ…ホルダ
３０ 空間 DESCRIPTION OF SYMBOLS 1 ... Stack 2, 20 ... Insulation frame 3 ... Semiconductor chip 5A, 5B ... Conductor block 5A1, 5A2 ... Extension end part 7 ... Coil spring 10A, 10B ... Holder 30 Space

Claims (6)

絶縁板の内部に空間を設けた絶縁フレームの前記空間内において、３個の導体ブロックを積層し、隣接する前記導体ブロック間それぞれに、両面にモリブデン板を取付けた半導体チップを挟み込み、前記導体ブロックそれぞれに、圧接方向と直角な方向に貫通穴を設け、前記導体ブロックのうちの外側に位置する導体ブロックのさらに外側に弾性体を配置し、
前記弾性体を前記絶縁フレームの空間の内周面に圧接させ、当該圧接力の反作用力にて前記導体ブロック間に前記半導体チップを加圧状態で挟み込んだことを特徴とする半導体素子スタック。 Three conductor blocks are laminated in the space of the insulating frame provided with a space inside the insulating plate, and a semiconductor chip having a molybdenum plate attached on both sides is sandwiched between the adjacent conductor blocks, and the conductor block Each is provided with a through hole in a direction perpendicular to the pressure contact direction, and an elastic body is disposed on the outer side of the conductor block located outside the conductor block,
A semiconductor element stack, wherein the elastic body is pressed against an inner peripheral surface of the space of the insulating frame, and the semiconductor chip is sandwiched between the conductor blocks by a reaction force of the pressing force. 前記弾性体はコイルばねであり、
前記半導体チップを加圧する当該コイルばねの端部と絶縁フレームとの間にばねホルダを設け、当該ばねホルダに設けた穴を通過後に開くバネ性のある金属板にて前記コイルばねの端部を弾性的に受持したことを特徴とする請求項１に記載の半導体素子スタック。 The elastic body is a coil spring;
A spring holder is provided between the end of the coil spring that pressurizes the semiconductor chip and the insulating frame, and the end of the coil spring is formed with a springy metal plate that opens after passing through a hole provided in the spring holder. 2. The semiconductor element stack according to claim 1, wherein the semiconductor element stack is elastically received. 前記コイルばねの前記導体ブロックに圧接している側の端部に、当該コイルばねの中心軸方向と同方向に雌ねじが切られたフランジを嵌合させ、
前記絶縁フレームとばねホルダには、前記コイルばねを通して前記フランジの雌ねじにまでボルトを螺入させることができるボルト通し穴を設けたことを特徴とする請求項２に記載の半導体素子スタック。 A flange having a female thread cut in the same direction as the central axis direction of the coil spring is fitted to the end of the coil spring that is in pressure contact with the conductor block,
The semiconductor element stack according to claim 2, wherein the insulating frame and the spring holder are provided with bolt through holes through which the bolts can be screwed into the female threads of the flanges through the coil springs. 前記３個の導体ブロックのうちの中央の導体ブロックを前記絶縁フレームに嵌合させたことを特徴とする請求項１〜３のいずれかに記載の半導体素子スタック。   The semiconductor element stack according to claim 1, wherein a central conductor block of the three conductor blocks is fitted to the insulating frame. 絶縁板の内部に３つの空間を並列するように設けた絶縁フレームの前記空間各々において、３個の導体ブロックを積層し、隣接する前記導体ブロック間それぞれに、両面にモリブデン板を取付けた半導体チップを挟み込み、前記導体ブロックそれぞれに、圧接方向と直角な方向に貫通穴を設け、前記導体ブロックのうちの外側に位置する導体ブロックのさらに外側に弾性体を配置し、前記弾性体を前記絶縁フレームの空間の内周面に圧接させ、当該圧接力の反作用力にて前記導体ブロック間に前記半導体チップを加圧状態で挟み込んだことを特徴とする半導体素子スタック。   A semiconductor chip in which three conductor blocks are stacked in each of the spaces of the insulating frame provided so that three spaces are arranged in parallel inside the insulating plate, and molybdenum plates are attached to both surfaces between the adjacent conductor blocks. Each of the conductor blocks is provided with a through hole in a direction perpendicular to the pressure contact direction, an elastic body is disposed further outside the conductor block located outside the conductor block, and the elastic body is attached to the insulating frame. A semiconductor element stack, wherein the semiconductor chip is pressed between the conductor blocks by a reaction force of the pressure contact force and is pressed between the conductor blocks in a pressurized state. 前記絶縁フレームに、前記３つの空間それぞれに位置する同相の導体ブロックに対して共通に電気的接続がされた導電帯を設けたことを特徴とする請求項５に記載の半導体素子スタック。

6. The semiconductor element stack according to claim 5, wherein the insulating frame is provided with a conductive band that is electrically connected in common to the in-phase conductor blocks located in each of the three spaces.

JP2006185562A 2006-07-05 2006-07-05 Semiconductor element stack Pending JP2008016601A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006185562A JP2008016601A (en) 2006-07-05 2006-07-05 Semiconductor element stack

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006185562A JP2008016601A (en) 2006-07-05 2006-07-05 Semiconductor element stack

Publications (1)

Publication Number Publication Date
JP2008016601A true JP2008016601A (en) 2008-01-24

Family

ID=39073348

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006185562A Pending JP2008016601A (en) 2006-07-05 2006-07-05 Semiconductor element stack

Country Status (1)

Country Link
JP (1) JP2008016601A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101978494A (en) * 2008-03-20 2011-02-16 Abb技术有限公司 Voltage source converter
CN111146169A (en) * 2018-11-06 2020-05-12 株洲中车时代电气股份有限公司 Conductive disc spring assembly for crimping module

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS557360U (en) * 1978-06-28 1980-01-18
JPH08111504A (en) * 1994-10-12 1996-04-30 Toshiba Corp Semiconductor stack
JP2001291824A (en) * 2000-04-11 2001-10-19 Fuji Electric Co Ltd Flat type semiconductor device and its manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS557360U (en) * 1978-06-28 1980-01-18
JPH08111504A (en) * 1994-10-12 1996-04-30 Toshiba Corp Semiconductor stack
JP2001291824A (en) * 2000-04-11 2001-10-19 Fuji Electric Co Ltd Flat type semiconductor device and its manufacturing method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101978494A (en) * 2008-03-20 2011-02-16 Abb技术有限公司 Voltage source converter
US8339823B2 (en) 2008-03-20 2012-12-25 Abb Technology Ag Voltage source converter
KR101243515B1 (en) * 2008-03-20 2013-03-20 에이비비 테크놀로지 아게 A voltage source converter
CN111146169A (en) * 2018-11-06 2020-05-12 株洲中车时代电气股份有限公司 Conductive disc spring assembly for crimping module

Similar Documents

Publication Publication Date Title
KR102354246B1 (en) Power semiconductor device
US9041196B2 (en) Semiconductor module arrangement and method for producing and operating a semiconductor module arrangement
JP6075227B2 (en) Power converter
US10312213B2 (en) Power semiconductor device comprising a substrate and load current terminal elements
US20200058574A1 (en) Semiconductor device and power convertor
WO2015162712A1 (en) Semiconductor module and power converter using same
KR102224471B1 (en) Power semiconductor device
JP2008016601A (en) Semiconductor element stack
JP6686848B2 (en) Power module
US20180374817A1 (en) Semiconductor apparatus
JP6056286B2 (en) Semiconductor module and semiconductor module manufacturing method
JP2015133281A (en) Terminal block, and power conversion system with the same
EP3513432B1 (en) Press-pack power module
JP2005209784A (en) Pressure contact semiconductor device and converter using same
US11387219B2 (en) Power semiconductor module with power semiconductor switches
JP2009094164A (en) Power semiconductor element in inverter device
US20130043579A1 (en) Power semiconductor arrangement, power semiconductor module with multiple power semiconductor arrangements, and module assembly comprising multiple power semiconductor modules
JP2013236035A (en) Semiconductor module and manufacturing method of the same
CN216982372U (en) Radiating assembly structure of power part
JPH1075564A (en) Semiconductor power converter
JP4070531B2 (en) Semiconductor device
JPH098224A (en) Semiconductor module and power converter
JP7151638B2 (en) Power module manufacturing method
JPH11312782A (en) Semiconductor module
JP2005072249A (en) Method for fixing semiconductor discrete part and discrete semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Effective date: 20090220

Free format text: JAPANESE INTERMEDIATE CODE: A621

A977 Report on retrieval

Effective date: 20090915

Free format text: JAPANESE INTERMEDIATE CODE: A971007

A131 Notification of reasons for refusal

Effective date: 20120110

Free format text: JAPANESE INTERMEDIATE CODE: A131

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120508