JP2007524980A - 減少されたコンタクト高さでのバイポーラ及びcmosの集積回路構造体 - Google Patents
減少されたコンタクト高さでのバイポーラ及びcmosの集積回路構造体 Download PDFInfo
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- JP2007524980A JP2007524980A JP2005512432A JP2005512432A JP2007524980A JP 2007524980 A JP2007524980 A JP 2007524980A JP 2005512432 A JP2005512432 A JP 2005512432A JP 2005512432 A JP2005512432 A JP 2005512432A JP 2007524980 A JP2007524980 A JP 2007524980A
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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Abstract
【解決手段】 単一の基板上に配置された複数の相補型金属酸化膜半導体(CMOS)トランジスタ及び複数の垂直バイポーラ・トランジスタを含む集積回路構造体のための方法及び構造体が開示される。垂直バイポーラ・トランジスタは、CMOSトランジスタより高さのあるデバイスである。この構造体においては、保護層が、基板の上に、及び、垂直バイポーラ・トランジスタとCMOSトランジスタとの間に配置される。配線層は保護層の上にある。垂直バイポーラ・トランジスタは、配線層と直接接触しており、CMOSトランジスタは保護層を通って延びるコンタクトによって配線層に接続されている。
【選択図】 図6
Description
本発明、並びに本発明の様々な特徴及び利点となる細部は、添付図面及び以下の詳細な記述において説明されている、限定されない実施形態を参照することによって、より十分に説明される。図面に描かれている構造体が必ずしも尺度に従って描かれてはいないことを心に留めておかれたい。周知の部品及び処理技術に関する説明は、本発明を不必要に不明確にしないように省かれる。ここで用いられている例は、単に、本発明が実行されうる方法の理解を促進し、さらに当業者が本発明を実行可能となるようにすることを意図しているだけである。従って、例は、本発明の範囲を限定するものとして解釈されるべきではない。
Claims (6)
- 集積回路構造体であって、
基板と、
前記基板上に配置された複数の異なる高さのデバイスと、
前記基板の上に及び前記デバイスの間に配置された保護層と、
前記保護層の上の配線層と、
を備え、最も高さのある前記デバイスが前記配線層と直接接触し、より高さの低い前記デバイスが前記保護層を通って延びるコンタクトによって前記配線層に接続されている、集積回路構造体。 - 前記配線層の上にビア層をさらに備え、前記最も高さのあるデバイスが、前記ビア層に直接接続された第2のコンタクトを含む、請求項1に記載の集積回路構造体。
- 前記第2のコンタクトが、前記配線層を通って前記ビア層に延びる、請求項2に記載の集積回路構造体。
- 前記第2のコンタクトが、前記配線層内に配置されている、請求項2に記載の集積回路構造体。
- 前記配線層内の前記第2のコンタクトが、前記配線層内の配線とは異なる材料を含む、請求項4に記載の集積回路構造体。
- 前記最も高さのあるデバイスが、前記より高さの低いデバイスとは異なるタイプのデバイスからなる、請求項1に記載の集積回路構造体。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2003/040003 WO2005062380A1 (en) | 2003-12-16 | 2003-12-16 | Bipolar and cmos integration with reduced contact height |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007524980A true JP2007524980A (ja) | 2007-08-30 |
JP4716870B2 JP4716870B2 (ja) | 2011-07-06 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005512432A Expired - Fee Related JP4716870B2 (ja) | 2003-12-16 | 2003-12-16 | 減少されたコンタクト高さでのバイポーラ及びcmosの集積回路構造体 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7701015B2 (ja) |
EP (1) | EP1695383A4 (ja) |
JP (1) | JP4716870B2 (ja) |
CN (1) | CN100442490C (ja) |
AU (1) | AU2003300962A1 (ja) |
WO (1) | WO2005062380A1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8994179B2 (en) * | 2008-08-29 | 2015-03-31 | Infineon Technologies Ag | Semiconductor device and method for making same |
US9425269B1 (en) | 2015-06-23 | 2016-08-23 | Globalfoundries Inc. | Replacement emitter for reduced contact resistance |
US9859172B1 (en) | 2016-09-29 | 2018-01-02 | International Business Machines Corporation | Bipolar transistor compatible with vertical FET fabrication |
US10332972B2 (en) * | 2017-11-20 | 2019-06-25 | International Business Machines Corporation | Single column compound semiconductor bipolar junction transistor fabricated on III-V compound semiconductor surface |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6297349A (ja) * | 1985-10-24 | 1987-05-06 | Agency Of Ind Science & Technol | 配線およびその形成方法 |
JP2001267520A (ja) * | 2000-03-21 | 2001-09-28 | Toshiba Corp | 半導体装置およびその製造方法 |
WO2003021676A2 (de) * | 2001-08-31 | 2003-03-13 | Infineon Technologies Ag | Kontaktierung des emitterkontakts einer halbleitervorrichtung |
JP2003110095A (ja) * | 2001-08-08 | 2003-04-11 | Agilent Technol Inc | 集積回路およびその形成方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4933297A (en) * | 1989-10-12 | 1990-06-12 | At&T Bell Laboratories | Method for etching windows having different depths |
JP3146316B2 (ja) * | 1991-05-17 | 2001-03-12 | 日本テキサス・インスツルメンツ株式会社 | 半導体装置及びその製造方法 |
US5641691A (en) * | 1995-04-03 | 1997-06-24 | The United States Of America As Represented By The Secretary Of The Navy | Method for fabricating complementary vertical bipolar junction transistors in silicon-on-sapphire |
JPH10189483A (ja) * | 1996-12-26 | 1998-07-21 | Fujitsu Ltd | 半導体装置の製造方法及び半導体装置 |
EP0996160A1 (en) * | 1998-10-12 | 2000-04-26 | STMicroelectronics S.r.l. | Contact structure for a semiconductor device |
US6399993B1 (en) * | 1999-07-07 | 2002-06-04 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US6825496B2 (en) * | 2001-01-17 | 2004-11-30 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device |
JP2004071700A (ja) * | 2002-08-02 | 2004-03-04 | Nec Electronics Corp | 半導体記憶装置及びその製造方法 |
-
2003
- 2003-12-16 US US10/596,573 patent/US7701015B2/en not_active Expired - Fee Related
- 2003-12-16 AU AU2003300962A patent/AU2003300962A1/en not_active Abandoned
- 2003-12-16 CN CNB2003801108278A patent/CN100442490C/zh not_active Expired - Fee Related
- 2003-12-16 JP JP2005512432A patent/JP4716870B2/ja not_active Expired - Fee Related
- 2003-12-16 WO PCT/US2003/040003 patent/WO2005062380A1/en active Application Filing
- 2003-12-16 EP EP03819162A patent/EP1695383A4/en not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6297349A (ja) * | 1985-10-24 | 1987-05-06 | Agency Of Ind Science & Technol | 配線およびその形成方法 |
JP2001267520A (ja) * | 2000-03-21 | 2001-09-28 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2003110095A (ja) * | 2001-08-08 | 2003-04-11 | Agilent Technol Inc | 集積回路およびその形成方法 |
WO2003021676A2 (de) * | 2001-08-31 | 2003-03-13 | Infineon Technologies Ag | Kontaktierung des emitterkontakts einer halbleitervorrichtung |
Also Published As
Publication number | Publication date |
---|---|
EP1695383A4 (en) | 2007-12-12 |
US7701015B2 (en) | 2010-04-20 |
JP4716870B2 (ja) | 2011-07-06 |
EP1695383A1 (en) | 2006-08-30 |
CN1879216A (zh) | 2006-12-13 |
US20090039522A1 (en) | 2009-02-12 |
WO2005062380A1 (en) | 2005-07-07 |
AU2003300962A1 (en) | 2005-07-14 |
CN100442490C (zh) | 2008-12-10 |
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