JP2007317692A - Semiconductor device, and its manufacturing process - Google Patents

Semiconductor device, and its manufacturing process Download PDF

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JP2007317692A
JP2007317692A JP2006142443A JP2006142443A JP2007317692A JP 2007317692 A JP2007317692 A JP 2007317692A JP 2006142443 A JP2006142443 A JP 2006142443A JP 2006142443 A JP2006142443 A JP 2006142443A JP 2007317692 A JP2007317692 A JP 2007317692A
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multilayer wiring
film
groove
wiring circuit
semiconductor device
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Aiko Mizusawa
愛子 水澤
Osamu Okada
修 岡田
Takeshi Wakabayashi
猛 若林
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent exfoliation between insulating films in a semiconductor device where two layers of insulating film composed of a low dielectric constant material such as BCB and two layers of interconnection are laminated alternately on a silicon substrate. <P>SOLUTION: On the upper surface of a passivation film 3 of silicon oxide, or the like, which is provided on the upper surface of a silicon substrate 1 excepting the peripheral part thereof, first and second insulating films 5 and 9 and first and second interconnections 8 and 12 formed of the low dielectric constant material such as BCB and the like are laminated alternately. Upper surface of the second insulating film 9 including the second interconnection 12 and the side face of the first and second insulating films 5 and 9 are covered with a sealing film 14 of epoxy-based resin, or the like. With such an arrangement, exfoliation can be prevented between the first and second insulating films 5 and 9. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

この発明は半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

従来の半導体装置には、ＣＳＰ(chip size package)と呼ばれるもので、半導体基板上に設けられた酸化シリコン等からなるパッシベーション膜の上面にポリイミド系樹脂からなる保護膜が設けられ、保護膜の上面に配線が設けられ、配線の接続パッド部上面に柱状電極が設けられ、配線上および保護膜の上面にエポキシ系樹脂等からなる封止膜がその上面が柱状電極の上面と面一となるように設けられ、柱状電極の上面に半田ボールが設けられたものがある（例えば、特許文献１参照）。   A conventional semiconductor device is called a CSP (chip size package), and a protective film made of polyimide resin is provided on an upper surface of a passivation film made of silicon oxide or the like provided on a semiconductor substrate. Wiring is provided, columnar electrodes are provided on the upper surface of the connection pad portion of the wiring, and an upper surface of the sealing film made of epoxy resin on the wiring and the upper surface of the protective film is flush with the upper surface of the columnar electrode. And a solder ball is provided on the upper surface of the columnar electrode (see, for example, Patent Document 1).

特開２００４−３４９４６１号公報JP 2004-349461 A

ところで、最近では、上記のような半導体装置を高周波用として用いるため、保護膜（絶縁膜）の材料として、誘電率がポリイミド系樹脂の誘電率３．３程度よりも低いＢＣＢ（benzocyclobutene）（誘電率２．５程度）等の低誘電率材料を用いる技術が注目されている。この場合、上記のような半導体装置には、半導体基板上のパッシベーション膜上に絶縁膜と配線とを交互に積層して多層配線構造としたものがある。   Recently, since the semiconductor device as described above is used for high frequency, BCB (benzocyclobutene) (dielectric) having a dielectric constant lower than the dielectric constant of about 3.3 of a polyimide resin is used as a material for the protective film (insulating film). A technique using a low dielectric constant material such as a ratio of about 2.5) has attracted attention. In this case, some semiconductor devices as described above have a multilayer wiring structure in which insulating films and wirings are alternately stacked on a passivation film on a semiconductor substrate.

しかして、ＢＣＢ等の低誘電率材料は、その分子組成が電気双極子を持たない、非極性結合を有するものであるために、このような材料を用いて多層配線構造を形成すると絶縁膜相互の界面の結合力が不足し、半導体ウエハをダイシングする工程において、絶縁膜が剥離するという問題がある。絶縁膜の剥離は、水分の浸入や、機械的ストレスの発生に直結するため、半導体装置の信頼性を大きく損なうものである。   A low dielectric constant material such as BCB has a non-polar bond with a molecular composition that does not have an electric dipole. Therefore, when a multilayer wiring structure is formed using such a material, insulating films can be connected to each other. There is a problem that the insulating film peels off in the process of dicing the semiconductor wafer due to insufficient bonding force at the interface. The peeling of the insulating film is directly linked to the ingress of moisture and the occurrence of mechanical stress, and thus greatly impairs the reliability of the semiconductor device.

そこで、この発明は、ＢＣＢ等の低誘電率材料からなる絶縁膜の相互の剥離を確実に防止して信頼性を向上することができる半導体装置およびその製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reliably prevent mutual peeling of insulating films made of a low dielectric constant material such as BCB and improve reliability.

この発明は、上記目的を達成するため、半導体基板上の周辺部を除く領域にＢＣＢ、フッ化エチレン樹脂（テフロン（登録商標））、フッ素化ポリイミド、ポリオレフィン樹脂、ポリイミド等の樹脂にフィラーを加えた材料、有機ポリマー系のＬｏｗ−ｋ材料のいずれかを含む複数の絶縁膜と接続パッド部を有する少なくとも１つの配線とが交互に積層された多層配線回路部を設け、多層配線回路部の複数の絶縁膜の側面を封止膜（あるいは保護膜）で覆うようにしたことを特徴とするものである。   In order to achieve the above object, the present invention adds a filler to a resin such as BCB, a fluorinated ethylene resin (Teflon (registered trademark)), a fluorinated polyimide, a polyolefin resin, and a polyimide in the region excluding the peripheral portion on the semiconductor substrate. A multilayer wiring circuit portion in which a plurality of insulating films including any one of the above materials and organic polymer low-k materials and at least one wiring having a connection pad portion are alternately stacked is provided, and a plurality of multilayer wiring circuit portions are provided. The side surface of the insulating film is covered with a sealing film (or a protective film).

この発明によれば、半導体基板上の周辺部を除く領域にＢＣＢ等の低誘電率材料からなる複数の絶縁膜と接続パッド部を有する少なくとも１つの配線とが交互に積層された多層配線回路部を設け、多層配線回路部の複数の絶縁膜の側面を封止膜（あるいは保護膜）で覆っているので、ＢＣＢ等の低誘電率材料からなる絶縁膜の相互の剥離を確実に防止して信頼性を向上することができる。   According to the present invention, a multilayer wiring circuit portion in which a plurality of insulating films made of a low dielectric constant material such as BCB and at least one wiring having a connection pad portion are alternately stacked in a region excluding the peripheral portion on the semiconductor substrate. Since the side surfaces of the plurality of insulating films of the multilayer wiring circuit portion are covered with a sealing film (or protective film), it is possible to reliably prevent the insulating films made of a low dielectric constant material such as BCB from being separated from each other. Reliability can be improved.

（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の断面図を示す。この半導体装置は、一般的にはＣＳＰと呼ばれるものであり、シリコン基板（半導体基板）１を備えている。シリコン基板１の上面には所定の機能の集積回路（図示せず）が設けられ、上面周辺部には、２個のみを図示するが実際には多数の、アルミニウム系金属等からなる接続パッド２が集積回路に接続されて設けられている。 (First embodiment)
FIG. 1 is a sectional view of a semiconductor device as a first embodiment of the present invention. This semiconductor device is generally called a CSP and includes a silicon substrate (semiconductor substrate) 1. An integrated circuit (not shown) having a predetermined function is provided on the upper surface of the silicon substrate 1, and only two of them are shown in the periphery of the upper surface, but a large number of connection pads 2 made of aluminum metal or the like are actually shown. Are connected to the integrated circuit.

接続パッド２の中央部を除くシリコン基板１の上面には酸化シリコン等からなるパッシベーション膜３が設けられ、接続パッド２の中央部はパッシベーション膜３に設けられた開口部４を介して露出されている。パッシベーション膜３の上面の周辺部を除く領域には、ＢＣＢ、フッ化エチレン樹脂（テフロン（登録商標））、フッ素化ポリイミド、ポリオレフィン樹脂、ポリイミド等の樹脂にフィラーを加えた材料、有機ポリマー系のＬｏｗ−ｋ材料のいずれかを含む第１の絶縁膜５が設けられている。パッシベーション膜３の開口部４に対応する部分における第１の絶縁膜５には、パッシベーション膜３の開口部４よりもやや大きめの開口部６が設けられている。   A passivation film 3 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 1 except for the central part of the connection pad 2, and the central part of the connection pad 2 is exposed through an opening 4 provided in the passivation film 3. Yes. In the region excluding the peripheral portion on the upper surface of the passivation film 3, a material obtained by adding a filler to a resin such as BCB, fluorinated ethylene resin (Teflon (registered trademark)), fluorinated polyimide, polyolefin resin, polyimide, or an organic polymer type A first insulating film 5 containing any of the low-k materials is provided. An opening 6 that is slightly larger than the opening 4 of the passivation film 3 is provided in the first insulating film 5 at a portion corresponding to the opening 4 of the passivation film 3.

第１の絶縁膜５の上面には銅等からなる第１の下地金属層７が設けられている。第１の下地金属層７の上面全体には銅からなる第１の配線８が設けられている。第１の下地金属層７を含む第１の配線８の一端部は、パッシベーション膜３および第１の絶縁膜５の開口部４、６を介して接続パッド２に接続されている。   A first base metal layer 7 made of copper or the like is provided on the upper surface of the first insulating film 5. A first wiring 8 made of copper is provided on the entire top surface of the first base metal layer 7. One end of the first wiring 8 including the first base metal layer 7 is connected to the connection pad 2 via the openings 4 and 6 of the passivation film 3 and the first insulating film 5.

第１の配線８を含む第１の絶縁膜５の上面にはＢＣＢ、フッ化エチレン樹脂（テフロン（登録商標））、フッ素化ポリイミド、ポリオレフィン樹脂、ポリイミド等の樹脂にフィラーを加えた材料、有機ポリマー系のＬｏｗ−ｋ材料のいずれかを含む第２の絶縁膜９が設けられている。第１の配線８の接続パッド部に対応する部分における第２の絶縁膜９には開口部１０が設けられている。第２の絶縁膜９の上面には銅等からなる第２の下地金属層１１が設けられている。第２の下地金属層１１の上面全体には銅からなる第２の配線１２が設けられている。第２の下地金属層１１を含む第２の配線１２の一端部は、第２の絶縁膜９の開口部１０を介して第１の配線８の接続パッド部に接続されている。ここで、第１、第２の絶縁膜５、９および第１、第２の配線８、１２により、多層配線回路部が構成されている。   A material obtained by adding a filler to a resin such as BCB, fluorinated ethylene resin (Teflon (registered trademark)), fluorinated polyimide, polyolefin resin, polyimide, or the like on the upper surface of the first insulating film 5 including the first wiring 8, organic A second insulating film 9 including any one of polymer-based Low-k materials is provided. An opening 10 is provided in the second insulating film 9 in a portion corresponding to the connection pad portion of the first wiring 8. A second base metal layer 11 made of copper or the like is provided on the upper surface of the second insulating film 9. A second wiring 12 made of copper is provided on the entire upper surface of the second base metal layer 11. One end of the second wiring 12 including the second base metal layer 11 is connected to the connection pad portion of the first wiring 8 through the opening 10 of the second insulating film 9. Here, the first and second insulating films 5 and 9 and the first and second wirings 8 and 12 constitute a multilayer wiring circuit section.

第２の配線１２の接続パッド部上面には銅からなる柱状電極１３が設けられている。第２の配線１２を含む第２の絶縁膜９の上面およびパッシベーション膜３の周辺部上面にはエポキシ系樹脂等からなる封止膜１４がその上面が柱状電極１３の上面と面一となるように設けられている。この状態では、第１、第２の絶縁膜５、９の側面は封止膜１４によって覆われている。柱状電極１３の上面には半田ボール１５が設けられている。   A columnar electrode 13 made of copper is provided on the upper surface of the connection pad portion of the second wiring 12. On the upper surface of the second insulating film 9 including the second wiring 12 and the upper surface of the peripheral portion of the passivation film 3, the sealing film 14 made of epoxy resin or the like is flush with the upper surface of the columnar electrode 13. Is provided. In this state, the side surfaces of the first and second insulating films 5 and 9 are covered with the sealing film 14. A solder ball 15 is provided on the upper surface of the columnar electrode 13.

以上のように、この半導体装置では、第１、第２の絶縁膜５、９の側面を封止膜１４によって覆っているので、第１、第２の絶縁膜５、９をＢＣＢ等の低誘電率材料によって形成しても、第１、第２の絶縁膜５、９間において剥離が生じにくいようにすることができる。この点は、ＢＣＢ等の低誘電率材料からなる絶縁膜および配線を各々３層以上交互に積層した多層配線回路部の場合も同様である。   As described above, in this semiconductor device, since the side surfaces of the first and second insulating films 5 and 9 are covered with the sealing film 14, the first and second insulating films 5 and 9 are made of a low material such as BCB. Even if it is formed of a dielectric constant material, it is possible to prevent separation between the first and second insulating films 5 and 9. This is the same in the case of a multilayer wiring circuit unit in which three or more layers of insulating films and wirings made of a low dielectric constant material such as BCB are alternately stacked.

次に、この半導体装置の製造方法の一例について説明する。まず、図２に示すように、ウエハ状態のシリコン基板（以下、半導体ウエハ２１という）上にアルミニウム系金属等からなる接続パッド２および酸化シリコン等からなるパッシベーション膜３が設けられ、接続パッド２の中央部がパッシベーション膜３に形成された開口部４を介して露出されたものを用意する。   Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 2, a connection pad 2 made of an aluminum-based metal or the like and a passivation film 3 made of silicon oxide or the like are provided on a silicon substrate in a wafer state (hereinafter referred to as a semiconductor wafer 21). The one whose central portion is exposed through the opening 4 formed in the passivation film 3 is prepared.

この場合、半導体ウエハ２１の上面の各半導体装置形成領域には所定の機能の集積回路（図示せず）が形成され、接続パッド２はそれぞれ対応する領域に形成された集積回路に電気的に接続されている。なお、図２において、符号２２で示す領域はダイシングストリートに対応する領域である。   In this case, an integrated circuit (not shown) having a predetermined function is formed in each semiconductor device formation region on the upper surface of the semiconductor wafer 21, and the connection pads 2 are electrically connected to the integrated circuits formed in the corresponding regions. Has been. In FIG. 2, an area indicated by reference numeral 22 is an area corresponding to dicing street.

次に、図３に示すように、スクリーン印刷法、スピンコート法等により、パッシベーション膜３の開口部４を介して露出された接続パッド２の上面を含むパッシベーション膜３の上面に、ＢＣＢ、フッ化エチレン樹脂（テフロン（登録商標））、フッ素化ポリイミド、ポリオレフィン樹脂、ポリイミド等の樹脂にフィラーを加えた材料、有機ポリマー系のＬｏｗ−ｋ材料のいずれかを含む第１の絶縁膜５を形成する。次に、フォトリソグラフィ法により、パッシベーション膜３の開口部４に対応する部分における第１の絶縁膜５に、パッシベーション膜３の開口部４よりもやや大きめの開口部６を形成する。   Next, as shown in FIG. 3, BCB, fluorine, etc. are formed on the upper surface of the passivation film 3 including the upper surface of the connection pad 2 exposed through the opening 4 of the passivation film 3 by screen printing, spin coating, or the like. A first insulating film 5 containing any one of a fluoroethylene resin (Teflon (registered trademark)), a fluorinated polyimide, a polyolefin resin, a material obtained by adding a filler to a resin such as polyimide, or an organic polymer low-k material is formed. To do. Next, an opening 6 slightly larger than the opening 4 of the passivation film 3 is formed in the first insulating film 5 at a portion corresponding to the opening 4 of the passivation film 3 by photolithography.

次に、図４に示すように、パッシベーション膜３および第１の絶縁膜５の開口部４、６を介して露出された接続パッド２の上面を含む第１の絶縁膜５の上面全体に第１の下地金属層７を形成する。この場合、第１の下地金属層７は、無電解メッキにより形成された銅層のみであってもよく、またスパッタにより形成された銅層のみであってもよく、さらにスパッタにより形成されたチタン等の薄膜層上にスパッタにより銅層を形成したものであってもよい。   Next, as shown in FIG. 4, the entire upper surface of the first insulating film 5 including the upper surface of the connection pad 2 exposed through the openings 4 and 6 of the passivation film 3 and the first insulating film 5 is formed on the entire upper surface. 1 base metal layer 7 is formed. In this case, the first base metal layer 7 may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and titanium formed by sputtering. A copper layer may be formed on the thin film layer by sputtering.

次に、第１の下地金属層７の上面にメッキレジスト膜２３をパターン形成する。この場合、第１の配線８形成領域に対応する部分におけるメッキレジスト膜２３には開口部２４が形成されている。次に、第１の下地金属層７をメッキ電流路とした銅の電解メッキを行なうことにより、メッキレジスト膜２３の開口部２４内の第１の下地金属層７の上面に第１の配線８を形成する。次に、メッキレジスト膜２３を剥離し、次いで、第１の配線８をマスクとして第１の下地金属層７の不要な部分をエッチングして除去すると、図５に示すように、第１の配線８下にのみ第１の下地金属層７が残存される。   Next, a plating resist film 23 is patterned on the upper surface of the first base metal layer 7. In this case, an opening 24 is formed in the plating resist film 23 in a portion corresponding to the first wiring 8 formation region. Next, the first wiring 8 is formed on the upper surface of the first base metal layer 7 in the opening 24 of the plating resist film 23 by performing electrolytic plating of copper using the first base metal layer 7 as a plating current path. Form. Next, the plating resist film 23 is peeled off, and then unnecessary portions of the first base metal layer 7 are removed by etching using the first wiring 8 as a mask. As shown in FIG. 8, the first base metal layer 7 remains only under.

次に、図６に示すように、スクリーン印刷法、スピンコート法等により、第１の配線８を含む第１の絶縁膜５の上面に、ＢＣＢ、フッ化エチレン樹脂（テフロン（登録商標））、フッ素化ポリイミド、ポリオレフィン樹脂、ポリイミド等の樹脂にフィラーを加えた材料、有機ポリマー系のＬｏｗ−ｋ材料のいずれかを含む第２の絶縁膜９を形成する。   Next, as shown in FIG. 6, BCB, fluoroethylene resin (Teflon (registered trademark)) is formed on the upper surface of the first insulating film 5 including the first wiring 8 by screen printing, spin coating, or the like. Then, a second insulating film 9 containing any of a material obtained by adding a filler to a resin such as fluorinated polyimide, polyolefin resin, or polyimide, or an organic polymer low-k material is formed.

次に、図７に示すように、レーザビームを照射するレーザ加工により、第１の配線８の接続パッド部に対応する部分における第１の絶縁膜９に開口部１０を形成し、且つ、ダイシングストリート２２およびその両側の領域における第１、第２の絶縁膜５、９に溝２５を形成する。この状態では、ダイシングストリート２２およびその両側の領域におけるパッシベーション膜３の上面は溝２５を介して露出されている。   Next, as shown in FIG. 7, an opening 10 is formed in the first insulating film 9 in a portion corresponding to the connection pad portion of the first wiring 8 by laser processing with laser beam irradiation, and dicing is performed. A trench 25 is formed in the first and second insulating films 5 and 9 in the street 22 and regions on both sides thereof. In this state, the upper surface of the passivation film 3 in the dicing street 22 and the regions on both sides thereof is exposed through the groove 25.

ここで、一例として、溝２５の幅は、１０〜１０００μｍ×２＋ダイシングストリート２２（ダイシングカッタ）の幅となっている。すなわち、図１を参照して説明すると、第１、第２の絶縁膜５、９の側面を覆っている封止膜１４の幅は１０〜１０００μｍである。なお、レーザビームを照射するレーザ加工の代わりに、金属マスクをマスクとしてＣＦ4ガスやＳＦ6ガス等を用いたブラズマエッチング（ドライエッチング）を行うようにしてもよい。 Here, as an example, the width of the groove 25 is the width of 10 to 1000 μm × 2 + dicing street 22 (dicing cutter). That is, referring to FIG. 1, the width of the sealing film 14 covering the side surfaces of the first and second insulating films 5 and 9 is 10 to 1000 μm. Note that plasma etching (dry etching) using CF 4 gas, SF 6 gas, or the like may be performed using a metal mask as a mask instead of laser processing with laser beam irradiation.

次に、図８に示すように、第２の絶縁膜９の開口部１０を介して露出された第１の配線８の接続パッド部上面および溝２５を介して露出されたパッシベーション膜３の上面を含む第２の絶縁膜９の上面全体に、無電解メッキ等により、第２の下地金属層１１を形成する。次に、第２の下地金属層１１の上面にメッキレジスト膜２６をパターン形成する。この場合、第２の配線１２形成領域に対応する部分におけるメッキレジスト膜２６には開口部２７が形成されている。次に、第２の下地金属層１１をメッキ電流路とした銅の電解メッキを行なうことにより、メッキレジスト膜２６の開口部２７内の第２の下地金属層１１の上面に第２の配線１２を形成する。次に、メッキレジスト膜２６を剥離する。   Next, as shown in FIG. 8, the connection pad portion upper surface of the first wiring 8 exposed through the opening 10 of the second insulating film 9 and the upper surface of the passivation film 3 exposed through the groove 25. A second base metal layer 11 is formed on the entire upper surface of the second insulating film 9 including, by electroless plating or the like. Next, a plating resist film 26 is patterned on the upper surface of the second base metal layer 11. In this case, an opening 27 is formed in the plating resist film 26 in a portion corresponding to the second wiring 12 formation region. Next, the second wiring 12 is formed on the upper surface of the second base metal layer 11 in the opening 27 of the plating resist film 26 by performing electrolytic plating of copper using the second base metal layer 11 as a plating current path. Form. Next, the plating resist film 26 is peeled off.

次に、図９に示すように、第２の配線１２を含む第２の下地金属層１１の上面にメッキレジスト膜２８をパターン形成する。この場合、第２の配線１２の接続パッド部（柱状電極１３形成領域）に対応する部分におけるメッキレジスト膜２８には開口部２９が形成されている。次に、第２の下地金属層１１をメッキ電流路とした銅の電解メッキを行うことにより、メッキレジスト膜２８の開口部２９内の第２の配線１２の接続パッド部上面に柱状電極１３を形成する。次に、メッキレジスト膜２８を剥離し、次いで、第２の配線１２をマスクとして第２の下地金属層１１の不要な部分をエッチングして除去すると、図１０に示すように、第２の配線１２下にのみ第２の下地金属層１１が残存される。   Next, as shown in FIG. 9, a plating resist film 28 is patterned on the upper surface of the second base metal layer 11 including the second wiring 12. In this case, an opening 29 is formed in the plating resist film 28 in a portion corresponding to the connection pad portion (columnar electrode 13 formation region) of the second wiring 12. Next, by performing electrolytic plating of copper using the second base metal layer 11 as a plating current path, the columnar electrode 13 is formed on the upper surface of the connection pad portion of the second wiring 12 in the opening 29 of the plating resist film 28. Form. Next, the plating resist film 28 is peeled off, and then unnecessary portions of the second base metal layer 11 are removed by etching using the second wiring 12 as a mask, as shown in FIG. The second base metal layer 11 is left only under 12.

次に、図１１に示すように、スクリーン印刷法、スピンコート法等により、第２の配線１２、柱状電極１３を含む第２の絶縁膜９の上面および溝２５を介して露出されたパッシベーション膜３の上面にエポキシ系樹脂等からなる封止膜１４をその厚さが柱状電極１３の高さよりも厚くなるように形成する。したがって、この状態では、柱状電極１３の上面は封止膜１４によって覆われている。また、第１、第２の絶縁膜５、９の側面は封止膜１４によって覆われている。   Next, as shown in FIG. 11, the passivation film exposed through the upper surface of the second insulating film 9 including the second wiring 12 and the columnar electrode 13 and the groove 25 by screen printing, spin coating, or the like. A sealing film 14 made of an epoxy resin or the like is formed on the upper surface of 3 so that its thickness is greater than the height of the columnar electrode 13. Therefore, in this state, the upper surface of the columnar electrode 13 is covered with the sealing film 14. The side surfaces of the first and second insulating films 5 and 9 are covered with a sealing film 14.

次に、封止膜１４の上面側を適宜に研削し、図１２に示すように、柱状電極１３の上面を露出させ、且つ、この露出された柱状電極１３の上面を含む封止膜１４の上面を平坦化する。次に、図１３に示すように、柱状電極１３の上面に半田ボール１５を形成する。次に、図１４に示すように、封止膜１４、パッシベーション膜３および半導体ウエハ２１を溝２５内の中央部のダイシングストリート２２に沿って切断すると、図１に示すように、第１、第２の絶縁膜５、９の側面が封止膜１４によって覆われた構造の半導体装置が複数個得られる。   Next, the upper surface side of the sealing film 14 is appropriately ground to expose the upper surface of the columnar electrode 13 and the sealing film 14 including the exposed upper surface of the columnar electrode 13 as shown in FIG. Flatten the top surface. Next, as shown in FIG. 13, solder balls 15 are formed on the upper surface of the columnar electrode 13. Next, as shown in FIG. 14, when the sealing film 14, the passivation film 3, and the semiconductor wafer 21 are cut along the dicing street 22 at the center in the groove 25, the first and first A plurality of semiconductor devices having a structure in which the side surfaces of the two insulating films 5 and 9 are covered with the sealing film 14 are obtained.

なお、上記実施形態において、パッシベーション膜３の上面が溝２５の底部の如く図示されているが、レーザビームによりパッシベーション膜３が途中までまたは全部除去されるように溝２５を形成し、溝２５の底部がパッシベーション膜３の上面より陥没するようにしてもよい。また、レーザビームによりパッシベーション膜３の全部および半導体ウエハ２１の上面が除去されるように溝２５を形成し、溝２５の底部が半導体ウエハ２１の上面より陥没するようにしてもよい。   In the above embodiment, the upper surface of the passivation film 3 is illustrated as the bottom of the groove 25. However, the groove 25 is formed so that the passivation film 3 is partially or completely removed by a laser beam. The bottom may be recessed from the upper surface of the passivation film 3. Alternatively, the groove 25 may be formed so that the entire passivation film 3 and the upper surface of the semiconductor wafer 21 are removed by the laser beam, and the bottom of the groove 25 may be recessed from the upper surface of the semiconductor wafer 21.

（第２実施形態）
図１５はこの発明の第２実施形態としての半導体装置の断面図を示す。この半導体装置において、図１に示す半導体装置と異なる点は、第１の絶縁膜５の開口部６の大きさをパッシベーション膜３の開口部４の大きさと同じとした点である。この場合、図２に示す状態において、パッシベーション膜３に開口部４を形成せず、図３に示す工程において、第１の絶縁膜５およびパッシベーション膜３に開口部６、４を連続して形成すると、工程数を少なくすることができる。 (Second Embodiment)
FIG. 15 is a sectional view of a semiconductor device as a second embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that the size of the opening 6 of the first insulating film 5 is the same as the size of the opening 4 of the passivation film 3. In this case, the opening 4 is not formed in the passivation film 3 in the state shown in FIG. 2, and the openings 6 and 4 are continuously formed in the first insulating film 5 and the passivation film 3 in the step shown in FIG. Then, the number of processes can be reduced.

（第３実施形態）
図１６はこの発明の第２実施形態としての半導体装置の断面図を示す。この半導体装置において、図１５に示す半導体装置と異なる点は、第２の絶縁膜９の上面および第１、第２の絶縁膜５、９の側面にポリイミド系樹脂等からなる保護膜１６を設け、保護膜１６の上面に第２の下地金属層１１を含む第２の配線１２を第２、保護膜９、１６の開口部１０、１７を介して第１の配線８の接続パッド部に接続させて設けた点である。この場合、保護膜１６の上面および側面は封止膜１４によって覆われている。 (Third embodiment)
FIG. 16 is a sectional view of a semiconductor device as a second embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 15 in that a protective film 16 made of polyimide resin or the like is provided on the upper surface of the second insulating film 9 and the side surfaces of the first and second insulating films 5 and 9. The second wiring 12 including the second base metal layer 11 on the upper surface of the protective film 16 is connected to the connection pad portion of the first wiring 8 through the openings 10 and 17 of the second and protective films 9 and 16. It is the point which was allowed to be provided. In this case, the upper surface and side surfaces of the protective film 16 are covered with the sealing film 14.

この半導体装置を製造する場合には、一例として、図７に示す工程後に、図１７に示すように、スクリーン印刷法、スピンコート法等により、第２の絶縁膜９の開口部１０を介して露出された第１の配線８の接続パッド部上面を含む第２の絶縁膜９の上面および溝２５を介して露出されたパッシベーション膜３の上面にポリイミド系樹脂等からなる保護膜１６を形成する。   In the case of manufacturing this semiconductor device, as an example, after the step shown in FIG. 7, as shown in FIG. 17, through the opening 10 of the second insulating film 9 by screen printing, spin coating, or the like. A protective film 16 made of polyimide resin or the like is formed on the upper surface of the second insulating film 9 including the upper surface of the exposed connection pad portion of the first wiring 8 and the upper surface of the passivation film 3 exposed through the groove 25. .

次に、図１８に示すように、レーザビームを照射するレーザ加工により、第２の絶縁膜９の開口部１０に対応する部分における保護膜１６に開口部１７を形成し、且つ、ダイシングストリート２２およびその両側の領域における保護膜１６に溝２５よりもやや幅狭の溝２５ａを形成する。以下の工程は、上記第１実施形態の場合と同様であるので、省略する。   Next, as shown in FIG. 18, an opening 17 is formed in the protective film 16 in a portion corresponding to the opening 10 of the second insulating film 9 by laser processing with laser beam irradiation, and a dicing street 22 is formed. Then, a groove 25 a slightly narrower than the groove 25 is formed in the protective film 16 in the regions on both sides thereof. Since the following steps are the same as those in the first embodiment, a description thereof will be omitted.

なお、上記第３実施形態において、保護膜１６の膜厚を厚く形成し、第１、第２の絶縁膜５、９は保護膜１６のみで覆い、封止膜１４は保護膜１６の上部側のみを覆う構造としてもよい。   In the third embodiment, the protective film 16 is formed thick, the first and second insulating films 5 and 9 are covered only with the protective film 16, and the sealing film 14 is on the upper side of the protective film 16. It is good also as a structure which covers only.

この発明の第１実施形態としての半導体装置の断面図。1 is a cross-sectional view of a semiconductor device as a first embodiment of the present invention. 図１に示す半導体装置の製造に際し、当初用意したものの断面図。Sectional drawing of what was initially prepared in the case of manufacture of the semiconductor device shown in FIG. 図２に続く工程の断面図。Sectional drawing of the process following FIG. 図３に続く工程の断面図。Sectional drawing of the process following FIG. 図４に続く工程の断面図。Sectional drawing of the process following FIG. 図５に続く工程の断面図。Sectional drawing of the process following FIG. 図６に続く工程の断面図。Sectional drawing of the process following FIG. 図７に続く工程の断面図。Sectional drawing of the process following FIG. 図８に続く工程の断面図。FIG. 9 is a cross-sectional view of the process following FIG. 8. 図９に続く工程の断面図。Sectional drawing of the process following FIG. 図１０に続く工程の断面図。Sectional drawing of the process following FIG. 図１１に続く工程の断面図。Sectional drawing of the process following FIG. 図１２に続く工程の断面図。Sectional drawing of the process following FIG. 図１３に続く工程の断面図。Sectional drawing of the process following FIG. この発明の第２実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 2nd Embodiment of this invention. この発明の第３実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 3rd Embodiment of this invention. 図１６に示す半導体装置の製造に際し、所定の工程の断面図。FIG. 17 is a cross-sectional view of a predetermined process when the semiconductor device shown in FIG. 16 is manufactured. 図１７に続く工程の断面図。FIG. 18 is a cross-sectional view of the process following FIG. 17.

符号の説明Explanation of symbols

１ シリコン基板
２ 接続パッド
３ パッシベーション膜
５ 第１の絶縁膜
７ 第１の下地金属層
８ 第１の配線
９ 第２の絶縁膜
１１ 第２の下地金属層
１２ 第２の配線
１３ 柱状電極
１４ 封止膜
１５ 半田ボール
１６ 保護膜
２１ 半導体ウエハ
２２ ダイシングストリート
２５ 溝 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Connection pad 3 Passivation film 5 1st insulating film 7 1st base metal layer 8 1st wiring 9 2nd insulating film 11 2nd base metal layer 12 2nd wiring 13 Columnar electrode 14 Sealing Stop film 15 Solder ball 16 Protective film 21 Semiconductor wafer 22 Dicing street 25 Groove

Claims (10)

半導体基板と、前記半導体基板上の周辺部を除く領域にＢＣＢ、フッ化エチレン樹脂（テフロン（登録商標））、フッ素化ポリイミド、ポリオレフィン樹脂、ポリイミド等の樹脂にフィラーを加えた材料、有機ポリマー系のＬｏｗ−ｋ材料のいずれかを含む複数の絶縁膜と接続パッド部を有する少なくとも１つの配線とが交互に積層された多層配線回路部と、前記多層配線回路部の配線の接続パッド部上に設けられた柱状電極と、前記多層配線回路部および前記半導体基板の周辺部を覆って設けられた封止膜とを備え、前記多層配線回路部の複数の絶縁膜の側面が前記封止膜によって覆われていることを特徴とする半導体装置。   A material obtained by adding a filler to a semiconductor substrate and a resin such as BCB, fluorinated ethylene resin (Teflon (registered trademark)), fluorinated polyimide, polyolefin resin, polyimide, etc., in an area other than the peripheral portion on the semiconductor substrate, an organic polymer system A multilayer wiring circuit portion in which a plurality of insulating films including any of the low-k materials and at least one wiring having a connection pad portion are alternately laminated, and a wiring pad portion of the multilayer wiring circuit portion; A columnar electrode provided; and a sealing film provided to cover a peripheral portion of the multilayer wiring circuit portion and the semiconductor substrate, and the side surfaces of the plurality of insulating films of the multilayer wiring circuit portion are formed by the sealing film. A semiconductor device which is covered. 半導体基板と、前記半導体基板上の周辺部を除く領域にＢＣＢ、フッ化エチレン樹脂（テフロン（登録商標））、フッ素化ポリイミド、ポリオレフィン樹脂、ポリイミド等の樹脂にフィラーを加えた材料、有機ポリマー系のＬｏｗ−ｋ材料のいずれかを含む複数の絶縁膜と接続パッド部を有する少なくとも１つの配線とが交互に積層された多層配線回路部と、前記多層配線回路部の上面および側面を覆って設けられた保護膜と、前記保護膜上に設けられ、接続パッド部を有する上層配線と、前記上層配線の接続パッド部上に設けられた柱状電極と、前記柱状電極間に設けられた封止膜とを備えていることを特徴とする半導体装置。   A material obtained by adding a filler to a semiconductor substrate and a resin such as BCB, fluorinated ethylene resin (Teflon (registered trademark)), fluorinated polyimide, polyolefin resin, polyimide, etc., in an area other than the peripheral portion on the semiconductor substrate, an organic polymer system A multilayer wiring circuit portion in which a plurality of insulating films containing any of the low-k materials and at least one wiring having a connection pad portion are alternately laminated, and covering the upper surface and side surfaces of the multilayer wiring circuit portion A protective film provided on the protective film and having a connection pad portion, a columnar electrode provided on the connection pad portion of the upper wiring, and a sealing film provided between the columnar electrodes And a semiconductor device. 請求項２に記載の発明において、前記保護膜は前記半導体基板上の周辺部を除く領域に設けられ、前記多層配線回路部の側面は前記保護膜で覆われ、前記保護膜の側面は前記封止膜で覆われていることを特徴とする半導体装置。   In the invention according to claim 2, the protective film is provided in a region excluding a peripheral part on the semiconductor substrate, a side surface of the multilayer wiring circuit part is covered with the protective film, and a side surface of the protective film is the sealing member. A semiconductor device characterized by being covered with a stop film. 請求項１または３に記載の発明において、前記多層配線回路部は前記半導体基板上に設けられたパッシベーション膜上の周辺部を除く領域に設けられ、前記パッシベーション膜の周辺部上に前記封止膜が設けられていることを特徴とする半導体装置。   4. The invention according to claim 1, wherein the multilayer wiring circuit portion is provided in a region excluding a peripheral portion on a passivation film provided on the semiconductor substrate, and the sealing film is provided on a peripheral portion of the passivation film. A semiconductor device is provided. 請求項１〜４のいずれかに記載の発明において、前記柱状電極上に半田ボールが設けられていることを特徴とする半導体装置。   5. The semiconductor device according to claim 1, wherein solder balls are provided on the columnar electrodes. 半導体ウエハ上に、ＢＣＢ、フッ化エチレン樹脂（テフロン（登録商標））、フッ素化ポリイミド、ポリオレフィン樹脂、ポリイミド等の樹脂にフィラーを加えた材料、有機ポリマー系のＬｏｗ−ｋ材料のいずれかを含む複数の絶縁膜と少なくとも１つの配線とを交互に積層して多層配線回路部を形成する工程と、
ダイシングストリート上およびその両側の領域における前記多層配線回路部の複数の絶縁膜を除去して溝を形成し、該溝を介して前記多層配線回路部の側面および前記半導体ウエハの上面を露出させる工程と、
前記多層配線回路部上に、接続パッド部を有する上層配線を形成する工程と、
前記上層配線の接続パッド部上に柱状電極を形成する工程と、
前記柱状電極間および前記溝内に充填された封止膜を形成する工程と、
前記溝内の前記封止膜および前記半導体ウエハを切断して、個々の半導体装置を複数個得る工程と、
を含むことを特徴とする半導体装置の製造方法。 Includes any of BCB, fluorinated ethylene resin (Teflon (registered trademark)), fluorinated polyimide, polyolefin resin, polyimide, and other materials with fillers or organic polymer low-k materials on a semiconductor wafer A step of alternately laminating a plurality of insulating films and at least one wiring to form a multilayer wiring circuit portion;
Removing a plurality of insulating films of the multilayer wiring circuit portion on the dicing street and regions on both sides thereof to form a groove, and exposing a side surface of the multilayer wiring circuit portion and an upper surface of the semiconductor wafer through the groove; When,
Forming an upper layer wiring having a connection pad on the multilayer wiring circuit unit;
Forming a columnar electrode on a connection pad portion of the upper layer wiring;
Forming a sealing film filled between the columnar electrodes and in the groove;
Cutting the sealing film and the semiconductor wafer in the groove to obtain a plurality of individual semiconductor devices;
A method for manufacturing a semiconductor device, comprising: 半導体ウエハ上に、ＢＣＢ、フッ化エチレン樹脂（テフロン（登録商標））、フッ素化ポリイミド、ポリオレフィン樹脂、ポリイミド等の樹脂にフィラーを加えた材料、有機ポリマー系のＬｏｗ−ｋ材料のいずれかを含む複数の絶縁膜と少なくとも１つの配線とを交互に積層して多層配線回路部を形成する工程と、
ダイシングストリート上およびその両側の領域における前記多層配線回路部の複数の絶縁膜を除去して第１の溝を形成し、該第１の溝を介して前記多層配線回路部の側面および前記半導体ウエハの上面を露出させる工程と、
前記第１の溝内および前記多層配線回路部上に保護膜を形成する工程と、
ダイシングストリート上およびその両側の領域における前記保護膜を除去して前記第１の溝よりも幅狭の第２の溝を形成し、該第２の溝を介して前記保護膜の側面および前記半導体ウエハの上面を露出させる工程と、
前記保護膜上に接続パッド部を有する上層配線を形成する工程と、
前記上層配線の接続パッド部上に柱状電極を形成する工程と、
前記柱状電極間および前記第２の溝内に充填された封止膜を形成する工程と、
前記第２の溝内の前記封止膜および前記半導体ウエハを切断して、個々の半導体装置を複数個得る工程と、
を含むことを特徴とする半導体装置の製造方法。 Includes any of BCB, fluorinated ethylene resin (Teflon (registered trademark)), fluorinated polyimide, polyolefin resin, polyimide, and other materials with fillers or organic polymer low-k materials on a semiconductor wafer A step of alternately laminating a plurality of insulating films and at least one wiring to form a multilayer wiring circuit portion;
A plurality of insulating films of the multilayer wiring circuit portion on the dicing street and on both sides thereof are removed to form a first groove, and the side surface of the multilayer wiring circuit portion and the semiconductor wafer are formed through the first groove. Exposing the upper surface of
Forming a protective film in the first groove and on the multilayer wiring circuit portion;
The protective film on the dicing street and the regions on both sides thereof is removed to form a second groove narrower than the first groove, and the side surface of the protective film and the semiconductor are formed through the second groove. Exposing the upper surface of the wafer;
Forming an upper layer wiring having a connection pad portion on the protective film;
Forming a columnar electrode on a connection pad portion of the upper layer wiring;
Forming a sealing film filled between the columnar electrodes and in the second groove;
Cutting the sealing film and the semiconductor wafer in the second groove to obtain a plurality of individual semiconductor devices;
A method for manufacturing a semiconductor device, comprising: 請求項７に記載の発明において、前記半導体ウエハを切断する工程は、前記保護膜の側面に、前記第２の溝内に充填された封止膜が残存するように切断することを特徴とする半導体装置の製造方法。   8. The semiconductor device according to claim 7, wherein the step of cutting the semiconductor wafer is performed so that a sealing film filled in the second groove remains on a side surface of the protective film. A method for manufacturing a semiconductor device. 請求項６〜８のいずれかに記載の発明において、前記多層配線回路部の複数の絶縁膜を除去する工程は、レーザビームを照射する工程を含むことを特徴とする半導体装置の製造方法。   9. The method of manufacturing a semiconductor device according to claim 6, wherein the step of removing the plurality of insulating films of the multilayer wiring circuit portion includes a step of irradiating a laser beam. 請求項６〜８のいずれかに記載の発明において、前記封止膜を形成した後に、前記柱状電極上に半田ボールを形成する工程を有することを特徴とする半導体装置の製造方法。   9. The method of manufacturing a semiconductor device according to claim 6, further comprising a step of forming solder balls on the columnar electrodes after forming the sealing film.
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