JP2007299984A - Laminated ceramic electronic component - Google Patents

Laminated ceramic electronic component Download PDF

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JP2007299984A
JP2007299984A JP2006127650A JP2006127650A JP2007299984A JP 2007299984 A JP2007299984 A JP 2007299984A JP 2006127650 A JP2006127650 A JP 2006127650A JP 2006127650 A JP2006127650 A JP 2006127650A JP 2007299984 A JP2007299984 A JP 2007299984A
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internal electrode
tip
wide portion
width
wide
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JP4770570B2 (en
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Satomi Okuni
聡巳 大國
Atsushi Yasuda
厚 安田
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Murata Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors

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  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated ceramic electronic component which hardly causes a variation in electric characteristics due to layer displacement etc occurring in a ceramic green sheet, and hardly produces damage etc caused by a concentration of an electric field on the tip of an internal electrode. <P>SOLUTION: The laminated ceramic electronic component 1 has such a configuration that the internal electrodes 3 and 5 of a first and a third layers are formed respectively at the same height separating from each other by a gap, the internal electrodes 4 and 6 of a second and a fourth layers are formed respectively at a different height separating from each other by a gap G2, the tip corners of the wide parts 3b to 6b of the first to fourth layers are each formed into a shape with corners whose inner angles are obtuse or a roundish shape, the tip corners of the wide parts 3b and 5b of the first and third layers do not overlap with the internal electrode 2 of the second layer through a ceramic layer, and the tip corners of the wide parts 4b and 6b of the second and fourth layers do not overlap with the internal electrode 3 of the first layer through a ceramic layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、例えば積層セラミックコンデンサのような積層セラミック電子部品に関し、より詳細には、内部電極の平面形状が改良されている積層セラミック電子部品に関する。   The present invention relates to a multilayer ceramic electronic component such as a multilayer ceramic capacitor, and more particularly to a multilayer ceramic electronic component in which the planar shape of internal electrodes is improved.

積層セラミックコンデンサなどの積層セラミック電子部品の製造に際しては、複数層のセラミックグリーンシートを、複数の内部電極を間に介在させて積層してなるセラミック生チップを焼成することにより、セラミック積層体が得られている。内部電極と、セラミック層とは異なる材料からなる。従って、一体焼成法により得られた上記セラミック積層体では、内部電極とセラミック層との間で、デラミネーションと称されている剥離が生じることがあった。デラミネーションを防止するために、従来、内部電極のセラミック積層体外表面に引き出されている部分の幅を細くした構造が知られている。この構造では、内部電極引き出し部の上下に積層されているセラミック層同士の接合性が高められ、デラミネーションが抑制される。   When manufacturing a multilayer ceramic electronic component such as a multilayer ceramic capacitor, a ceramic multilayer body is obtained by firing a ceramic green chip formed by laminating a plurality of layers of ceramic green sheets with a plurality of internal electrodes interposed therebetween. It has been. The internal electrode and the ceramic layer are made of different materials. Therefore, in the ceramic laminate obtained by the integral firing method, delamination called delamination may occur between the internal electrode and the ceramic layer. In order to prevent delamination, a structure in which the width of the portion of the internal electrode drawn out to the outer surface of the ceramic laminate is conventionally known is known. In this structure, the bondability between the ceramic layers laminated on the upper and lower sides of the internal electrode lead portion is enhanced, and delamination is suppressed.

下記の特許文献１には、このような内部電極引き出し部の幅が狭くされている積層セラミックコンデンサが開示されている。図４（ａ），（ｂ）は、特許文献１に記載の積層セラミックコンデンサにおいて、セラミック積層体内に配置されている内部電極形状を説明するための各模式的平面図である。   Patent Document 1 below discloses a multilayer ceramic capacitor in which the width of the internal electrode lead-out portion is narrowed. 4A and 4B are schematic plan views for explaining the shapes of internal electrodes arranged in the ceramic multilayer body in the multilayer ceramic capacitor described in Patent Document 1. FIG.

図４（ａ）に示すように、セラミック積層体１０１内のある高さ位置に、第１の内部電極１０２が配置されている。内部電極１０２は、セラミック積層体１０１の第１の端面１０１ａに引き出されており、かつ相対的に幅の狭い幅細部１０２ａと、幅細部１０２ａの先端側に連ねられており、かつ相対的に幅の広い幅広部１０２ｂとを有する。   As shown in FIG. 4A, the first internal electrode 102 is disposed at a certain height position in the ceramic laminate 101. The internal electrode 102 is drawn out to the first end surface 101a of the ceramic laminate 101, and is connected to the relatively narrow width detail 102a and the distal end side of the width detail 102a, and is relatively wide. Wide portion 102b.

他方、図４（ｂ）に示すように、第１の内部電極１０２とは異なる高さ位置に、第２の内部電極１０３が配置されている。第２の内部電極１０３は、第２の端面１０１ｂに引き出されている相対的に幅の狭い幅細部１０３ａと、幅細部１０３ａに連ねられている相対的に幅の広い幅広部１０３ｂとを有する。第１の内部電極１０２の幅広部１０２ｂと、第２の内部電極１０３の幅広部１０３ｂとがセラミック層を介して対向され、それによって静電容量が取り出されている。   On the other hand, as shown in FIG. 4B, the second internal electrode 103 is disposed at a height position different from that of the first internal electrode 102. The second internal electrode 103 has a relatively narrow width detail 103a led out to the second end face 101b and a relatively wide section 103b connected to the width detail 103a. The wide portion 102b of the first internal electrode 102 and the wide portion 103b of the second internal electrode 103 are opposed to each other through the ceramic layer, thereby taking out the capacitance.

第１の内部電極１０２の幅広部１０２ｂの先端のコーナー部１０２ｃは丸められており、第２の内部電極１０３の幅広部１０３ｂの先端両側に位置するコーナー部１０３ｃも丸められている。それによって、電界集中の抑制が果たされている。   The corner portion 102c at the tip of the wide portion 102b of the first internal electrode 102 is rounded, and the corner portions 103c located on both sides of the tip of the wide portion 103b of the second internal electrode 103 are also rounded. Thereby, the electric field concentration is suppressed.

加えて、図４（ｃ）において、第１の内部電極１０２と、第２の内部電極１０３とが積層されている関係を模式的平面図で示すように、第１の内部電極１０２の上記コーナー部１０２ｃは、第２の内部電極１０３とセラミック層を介して重なり合わないように配置されている。より具体的には、セラミック積層体１０１を、下方に投影した場合、コーナー部１０２ｃと、第２の内部電極１０３とが重ならないように、コーナー部１０２ｃは、第２の内部電極１０３が設けられている部分よりも外側に位置されている。同様に、セラミック積層体１０１下方に投影した場合、第２の内部電極１０３の幅広部１０３ｂの先端のコーナー部１０３ｃもまた、第１の内部電極１０２の外側に位置されている。   In addition, in FIG. 4C, the corners of the first internal electrode 102 are shown in a schematic plan view showing the relationship in which the first internal electrode 102 and the second internal electrode 103 are laminated. The portion 102c is arranged so as not to overlap the second internal electrode 103 with the ceramic layer interposed therebetween. More specifically, when the ceramic laminate 101 is projected downward, the corner portion 102c is provided with the second internal electrode 103 so that the corner portion 102c and the second internal electrode 103 do not overlap. It is located outside the part. Similarly, when projected below the ceramic laminate 101, the corner portion 103 c at the tip of the wide portion 103 b of the second internal electrode 103 is also positioned outside the first internal electrode 102.

すなわち、電界が集中しやすい幅広部１０２ｂ，１０３ｂの先端のコーナー部１０２ｃ，１０３ｃは、丸められていることにより電界集中が生じ難いだけでなく、異なる電位に接続される第２の内部電極１０３または第１の内部電極１０２とセラミック層を介して重なり合わないように配置されていることによって、電界集中の抑制が図られている。   That is, the corner portions 102c and 103c at the tips of the wide portions 102b and 103b where the electric field tends to concentrate are not only less likely to cause electric field concentration due to being rounded, but also the second internal electrode 103 connected to a different potential or By arranging the first inner electrode 102 and the ceramic layer so as not to overlap each other, the electric field concentration is suppressed.

しかしながら、特許文献１に記載の積層セラミックコンデンサでは、第１の内部電極１０２と、第２の内部電極１０３とが交互に多数積層されるが、内部電極１０２の先端と、第２の端面１０１ｂ側に設けられる外部電極との間の距離及び第２の内部電極１０３の先端と第１の端面１０１ａを覆うように形成される外部電極との間の距離が、セラミックグリーンシートの積層ずれが生じた場合にばらつくおそれがあった。   However, in the multilayer ceramic capacitor described in Patent Document 1, a large number of first internal electrodes 102 and second internal electrodes 103 are alternately stacked, but the tip of the internal electrode 102 and the second end face 101b side The distance between the external electrode provided on the first electrode and the distance between the tip of the second internal electrode 103 and the external electrode formed so as to cover the first end surface 101a caused the stacking deviation of the ceramic green sheets. There was a risk of variation.

すなわち、上記セラミック積層体１０１の製造に際しては、前述したように、セラミックグリーンシート上に内部電極パターンを形成した後、内部電極パターンが形成されたセラミックグリーンシートを、内部電極同士が所定の位置関係となるように積層される。この場合、セラミックグリーンシートの積層ずれが生じると、得られたセラミック積層体１０１において、上記距離がばらつくおそれがあった。そのため、第１，第２の内部電極１０２，１０３間の対向面積がばらつき、容量がばらつくおそれがあった。   That is, when the ceramic laminate 101 is manufactured, as described above, after the internal electrode pattern is formed on the ceramic green sheet, the ceramic green sheet on which the internal electrode pattern is formed has a predetermined positional relationship between the internal electrodes. It is laminated so that In this case, when the stacking deviation of the ceramic green sheets occurs, the distance may vary in the ceramic laminate 101 obtained. For this reason, there is a possibility that the facing area between the first and second internal electrodes 102 and 103 varies and the capacitance varies.

他方、上記のような積層ずれによる容量ばらつきを防止する構造の一例が下記の特許文献２に開示されている。特許文献２では、第１の内部電極の先端に、所定のギャップを隔てて、第２の端面に引き出されている第１のダミー電極が設けられている。他方、第２の内部電極が形成される高さ位置では、第２の内部電極の先端と所定のギャップを隔てて、第１の端面に引き出される第２のダミー電極が形成されている。従って、上記各ギャップの距離を一定としておけば、セラミックグリーンシートの積層ずれが生じたとしても、内部電極とダミー電極との間のギャップが常に一定であるため、容量ばらつきを低減することができる。
特開２００４−２２８５１４号公報 特開２００５−２１６９５５号公報 On the other hand, an example of a structure for preventing the capacitance variation due to the stacking deviation as described above is disclosed in Patent Document 2 below. In Patent Document 2, a first dummy electrode led out to a second end face is provided at a tip end of a first internal electrode with a predetermined gap therebetween. On the other hand, at the height position where the second internal electrode is formed, a second dummy electrode is formed to be drawn to the first end face with a predetermined gap from the tip of the second internal electrode. Therefore, if the distance between the gaps is constant, the gap between the internal electrode and the dummy electrode is always constant even if the ceramic green sheet is misaligned, so that variation in capacitance can be reduced. .
JP 2004-228514 A JP 2005-216955 A

前述したように、特許文献１に記載の積層セラミック電子部品では、製造過程においてセラミックグリーンシートの積層ずれが生じた場合、容量などの電気的特性のばらつきが生じるという問題があった。   As described above, the multilayer ceramic electronic component described in Patent Document 1 has a problem that electrical characteristics such as capacitance vary when the ceramic green sheet is displaced in the manufacturing process.

他方、特許文献２に記載の積層セラミック電子部品では、上記第１，第２のダミー電極を形成することにより、積層ずれに起因する容量ばらつきを抑制することができる。   On the other hand, in the multilayer ceramic electronic component described in Patent Document 2, by forming the first and second dummy electrodes, it is possible to suppress variation in capacitance due to stacking deviation.

しかしながら、特許文献２の図２及び図８等においては、上記のようなダミー電極が設けられている積層セラミックコンデンサは開示されているものの、内部電極先端両側のコーナー部が、セラミック層を介して重なり合っている他の電位に接続される内部電極と重なり合う位置に設けられているため、電界集中が生じやすく、耐圧が低くなるという問題があった。また、特許文献２の図９及び図１０では、内部電極の先端のコーナー部が、他の電位に接続される内部電極とセラミック層を介して重なり合わない構成は示されているものの、ここでは、内部電極先端のコーナー部分の内角が鋭角であり、やはり電界集中が生じやすいという問題があった。   However, in FIGS. 2 and 8 of Patent Document 2, the multilayer ceramic capacitor provided with the dummy electrodes as described above is disclosed, but the corners on both sides of the tip of the internal electrode are interposed via the ceramic layer. Since it is provided at a position overlapping with the overlapping internal electrodes connected to other potentials, there is a problem that electric field concentration tends to occur and the withstand voltage is lowered. 9 and 10 of Patent Document 2 show a configuration in which the corner portion at the tip of the internal electrode does not overlap with the internal electrode connected to another potential via the ceramic layer. The internal angle of the corner portion at the tip of the internal electrode is an acute angle, and there is a problem that electric field concentration tends to occur.

本発明の目的は、上述した従来技術の現状に鑑み、セラミックグリーンシートの積層ずれ等に起因する電気的特性のばらつきが生じ難いだけでなく、内部電極先端のコーナー部における電界集中が生じ難い、信頼性に優れた積層セラミック電子部品を提供することにある。   The object of the present invention is not only less likely to cause variations in electrical characteristics due to misalignment of ceramic green sheets in view of the current state of the prior art described above, but also less likely to cause electric field concentration at the corner portion of the internal electrode tip. An object of the present invention is to provide a multilayer ceramic electronic component having excellent reliability.

本発明によれば、複数のセラミック層が焼成により一体化されており、対向し合う第１の端面と第２の端面とを有するセラミック積層体と、前記セラミック積層体内に形成されており、前記第１の端面に引き出されている第１の幅細部と第１の幅細部に連ねられており、第２の端面側に位置している第１の幅広部とを有する第１の内部電極と、前記第１の内部電極と重なり合うように第１の内部電極とは異なる高さ位置に形成されており、前記第２の端面に引き出された第２の幅細部と、第２の幅細部に連ねられており、第１の端面側に位置している第２の幅広部とを有する第２の内部電極と、前記第１の内部電極と同じ高さ位置に設けられており、第１の内部電極の前記第１の幅広部の先端とギャップを隔てて対向するように設けられた第３の幅広部と、第３の幅広部に連ねられており、かつ第２の端面に引き出されている第３の幅細部とを有する第３の内部電極と、前記第２の内部電極と同じ高さ位置に設けられており、前記第２の内部電極の第２の幅広部の先端とギャップを隔てて対向するように設けられた第４の幅広部と、第４の幅広部に連ねられており、かつ第１の端面に引き出されている第４の幅細部とを有する第４の内部電極と、前記第１，第２の端面にそれぞれ設けられた第１，第２の外部電極とを備え、前記第１〜第４の幅広部の各先端のコーナー部は、内角が鈍角である角部を有する形状あるいは丸みを帯びた形状とされており、前記第１〜第４の幅広部下方に投影した際に、前記第１の幅広部先端のコーナー部及び前記第３の幅広部先端のコーナー部が前記第２の内部電極に重なっておらず、前記第２の幅広部先端のコーナー部及び前記第４の幅広部先端のコーナー部が前記第１の内部電極に重なっていないことを特徴とする、積層セラミック電子部品が提供される。   According to the present invention, a plurality of ceramic layers are integrated by firing, and are formed in a ceramic laminate having a first end face and a second end face facing each other, and the ceramic laminate, A first internal electrode having a first width detail drawn to the first end face and a first wide portion connected to the first width detail and located on the second end face side; The second inner electrode is formed at a different height from the first inner electrode so as to overlap the first inner electrode, and the second width detail drawn to the second end face and the second width detail are A second internal electrode that is connected and has a second wide portion located on the first end face side, and is provided at the same height as the first internal electrode; A first electrode provided to face the tip of the first wide portion of the internal electrode with a gap therebetween. And a third internal electrode having a third width detail connected to the third wide portion and drawn to the second end face, and having the same height as the second internal electrode A fourth wide portion provided to be opposed to the tip of the second wide portion of the second internal electrode across a gap, and connected to the fourth wide portion. And a fourth internal electrode having a fourth width detail drawn to the first end face, and first and second external electrodes respectively provided on the first and second end faces. A corner portion at each tip of the first to fourth wide portions is formed into a shape having a corner portion whose inner angle is an obtuse angle or a rounded shape, and below the first to fourth wide portions. When the projection is performed, the corner portion at the tip of the first wide portion and the corner portion at the tip of the third wide portion are The multilayer ceramics are characterized in that they do not overlap with the second internal electrode, and the corner portion at the tip of the second wide portion and the corner portion at the tip of the fourth wide portion do not overlap with the first internal electrode. Electronic components are provided.

本発明に係る積層セラミック電子部品のある特定の局面では、前記第１の内部電極と、前記第２の内部電極とがセラミック層を介して重なり合っている部分において容量が取り出され、前記第３，第４の内部電極同士がセラミック層を介して重なり合わないように配置されている。この場合には、本発明に従って、積層ずれに起因する静電容量のばらつきが生じ難く、電界集中が生じ難い積層セラミックコンデンサを提供することができる。   In a specific aspect of the multilayer ceramic electronic component according to the present invention, a capacitance is taken out at a portion where the first internal electrode and the second internal electrode overlap with each other via a ceramic layer, The fourth internal electrodes are arranged so as not to overlap each other through the ceramic layer. In this case, according to the present invention, it is possible to provide a multilayer ceramic capacitor in which variation in capacitance due to stacking deviation hardly occurs and electric field concentration hardly occurs.

本発明に係る積層セラミック電子部品の他の特定の局面では、前記第１の内部電極の第１の幅広部の先端と、前記第３の内部電極の第３の幅広部先端との間のギャップ幅と、前記第２の内部電極の第２の幅広部先端と、前記第４の内部電極の第４の幅広部との先端との間のギャップ幅が等しくされている。この場合には、第１，第３の内部電極間のギャップ幅及び第２，第４の内部電極間のギャップ幅が等しくされるので、第１，第３の内部電極を有する電極パターン及び第２，第４の内部電極を有する電極パターンを共通化することができ、製造工程の簡略化を図ることができる。   In another specific aspect of the multilayer ceramic electronic component according to the present invention, the gap between the tip of the first wide portion of the first internal electrode and the tip of the third wide portion of the third internal electrode The width and the gap width between the tip of the second wide portion of the second internal electrode and the tip of the fourth wide portion of the fourth internal electrode are made equal. In this case, since the gap width between the first and third internal electrodes and the gap width between the second and fourth internal electrodes are equalized, the electrode pattern having the first and third internal electrodes and the first The electrode patterns having the second and fourth internal electrodes can be shared, and the manufacturing process can be simplified.

本発明に係る積層セラミック電子部品において、好ましくは、前記第１の内部電極の第１の幅細部の幅方向寸法と、前記第３の内部電極の第３の幅細部の幅方向寸法とが等しく、前記第２の内部電極と第２の幅細部の幅寸法と、前記第４の内部電極の前記第４の幅細部の幅方向寸法とが等しくされている。この場合には、第１の内部電極の幅細部と、第３の内部電極の幅細部とが連ねられたマザーの内部電極パターン、並びに第２の内部電極の幅細部と、第４の内部電極の幅細部とが連ねられたマザーの内部電極パターンを用意することにより、容易に第１，第３の内部電極及び第２，第４の内部電極を、マザーの積層体を切断することにより形成することができる。   In the multilayer ceramic electronic component according to the present invention, preferably, the width direction dimension of the first width detail of the first internal electrode is equal to the width direction dimension of the third width detail of the third internal electrode. The width dimension of the second inner electrode and the second width detail is made equal to the width dimension of the fourth width detail of the fourth inner electrode. In this case, the mother internal electrode pattern in which the width detail of the first internal electrode and the width detail of the third internal electrode are connected, and the width detail of the second internal electrode and the fourth internal electrode By preparing a mother internal electrode pattern in which the width details are connected, the first, third, second, and fourth internal electrodes are easily formed by cutting the mother laminate. can do.

本発明に係る積層セラミック電子部品のさらに特定の局面では、前記高さ方向の下方位置に第１，第２の内部電極を投影した場合に、前記第１の内部電極の前記第１の幅広部先端のコーナー部が、前記第２の内部電極の幅広部よりも外側に位置しており、前記第２の内部電極の前記第２の幅広部先端のコーナー部が、前記第１の内部電極の外側に位置している。この場合には、第１の内部電極の第１の幅広部先端の両側のコーナー部が、第２の内部電極の幅広部よりも外側に位置しているため、該コーナー部が、第２の内部電極と積層方向において確実に重なり合わない。同様に、第２の内部電極の第２の幅広部先端のコーナー部が、第１の内部電極の外側に位置している場合にも、第２の幅細部先端のコーナー部と、第１の内部電極とがセラミック層を介して重なり合わない位置に確実に配置される。   In a more specific aspect of the multilayer ceramic electronic component according to the present invention, when the first and second internal electrodes are projected on the lower position in the height direction, the first wide portion of the first internal electrode A corner portion at the front end is located outside the wide portion of the second internal electrode, and a corner portion at the front end of the second wide portion of the second internal electrode is located on the first internal electrode. Located on the outside. In this case, since the corner portions on both sides of the first wide portion tip of the first internal electrode are located outside the wide portion of the second internal electrode, the corner portion is It does not overlap with the internal electrodes in the stacking direction. Similarly, when the corner portion at the tip of the second wide portion of the second internal electrode is located outside the first internal electrode, the corner portion at the tip of the second width detail, The internal electrode is reliably disposed at a position where it does not overlap with the ceramic layer.

本発明に係る積層セラミック電子部品では、第１の内部電極が形成されている位置において、第１の内部電極の第１の幅広部の先端とギャップを隔てて、第３の内部電極が設けられており、第２の内部電極が形成されている高さ位置においても、第２の内部電極の第２の幅広部とギャップを隔てて対向するように第４の内部電極が設けられており、第３，第４の内部電極が、それぞれ、第２の端面及び第１の端面に引き出されているため、セラミック積層体の製造工程において積層ずれが生じたとしても、積層ずれによる第１，第２の内部電極間の対向面的や第３，第４の内部電極間の対向面積のばらつきが生じ難い。従って、静電容量などの電気的特性のばらつきを低減することかできる。   In the multilayer ceramic electronic component according to the present invention, the third internal electrode is provided at a position where the first internal electrode is formed, with a gap from the tip of the first wide portion of the first internal electrode. The fourth internal electrode is provided so as to face the second wide portion of the second internal electrode with a gap at the height position where the second internal electrode is formed, Since the third and fourth internal electrodes are drawn out to the second end surface and the first end surface, respectively, even if a stacking shift occurs in the manufacturing process of the ceramic laminate, Variations in the opposing area between the two internal electrodes and the opposing area between the third and fourth internal electrodes are unlikely to occur. Therefore, variation in electrical characteristics such as capacitance can be reduced.

加えて、第１〜第４の幅広部の各先端のコーナー部は、内角が鈍角である角部を有する形状あるいは丸みを帯びた形状とされているので、該コーナー部において電界集中が生じ難い。さらに、第１，第３の幅広部先端のコーナー部が、第２の内部電極にセラミック層を介して重なっておらず、第２，第４の幅広部先端のコーナー部が、セラミック層を介して第１の内部電極に重なっていないため、それによっても、第１〜第４の幅広部の先端のコーナー部における電界集中が生じ難い。   In addition, since the corner portions at the tips of the first to fourth wide portions have a corner portion with an obtuse internal angle or a rounded shape, electric field concentration hardly occurs at the corner portion. . Further, the corner portion at the tip of the first and third wide portions does not overlap the second internal electrode via the ceramic layer, and the corner portion at the tip of the second and fourth wide portions does not pass through the ceramic layer. Therefore, the electric field concentration hardly occurs at the corners at the tips of the first to fourth wide portions.

従って、電界集中による破壊やクラックの発生が生じ難い、信頼性に優れた積層セラミック電子部品を提供することができる。   Therefore, it is possible to provide a monolithic ceramic electronic component that is less likely to be broken or cracked due to electric field concentration and has excellent reliability.

以下、図面を参照しつつ、本発明の具体的な実施形態を説明することにより、本発明を明らかにする。   Hereinafter, the present invention will be clarified by describing specific embodiments of the present invention with reference to the drawings.

図１は、本発明の一実施形態に係る積層セラミック電子部品としての積層セラミックコンデンサを示す正面断面図である。積層セラミックコンデンサ１は、セラミック積層体２を有する。セラミック積層体２は、チタン酸バリウム系セラミックスのような適宜の誘電体セラミックスからなる。セラミック積層体２は、対向し合う第１の端面２ａと、第２の端面２ｂとを有する直方体状の形状を有する。セラミック積層体２内においては、第１の内部電極３と、第２の内部電極４とがセラミック層を介して重なり合うように配置されている。言い換えれば、第１の内部電極３と第２の内部電極４とは、セラミック積層体２の異なる高さ位置に形成されている。   FIG. 1 is a front sectional view showing a multilayer ceramic capacitor as a multilayer ceramic electronic component according to an embodiment of the present invention. The multilayer ceramic capacitor 1 has a ceramic multilayer body 2. The ceramic laminate 2 is made of an appropriate dielectric ceramic such as a barium titanate ceramic. The ceramic laminate 2 has a rectangular parallelepiped shape having a first end surface 2a and a second end surface 2b facing each other. In the ceramic laminate 2, the first internal electrode 3 and the second internal electrode 4 are arranged so as to overlap with each other with the ceramic layer interposed therebetween. In other words, the first internal electrode 3 and the second internal electrode 4 are formed at different height positions of the ceramic laminate 2.

そして、第１の内部電極３が形成されている高さ位置において、ギャップＧ１を隔てて、第３の内部電極５が形成されている。同様に、第２の内部電極４が形成されている高さ位置において、第２の内部電極４の先端とギャップＧ２を隔てて、第４の内部電極６が形成されている。   A third internal electrode 5 is formed at a height position where the first internal electrode 3 is formed with a gap G1 therebetween. Similarly, a fourth internal electrode 6 is formed at a height position where the second internal electrode 4 is formed, with a gap G2 from the tip of the second internal electrode 4.

第１〜第４の内部電極３〜６の平面形状を、図２（ａ），（ｂ）を参照して説明する。   The planar shapes of the first to fourth internal electrodes 3 to 6 will be described with reference to FIGS.

図２（ａ）は、第１の内部電極３と、第２の内部電極５とが形成されている高さ位置のセラミック積層体２の模式的平面断面図である。   FIG. 2A is a schematic plan cross-sectional view of the ceramic laminated body 2 at a height position where the first internal electrode 3 and the second internal electrode 5 are formed.

第１の内部電極３は、相対的に幅の狭い第１の幅細部３ａと、相対的に幅の広い第１の幅広部３ｂとを有する。第１の幅細部３ａの端部が第１の端面２ａに引き出されている。また、第１の幅広部３ｂは、第１の幅細部３ａの先端側に連ねられている。第１の幅細部３ａと、第１の幅広部３ｂとが連ねられている部分においては、第１の幅細部３ａから第１の幅広部３ｂに向かって幅方向寸法が徐々に大きくなる幅方向寸法変化部３ｃが設けられている。そして、第１の幅広部３ｂの内側先端の幅方向両側には、コーナー部３ｄ，３ｅが設けられている。ここでは、コーナー部３ｄ，３ｅは、矩形の１つのコーナーを切り落とすことにより設けれた形状を有し、従って、コーナー部３ｄ，３ｅは、いずれも、内角が鈍角である角部Ａ，Ｂを有する。   The first internal electrode 3 has a first narrow detail 3a having a relatively narrow width and a first wide portion 3b having a relatively wide width. The end of the first width detail 3a is drawn out to the first end face 2a. The first wide portion 3b is connected to the distal end side of the first width detail 3a. In the portion where the first width detail 3a and the first wide portion 3b are connected, the width direction dimension gradually increases from the first width detail 3a toward the first wide portion 3b. A dimension changing portion 3c is provided. And corner part 3d, 3e is provided in the width direction both sides of the inner side front-end | tip of 1st wide part 3b. Here, the corner portions 3d and 3e have a shape provided by cutting out one corner of the rectangle, and therefore, the corner portions 3d and 3e have the corner portions A and B whose interior angles are obtuse angles. Have.

他方、第３の内部電極５もまた、相対的に幅の狭い第３の幅細部５ａと、第３の幅細部５ａの内側に連ねられた相対的に幅の広い第３の幅広部５ｂとを有する。第３の幅細部５ａは、第２の端面２ｂに引き出されている。第３の幅細部５ａから、第３の幅広部５ｂに連なる部分においては、幅方向寸法が内側にいくにつれて大きくなる幅方向寸法変化部５ｃが設けられている。   On the other hand, the third internal electrode 5 also has a relatively narrow third width detail 5a, and a relatively wide third wide portion 5b connected to the inside of the third width detail 5a. Have The third width detail 5a is drawn out to the second end face 2b. In the portion extending from the third width detail 5a to the third wide portion 5b, there is provided a width direction dimension changing portion 5c that increases as the width direction dimension goes inward.

第３の幅広部５ｃにおいても、先端両側に、内角が鈍角である２つの角部Ｃ，Ｄを有するコーナー部５ｄ，５ｅが設けられている。   Also in the third wide portion 5c, corner portions 5d and 5e having two corner portions C and D whose inner angles are obtuse angles are provided on both sides of the tip.

そして、第１の幅広部３ｂの先端と、第３の幅広部５ｂの先端とが、上述したギャップＧ１を隔てて対向されている。   And the front-end | tip of the 1st wide part 3b and the front-end | tip of the 3rd wide part 5b are opposed across the gap G1 mentioned above.

他方、図２（ｂ）に示すように、第２の内部電極４が形成されている高さ位置においては、第２の内部電極４と、第４の内部電極６とがギャップＧ２を介して対向されている。第２の内部電極４は、第１の内部電極３と同様に、相対的に幅の狭い第２の幅細部４ａと、相対的に幅の広い第２の幅広部４ｂと、両者が連ねられている部分、幅方向寸法が内側にいくにつれて大きくされている幅方向寸法変化部４ｃとを有する。第２の幅細部４ａが、第２の端面２ｂに引き出されている。   On the other hand, as shown in FIG. 2B, at the height position where the second internal electrode 4 is formed, the second internal electrode 4 and the fourth internal electrode 6 pass through the gap G2. Opposed. Similarly to the first internal electrode 3, the second internal electrode 4 includes a second width detail 4 a having a relatively narrow width and a second wide width portion 4 b having a relatively wide width. And a width direction dimension changing portion 4c which is enlarged as the width direction dimension goes inward. A second width detail 4a is drawn out to the second end face 2b.

第２の内部電極４においても、第２の幅広部４ｂの先端の両側のコーナー部４ｄ，４ｅは、内角が鈍角である２つの角部Ｅ，Ｆを有する。   Also in the second internal electrode 4, the corner portions 4d and 4e on both sides of the tip of the second wide portion 4b have two corner portions E and F whose inner angles are obtuse angles.

第４の内部電極６も、第３の内部電極５と同様に、第４の幅細部６ａ及び第４の幅広部６ｂと、幅方向寸法が内側にいくにつれて増大する幅方向寸法変化部６ｃとを有する。第４の幅細部６ａの一端が第１の端面２ａに引き出されている。また、第４の幅広部６ｂの先端両側のコーナー部６ｄ，６ｅもまた、第３の内部電極５の場合と同様に、内角が鈍角である２つの角部Ｈ，Ｉを有する。   Similarly to the third internal electrode 5, the fourth internal electrode 6 includes a fourth width detail 6 a and a fourth wide portion 6 b, and a width direction dimension changing portion 6 c that increases as the width direction dimension goes inward. Have One end of the fourth width detail 6a is drawn out to the first end face 2a. Similarly to the third internal electrode 5, the corner portions 6d and 6e on both ends of the fourth wide portion 6b also have two corner portions H and I whose obtuse angles are internal angles.

そして、第４の内部電極の第４の幅広部６ｂの先端が、第２の内部電極４の第２の幅広部４ｂの先端とギャップＧ２を隔てて対向されている。   The tip of the fourth wide portion 6b of the fourth internal electrode is opposed to the tip of the second wide portion 4b of the second internal electrode 4 with a gap G2.

そして、図２（ｃ）に第１，第３の内部電極３，５と、第２，第４の内部電極４，６との積層関係を模式的平面断面図で示す。図２（ｃ）から明らかなように、第１の内部電極３の第１の幅広部３ｂの先端両側の角部Ａ，Ｂは、下方に位置している第２の内部電極４と重なり合わない位置に設けられている。他方、第２の内部電極４の第２の幅広部４ｂの先端の角部Ｅ，Ｆもまた、セラミック層を介して第１の内部電極３と重なり合わないように配置されている。   FIG. 2C shows a schematic plane cross-sectional view of the laminated relationship between the first and third internal electrodes 3 and 5 and the second and fourth internal electrodes 4 and 6. As is apparent from FIG. 2C, the corners A and B on both ends of the first wide portion 3b of the first internal electrode 3 overlap with the second internal electrode 4 positioned below. There is no position. On the other hand, the corners E and F at the tip of the second wide portion 4b of the second internal electrode 4 are also arranged so as not to overlap the first internal electrode 3 through the ceramic layer.

言い換えれば、セラミック積層体２を上記高さ位置の基準となる高さ方向すなわち、セラミック層の積層方向において、下方に投影した場合、第１の内部電極３の角部Ａ，Ｂは、第２の内部電極４に重なり合わない位置に設けられており、第２の内部電極４の角部Ｅ，Ｆは、第１の内部電極３と重なり合わない位置に設けられている。   In other words, when the ceramic laminated body 2 is projected downward in the height direction serving as a reference for the height position, that is, the ceramic layer laminating direction, the corner portions A and B of the first internal electrode 3 are second The corners E and F of the second internal electrode 4 are provided at positions that do not overlap with the first internal electrode 3.

同様に、第３の内部電極５の第３の幅広部５ｂの先端の角部Ｃ，Ｄは、第２の内部電極４と重なり合わない位置に設けられており、第４の内部電極６の第４の幅広部６ｂの先端の角部Ｈ，Ｉは、第１の内部電極３と重なり合わない位置に設けられている。   Similarly, the corners C and D at the tip of the third wide portion 5 b of the third internal electrode 5 are provided at positions that do not overlap with the second internal electrode 4. The corners H and I at the tip of the fourth wide portion 6 b are provided at positions that do not overlap the first internal electrode 3.

他方、図１に示すように、セラミック積層体２内においては、上記第１，第３の内部電極３，５及び第２，第４の内部電極４，６が、高さ方向すなわち、積層方向において交互に配置されている。そして、第１の端面２ａを覆うように第１の外部電極７が、第２の端面２ｂを覆うように第２の外部電極８が形成されている。従って、第１，第２の外部電極７，８から、第１，第２の内部電極３，４間の重なり合いによる静電容量を取り出すことができる。このような積層セラミックコンデンサ１は、例えば以下の方法で得ることができる。   On the other hand, as shown in FIG. 1, in the ceramic laminate 2, the first and third inner electrodes 3, 5 and the second and fourth inner electrodes 4, 6 are arranged in the height direction, that is, in the laminating direction. Are alternately arranged. A first external electrode 7 is formed so as to cover the first end face 2a, and a second external electrode 8 is formed so as to cover the second end face 2b. Therefore, the electrostatic capacitance due to the overlap between the first and second inner electrodes 3 and 4 can be taken out from the first and second outer electrodes 7 and 8. Such a multilayer ceramic capacitor 1 can be obtained, for example, by the following method.

図３（ａ）に示すように、マザーのセラミックグリーンシート１２上に、複数の第１のマザーの内部電極パターン１１を印刷する。マザーの内部電極パターン１１は、上記第１，第３の内部電極３，５が互いの幅細部３ａ，５ａの部分で背中合わせとなるように連ねられた平面形状を有する。すなわち、複数のマザーの内部電極パターン１１が、マザーのグリーンシート１２上において、整列配置されている。   As shown in FIG. 3A, a plurality of first mother internal electrode patterns 11 are printed on a mother ceramic green sheet 12. The mother internal electrode pattern 11 has a planar shape in which the first and third internal electrodes 3 and 5 are connected to each other so as to be back-to-back at the width details 3a and 5a. That is, a plurality of mother internal electrode patterns 11 are arranged in alignment on the mother green sheet 12.

他方、図３（ｂ）に示すように、別のマザーのセラミックグリーンシート１４上に、図３（ｂ）に示すように、第２のマザーの内部電極パターン１３を印刷する。第２のマザーの内部電極パターン１３は、第２，第４の内部電極４，６を、第２の幅細部４ａと、第４の幅細部６ａとを連ねるようにして一体化した形状を有する。複数の第２の内部電極パターン１３が、図３（ｂ）に示すように、マザーのセラミックグリーンシート１４上において、最終的に第１，第２の端面２ａ，２ｂを結ぶ対向方向に沿って整列形成されている。   On the other hand, as shown in FIG. 3B, the second mother internal electrode pattern 13 is printed on the ceramic green sheet 14 of another mother as shown in FIG. 3B. The internal electrode pattern 13 of the second mother has a shape in which the second and fourth internal electrodes 4 and 6 are integrated so that the second width detail 4a and the fourth width detail 6a are connected. . As shown in FIG. 3 (b), a plurality of second internal electrode patterns 13 are finally formed on the mother ceramic green sheet 14 along the opposing direction connecting the first and second end faces 2a and 2b. Aligned and formed.

マザーのセラミックグリーンシート１２，１４を複数枚積層し、上下に無地のマザーのセラミックグリーンシートを積層して、マザーの積層体を得る。このマザーの積層体を図３（ａ）の切断線Ｊ，Ｋに沿って切断することにより、個々の積層セラミックコンデンサ単位のセラミック生チップを得ることができる。このセラミック生チップを焼成することにより、上記セラミック積層体２を得ることができる。   A plurality of mother ceramic green sheets 12 and 14 are laminated, and a plain mother ceramic green sheet is laminated on the top and bottom to obtain a mother laminate. By cutting the mother laminated body along the cutting lines J and K in FIG. 3A, a ceramic green chip of each laminated ceramic capacitor unit can be obtained. The ceramic laminate 2 can be obtained by firing this ceramic raw chip.

この場合、マザーのセラミック積層体を得るに際しての積層工程において、マザーのセラミックグリーンシート１２，１４の積層ずれが生じたとしても、第１の内部電極３と第３の内部電極５との間のギャップＧ１及び第２の内部電極４と第４の内部電極６との間のギャップＧ２の寸法は常に一定とされているため、積層ずれに起因する容量ばらつきが生じ難い。   In this case, even if the mother ceramic green sheets 12 and 14 are misaligned in the stacking step when obtaining the mother ceramic laminate, the gap between the first internal electrode 3 and the third internal electrode 5 is reduced. Since the dimension of the gap G1 and the gap G2 between the second internal electrode 4 and the fourth internal electrode 6 is always constant, capacitance variation due to stacking deviation hardly occurs.

なお、本実施形態の積層セラミックコンデンサ１では、上記ギャップＧ１のギャップ幅と、ギャップＧ２のギャップ幅とが等しくされている。従って、マザーの内部電極パターン１１，１３を共通化することができ、マザーの内部電極パターンの種類を少なくすることができる。   In the multilayer ceramic capacitor 1 of the present embodiment, the gap width of the gap G1 and the gap width of the gap G2 are equal. Therefore, the mother internal electrode patterns 11 and 13 can be made common, and the types of mother internal electrode patterns can be reduced.

また、第１の幅細部３ａの幅方向寸法と、第３の幅細部５ａの幅方向寸法とが等しくされており、第２の幅細部４ａの幅方向寸法と、第４の幅細部６ａの幅方向寸法とが等しくされている。従って、上記のように、第１，第３の内部電極パターンを一体化したマザーの内部電極パターン１１や、第２，第４の内部電極を一体化した形状の第２のマザーの電極パターン１２を容易に形成することができる。そして、マザーの内部電極パターンの形状の簡略化を図ることができる。   In addition, the width direction dimension of the first width detail 3a is equal to the width direction dimension of the third width detail 5a, and the width direction dimension of the second width detail 4a is equal to that of the fourth width detail 6a. The width direction dimension is made equal. Therefore, as described above, the mother internal electrode pattern 11 in which the first and third internal electrode patterns are integrated, and the second mother electrode pattern 12 in the shape in which the second and fourth internal electrodes are integrated. Can be easily formed. Further, the shape of the mother internal electrode pattern can be simplified.

また、本実施形態では、上記のように、第１〜第４の内部電極の第１〜第４の幅広部３ｂ〜６ｂの先端両側のコーナー部が、内角が鈍角である２つの角部Ａ，Ｂ〜Ｈ，Ｉを有する。従って、内角が鋭角である先端部分の場合に比べて、電界集中が生じ難い。   In the present embodiment, as described above, the corner portions on both ends of the first to fourth wide portions 3b to 6b of the first to fourth internal electrodes have two corner portions A whose inner angles are obtuse angles. , B to H, I. Therefore, electric field concentration is less likely to occur than in the case of the tip portion having an acute inner angle.

加えて、第１〜第４の幅広部３ｂ〜６ｂの先端の角部Ａ，Ｂ〜Ｈ，Ｉが、それぞれ、セラミック層を介して隣接している第２の内部電極４または第１の内部電極３に重なり合わないように配置されているので、それによっても電界集中が生じ難くされている。従って、積層セラミックコンデンサ１は、電界集中によるクラックや破壊が生じ難い。   In addition, the corner portions A, B to H, I at the tips of the first to fourth wide portions 3b to 6b are respectively adjacent to each other via the ceramic layer, or the second inner electrode 4 or the first inner portion. Since the electrodes 3 are arranged so as not to overlap with each other, the electric field concentration is hardly caused thereby. Therefore, the multilayer ceramic capacitor 1 is unlikely to crack or break due to electric field concentration.

よって、本実施形態によれば、電界集中によるクラックや破壊が生じ難い、信頼性に優れた積層セラミックコンデンサ１を提供することができる。   Therefore, according to the present embodiment, it is possible to provide the multilayer ceramic capacitor 1 that is not easily cracked or broken due to electric field concentration and has excellent reliability.

これを、具体的な実験に基づき説明する。   This will be described based on specific experiments.

上記セラミック積層体２として、３．２ｍｍ×２．５ｍｍ×高さ２．０ｍｍのＢａＴｉＯ３系セラミックスからなるセラミック積層体を用意した。なお、第１，第２の内部電極３，４間のセラミック層の厚みは４．４μｍとし、第１，第２の内部電極３，４が積層されている部分の上下のセラミック層のそれぞれの厚みは２５０μｍとし、第１，第２の内部電極３，４間のセラミック層の数は２５０枚とした。また、第１，第２の内部電極３，４及び第３，第４の内部電極５，６は、Ｎｉペーストのスクリーン印刷により形成した。 As the ceramic laminate 2, a ceramic laminate made of BaTiO 3 ceramics having a size of 3.2 mm × 2.5 mm × height 2.0 mm was prepared. The thickness of the ceramic layer between the first and second internal electrodes 3 and 4 is 4.4 μm, and each of the ceramic layers above and below the portion where the first and second internal electrodes 3 and 4 are laminated. The thickness was 250 μm, and the number of ceramic layers between the first and second internal electrodes 3 and 4 was 250. The first and second internal electrodes 3 and 4 and the third and fourth internal electrodes 5 and 6 were formed by screen printing of Ni paste.

第１，第２の外部電極７，８は、Ｃｕペーストを焼き付けて得られた焼結膜上に、Ｍｎメッキ膜及びＳｉメッキ膜を順に形成することにより設けた。   The first and second external electrodes 7 and 8 were provided by sequentially forming a Mn plating film and a Si plating film on a sintered film obtained by baking a Cu paste.

このようにして得られた上記実施形態の積層セラミックコンデンサ１を１００個用意し、１５０℃の温度で５０Ｖの直流電圧を一定時間印加した。上記電圧を１０００時間印加した後、２０００時間印加した後、及び３０００時間印加した後に、それぞれ、絶縁劣化が生じていた積層セラミックコンデンサの数を求めた。その結果、１０００時間経過後及び２０００時間経過後のいずれにおいても、積層セラミックコンデンサにおいて、絶縁抵抗の劣化は認められなかった。また、３０００時間経過後には、１００個の積層セラミックコンデンサの内２個の積層セラミックコンデンサにおいて絶縁抵抗が劣化したが、劣化した積層セラミックコンデンサの内部を破断して観察したところ、内部電極コーナー部における破損は認められなかった。   100 multilayer ceramic capacitors 1 of the above-described embodiment thus obtained were prepared, and a DC voltage of 50 V was applied for a certain time at a temperature of 150 ° C. After applying the above voltage for 1000 hours, after applying for 2000 hours, and after applying for 3000 hours, the number of multilayer ceramic capacitors in which insulation deterioration had occurred was determined. As a result, no deterioration in insulation resistance was observed in the multilayer ceramic capacitor after 1000 hours and after 2000 hours. In addition, after 3000 hours, the insulation resistance deteriorated in two of the 100 multilayer ceramic capacitors. When the interior of the deteriorated multilayer ceramic capacitor was broken and observed, No damage was observed.

従って、上記実施形態の積層セラミックコンデンサ１によれば、電界集中による破壊が生じ難いことが裏付けられる。   Therefore, according to the multilayer ceramic capacitor 1 of the above embodiment, it is proved that the breakdown due to the electric field concentration hardly occurs.

なお、上記実施形態では、内部電極３〜６の幅広部３ｂ〜６ｂの先端のコーナー部は２つの角部Ａ，Ｂ〜Ｈ，Ｉを有するように形成されていたが、コーナー部は、丸みを帯びた形状とされていてもよい。すなわち、図４に示した従来例の内部電極１０２の先端のコーナー部１０２ｃと同様に丸められた平面形状を有していてもよい。   In the above embodiment, the corner portions at the tips of the wide portions 3b to 6b of the internal electrodes 3 to 6 are formed to have two corner portions A, B to H, and I. However, the corner portions are rounded. It may be in a tinged shape. That is, it may have a rounded planar shape similar to the corner portion 102c at the tip of the internal electrode 102 of the conventional example shown in FIG.

上記実施形態では、積層セラミックコンデンサにつき説明したが、本発明は、積層セラミックコンデンサ以外の積層型のサーミスタや積層型圧電セラミック部品などの様々な積層セラミック電子部品に適用することができる。   Although the multilayer ceramic capacitor has been described in the above embodiment, the present invention can be applied to various multilayer ceramic electronic components such as multilayer thermistors and multilayer piezoelectric ceramic components other than multilayer ceramic capacitors.

本発明の一実施形態の積層セラミックコンデンサの正面断面図。1 is a front sectional view of a multilayer ceramic capacitor according to an embodiment of the present invention. （ａ）は第１，第３の内部電極が形成されている部分のセラミック積層体の模式的平面断面図であり、（ｂ）は、第２，第４の内部電極が形成されている高さ位置のセラミック積層体の模式的平面断面図であり、（ｃ）は、第１，第３の内部電極と第２，第４の内部電極との重なり状態を示す模式的平面図である。(A) is a schematic plan cross-sectional view of the ceramic laminated body of the portion where the first and third internal electrodes are formed, and (b) is a high view where the second and fourth internal electrodes are formed. It is a typical plane sectional view of a ceramic layered product of a position, and (c) is a schematic plan view showing an overlapping state of the 1st, 3rd internal electrode, and the 2nd, 4th internal electrode. （ａ），（ｂ）は、それぞれ、第１，第３の内部電極を形成するための第１のマザーの電極パターンを第１のマザーのセラミックグリーンシートに印刷した状態、及び第２，第４の内部電極を形成するための第２のマザーの電極パターンを第２のセラミックグリーンシート上に印刷した状態を示す各模式的平面図。(A), (b) is the state which printed the electrode pattern of the 1st mother for forming the 1st and 3rd internal electrode on the ceramic green sheet of the 1st mother, respectively, Each schematic plan view which shows the state which printed the electrode pattern of the 2nd mother for forming 4 internal electrodes on the 2nd ceramic green sheet. （ａ）は、従来の積層セラミックコンデンサにおいてある高さ位置に形成される内部電極の平面形状を示すセラミック積層体の模式的平面断面図であり、（ｂ）は、（ａ）に示した内部電極と異なる高さ位置に形成されている内部電極の形状を説明するためのセラミック積層体の模式的平面断面図であり、（ｃ）は、（ａ）及び（ｂ）に示されている内部電極間の重なり状態を説明するための模式的平面断面図。(A) is a typical plane sectional view of a ceramic layered product showing a plane shape of an internal electrode formed in a certain height position in a conventional multilayer ceramic capacitor, and (b) is an internal view shown in (a). It is a typical plane sectional view of the ceramic laminated body for demonstrating the shape of the internal electrode currently formed in the height position different from an electrode, (c) is the inside shown by (a) and (b) The typical plane sectional view for explaining the overlapping state between electrodes.

符号の説明Explanation of symbols

１…セラミック積層電子部品としての積層セラミックコンデンサ
２…セラミック積層体
２ａ，２ｂ…端面
３…第１の内部電極
３ａ…第１の幅細部
３ｂ…第１の幅広部
３ｃ…幅方向寸法変化部
３ｄ，３ｅ…コーナー部
４…第２の内部電極
４…第２の内部電極
４ａ…第２の幅細部
４ｂ…第２の幅広部
４ｃ…幅方向寸法変化部
４ｄ，４ｅ…コーナー部
５…第３の内部電極
５…第３の内部電極
５ａ…第３の幅細部
５ｂ…第３の幅広部
５ｃ…幅方向寸法変化部
５ｄ，５ｅ…コーナー部
６…第４の内部電極
６…第４の内部電極
６ａ…第４の幅細部
６ｂ…第４の幅広部
６ｃ…幅方向寸法変化部
６ｄ，６ｅ…コーナー部
１１…第１のマザーの電極パターン
１２…第２のマザーの電極パターン
１３…第１のマザーのセラミックグリーンシート
１４…第２のマザーのセラミックグリーンシート
Ｅ，Ｆ…角部 DESCRIPTION OF SYMBOLS 1 ... Multilayer ceramic capacitor as a ceramic multilayer electronic component 2 ... Ceramic laminated body 2a, 2b ... End surface 3 ... 1st internal electrode 3a ... 1st width detail 3b ... 1st wide part 3c ... Width direction dimension change part 3d , 3e ... corner 4 ... second internal electrode 4 ... second internal electrode 4a ... second width detail 4b ... second wide part 4c ... width direction dimension changing part 4d, 4e ... corner 5 ... third Internal electrode 5 ... 3rd internal electrode 5a ... 3rd width details 5b ... 3rd wide part 5c ... Width direction dimension change part 5d, 5e ... Corner part 6 ... 4th internal electrode 6 ... 4th inside Electrode 6a ... 4th width detail 6b ... 4th wide part 6c ... Width direction dimension change part 6d, 6e ... Corner part 11 ... 1st mother electrode pattern 12 ... 2nd mother electrode pattern 13 ... 1st Mother of ceramic green sheet 14 ... Second mother's ceramic green sheet E, F ... Corner

Claims (5)

複数のセラミック層が焼成により一体化されており、対向し合う第１の端面と第２の端面とを有するセラミック積層体と、
前記セラミック積層体内に形成されており、前記第１の端面に引き出されている第１の幅細部と第１の幅細部に連ねられており、第２の端面側に位置している第１の幅広部とを有する第１の内部電極と、
前記第１の内部電極と重なり合うように第１の内部電極とは異なる高さ位置に形成されており、前記第２の端面に引き出された第２の幅細部と、第２の幅細部に連ねられており、第１の端面側に位置している第２の幅広部とを有する第２の内部電極と、
前記第１の内部電極と同じ高さ位置に設けられており、第１の内部電極の前記第１の幅広部の先端とギャップを隔てて対向するように設けられた第３の幅広部と、第３の幅広部に連ねられており、かつ第２の端面に引き出されている第３の幅細部とを有する第３の内部電極と、
前記第２の内部電極と同じ高さ位置に設けられており、前記第２の内部電極の第２の幅広部の先端とギャップを隔てて対向するように設けられた第４の幅広部と、第４の幅広部に連ねられており、かつ第１の端面に引き出されている第４の幅細部とを有する第４の内部電極と、
前記第１，第２の端面にそれぞれ設けられた第１，第２の外部電極とを備え、
前記第１〜第４の幅広部の各先端のコーナー部は、内角が鈍角である角部を有する形状あるいは丸みを帯びた形状とされており、
前記第１〜第４の幅広部下方に投影した際に、
前記第１の幅広部先端のコーナー部及び前記第３の幅広部先端のコーナー部が前記第２の内部電極に重なっておらず、
前記第２の幅広部先端のコーナー部及び前記第４の幅広部先端のコーナー部が前記第１の内部電極に重なっていないことを特徴とする、積層セラミック電子部品。 A plurality of ceramic layers integrated by firing, a ceramic laminate having a first end face and a second end face facing each other;
The first width detail formed in the ceramic laminate, connected to the first width detail drawn to the first end face and the first width detail, and located on the second end face side. A first internal electrode having a wide portion;
The first internal electrode is formed at a height different from that of the first internal electrode so as to overlap the first internal electrode, and is connected to the second width detail drawn to the second end surface and the second width detail. A second internal electrode having a second wide portion located on the first end face side,
A third wide portion provided at the same height as the first internal electrode, and facing the tip of the first wide portion of the first internal electrode across a gap; A third internal electrode connected to the third wide portion and having a third width detail drawn to the second end face;
A fourth wide portion that is provided at the same height as the second internal electrode, and that is opposed to the tip of the second wide portion of the second internal electrode across a gap; A fourth internal electrode connected to the fourth wide portion and having a fourth width detail drawn to the first end face;
First and second external electrodes respectively provided on the first and second end faces,
The corner portions at the respective ends of the first to fourth wide portions are formed into a shape having a corner portion whose inner angle is an obtuse angle or a rounded shape,
When projected below the first to fourth wide portions,
The corner portion at the tip of the first wide portion and the corner portion at the tip of the third wide portion do not overlap the second internal electrode,
A multilayer ceramic electronic component, wherein a corner portion at the tip of the second wide portion and a corner portion at the tip of the fourth wide portion do not overlap the first internal electrode. 前記第１の内部電極と、前記第２の内部電極とがセラミック層を介して重なり合っている部分において容量が取り出され、前記第３，第４の内部電極同士がセラミック層を介して重なり合わないように配置されている、請求項１に記載の積層セラミック電子部品。   Capacitance is taken out at the portion where the first internal electrode and the second internal electrode overlap through the ceramic layer, and the third and fourth internal electrodes do not overlap through the ceramic layer. The multilayer ceramic electronic component according to claim 1, which is arranged as described above. 前記第１の内部電極の第１の幅広部の先端と、前記第３の内部電極の第３の幅広部先端との間のギャップ幅と、前記第２の内部電極の第２の幅広部先端と、前記第４の内部電極の第４の幅広部との先端との間のギャップ幅が等しくされている、請求項１または２に記載の積層セラミック電子部品。   The gap width between the tip of the first wide portion of the first internal electrode and the tip of the third wide portion of the third internal electrode, and the tip of the second wide portion of the second internal electrode 3. The multilayer ceramic electronic component according to claim 1, wherein a gap width between the first internal electrode and a tip of the fourth internal electrode and the fourth wide portion is made equal. 前記第１の内部電極の第１の幅細部の幅方向寸法と、前記第３の内部電極の第３の幅細部の幅方向寸法とが等しく、前記第２の内部電極と第２の幅細部の幅寸法と、前記第４の内部電極の前記第４の幅細部の幅方向寸法とが等しくされている、請求項１〜３のいずれか１項に記載の積層セラミック電子部品。   The widthwise dimension of the first width detail of the first internal electrode is equal to the widthwise dimension of the third width detail of the third internal electrode, and the second internal electrode and the second width detail are equal. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein a width dimension of the fourth internal electrode is equal to a width direction dimension of the fourth width detail of the fourth internal electrode. 前記高さ方向の下方位置に第１，第２の内部電極を投影した場合に、前記第１の内部電極の前記第１の幅広部先端のコーナー部が、前記第２の内部電極の幅広部よりも外側に位置しており、前記第２の内部電極の前記第２の幅広部先端のコーナー部が、前記第１の内部電極の外側に位置している、請求項１に記載の積層セラミック電子部品。   When the first and second internal electrodes are projected onto the lower position in the height direction, the corner portion at the tip of the first wide portion of the first internal electrode is the wide portion of the second internal electrode. 2. The multilayer ceramic according to claim 1, wherein a corner portion at a tip of the second wide portion of the second internal electrode is positioned outside the first internal electrode. Electronic components.
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