JP2007274659A - Radar interference wave detection circuit - Google Patents

Radar interference wave detection circuit Download PDF

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JP2007274659A
JP2007274659A JP2006122649A JP2006122649A JP2007274659A JP 2007274659 A JP2007274659 A JP 2007274659A JP 2006122649 A JP2006122649 A JP 2006122649A JP 2006122649 A JP2006122649 A JP 2006122649A JP 2007274659 A JP2007274659 A JP 2007274659A
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Katsumi Tokuyama
勝己 徳山
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KEY STREAM KK
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Abstract

<P>PROBLEM TO BE SOLVED: To detect the effective length of a pulse width of an irregular peak pulse whose reception level goes up and down in the vicinity of a threshold, or a peak pulse similar to a random noise, and a no-signal section after a constant pulse, and to reduce the error detection probability of radar interference waves. <P>SOLUTION: The frequency beyond the threshold and the frequency below the threshold are counted to perform effectiveness determination of the pulse by using a threshold detection circuit and an up/down counter of a reception field strength signal level. Simultaneously, effectiveness of the pulse is determined which is stable in a circuit for counting a time width from the start to the end of the effective pulse. Reception IQ signal power which has a constant temporal space from the start of the effective pulse is compared with signal power after limiting a passband with a steep digital filter. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、気象レーダ等のレーダと使用する周波数帯域を共有する５ＧＨｚ帯小電力データ通信システム又はＩＥＥＥ８０２．１１ａ規格に準拠する無線ＬＡＮ装置のレーダ干渉波の検出方法に関するものである。  The present invention relates to a radar interference wave detection method for a 5 GHz band low-power data communication system or a wireless LAN device compliant with the IEEE802.11a standard sharing a frequency band to be used with a radar such as a weather radar.

１９９９年１１月にヨーロッパ無線通信委員会（Ｅｕｒｏｐｅａｎ Ｒａｄｉｏｃｏｍｍｕｎｉｃａｔｉｏｎｓ Ｃｏｍｍｉｔｔｅｅ）は通信前に周波数の空き帯域を調べてから電波を発することで電波の混信を防ぐ機能（Ｄｙｎａｍｉｃ Ｆｒｅｑｕｅｎｃｙ Ｓｅｌｅｃｔｉｏｎ、ＤＦＳ）をＨＹＰＥＲＬＡＮｓに使用する事を採択し、Ｅｕｒｏｐｅａｎ Ｔｅｌｅｃｏｍｍｕｎｉｃａｔｉｏｎｓ Ｓｔａｎｄａｒｄｓ Ｉｎｓｔｉｔｕｔｅ（ＥＴＳＩ）は２０００年４月にＥＴＳＩ ＴＳ １０１ ７６１−２Ｖ１．１．１ＨＹＰＥＲＬＡＮ Ｔｙｐｅ２を制定した。米国では無線ＬＡＮの追加機能として、このＤＦＳをＩＥＥＥ Ｓｔｄ．８０２．１１ｈ−２００３で制定した。同様に、日本では総務省令第９４号にて２００５年５月に電波法の改訂がおこなわれ、５２５０−５３５０ＭＨｚ帯を使用する親局無線設備はＤＦＳの機能の具備が義務付けられた。  In November 1999, the European Radiocommunications Committee used HYPERLANs to prevent radio frequency interference (DFS) by emitting radio waves after checking available frequency bands before communication. In April 2000, the European Telecommunications Standards Institute (ETSI) established ETSI TS 101 761-2V1.1.1 HYPERLAN Type2. In the United States, as an additional function of wireless LAN, this DFS is used as IEEE Std. Established in 802.11h-2003. Similarly, in Japan, the Radio Law was revised in May 2005 by the Ministry of Internal Affairs and Communications Ordinance No. 94, and the master station radio equipment using the 5250-5350 MHz band was required to have DFS function.

無線ＬＡＮで検出すべき受信するレーダ干渉波の例を図１に示す。最大等価等方出力が０．２Ｗ未満の無線ＬＡＮはパルス幅１ｕｓｅｃ、周波数７００Ｈｚ又は、パルス幅２．５ｕｓｅｃ、周波数２６０Ｈｚ、連続するパルスの数が１８で−６２ｄＢｍの受信入力のレーダ干渉波を検出する機能を備える必要がある。  An example of a received radar interference wave to be detected by the wireless LAN is shown in FIG. A wireless LAN with a maximum equivalent isotropic output of less than 0.2 W detects a radar interference wave of a received input of -62 dBm with a pulse width of 1 usec, a frequency of 700 Hz, or a pulse width of 2.5 usec, a frequency of 260 Hz, and the number of consecutive pulses is 18. It is necessary to have the function to do.

レーダ干渉波を検出する従来技術の一例を図２に示す。無線ＬＡＮの信号（ＯＦＤＭ）はアンテナ１０１で受信し、受信機１０２でベースバンド信号に復調する。このベースバンド信号はディジタル処理回路１０３にあるＡ／Ｄ変換器でアナログ信号をディジタル信号に変換した後、ディジタル処理によってＯＦＤＭ信号を情報信号復調する。アクセス制御回路１０４は情報信号の内容を高速で分析し、再送等の送受信アクセス制御を行う。プロトコルエンジン回路１０６では無線ＬＡＮに関わる通信手順を実行し、正常な情報の授受を行う。又、ディジタル処理回路１０３は常時Ａ／Ｄ変換器のディジタル信号出力をデータ記憶装置に蓄積すると同時にこの記憶装置からデータを読み出し、高速フーリエ変換してレーダ干渉波のスペクトラムとパルス幅の情報を検出し、その波形情報をレーダ波検出回路１０５に渡す。レーダ波検出回路１０５は波形情報と受信機１０２の利得制御情報を基に受信強度の算出を行い受信信号が閾値以上であるかの判断とパルスの発生時間を分析して、レーダ干渉波の有無を判断している。  An example of a conventional technique for detecting radar interference waves is shown in FIG. The wireless LAN signal (OFDM) is received by the antenna 101 and demodulated into a baseband signal by the receiver 102. This baseband signal is converted from an analog signal to a digital signal by an A / D converter in the digital processing circuit 103, and then an OFDM signal is demodulated as an information signal by digital processing. The access control circuit 104 analyzes the contents of the information signal at high speed and performs transmission / reception access control such as retransmission. The protocol engine circuit 106 executes a communication procedure related to the wireless LAN and exchanges normal information. The digital processing circuit 103 always stores the digital signal output of the A / D converter in the data storage device, and simultaneously reads out the data from the storage device, and performs fast Fourier transform to detect the radar interference wave spectrum and pulse width information. Then, the waveform information is passed to the radar wave detection circuit 105. The radar wave detection circuit 105 calculates the reception intensity based on the waveform information and the gain control information of the receiver 102, determines whether the received signal is equal to or greater than the threshold, analyzes the pulse generation time, and determines whether there is a radar interference wave. Judging.

他のレーダ干渉波を検出する従来技術としては、指数比例特性を有する受信電界強度（ＲＳＳＩ）信号を使用して、受信キャリヤが指定の閾値を超える時間が伝送するパケットより短いことをもってレーダ干渉波であることを判断する方法が提案されていた。
ＵＳ６，６９７，０１３ 特開平５−１３００５３号 特開平６−３７７６２号 ＥＲＣ Ｄｅｃｉｓｉｏｎ ｏｆ ２９ Ｎｏｖｅｍｂｅｒ １９９９ ｏｎ ｔｈｅ ｈａｒｍｏｎｉｚｅｄ ｆｒｅｑｕｅｎｃｙ ｂａｎｄｓ ｔｏ ｂｅ ｄｅｓｉｇｎｅｄ ｆｏｒ ｔｈｅ ｉｎｔｒｏｄｕｃｔｉｏｎ ｏｆ Ｈｉｇｈ Ｐｅｒｆｏｒｍａｎｃｅ Ｒａｄｉｏ Ｌｏｃａｌ Ａｒｅａ Ｎｅｔｗｏｒｋｓ（ＥＲＣ／ＤＥＣ／（９９）２３） As a conventional technique for detecting other radar interference waves, a reception field strength (RSSI) signal having an exponential proportional characteristic is used, and the time when the reception carrier exceeds a specified threshold is shorter than the transmitted packet. A method for determining whether or not this is the case has been proposed.
US 6,697,013 JP-A-5-130053 JP-A-6-37762 ERC Decision of 29 November 1999 on the harmonized frequency bands to be designed for the introduction of High Performance Radio 23

しかしながら、信号処理する方法では、ディジタル変換した受信信号をデータ記憶装置に蓄積し、情報処理する必要がある。レーダが送信するパルス幅１ｕｓｅｃ又は２．５ｕｓｅｃのデータを蓄積するには少なくとも、パルス幅１ｕｓｅｃが処理できる分解能のサンプリング周波数以上で、２．５ｕｓｅｃ以上の区間のＩＱデータを蓄積する必要がある。無線ＬＡＮとしてＯＦＤＭ信号を復調するためにサンプリング周波数４０Ｍｓｐｓが使用されており、このサンプリングデータをレーダ干渉波検出に共用する。この蓄積したデータをもとに信号処理を行う事により、正確なレーダ干渉波の検出が可能となるが、この信号処理に供するハード回路規模は大きく、消費電流の増加とＬＳＩのチップサイズが大きくなる課題がある。  However, in the signal processing method, the digitally converted received signal needs to be stored in a data storage device and processed. In order to accumulate data with a pulse width of 1 usec or 2.5 usec transmitted by the radar, it is necessary to accumulate IQ data of a section of 2.5 usec or more at least at a sampling frequency with a resolution that can be processed by the pulse width of 1 usec. A sampling frequency of 40 Msps is used for demodulating an OFDM signal as a wireless LAN, and this sampling data is shared for radar interference wave detection. By performing signal processing based on this accumulated data, it is possible to accurately detect radar interference waves, but the hardware circuit used for this signal processing is large, increasing the current consumption and increasing the chip size of the LSI. There is a problem.

他の受信キャリヤが指定の閾値を超える時間が伝送するパケットより短いことをもってレーダ干渉波であることを判断する方法は簡単な論理で回路規模は非常に少なくて実現できるが、レーダ干渉波が多重回折による波形歪を有し、その信号レベル変動が閾値近傍である場合、及び、ＯＦＤＭ信号はランダム雑音に近い波形を持っており、そのレベルの平均値が指定の閾値に近いレベルの場合、瞬時的な受信信号レベルは閾値を上下し、単純なレベル判定では誤動作する確率が上がる欠点を持っている。  The method for determining that the other receiving carrier exceeds the specified threshold is shorter than the packet to be transmitted is a radar interference wave, and can be realized with simple logic and a very small circuit scale. When there is waveform distortion due to diffraction and the signal level fluctuation is near the threshold, and when the OFDM signal has a waveform close to random noise and the average value of the level is close to the specified threshold, the instantaneous A typical received signal level has a disadvantage that the threshold is raised and lowered, and the probability of malfunctioning increases with simple level determination.

更に、レーダシステムと共有する無線ＬＡＮの周波数は、５，２８０ＭＨｚ、５，３００ＭＨｚと５，３２０ＭＨｚが割り当てられ、その周波数間隔は２０ＭＨｚである。一方、レーダ波は５，２６０ＭＨｚから５ＭＨｚ間隔で割り当てられている。従い、無線ＬＡＮの受信機ではレーダ干渉波は同一受信周波数と上下に５ＭＨｚ、１０ＭＨｚ、１５ＭＨｚと５ＭＨｚ毎に干渉波として受信する。ＯＦＤＭ信号の占有帯域幅は１６．６ＭＨｚ（＋／−８．３ＭＨｚ）であり、キャリヤ周波数から＋／−１０ＭＨｚ離れた周波数に尽ける信号レベルは帯域内信号レベルと比較して約２０ｄＢ低い。一方、ＲＳＳＩは１６．６ＭＨｚ帯域幅のＯＦＤＭ信号を検出するが、無線部に使用されているＲＳＳＩ用のアナログ通過帯域フィルタは急峻でなく、１０ＭＨｚ離れたレーダ干渉波はほとんど除去できず、帯域内の干渉波として誤検出する可能性を有する。  Furthermore, the frequency of the wireless LAN shared with the radar system is assigned 5,280 MHz, 5,300 MHz, and 5,320 MHz, and the frequency interval is 20 MHz. On the other hand, radar waves are allocated at intervals of 5260 MHz to 5 MHz. Accordingly, a radar interference wave is received as an interference wave at the same reception frequency and every 5 MHz, 10 MHz, 15 MHz, and 5 MHz at the wireless LAN receiver. The occupied bandwidth of the OFDM signal is 16.6 MHz (+/− 8.3 MHz), and the signal level exhausted at a frequency +/− 10 MHz away from the carrier frequency is about 20 dB lower than the in-band signal level. On the other hand, RSSI detects an OFDM signal having a 16.6 MHz bandwidth, but the analog passband filter for RSSI used in the radio unit is not steep, and radar interference waves separated by 10 MHz can hardly be removed. There is a possibility of erroneous detection as an interference wave.

請求項１では、ＲＳＳＩ信号レベルの閾値検出回路とアップ・ダウンカウンターを用いて、閾値を超える回数と閾値未満の回数を計数してパルスの有効判定を行うと同時に、パルスの開始から終了までの時間幅を計数する。  In claim 1, the RSSI signal level threshold value detection circuit and the up / down counter are used to count the number of times exceeding the threshold value and the number of times less than the threshold value to determine the validity of the pulse, and at the same time from the start to the end of the pulse. Count the time span.

更に請求項２では、パルスの開始時から一定の時間間隔の受信ＩＱ信号電力と急峻なディジタルフィルタで通過帯域制限した後のＩＱ信号電力の比較を行い、前述のパルスの帯域内外判定を行う。  Further, in claim 2, the received IQ signal power at a fixed time interval from the start of the pulse is compared with the IQ signal power after the pass band is limited by the steep digital filter, and the above-described in-band determination of the pulse is performed.

請求項１の発明によれば、受信レベルが閾値近傍を上下する不規則な波高パルスやランダム雑音に近い波高パルスのパルス幅の有効長と一定のパルス後の無信号区間を検出し、レーダ干渉波の誤検出確率の低減を可能とする。  According to the first aspect of the present invention, the effective length of the pulse width of the irregular pulse height pulse whose reception level fluctuates in the vicinity of the threshold value or the pulse height pulse close to random noise and the no-signal section after a certain pulse are detected, and radar interference is detected. This makes it possible to reduce the false detection probability of waves.

また、請求項２の発明によれば、請求項１と請求項２の発明の検出情報が受信している無線チャネルの帯域内である事を確定し、受信帯域外のレーダ干渉波による誤検出の低減を可能とする。  According to the invention of claim 2, it is determined that the detection information of the invention of claims 1 and 2 is within the band of the received radio channel, and erroneous detection due to radar interference waves outside the reception band. Can be reduced.

発明を実施するため最良の形態BEST MODE FOR CARRYING OUT THE INVENTION

本発明のレーダ干渉波検出回路は、ＲＳＳＩ信号を使用してレーダパルス幅を測定し、同時刻に受信したベースバンド信号のスペクトラムで受信帯域内外の判定を行う。  The radar interference wave detection circuit of the present invention measures the radar pulse width using the RSSI signal, and determines whether the reception band is inside or outside the spectrum of the baseband signal received at the same time.

以下、この発明の実施の形態について図３、図４、図５と図６を用いて説明する。  Hereinafter, embodiments of the present invention will be described with reference to FIGS. 3, 4, 5 and 6.

図３はレーダ干渉波検出回路の構成例を示す。アンテナ２０１で受信した５ＧＨｚ帯の占有帯域幅１６．６ＭＨｚのＯＦＤＭ無線信号は高周波増幅器２０２で増幅され、ローカル発信器２０４より供給される受信周波数と同一のローカル信号によってＩＱ復調器２０３で０Ｈｚから８．３ＭＨＺのＩＱベースバンド信号に復調される。この復調方式はダイレクトコンバージョン受信方式と称される。  FIG. 3 shows a configuration example of the radar interference wave detection circuit. An OFDM radio signal having an occupied bandwidth of 16.6 MHz in the 5 GHz band received by the antenna 201 is amplified by the high-frequency amplifier 202, and is output from 0 Hz to 8 by the IQ demodulator 203 using the same local signal as the reception frequency supplied from the local oscillator 204. .3MHZ demodulated to IQ baseband signal. This demodulation method is called a direct conversion reception method.

ＩＱベースバンド信号は低域通過フィルタ２０５で帯域外信号を除去し、可変利得のベースバンド増幅器２０６で増幅し、４０Ｍｓｐｓのサンプリング周波数を使用するアナログ・ディジタル変換器（ＢＢＡＤＣ）２０７でＩＱディジタル信号に変換される。このＩＱディジタル信号はこの構成例に記載されていないＯＦＤＭ信号復調器で情報信号に復調される。  The IQ baseband signal is removed from the out-of-band signal by the low-pass filter 205, amplified by the variable gain baseband amplifier 206, and converted to the IQ digital signal by the analog-to-digital converter (BBADC) 207 using a sampling frequency of 40 Msps. Converted. This IQ digital signal is demodulated into an information signal by an OFDM signal demodulator not described in this configuration example.

又、ＩＱベースバンド信号は固定利得の対数直線性を有する受信電界強度（ＲＳＳＩ）増幅器２１０で変換しモニタ表示に使用される。このＲＳＳＩ増幅器２１０は時定数０．１ｕｓｅｃで対数直線変換を行うが、この時定数より早いＯＦＤＭの瞬時波形はＲＳＳＩ出力の平均値に重畳される。  The IQ baseband signal is converted by a received electric field strength (RSSI) amplifier 210 having a logarithmic linearity with a fixed gain and used for monitor display. The RSSI amplifier 210 performs logarithmic linear conversion with a time constant of 0.1 usec. An instantaneous waveform of OFDM that is earlier than this time constant is superimposed on the average value of the RSSI output.

受信周波数と同一周波数のレーダ干渉波を受信した場合、ＲＳＳＩ増幅器２１０の出力はＲＳＳＩアナログ・ディジタル変換器（ＲＳＳＩＡＤＣ）２１１でディジタル値に変換し、ＲＳＳＩ判定器２１２はＲＳＳＩ信号が閾値より大きい場合［１］を、小さい場合［０］を出力し、レーダパルス幅判定回路２１３に情報を渡す。  When a radar interference wave having the same frequency as the reception frequency is received, the output of the RSSI amplifier 210 is converted into a digital value by the RSSI analog-to-digital converter (RSSIADC) 211, and the RSSI determiner 212 determines that the RSSI signal is larger than the threshold value [ 1] is output, and if it is smaller, [0] is output and information is passed to the radar pulse width determination circuit 213.

レーダパルス幅判定回路２１３はＲＳＳＩが閾値以上の回数を加算し、閾値以下の回数を減算するアップ・ダウンカウンター（以下ＰｗｅｒＣｎｔと略す）とパルスの開始から終了までの時間幅を計数するカウンター（以下ＷｉｄｔｈＣｎｔと略す）の基本回路とＲＳＳＩが閾値以上である事を示すフラグ（以下ＲＳＳＩｆｌａｇと略す）、過去にＲＳＳＩが閾値以上であった事を示すフラグ（以下Ｐｗｒｆｌａｇと略す）、アップ・ダウンカウンター値が規定の数値にこでは初期値より７大きい値：０．７ｕｓｅｃ、最小パルス幅を示す）に達した事を示すフラグ（以下ＰｗｒＤｅｔｆｌａｇと略す）、帯域判定回路２０９で生成される帯域内信号を示すフラグ（以下ＩｎＢａｎｄｆｌａｇと略す）とパルスがレーダ干渉波である事を示すフラグ（以下ＲａｄａｒＤｅｔｆｌａｇと略す）と各種フラグ及びカウンター値による条件分岐回路等で構成される。真値の場合のフラグは［１］を示す。  Radar pulse width determination circuit 213 adds up / down counter (hereinafter abbreviated as PwerCnt) that adds the number of times RSSI is equal to or greater than a threshold value, and subtracts the number of times less than or equal to the threshold value, and a counter (hereinafter referred to as pulse width count) Basic circuit of WidthCnt) and a flag indicating that RSSI is equal to or greater than a threshold (hereinafter abbreviated as RSSIflag), a flag indicating that RSSI was equal to or greater than a threshold in the past (hereinafter abbreviated as Pwrflag), and an up / down counter value Is a specified numerical value, a flag (hereinafter abbreviated as PwrDetflag) indicating that the value reached 7 larger than the initial value: 0.7 usec, indicating a minimum pulse width), and an in-band signal generated by the band determination circuit 209. A flag (hereinafter abbreviated as InBandflag) and a pulse indicating a radar interference wave Lag (hereinafter referred to as RadarDetflag) and composed of a conditional branch circuit or the like according to various flags and the counter value. The flag in the case of a true value indicates [1].

レーダパルス幅判定回路２１３は１０ＭＨｚのクロックで動作し、クロック毎の動作を図４レーダパルス幅判定回路の動作手順に示し、カウンターの動きを図５に示す。  The radar pulse width determination circuit 213 operates with a clock of 10 MHz, the operation for each clock is shown in the operation procedure of the radar pulse width determination circuit in FIG. 4, and the operation of the counter is shown in FIG.

初期状態では全てのフラグとカウンター値は［０］で、受信入力が無いため、ステップ３０１でＲＳＳＩｆｌａｇによる分岐とステップ３２１でＰｗｅｒｆｌａｇによる分岐を経由し、状態の変化無くクロック内の処理は終了する。  In the initial state, all the flags and counter values are [0] and there is no reception input. Therefore, the process in the clock is terminated without changing the state through the branch by RSSI flag in step 301 and the branch by Pwerflag in step 321.

閾値以上の受信入力が発生した場合（ＲＳＳＩｆｌａｇ＝１）、最初のクロック内で次の処理する。ステップ３０１でＲＳＳＩｆｌａｇによる分岐とステップ３０２でＰｗｒｆｌａｇによる分岐を経てステップ３０８に行く。ステップ３０８ではＰｗｒｆｌａｇを［１］に設定し、ＰｗｒＣｎｔに初期値［３２］を設定する。更にステップ３０９でＷｉｄｔｈＣｎｔに［１］を加算し、クロック内の処理を終える。  When a reception input exceeding the threshold value is generated (RSSIflag = 1), the next process is performed within the first clock. Step 301 is followed by branching by RSSI flag and step 302 by branching by Pwrflag. In step 308, Pwrflag is set to [1], and an initial value [32] is set to PwrCnt. In step 309, [1] is added to WidthCnt, and the processing in the clock is finished.

次のクロック（２回目）でＲＳＳＩ以上の受信入力が連続した場合、ステップ３０１でＲＳＳＩｆｌａｇによる分岐とステップ３０２でＰｗｒｆｌａｇによる分岐を経てステップ３０３に行く。ここでは前の処理のＰｗｒＣｎｔが［３２］であるため、ステップ３０４に進む。ステップ３０４では過去のＰｗｒＤｅｔｆｌａｇが［０］であるためステップ３０５に移行する。ステップ３０５ではＰｗｒＣｎｔに［１］を加算しステップ３０６に移行する。ＰｗｒＣｎｔの加算結果は［３３］となる。ステップ３０６ではＰｗｒＣｎｔが［３３］であるためステップ３０９に移行する。ステップ３０９でＷｉｄｔｈＣｎｔに［１］を加算し、ＷｉｄｔｈＣｎｔの加算結果は［２］となり、クロック内の処理を終える。更に連続してＲＳＳＩが閾値以上の場合、３回目から７回目までのクロックの処理は、２回目と同一の処理経路をとりＰｗｒＣｎｔとＷｉｄｔｈＣｎｔが増加して行く。  If reception input equal to or higher than RSSI continues at the next clock (second time), the process goes to step 303 after branching by RSSI flag in step 301 and branching by Pwrflag in step 302. Here, since PwrCnt of the previous process is [32], the process proceeds to step 304. In step 304, since the past PwrDetflag is [0], the process proceeds to step 305. In step 305, [1] is added to PwrCnt and the process proceeds to step 306. The addition result of PwrCnt is [33]. In step 306, since PwrCnt is [33], the process proceeds to step 309. In step 309, [1] is added to WidthCnt, the addition result of WidthCnt is [2], and the processing in the clock is finished. Further, when RSSI is continuously greater than or equal to the threshold, the clock processing from the third time to the seventh time takes the same processing path as the second time, and PwrCnt and WidthCnt increase.

更に８回目のクロック時もＲＳＳＩが閾値以上の場合、前述の処理と同一経路を辿るが、ステップ３０５のＰｗｒＣｎｔの加算結果は［３９］となり、次のステップ３０６ではＰｗｒＣｎｔが［３９］であるためステップ３０７に移行する。ステップ３０７ではＰｗｒＤｅｔｆｌａｇを［１］に設定し、ステップ３０９でＷｉｄｔｈＣｎｔに［１］を加算し、クロック内の処理を終える。この時点のＷｉｄｔｈＣｎｔは［８］を示す。  Furthermore, if the RSSI is equal to or greater than the threshold at the eighth clock, the same route as described above is followed, but the addition result of PwrCnt in step 305 is [39], and in the next step 306, PwrCnt is [39]. The process proceeds to step 307. In step 307, PwrDetflag is set to [1]. In step 309, [1] is added to WidthCnt, and the processing in the clock is finished. Width Cnt at this time indicates [8].

更に９回目と１０回目のクロック時にＲＳＳＩが閾値以上の場合、ステップ３０１とステップ３０２を経てステップ３０３に移行する。ステップ３０３ではＰｗｒＣｎｔが［３９］であるためステップ３０９に移行し、ＷｉｄｔｈＣｎｔに［１］を加算し、クロック内の処理を終える。この処理は、ＰｗｒＣｎｔを［３９］に維持し、ＷｉｄｔｈＣｎｔをカウントアップしている。  Further, if the RSSI is equal to or greater than the threshold value at the ninth and tenth clocks, the process proceeds to step 303 through step 301 and step 302. In step 303, since PwrCnt is [39], the process proceeds to step 309, [1] is added to WidthCnt, and the processing in the clock is finished. In this process, PwrCnt is maintained at [39] and WidthCnt is counted up.

１１回目のクロック時（１回目のクロックより１ｕｓｅｃ経過）にＲＳＳＩが閾値以下の場合、ステップ３０１からステップ３２１を経由してステップ３２２に至る。ステップ３２２ではＰｗｒＣｎｔから［１］を減算し、減算結果が［３８］になる。次のステップ３２３ではＰｗｒＣｎｔの値が［２３］でないため、ステップ３０９に移行し、ＷｉｄｔｈＣｎｔに［１］を加算し、クロック内の処理を終える。  If the RSSI is equal to or less than the threshold at the eleventh clock (1 usec has elapsed from the first clock), the process goes from step 301 to step 322 via step 321. In step 322, [1] is subtracted from PwrCnt, and the subtraction result is [38]. In the next step 323, since the value of PwrCnt is not [23], the process proceeds to step 309, [1] is added to WidthCnt, and the processing in the clock is finished.

１２回目以降のクロック時も同様に連続してＲＳＳＩが閾値以下の場合、１１回目のクロック時と同一の処理経路をとりＰｗｒＣｎｔから［１］を減算し、ＷｉｄｔｈＣｎｔに［１］を加算してクロック内の処理を終了する。  Similarly, when the RSSI is continuously below the threshold at the 12th clock and thereafter, the same processing path as that at the 11th clock is taken, [1] is subtracted from PwrCnt, and [1] is added to WidthCnt. The process in is terminated.

２６回目のクロック時（ＲＳＳＩが閾値以下になって１．５ｕｓｅｃ後、無信号区間）は、ステップ３０１とステップ３２１を経由してステップ３２２に移行する。ステップ３２２でＰｗｒＣｎｔを［１］減算しステップ３２３に移行する。この時のＰｗｒＣｎｔの減算結果が［２３］であるため、ステップ３２４に移行する。又この時のＷｉｄｔｈＣｎｔは［２７］でステップ３２４の分岐条件より、ステップ３２５に移行する。ステップ３２５の分岐条件であるＰｗｒＤｅｔｆｌａｇは８回目のクロック時に［１］となっており、ステップ３２６に移行する。ステップ３２６のＩｎＢａｎｄｆｌａｇの情報は後述の帯域内電力判定回路から与えられ、閾値を超えるＲＳＳＩのスペクトラムが受信帯域内である場合［１］が既に来ており、ステップ３２７に移行する。ステップ３２７では、レーダ干渉波の受信を示すＲａｄＭＤｅｔｆｌａｇを［１］にし、レーダーパルス幅判定器で使用しているカウンターとフラグの初期化を行う。ＲａｄａｒＤｅｔｆｌａｇは上位のファームウェアで常時監視し、ファームウェアによる読み取り処理が完了した時点で［０］に戻し正常受信の処理が全て終了する。  At the time of the 26th clock (1.5 seconds after the RSSI becomes equal to or less than the threshold), the process proceeds to step 322 via step 301 and step 321. In step 322, [1] is subtracted from PwrCnt and the process proceeds to step 323. Since the subtraction result of PwrCnt at this time is [23], the process proceeds to step 324. Also, WidthCnt at this time is [27], and the process proceeds to step 325 from the branch condition in step 324. PwrDetflag, which is the branch condition in step 325, is [1] at the eighth clock, and the process proceeds to step 326. The InBandflag information in step 326 is given from an in-band power determination circuit described later. When the RSSI spectrum exceeding the threshold is within the reception band, [1] has already come, and the process proceeds to step 327. In step 327, the RadMDetflag indicating the reception of the radar interference wave is set to [1], and the counter and flag used in the radar pulse width determiner are initialized. The RadarDetflag is constantly monitored by the upper firmware, and when the reading process by the firmware is completed, it is returned to [0] and all the normal reception processes are completed.

上記は１ｕｓｅｃパルス幅のレーダ干渉波で説明したが、この説明では有効パルス幅の最小値を０．７ｕｓｅｃとし、最大値は２．５ｕｓｅｃのパルス幅にマルチパス３００ｍの遅延の重畳を加味し、３．５ｕｓｅｃと定める。又、パルス終了後から連続して１．５ｕｓｅｃの無信号区間がある事を持って有効パルスの条件とする。この条件判断はステップ３２４で行い、有効パルス幅はＷｉｄｔｈＣｎｔが［１７］を超え、［５３］を超えてはならない。  The above is described with a radar interference wave having a 1 usec pulse width. In this description, the minimum effective pulse width is set to 0.7 usec, and the maximum value is obtained by adding a multipath 300 m delay to a 2.5 usec pulse width, It is determined as 3.5 usec. Also, the effective pulse condition is that there is a 1.5 usec no-signal section continuously after the end of the pulse. This condition determination is made in step 324, and the effective pulse width should not exceed [53] with WidthCnt exceeding [17].

ステップ３２５はＰｗｒＤｅｔｆｌａｇが［１］でＲＳＳＩの閾値を超える連続したパルスが［８］回、又は閾値を上下するＲＳＳＩにおいて、ＲＳＳＩの閾値を超える回数が平均値より８回多い場合に有効パルスと判断する。この処理はＲＳＳＩが雑音性である場合、その平均が閾値以上である事を保証する為に設ける。  Step 325 is determined to be an effective pulse when PwrDetflag is [1] and the number of consecutive pulses exceeding the RSSI threshold is [8] times, or the RSSI exceeding the threshold is 8 times more than the average value in the RSSI. To do. This processing is provided to ensure that the average is equal to or greater than the threshold when the RSSI is noisy.

又、ＲＳＳＩが雑音性である場合、ＰｗｒＣｎｔは上下を繰り返すが、一度ＰｗｒＤｅｔｆｌａｇが［１］を設定した条件化でＲＳＳＩが閾値を以下を検出し、ＰｗｒＣｎｔが［３９］以下になり、次にＲＳＳＩが閾値以上である場合、ステップ３１０で強制的にＰｗｒＣｎｔを［３９］に設定する。これは信号成分の閾値を超える最終クロック点を求めている。  Also, if RSSI is noisy, PwrCnt repeats up and down, but once PwrDetflag is set to [1], the RSSI detects the threshold below, PwrCnt falls below [39], and then RSSI Is greater than or equal to the threshold, step 310 forcibly sets PwrCnt to [39]. This seeks the last clock point that exceeds the signal component threshold.

ステップ３２４、ステップ３２５とステップ３２６の条件を満たさぬ場合は、無効パルスと判断し、ステップ３２８に移行し、全てのカウンターとフラグの初期化を行う。  If the conditions of step 324, step 325, and step 326 are not satisfied, it is determined that the pulse is an invalid pulse, the process proceeds to step 328, and all counters and flags are initialized.

次に受信した信号の帯域内外判定方法を説明する。図３レーダ干渉波検出回路のベースバンド増幅器２０７は６０ｄＢ程度の利得可変範囲を有し、アンテナ２０１の入力端で−９２ｄＢｍの受信強度のＯＦＤＭ信号を受信するため、最大利得に設定して受信信号を待ち受けている。ここで−６２ｄＢｍの閾値を超えるレーダ干渉波を受信した場合、ベースバンド増幅器２０７は飽和したＩＱベースバンド信号をベースバンドアナログ・ディジタル変換器２０７に渡す。ベースバンドアナログ・ディジタル変換器２０７のＩＱディジタル信号出力はこの構成例に記載されていないＯＦＤＭ信号復調器で信号処理され、基準のレベルにすべく、ベースバンド増幅器２０７の利得を調整する。従い、数ｕｓｅｃのレーダ干渉波のＩＱベースバンド信号出力は時間の経過と供に変化する特性を示している。  Next, a method for determining whether the received signal is in or out of band will be described. 3 The baseband amplifier 207 of the radar interference wave detection circuit has a variable gain range of about 60 dB, and receives an OFDM signal having a reception intensity of −92 dBm at the input end of the antenna 201. I am waiting for you. Here, when a radar interference wave exceeding the threshold of −62 dBm is received, the baseband amplifier 207 passes the saturated IQ baseband signal to the baseband analog-digital converter 207. The IQ digital signal output of the baseband analog-to-digital converter 207 is signal-processed by an OFDM signal demodulator not described in this configuration example, and the gain of the baseband amplifier 207 is adjusted to reach a reference level. Accordingly, the IQ baseband signal output of the radar interference wave of several usec shows a characteristic that changes with time.

レーダ干渉波の帯域内外判定は８．３ＭＨｚ以下で３ｄＢの通過帯域損失、１０ＭＨｚ点で２０ｄＢ及び１５ＭＨｚ点で４０ｄＢの減衰特性と１８クロックの遅延時間を有するディジタル低域通過フィルタ２０８の前後の或る特定の時間幅（０．７ｕｓｅｃ）の電力を比較することによって実現できる。  Radar interference wave inside / outside determination is about 8.3 MHz or less, 3 dB passband loss, 20 dB at 10 MHz point, 40 dB attenuation at 15 MHz point, and before and after digital low-pass filter 208 having 18 clock delay time. This can be realized by comparing the power of a specific time width (0.7 usec).

図６に帯域判定回路２０９の動作手順を示す。帯域判定回路２０９は４０Ｍｓｐｓのクロックで動作し、測定時間幅を規定するカウンター（以下ＢａｎｄＣｎｔと略す）、ディジタル低域通過フィルタ２０８の前置の電力（Ｐｂ）を求める加算器とその累積和（以下ＡｃｃｍＰｂと略す）を求める加算器、ディジタル低域通過フィルタ２０８の後置の電力（Ｐａ）を求める加算器とその累積和（以下ＡｃｃｍＰａと略す）を求める加算器、測定時間が完了した事を示すフラグ（以下ＢａｎｄＣｎｔｆｌａｇと略す）各種フラグによる条件分岐回路等で構成される。初期値はカウンター値とフラグはすべて［０］に設定する。この回路の動作結果が帯域内である場合、帯域内信号である事を示すフラグ（以下ＩｎＢａｎｄｆｌａｇと略す）を［１］とし、帯域外の場合［０］を出力する。  FIG. 6 shows an operation procedure of the band determination circuit 209. The band determination circuit 209 operates with a clock of 40 Msps, a counter that defines the measurement time width (hereinafter abbreviated as BandCnt), an adder that calculates the power (Pb) before the digital low-pass filter 208, and a cumulative sum (hereinafter referred to as a cumulative sum). An adder for calculating AccmPb), an adder for calculating the power (Pa) after the digital low-pass filter 208, an adder for calculating its accumulated sum (hereinafter abbreviated as AccmPa), and indicating that the measurement time has been completed. A flag (hereinafter abbreviated as “BandCntflag”) includes a conditional branch circuit using various flags. The initial value is a counter value and all flags are set to [0]. When the operation result of this circuit is within the band, a flag indicating that it is an in-band signal (hereinafter abbreviated as InBandflag) is set to [1], and when it is out of band, [0] is output.

無入力の場合、ステップ４０１で前述のレーダパルス幅判定回路２１２で生成されるＰｗｒｆｌａｇが［０］であることより、この回路の処理は実行されず、クロック内の処理は完了する。  When there is no input, since the Pwrflag generated by the radar pulse width determination circuit 212 in step 401 is [0], the processing of this circuit is not executed and the processing within the clock is completed.

レーダ干渉波が検出された直後のクロックの処理は、ステップ４０１とステップ４０２を経て、ステップ４０３に移行する。ステップ４０３でＢａｎｄＣｎｔに［１］を加え、ステップ４０４の分岐処理を経てステップ４０５に移行する。ステップ４０５ではＰｂの電力｛Ｐｂ＝（Ｉ＾２＋Ｑ＾２）＾１／２｝を演算し、その演算結果をＡｃｃｕｍＰｂに加える。この処理を１８回繰り返す。  The processing of the clock immediately after the radar interference wave is detected goes to Step 403 through Step 401 and Step 402. In step 403, [1] is added to BandCnt, and the process proceeds to step 405 through the branch process in step 404. In step 405, Pb power {Pb = (I ^ 2 + Q ^ 2) ^ 1/2} is calculated, and the calculation result is added to AccumPb. This process is repeated 18 times.

１９回目から２８回目までは、ステップ４０１、ステップ４０２、ステップ４０３、ステップ４０４とステップ４０６を経てステップ４０７に移行する。ステップ４０７ではＰｂの電力｛Ｐｂ＝（Ｉ＾２＋Ｑ＾２）＾１／２｝を演算し、その演算結果をＡｃｃｕｍＰｂに加え、又ディジタル低域通過フィルタの遅延を経てこのクロックよりＰａの電力｛Ｐａ＝（Ｉ＾２＋Ｑ＾２）＾１／２｝を演算し、その演算結果をＡｃｃｕｍＰａに加える。２８回目まで、この処理を繰り返す。２８回目のＡｃｃｕｍＰｂには２８サンプル（０．７ｕｓｅｃ）間の累積和が得られている。  From the 19th time to the 28th time, the process proceeds to Step 407 through Step 401, Step 402, Step 403, Step 404 and Step 406. In step 407, the power of Pb {Pb = (I ^ 2 + Q ^ 2) ^ 1/2} is calculated, the calculation result is added to AccuPb, and the power of Pa from this clock is passed through the delay of the digital low-pass filter { Pa = (I ^ 2 + Q ^ 2) ^ 1/2} is calculated, and the calculation result is added to AccuPa. This process is repeated up to the 28th time. Accumulated sum of 28 samples (0.7 usec) is obtained for the 28th AccumPb.

２９回目から４６回目までは、ステップ４０１、ステップ４０２、ステップ４０３、ステップ４０４、ステップ４０６とステップ４０８を経てステップ４０９に移行する。ステップ４０９ではＰａの電力｛Ｐａ＝（Ｉ＾２＋Ｑ＾２）＾１／２｝を演算し、その演算結果をＡｃｃｕｍＰａに加える。２８回目のＡｃｃｕｍＰａには１８クロック遅延後の２８サンプル（０．７ｕｓｅｃ）間の累積和が得られている。  From the 29th time to the 46th time, the process proceeds to step 409 through step 401, step 402, step 403, step 404, step 406 and step 408. In step 409, Pa power {Pa = (I ^ 2 + Q ^ 2) ^ 1/2} is calculated, and the calculation result is added to AccuPa. Accumulated sum of 28 samples (0.7 usec) after 18 clock delays is obtained in the 28th AccumPa.

４７回目のクロックでは、ステップ４０１、ステップ４０２、ステップ４０３、ステップ４０４、ステップ４０６とステップ４０８を経てステップ４１０に移行する。ステップ４１０でＢａｎｄＣｎｔｆｌａｇに［１］を設定し、ステップ４１１でディジタル低域通過フィルタ前後の累積電力和の比較を行う。判断基準は２倍のＡｃｃｕｍＰａがＡｃｃｕｍＰｂより大きい場合は帯域内と判断する。帯域内であった場合ステップ１４２に移行し、ＩｎＢａｎｄｆｌａｇに［１］を設定する。帯域外の場合は［０］に設定し、クロック内と帯域判定回路の判断処理を完了する。この処理は４７／４０ｕｓｅｃの時間を要する。  In the 47th clock, the process proceeds to step 410 through step 401, step 402, step 403, step 404, step 406 and step 408. In Step 410, BandCntflag is set to [1], and in Step 411, the cumulative power sums before and after the digital low-pass filter are compared. The criterion is that if the double AccuPa is larger than AccuPb, it is determined to be within the band. If it is within the band, the process proceeds to step 142, and [1] is set to InBandflag. If it is out of band, it is set to [0], and the determination processing in the clock and the band determination circuit is completed. This process takes 47/40 usec.

４８回目以降の処理はステップ４０１とステップ４０２を経て終了しする。この回路に使用するカウンター、加算器とフラグはレーダパルス幅判定回路の動作完了時にすべて［０］に設定される。  The 48th and subsequent processes are completed through step 401 and step 402. The counter, adder, and flag used in this circuit are all set to [0] when the operation of the radar pulse width determination circuit is completed.

レーダパルスの波形の例を示す。An example of a radar pulse waveform is shown. 従来技術によるレーダ干渉波検出の実施例を示す。An example of radar interference wave detection according to the prior art will be described. レーダ干渉波検出回路の実施例を示す。An embodiment of a radar interference wave detection circuit will be described. レーダパルス幅判定回路の動作手順を示す。The operation procedure of the radar pulse width determination circuit is shown. レーダパルス幅判定回路に使用しているカウンターの動作例を示す。An example of the operation of the counter used in the radar pulse width determination circuit is shown. 帯域判定回路の動作手順を示す。The operation procedure of the band judgment circuit is shown.

符号の説明Explanation of symbols

１０１ アンテナ
１０２ 受信機
１０３ ディジタル処理回路
１０４ アクセス制御回路
１０５ レーダ波検出回路
１０６ プロトコルエンジン回路
２０１ アンテナ
２０２ 高周波増幅器
２０３ ＩＱ復調器
２０４ ローカル発信器
２０５ 低域通過フィルタ
２０６ ベースバンド増幅器
２０７ ベースバンドアナログ・ディジタル変換器（ＢＢＡＤＣ）
２０８ ディジタル低域通過フィルタ
２０９ 帯域判定回路
２１０ ＲＳＳＩ増幅器
２１１ ＲＳＳＩアナログ・ディジタル変換器（ＲＳＳＩＡＤＣ）
２１２ ＲＳＳＩ判定回路
２１３ レーダパルス幅判定回路
３０１ ＲＳＳＩの閾値上下（ＲＳＳＩｆｌａｇ）の分岐処理
３０２ 過去に閾値を超えるＲＳＳＩ検出の有無（Ｐｗｒｆｌａｇ）の分岐処理
３０３ アップ・ダウンカウンター（ＰｗｒＣｎｔ）値の分岐処理
３０４ 最小パルス幅の検出（ＰｗｒＤｅｔｆｌａｇ）の分岐処理
３０５ アップ・ダウンカウンター（ＰｗｒＣｎｔ）に［１］を加算する処理
３０６ アップ・ダウンカウンター（ＰｗｒＣｎｔ）値の分岐処理
３０７ 最小パルス幅の検出フラグ（ＰｗｒＤｅｔｆｌａｇ）を［１］に設定する処理
３０８ 過去に閾値を超えるＲＳＳＩ検出の有無示す（Ｐｗｒｆｌａｇ）を［１］に、アップ・ダウンカウンター（ＰｗｒＣｎｔ）に初期値［３２］を設定する処理
３０９ 時間幅を計数するカウンター（ＷｉｄｔｈＣｎｔ）に［１］を加算する処理
３１０ アップ・ダウンカウンター（ＰｗｒＣｎｔ）を［３９］に設定する処理
３２１ 過去に閾値を超えるＲＳＳＩ検出の有無（Ｐｗｒｆｌａｇ）の分岐処理
３２２ 時間幅を計数するカウンター（ＷｉｄｔｈＣｎｔ）に［１］を減算する処理
３２３ アップ・ダウンカウンター（ＰｗｒＣｎｔ）値の分岐処理
３２４ 時間幅を計数するカウンター（ＷｉｄｔｈＣｎｔ）の分岐処理
３２５ 最小パルス幅の検出（ＰｗｒＤｅｔｆｌａｇ）の分岐処理
３２６ 帯域内信号を示すフラグ（ＩｎＢａｎｄｆｌａｇ）の分岐処理
３２７ レーダ干渉波の検出を示すフラグ（ＲａｄａｒＤｅｔｆｌａｇ）を［１］に設定する処理及びすべてのカウンターとフラグを初期値の［０］に設定する処理
３２８ すべてのカウンターとフラグを初期値の［０］に設定する処理
４０１ 過去に閾値を超えるＲＳＳＩ検出の有無（Ｐｗｒｆｌａｇ）の分岐処理
４０２ 帯域測定完了を示すフラグ（ＢｎａｄＣｎｔｆｌａｇ）の分岐処理
４０３ 時間幅を計数するカウンター（ＢａｎｄＣｎｔ）に［１］を加算する処理
４０４ 時間幅を計数するカウンター（ＢａｎｄＣｎｔ）値の分岐処理
４０５ ディジタル低域通過フィルタの前置の電力（Ｐｂ）演算処理とその累積和（ＡｃｃｕｍＰｂ）を求める処理
４０６ 時間幅を計数するカウンター（ＢａｎｄＣｎｔ）値の分岐処理
４０７ ディジタル低域通過フィルタの前置の電力（Ｐｂ）演算処理とその累積和（ＡｃｃｕｍＰｂ）及び後置の電力（Ｐａ）演算処理とその累積和（ＡｃｃｕｍＰａ）を求める処理
４０８ 時間幅を計数するカウンター（ＢａｎｄＣｎｔ）値の分岐処理
４０９ ディジタル低域通過フィルタの後置の電力（Ｐａ）演算処理とその累積和（ＡｃｃｕｍＰａ）を求める処理
４１０ 帯域測定完了を示すフラグ（ＢｎａｄＣｎｔｆｌａｇ）を［１］に設定する処理
４１１ ディジタル低域通過フィルタの前後置の累積電力和を比較する処理
４１２ 帯域内信号である事を示すフラグ（ＩｎＢａｎｄｎａｇ）を［１］に設定する処理Reference Signs List 101 antenna 102 receiver 103 digital processing circuit 104 access control circuit 105 radar wave detection circuit 106 protocol engine circuit 201 antenna 202 high frequency amplifier 203 IQ demodulator 204 local oscillator 205 low pass filter 206 baseband amplifier 207 baseband analog / digital Converter (BBADC)
208 Digital Low-Pass Filter 209 Band Determination Circuit 210 RSSI Amplifier 211 RSSI Analog to Digital Converter (RSSIADC)
212 RSSI determination circuit 213 Radar pulse width determination circuit 301 Branching process of RSSI threshold above and below (RSSI flag) 302 Branching process of presence / absence of detection of RSSI exceeding the threshold (Pwrflag) 303 Branching process of up / down counter (PwrCnt) value 304 Branch processing of minimum pulse width detection (PwrDetflag) 305 Processing of adding [1] to up / down counter (PwrCnt) 306 Branch processing of up / down counter (PwrCnt) value 307 Minimum pulse width detection flag (PwrDetflag) Processing 308 for setting [1] 309 Processing for setting the initial value [32] for the up / down counter (PwrCnt) indicating the presence or absence of RSSI detection exceeding the threshold value (Pwrflag) in [1] 309 Counting the time width Processing to add [1] to the counter (WidthCnt) 310 Processing to set the up / down counter (PwrCnt) to [39] 321 Branch processing of presence / absence of RSSI detection exceeding the threshold (Pwrflag) 322 Count the time width Processing for subtracting [1] from the counter (WidthCnt) 323 Branch processing for up / down counter (PwrCnt) value 324 Counter processing for counting time width (WidthCnt) branch processing 325 Minimum pulse width detection (PwrDetflag) branch processing 326 Branch processing 327 of a flag indicating an in-band signal (InBandflag) Processing for setting a flag (RadarDetflag) indicating detection of a radar interference wave to [1] and processing for setting all counters and flags to an initial value [0] 328 You Processing for setting all counters and flags to the initial value [0] 401 Branch processing for presence / absence of RSSI detection exceeding the threshold (Pwrflag) 402 Branch processing for flag (BnadCntflag) indicating completion of bandwidth measurement 403 Time width Processing for adding [1] to the counter (BandCnt) for counting 404 Branch processing for the counter (BandCnt) value for counting time width 405 Power (Pb) calculation processing before the digital low-pass filter and its cumulative sum (AccumPb) 406 for calculating the time width of the counter (BandCnt) value branching process 407 Digital low-pass filter pre-power (Pb) calculation process, cumulative sum (AccumPb) and post-power (Pa) calculation Processing 408 hours to calculate processing and its cumulative sum (AccumPa) The counter (BandCnt) value branching process 409 for counting 409 The post-power (Pa) calculation process of the digital low-pass filter and the process for obtaining the accumulated sum (AccumPa) 410 The flag (BnadCntflag) indicating the completion of the band measurement is set to [1] 411 processing for setting the sum of power before and after the digital low-pass filter 412 processing for setting a flag (InBandnag) indicating that the signal is an in-band signal to [1]

Claims (2)

一定のクロックで動作するアップ・ダウンカンターとタイマーカウンターで構成されるパルス幅計数回路において、
最初に受信レベルが閾値以上である事を検出した場合、アップ・ダウンカンターに初期値を設定する機能、受信レベルが閾値以上である場合、アップ・ダウンカンターを加算し、閾値以下である場合、アップ・ダウンカンターを減算する機能、アップ・ダウンカンターに所定の上限値を設け、この上限値以上にカウントアップしない機能、上限値に達した情報生成する機能、一度上限値に達し、その後減算処理を行った次の処理で再度受信レベルが閾値以上である場合、アップ・ダウンカンターを上限値に設定する機能、アップ・ダウンカンターに所定の下限値を設け、下限値に達した情報を生成する機能、タイマーカウンターは最初に受信レベルが閾値以上である事を検出した時点で計数を開始し、アップ・ダウンカンターが下限に達した時点で計数を停止する機能とタイマーカウンターの計数値でパルスの有効性を判断する機能を有する事を特徴とするレーダ干渉波検出回路。In a pulse width counting circuit consisting of an up / down counter and timer counter that operate with a constant clock,
When it is first detected that the reception level is above the threshold, the function to set the initial value to the up / down counter, when the reception level is above the threshold, the up / down counter is added, and if it is below the threshold, A function to subtract up / down counters, a function that sets a predetermined upper limit value for up / down counters, a function that does not count above this upper limit value, a function that generates information that has reached the upper limit value, and once the upper limit value has been reached, a subtraction process When the reception level is equal to or higher than the threshold value again in the next processing, the function to set the up / down counter to the upper limit value, a predetermined lower limit value is provided for the up / down counter, and information that has reached the lower limit value is generated. Function, timer counter starts counting when it first detects that the reception level is above the threshold, and the up / down counter reaches the lower limit Radar interference wave detection circuit, characterized in that has a function of determining the validity of the pulse in the count value of the function and the timer counter stops counting at point. 請求項１のレーダ干渉波検出回路は更に、ディジタル低域通過帯域フィルタ回路、この回路の前後に置かれる電力演算回路と累積電力積算回路とこの２つの累積電力演算結果を比較判定する回路で構成し、前置の累積電力積算回路は最初に受信レベル検出回路の出力が受信レベル閾値を越えた時点から所定の時間の電力和を求め、後置の累積電力積算回路は最初に受信レベル検出回路の出力が受信レベル閾値を越えた時点より更にディジタル低域通過帯域フィルタ回路の有する遅延時間に相当する遅い時点より所定の時間の電力和を求めパルスが受信帯域内であるかの判断をする機能を有する事を特徴とするレーダ干渉波検出回路。  The radar interference wave detection circuit according to claim 1 further comprises a digital low-pass band filter circuit, a power calculation circuit placed before and after the circuit, a cumulative power integration circuit, and a circuit for comparing and determining the two cumulative power calculation results. The first cumulative power integration circuit calculates the power sum for a predetermined time from when the output of the reception level detection circuit first exceeds the reception level threshold, and the rear cumulative power integration circuit first receives the reception level detection circuit. A function for determining whether the pulse is within the reception band by obtaining the power sum of a predetermined time from a later time corresponding to the delay time of the digital low-pass filter circuit than when the output of the signal exceeds the reception level threshold A radar interference wave detection circuit characterized by comprising:
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