JP2007258394A - Manufacturing method for nitride semiconductor device - Google Patents
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本発明は信頼性向上を目的とした窒化物半導体素子に関する。 The present invention relates to a nitride semiconductor device for improving reliability.
III族窒化物半導体は、視光から紫外光領域に相当する３．４ｅＶのバンドギャップを持ち高効率な発光が可能であるため、発光ダイオード（ＬＥＤ）やレーザーダイオード（ＬＤ）としての製品化が成されている。特に蛍光体との組み合わせによる白色発光ダイオードの実現は発光ダイオード応用の新しい分野として期待されている。 Group III nitride semiconductors have a band gap of 3.4 eV, which corresponds to the ultraviolet region from the visible light, and can emit light with high efficiency. It is made. In particular, the realization of white light emitting diodes in combination with phosphors is expected as a new field of light emitting diode applications.
一般に半導体ウェハは、半導体単結晶基板の上にエピタキシャル成長により目的とする半導体層を成長させることにより得られる。しかし窒化物半導体の単結晶は未だ工業的には得られておらず、通常は高温で安定なサファイア（Ａｌ2Ｏ3）や炭化珪素（ＳｉＣ）、シリコン（Ｓｉ）等の異種基板が用いられる。 In general, a semiconductor wafer is obtained by growing a target semiconductor layer by epitaxial growth on a semiconductor single crystal substrate. However, single crystals of nitride semiconductors have not yet been industrially obtained, and different types of substrates such as sapphire (Al 2 O 3 ), silicon carbide (SiC), silicon (Si), etc., which are stable at high temperatures are usually used. .
上記にあげた異種基板は窒化物半導体との格子不整合が大きく、直接に窒化物半導体を成長させると結晶性の劣ったものしか得られず、特許文献１、特許文献２等にあげるバッファ層と呼ばれる特殊な層をまず異種基板上に成長させてから窒化物半導体層を成長する手法がとられる。
バッファ層自身は結晶成長として特殊な条件で成長させるため、その層自身の結晶性は劣っており、また基板上での均一性についても通常の半導体層に比べて確保しにくい性質がある。
バッファ層の結晶性が低い点を反映して窒化物半導体層に引き継がれる欠陥で最も密度の多いものが、螺旋転位、刃状転位等の転位であり窒化物半導体では１×１０8ｃｍ-2〜１×１０10ｃｍ-2の高密度の欠陥を有していることが知られている。
バッファ層の低結晶性より生ずる窒化物半導体層の結晶欠陥は転位以外にも存在し、例えば反転領域（Inversion Domain）と呼ばれる極性の反転した領域や積層欠陥（Stacking Fault)等が生じることが知られている。これらの欠陥の発生部分はウェハの特定の部分に限られるのではなくウェハ面内にランダムに発生する事が多い。
Since the buffer layer itself is grown under special conditions for crystal growth, the crystallinity of the layer itself is inferior, and the uniformity on the substrate is also difficult to ensure as compared with a normal semiconductor layer.
Reflecting the low crystallinity of the buffer layer, the defects with the highest density, which are inherited by the nitride semiconductor layer, are dislocations such as screw dislocations and edge dislocations, and 1 × 10 8 cm −2 in the nitride semiconductor. It is known to have high density defects of ˜1 × 10 10 cm −2 .
It is known that the crystal defects of the nitride semiconductor layer caused by the low crystallinity of the buffer layer exist in addition to dislocations, for example, an inversion region called an inversion domain or a stacking fault occurs. It has been. The occurrence of these defects is not limited to a specific part of the wafer, but often occurs randomly within the wafer surface.
窒化物半導体層中に存在している結晶欠陥は、窒化物半導体を用いて作成する素子特性に影響を与える。転位はＩｎＧａＮ結晶成長中にピットを発生させる起点となる事（非特許文献１）や移動度の低下をもたらす（非特許文献２）ことが知られている。また積層欠陥も界面に有する格子不整が点欠陥と関係することが知られている（非特許文献３）。
窒化物半導体層中の結晶欠陥は素子特性に影響を与えるために、欠陥が存在する素子を把握することが望まれる。初期特性に変化を与えるような欠陥の場合、初期検査で不良素子を同定し除去することも可能であるが、長期の通電試験に影響を与えるような場合、その同定に多大の時間が必要で全ての不良素子の把握は困難である。 Since crystal defects in the nitride semiconductor layer affect device characteristics, it is desirable to grasp the device in which the defect exists. In the case of a defect that changes the initial characteristics, it is possible to identify and remove the defective element in the initial inspection, but if it affects the long-term current test, it takes a lot of time to identify it. It is difficult to grasp all defective elements.
結晶欠陥にはヒロックやピットの様に光学顕微鏡で判別出来るような外観上の特徴を持つものもあるが、転位や反転領域を観察するには透過電子顕微鏡（ＴＥＭ）に因らねばならない。しかしＴＥＭは観察試料作成に多大な手間を要する破壊試験であり、観察できる領域は数μｍ幅の微小領域であるため、ウェハ面内にランダムに存在する欠陥の判別手段としては全く無力である。
上記の様に窒化物半導体中には欠陥が存在しており、その欠陥位置の同定を簡易な手段で可能にすることは、窒化物半導体素子の信頼性を向上する上で有効な手段となる。
Some crystal defects have appearance characteristics such as hillocks and pits that can be discriminated with an optical microscope, but in order to observe dislocations and inversion regions, they must be based on a transmission electron microscope (TEM). However, TEM is a destructive test that requires a great deal of labor to prepare an observation sample, and since the region that can be observed is a micro region with a width of several μm, it is completely ineffective as a means for discriminating defects randomly existing in the wafer surface.
As described above, a defect exists in the nitride semiconductor, and enabling identification of the defect position by a simple means is an effective means for improving the reliability of the nitride semiconductor element. .
本発明の目的は、窒化物半導体上の素子の信頼性を向上するため、その欠陥の個所を同定するための簡便な手段を提供することにある。すなわち従来ＴＥＭによる観察同定を必要とした転位や積層欠陥等の結晶欠陥を光学顕微鏡等の簡便な手段で観察可能な形状にし、欠陥部位の光学顕微鏡による判別を可能にすることを目的とする。 An object of the present invention is to provide a simple means for identifying the location of a defect in order to improve the reliability of a device on a nitride semiconductor. That is, it is an object of the present invention to form crystal defects such as dislocations and stacking faults that have been conventionally required for observation and identification with a TEM so that the defects can be observed with a simple means such as an optical microscope, so that the defect site can be identified with an optical microscope.
本発明は上記目的を達成するために研究した結果、半導体表面をエッチングすると結晶欠陥部分が優先的にエッチングされ、光学顕微鏡でも観察可能なエッチング穴が形成されることを見出し、これによって結晶欠陥の程度の判別に応用したものである。半導体表面をエッチングすることは特開平１１−１６８５２号公報に記載されているように公知である。しかしそのエッチングの目的はエッチングされた面に電極を形成する際の接触抵抗の低減であり、結晶欠陥とエッチングの関係については触れていない。 As a result of research to achieve the above object, the present invention has found that when a semiconductor surface is etched, a crystal defect portion is preferentially etched, and an etching hole that can be observed with an optical microscope is formed. This is applied to the determination of the degree. Etching the surface of a semiconductor is known as described in JP-A-11-16852. However, the purpose of the etching is to reduce the contact resistance when an electrode is formed on the etched surface, and the relationship between crystal defects and etching is not mentioned.
本発明は以下の請求項からなる。
（１）III族窒化物半導体素子の製造方法において、製造工程中に半導体の結晶欠陥を顕現化する工程及び顕現化された結晶欠陥の観察工程を含むことを特徴とするIII族窒化物半導体素子の製造方法。
（２）結晶欠陥を顕現化する工程が、基板上に少なくとも一層以上のIII族窒化物半導体を形成した半導体ウェハに対して、その電極形成を伴う素子化工程の前に行うことを特徴とする上記（１）に記載のIII族窒化物半導体素子の製造方法。
（３）結晶欠陥を顕現化する工程が、第１のエッチング工程である上記（１）または（２）に記載のIII族窒化物半導体素子の製造方法。
（４）結晶欠陥を顕現化する工程が、第１のエッチング工程と、その後に行う第２のエッチング工程の組み合わせからなることを特徴とする上記（１）〜（３）のいずれかに記載のIII族窒化物半導体素子の製造方法。
The present invention comprises the following claims.
(1) A method for manufacturing a group III nitride semiconductor device, comprising a step of revealing crystal defects in the semiconductor and an observation step of the revealed crystal defects in the manufacturing process. Manufacturing method.
(2) The step of revealing crystal defects is performed on a semiconductor wafer on which at least one group III nitride semiconductor is formed on a substrate before the device forming step accompanied with the electrode formation. The manufacturing method of the group III nitride semiconductor element as described in said (1).
(3) The method for producing a group III nitride semiconductor device according to (1) or (2), wherein the step of revealing crystal defects is a first etching step.
(4) The process according to any one of (1) to (3) above, wherein the step of revealing crystal defects is a combination of a first etching step and a second etching step performed thereafter. A method for manufacturing a group III nitride semiconductor device.
（５）第１のエッチング工程が、第１の湿式エッチング工程である上記（３）または（４）に記載のIII族窒化物半導体素子の製造方法。
（６）第１の湿式エッチング工程が、オルトリン酸（Ｈ3ＰＯ4）を主成分として含むエッチング液による工程であることを特徴とする上記（５）に記載のIII族窒化物半導体素子の製造方法。
（７）第１の湿式エッチング工程が、１２０℃〜３００℃の温度範囲で行われる上記（５）または（６）に記載のIII族窒化物半導体素子の製造方法。
（８）第１の湿式エッチング工程が、１５０℃〜２４０℃の温度範囲で行われる上記（５）〜（７）のいずれかに記載のIII族窒化物半導体素子の製造方法。
(5) The method for producing a group III nitride semiconductor device according to (3) or (4), wherein the first etching step is a first wet etching step.
(6) The first wet etching process is a process using an etching solution containing orthophosphoric acid (H 3 PO 4 ) as a main component, and manufacturing the group III nitride semiconductor device according to (5) above Method.
(7) The method for producing a group III nitride semiconductor device according to (5) or (6), wherein the first wet etching step is performed in a temperature range of 120 ° C. to 300 ° C.
(8) The method for producing a group III nitride semiconductor device according to any one of (5) to (7), wherein the first wet etching step is performed in a temperature range of 150 ° C. to 240 ° C.
（９）第２のエッチング工程が、湿式か乾式のいずれかの方法で行うことを特徴とする上記（４）〜（８）のいずれかに記載のIII族窒化物半導体素子の製造方法。
（１０）上記（５）〜（９）のいずれかに記載の第１の湿式エッチング工程により、半導体ウエハの結晶欠陥を１μｍ以上の大きさに顕現化させ、該半導体ウエハに電極形成を行うことを特徴とするIII族窒化物半導体素子の製造方法。
（１１）p型電極として透明電極を用いる上記（１）〜（１０）のいずれかに記載のIII族窒化物半導体素子の製造方法。
（１２）上記（１）〜（１１）に記載の観察工程の後に、顕現化された結晶欠陥に基づく素子の分別工程を有するIII族窒化物半導体素子の製造方法。
(9) The method for producing a group III nitride semiconductor device according to any one of (4) to (8), wherein the second etching step is performed by either a wet method or a dry method.
(10) The first wet etching process according to any one of the above (5) to (9) causes crystal defects of the semiconductor wafer to be manifested to a size of 1 μm or more, and electrodes are formed on the semiconductor wafer. A method for producing a group III nitride semiconductor device, characterized in that:
(11) The method for producing a group III nitride semiconductor device according to any one of (1) to (10), wherein a transparent electrode is used as the p-type electrode.
(12) A method for manufacturing a group III nitride semiconductor device, comprising a device separation step based on a crystal defect that has been revealed after the observation step according to (1) to (11).
本発明により窒化物半導体層中に存在する欠陥部位の特定をすることが可能で、欠陥部位を含んだ素子の特定をすることにより素子の信頼性を向上することが可能となる。 According to the present invention, it is possible to specify a defect site existing in the nitride semiconductor layer, and it is possible to improve the reliability of the device by specifying a device including the defect site.
本発明のIII族窒化物半導体（窒化物半導体と略すこともある）素子の製造には公知の方法を用いることができる。即ち、窒化物半導体積層物の基板には、サファイア単結晶（Ａｌ2Ｏ3；Ａ面、Ｃ面、Ｍ面、Ｒ面）、スピネル単結晶（ＭｇＡｌ2Ｏ4）等の酸化物単結晶、ＳｉＣ単結晶、Ｓｉなどの公知の基板材料を何ら制限なく用いることができる。これらの中でもサファイアやＳｉ、ＳｉＣが好ましい。比較的良質な大面積の結晶が容易に入手可能である。結晶基板の面方位は特に限定されないが、窒化物半導体がＣ面成長する面方位が好ましい。また、ジャスト基板でも良いしオフ角を付与した基板であっても良い。 A known method can be used for manufacturing the group III nitride semiconductor (sometimes abbreviated as nitride semiconductor) element of the present invention. That is, the substrate of the nitride semiconductor laminate includes oxide single crystals such as sapphire single crystals (Al 2 O 3 ; A plane, C plane, M plane, R plane), spinel single crystals (MgAl 2 O 4 ), Known substrate materials such as SiC single crystal and Si can be used without any limitation. Of these, sapphire, Si, and SiC are preferable. Relatively good quality large area crystals are readily available. The plane orientation of the crystal substrate is not particularly limited, but the plane orientation in which the nitride semiconductor grows on the C plane is preferable. Moreover, a just board | substrate may be sufficient and the board | substrate which provided the off angle may be sufficient.
上記基板上に、それぞれ窒化物半導体よりなるバッファ層、及び窒化物半導体からなる少なくとも一層以上の層を、それぞれの層に対して最適な条件で積層させる。この際、バッファ層の成長条件、不純物ドーピング条件、熱処理の方法については公知の技術をなんら支障なく用いることが出来る。
基板上に窒化物半導体層を積層したウェハに対し、その表面（電極形成面）において結晶欠陥を顕現化する処理（工程）を行う。結晶欠陥の顕現化とはＴＥＭでしか観察できなかった結晶欠陥を光学顕微鏡などを用いた簡便な方法で観察可能な形状することを云う。その方法の一つとして第１のエッチング処理が挙げられる。このエッチング処理は液相で行う湿式エッチングによることが好ましい。湿式エッチング処理はエッチング液の回りこみ作用により、結晶中に存在する欠陥部分について侵食する効果が可能となる。
A buffer layer made of a nitride semiconductor and at least one layer made of a nitride semiconductor are stacked on the substrate under optimum conditions for each layer. At this time, a known technique can be used without any problems as to the growth conditions of the buffer layer, the impurity doping conditions, and the heat treatment method.
A process (process) is performed on a wafer in which a nitride semiconductor layer is stacked on a substrate to reveal crystal defects on the surface (electrode formation surface). The manifestation of crystal defects refers to the formation of crystal defects that can only be observed with a TEM by a simple method using an optical microscope or the like. One of the methods is a first etching process. This etching process is preferably performed by wet etching performed in a liquid phase. In the wet etching process, an effect of eroding a defect portion existing in the crystal by the sneaking action of the etching solution becomes possible.
エッチング液としては、オルトリン酸（Ｈ3ＰＯ4）を主成分として含むエッチング液であることが望ましい。添加剤として硫酸（ＳＯ4）、アンモニア（ＮＨ3）を含む塩類を加えても良い。これらの塩類を加えることでエッチングにより生ずるピットの形状が変化するため、検査に適したエッチング穴が生ずるようにすれば良い。エッチング穴としては１μｍ以上の大きさとなるようにすれば光学顕微鏡での確認が可能となる。 The etchant is preferably an etchant containing orthophosphoric acid (H 3 PO 4 ) as a main component. Salts containing sulfuric acid (SO 4 ) and ammonia (NH 3 ) may be added as additives. The addition of these salts changes the shape of the pit generated by etching, so that an etching hole suitable for inspection may be formed. If the etching hole has a size of 1 μm or more, it can be confirmed with an optical microscope.
エッチングの温度としては１２０℃〜３００℃までの範囲で選べば良い。さらに望ましくは１５０〜２４０℃の間の範囲で選べばよい。エッチング温度は高い方がエッチング速度は大きく、欠陥の顕現化に必要な時間が短く出来る。
しかし結晶によってはＧａＮ表面の荒れが発生する傾向があり、その後の素子化工程で問題が生ずる場合がある。温度が低いと欠陥の顕現化に必要な時間が長くなる問題がある。荒れの発生とエッチング処理時間の短縮の点から選べばよい。
The etching temperature may be selected in the range of 120 ° C to 300 ° C. More preferably, it may be selected in the range of 150 to 240 ° C. The higher the etching temperature, the higher the etching rate, and the shorter the time required for revealing defects.
However, depending on the crystal, the surface of the GaN tends to be rough, and problems may occur in the subsequent device fabrication process. If the temperature is low, there is a problem that the time required to reveal defects becomes long. It may be selected from the viewpoint of occurrence of roughness and shortening of etching processing time.
第１の湿式エッチングの後には何らかの処理を行うことが望ましい。上記エッチングは高温で行われるため表面に酸化膜/変質層が残り、後の電極形成工程で問題が生ずることがある。そのため第１のエッチングに引き続き酸化膜/変質層除去のため、第２のエッチングを行うことが望ましい。第２のエッチングとしては湿式エッチング、乾式エッチングの何れでもよい。湿式エッチングの場合は加温したフッ酸（ＨＦ）、緩衝フッ酸（ＢＨＦ）、塩酸（ＨＣｌ）等の処理が有効である。また乾式エッチングとしては塩素系を用いたドライエッチングも適用可能である。 It is desirable to perform some processing after the first wet etching. Since the etching is performed at a high temperature, an oxide film / altered layer remains on the surface, which may cause a problem in the subsequent electrode formation process. Therefore, it is desirable to perform the second etching for removing the oxide film / altered layer following the first etching. As the second etching, either wet etching or dry etching may be used. In the case of wet etching, treatment with heated hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), hydrochloric acid (HCl), or the like is effective. As dry etching, dry etching using a chlorine system is also applicable.
エッチング穴の観察は電極を付ける前、あるいはその後に行うことが出来る。観察は光学顕微鏡で行うことができる。観察の結果、エッチング穴の少ないもの、多いものなどグレード分けすることができる。また特に悪いものは除去することもできる。
エッチング処理後電極を形成する。ｐ型電極はエッチング面に、ｎ型電極は半導体層の１部をエッチングしてｎ型層を露出させ、その面に形成する。ｐ型層はＡｕ、Ｐｔなどの透明薄層、ＩＴＯなどの透明材料が好ましい。電極形成後もその上から観察出来るからである。
The observation of the etching hole can be performed before or after attaching the electrode. Observation can be performed with an optical microscope. As a result of observation, grades such as those with few etching holes and those with many etching holes can be classified. Particularly bad ones can also be removed.
An electrode is formed after the etching process. The p-type electrode is formed on the etched surface, and the n-type electrode is formed on the surface by etching a part of the semiconductor layer to expose the n-type layer. The p-type layer is preferably a transparent thin layer such as Au or Pt, or a transparent material such as ITO. This is because it can be observed from above even after the electrodes are formed.
本発明による実施例を以下に示す。実施例では窒化物半導体発光素子に適用した例であるが、本発明の適用は発光素子のみに限定されるものではない。
（実施例１）
基板としてサファイア（Ａｌ2Ｏ3）Ｃ面基板２０１を用い、その上に特開２００３−２４３３０２号公報にある方法に従ってＡｌＮバッファを介してアンドープのＧａＮ層を６μｍ、Ｇｅを周期的にドープして平均のキャリア濃度が１×１０19ｃｍ-3となるようにしたｎ型コンタクト層を４μｍ、Ｉｎ0.1Ｇａ0.9Ｎからなる厚さ１２．５ｎｍのｎクラッド層、ＧａＮからなる厚さ１６ｎｍの障壁層とＩｎ0.2Ｇａ0.8Ｎからなる厚さ２．５ｎｍの井戸層を交互に５回積層させた後、最後に障壁層を設けた多重量子井戸構造の発光層、Ｍｇドープ（濃度８×１０19／ｃｍ3）Ａｌ0.07Ｇａ0.93からなる厚さ１０ｎｍのｐクラッド層、Ｍｇドープ（濃度８×１０19／ｃｍ3）Ａｌ0.03Ｇａ0.97Ｎからなる厚さ０．１５μｍのｐコンタクト層を順次積層して窒化物半導体層２０２（以下ウェハと称する。）を形成した（図１）。
Examples according to the present invention are shown below. In the embodiment, the present invention is applied to a nitride semiconductor light emitting device, but the application of the present invention is not limited to the light emitting device.
Example 1
A sapphire (Al 2 O 3 ) C-plane substrate 201 is used as a substrate, and an undoped GaN layer is periodically doped with 6 μm and Ge through an AlN buffer according to a method disclosed in Japanese Patent Application Laid-Open No. 2003-243302. An n-type contact layer having an average carrier concentration of 1 × 10 19 cm −3 is 4 μm, a 12.5 nm thick n-cladding layer made of In 0.1 Ga 0.9 N, and a 16 nm thick barrier layer made of GaN. And a well layer of 2.5 nm thickness composed of In 0.2 Ga 0.8 N are alternately stacked five times, and finally a light emitting layer having a multiple quantum well structure in which a barrier layer is provided, Mg doped (concentration 8 × 10 19 / cm 3 ) A p-cladding layer made of Al 0.07 Ga 0.93 and a thickness of 10 nm, and a Mg-doped (concentration 8 × 10 19 / cm 3 ) p-contact layer made of Al 0.03 Ga 0.97 N and a thickness of 0.15 μm. A nitride semiconductor layer 202 (hereinafter referred to as a wafer) was formed (FIG. 1).
作成したウェハの第１のエッチングを行う。エッチング液としてリン酸（Ｈ3ＰＯ4）を用い、塩類の添加は行っていない。リン酸を２００℃に加熱し、ウェハを１時間浸漬してエッチングを行った。１時間経過後ウェハを取り出し水洗を行う。
第１のエッチングが終了した段階でウェハを光学顕微鏡で観察したところ、５〜１０μｍの概ね６角形をした穴が観察できた。図２はその一例をしめす。穴はサファイア基板にまで達しており、穴の底にはサファイア基板が露出していた。
The first etching of the produced wafer is performed. Phosphoric acid (H 3 PO 4 ) is used as an etching solution, and no salt is added. Etching was performed by heating phosphoric acid to 200 ° C. and immersing the wafer for 1 hour. After 1 hour, the wafer is taken out and washed with water.
When the first etching was completed, the wafer was observed with an optical microscope. As a result, a generally hexagonal hole of 5 to 10 μm could be observed. FIG. 2 shows an example. The hole reached the sapphire substrate, and the sapphire substrate was exposed at the bottom of the hole.
穴の発生個所はウェハの周辺部に多くみられたが、ウェハ中央部にも散見された。同時に処理した複数のウェハで観察した結果、周辺部で穴が多く観察されるのは同様であったが、面内の穴の発生パターンはウェハによって違っており、特定のパターンは観察されなかった。
引き続いて第２のエッチングを行う。第２のエッチングは８０℃に加温したＨＣｌ（３０質量％）を用いた。液温が設定温度に達したところでウェハを浸漬し、１０分間保持した後にウェハを取り出し、水洗乾燥を行う。
Many holes were found in the periphery of the wafer, but were also found in the center of the wafer. As a result of observing multiple wafers processed at the same time, it was the same that many holes were observed in the periphery, but the pattern of holes in the plane was different depending on the wafer, and no specific pattern was observed. .
Subsequently, a second etching is performed. In the second etching, HCl (30% by mass) heated to 80 ° C. was used. When the liquid temperature reaches the set temperature, the wafer is immersed and held for 10 minutes, and then the wafer is taken out and washed with water and dried.
その後、半導体発光素子の素子化工程を行う。フォトリソ工程と公知のＣｌ2ガスによるＲＩＥにより、素子の境界部分およびｎ型コンタクト層となる部分を露出させる。その後、アセトンを用いてリソグラフに用いたレジストを除去する。
有機洗浄と８０℃に加温したＨＣｌ（３０％）での表面エッチングを行い、ウェハ表面の汚れと酸化物を除去した後、再度リソグラフによりｐ側電極領域の形成を行う。この有機洗浄後の加温したＨＣｌでの表面エッチングは、第２のエッチングと兼ねてもよい。しかし第１のエッチングによる酸化膜が残った窒化物半導体の表面に対してはフォトリソに用いるレジストの密着性が低下する場合があり、そのような場合には第１のエッチングに引き続き、第２のエッチングを行った方がよい。
Thereafter, an element forming process of the semiconductor light emitting element is performed. The boundary portion of the element and the portion that becomes the n-type contact layer are exposed by a photolithography process and RIE using a known Cl 2 gas. Then, the resist used for the lithograph is removed using acetone.
Organic cleaning and surface etching with HCl (30%) heated to 80 ° C. are performed to remove the dirt and oxide on the wafer surface, and then the p-side electrode region is formed again by lithography. The surface etching with heated HCl after the organic cleaning may also serve as the second etching. However, the adhesion of the resist used for photolithography may be reduced with respect to the surface of the nitride semiconductor where the oxide film is left by the first etching. In such a case, the second etching is continued following the first etching. It is better to perform etching.
リソグラフを行ったウェハを真空蒸着装置に導入し、１×１０-4Ｐａまで真空引き後、ＥＢ蒸着によりＰｔを５Å蒸着する。蒸着金属の厚みは水晶振動子による厚さ計でモニターする。引き続きＡｕを４０Å蒸着する。蒸着後、リフトオフにより透光性電極の形成を行う。再度、リソグラフによりｎパッド電極とｐパッド電極領域の形成を行う。パッド電極パターンを形成したウェハを蒸着装置に導入し、１×１０-4Ｐａに真空引き後Ｃｒ，Ｔｉ，Ａｕをこの順に各々４０ｎｍ、１００ｎｍ、１０００ｎｍの厚さでＥＢ蒸着を行い、リフトオフによりパッド電極を形成した。電極形成後に加熱は行う必要はない。 The lithographic wafer is introduced into a vacuum deposition apparatus, evacuated to 1 × 10 −4 Pa, and 5% Pt is deposited by EB deposition. The thickness of the deposited metal is monitored with a thickness gauge using a quartz crystal. Subsequently, 40 nm of Au is deposited. After vapor deposition, a translucent electrode is formed by lift-off. The n pad electrode and p pad electrode regions are again formed by lithography. The wafer on which the pad electrode pattern is formed is introduced into a vapor deposition apparatus, and after evacuation to 1 × 10 −4 Pa, Cr, Ti, and Au are deposited in this order in thicknesses of 40 nm, 100 nm, and 1000 nm, respectively, and the pad is lifted off. An electrode was formed. Heating is not necessary after electrode formation.
電極形成面（ｐ電極） より観察したところ、第１のエッチングで生じた穴上にもパターニングされた電極が形成されていた。穴の発生位置は、ウェハ面内で分布していることを反映し、穴位置と電極パターンの位置関係は様々であった。また異なったウェハでは、発生状況に違いがみられた。
電極形成後のウェハを研磨により８０μｍに薄片化し、ブレーカーにより個々の素子に分離した後、評価用のＴＯ‐１８ステムにマウントして発光出力、Ｉ−Ｖ特性の評価を行った。評価用にエッチング時に穴の発生していない正常な素子と穴の発生した部分上の素子とを分別して評価を行った。穴の発生した素子の発生頻度は正常な素子の６％程度であった。
When observed from the electrode forming surface (p electrode), a patterned electrode was formed also on the hole generated by the first etching. Reflecting the fact that the hole generation position is distributed in the wafer surface, the positional relationship between the hole position and the electrode pattern was various. Different wafers showed different occurrences.
The wafer after electrode formation was thinned to 80 μm by polishing, separated into individual elements by a breaker, and then mounted on an evaluation TO-18 stem to evaluate light emission output and IV characteristics. For evaluation, a normal element in which no hole was generated at the time of etching and an element on the portion in which the hole was generated were separated and evaluated. The frequency of occurrence of elements with holes was about 6% of normal elements.
正常な素子の特性は出力で６ｍＷ、１μＡ通電時のＶｆが２．４Ｖ、２０ｍＡ通電時のＶｆが３．１Ｖを示した。一方で穴の開いたウェハ部分上に形成された素子の特性を評価したところ、１μＡ通電時のＶｆが２Ｖ未満の素子が９０％以上みられた。
穴の開いた素子を除去後に３０ｍＡの通電条件で加速劣化試験を行った結果、出力の劣化率は１００時間後の出力が約３．０％の低下を示し、Ｖfが１．２％の低下を示した。
The characteristics of the normal element were 6 mW in output, Vf when energizing 1 μA was 2.4 V, and Vf when energizing 20 mA was 3.1 V. On the other hand, when the characteristics of the elements formed on the wafer portion with the holes were evaluated, 90% or more of the elements having a Vf of less than 2 V when 1 μA was applied.
As a result of the accelerated deterioration test under the 30 mA energization condition after removing the element with the hole, the output deterioration rate showed a decrease of about 3.0% in the output after 100 hours and a decrease in Vf of 1.2%. showed that.
（実施例２）
実施例１で行った第１のエッチング条件を変更して行った実施例について示す。ウェハの作成は実施例１と同じ条件で第１のエッチングを３００℃で実施した。
１０分のエッチングで最大１０μの穴が確認されたが、ウェハ全面に荒れが発生した。図３はその一例を示す。電極の形成を実施例１と同じ条件で実施したが、１μＡ通電時のＶｆが３．０Ｖ、２０ｍＡ通電時のＶｆが５Ｖ以上となった。
(Example 2)
An example performed by changing the first etching condition performed in Example 1 will be described. The wafer was produced by performing the first etching at 300 ° C. under the same conditions as in Example 1.
A maximum of 10 μ holes were confirmed after 10 minutes of etching, but the entire surface of the wafer was rough. FIG. 3 shows an example. The electrodes were formed under the same conditions as in Example 1. However, Vf at 1 μA energization was 3.0 V, and Vf at 20 mA energization was 5 V or more.
次に第１のエッチングを２５０℃で実施したところ、ウェハ全面に荒れが発生することはないが、ウェハ面内で荒れの発生に分布が生ずることが確認された。
また荒れの発生しないウェハもあった。荒れの発生しないウェハでは、２０ｍＡ通電時のＶfの値は正常（３．１Ｖ）であった。１μＡ通電時のＶｆが２．４Ｖであった。
荒れの発生したウェハの表面をＡＦＭ（原子間力顕微鏡）で観察したところ、表面に０．１〜０．２μｍの６角形をしたピットが高密度に観察された。これは光学顕微鏡で観察した穴とは大きさ、形状とも異なった欠陥であった。
Next, when the first etching was performed at 250 ° C., it was confirmed that although the surface of the wafer was not roughened, a distribution was generated in the surface of the wafer.
Some wafers were not rough. For a wafer with no roughness, the value of Vf at 20 mA energization was normal (3.1 V). Vf at the time of 1 μA energization was 2.4V.
When the surface of the roughened wafer was observed with an AFM (Atomic Force Microscope), hexagonal pits of 0.1 to 0.2 μm were observed at high density on the surface. This was a defect different in size and shape from the hole observed with an optical microscope.
（比較例）
比較のために本発明によらない従来例について示す。
ウェハの構造は実施例１と同様である。第１、第２のエッチングを行わない以外は実施例１と同じ条件で素子化工程を行った。ウェハの表面は鏡面のままであった。
素子化評価の結果、出力６ｍＷ、２０ｍＡ通電時Ｖｆが３．１Ｖ、１μＡ通電時のＶｆが２．４Ｖであった。加速劣化試験の結果、Ｖｆ劣化の平均は１．５％であったが、１０％以上の劣化を示す素子が約５％見られた。
(Comparative example)
For comparison, a conventional example not according to the present invention will be described.
The wafer structure is the same as that of the first embodiment. The element forming step was performed under the same conditions as in Example 1 except that the first and second etching were not performed. The surface of the wafer remained a mirror surface.
As a result of evaluation of the device, the output was 6 mW, the Vf when energizing 20 mA was 3.1 V, and the Vf when energizing 1 μA was 2.4 V. As a result of the accelerated deterioration test, the average of Vf deterioration was 1.5%, but about 5% of elements exhibiting deterioration of 10% or more were observed.
本発明によれば、窒化物半導体層に含まれる欠陥を光学顕微鏡で観察できるように顕現化することが出来、欠陥を含んだ素子を予め区別することが可能となるため、ウェハから生産する素子の信頼性を向上することが可能となる。 According to the present invention, defects contained in the nitride semiconductor layer can be manifested so that they can be observed with an optical microscope, and elements containing defects can be distinguished in advance. It becomes possible to improve the reliability.
１０１ パッド電極
１０２ 透明電極
２０１ 基板
２０２ 窒化物半導体層
101 Pad electrode 102 Transparent electrode 201 Substrate 202 Nitride semiconductor layer
Claims (12)
A method for manufacturing a group III nitride semiconductor device, comprising a device separation step based on crystallized crystal defects after the observation step according to claim 1.
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| JPH09330967A (en) * | 1996-06-12 | 1997-12-22 | Sumitomo Chem Co Ltd | Method for evaluating dislocation density of compound semiconductor |
| JPH10144989A (en) * | 1996-11-06 | 1998-05-29 | Sony Corp | Manufacture of semiconductor laser |
| JP2000188285A (en) * | 1998-10-13 | 2000-07-04 | Sony Corp | Etching method, crystallinity evaluating method, and manufacture of semiconductor device |
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| JP2005197289A (en) * | 2003-12-26 | 2005-07-21 | Nichia Chem Ind Ltd | Nitride semiconductor light emitting element and its manufacturing method |
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