JP2007250998A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

Info

Publication number
JP2007250998A
JP2007250998A JP2006074728A JP2006074728A JP2007250998A JP 2007250998 A JP2007250998 A JP 2007250998A JP 2006074728 A JP2006074728 A JP 2006074728A JP 2006074728 A JP2006074728 A JP 2006074728A JP 2007250998 A JP2007250998 A JP 2007250998A
Authority
JP
Japan
Prior art keywords
semiconductor chip
molded body
resin molded
substrate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2006074728A
Other languages
Japanese (ja)
Inventor
Munehide Nishiomote
宗英 西面
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2006074728A priority Critical patent/JP2007250998A/en
Publication of JP2007250998A publication Critical patent/JP2007250998A/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for preventing the contact of a wiring board and a semiconductor chip and a method for manufacturing it. <P>SOLUTION: The semiconductor chip 20 is provided with an electrode 24 and a bump 26 installed on the electrode 24 and a passivation film 28 constituted of radio materials on a surface on which an integrated circuit 22 is formed. A substrate 10 is provided with a wiring pattern 12, and the semiconductor chip 20 is mounted so that the pump 26 and the pattern 12 can be electrically connected so as to be faced to each other, and any opening is not formed in a region overlapped with the semiconductor chip 20 which is larger than the semiconductor chip 20. A first resin molded body 30 is arranged closer to the outer periphery of the semiconductor chip 20 than an electrode 24 between the passivation film 28 and the substrate 10. A second resin molded body 40 is formed closely to the semiconductor chip 20 and the substrate 10, and its hardness is made different from that of the first resin molded body 30. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

配線基板に半導体チップをフェースダウンボンディングすることが知られている（特許文献１参照）。半導体チップと配線基板の間に樹脂が設けると、樹脂が硬化収縮することで配線基板が反るので、配線基板が半導体チップのエッジに接触することが想定される。この場合、特に、配線が半導体チップに接触するとショートの可能性があるのでその対策が求められていた。
特開２００４−３２７９２０号公報 It is known that a semiconductor chip is face-down bonded to a wiring board (see Patent Document 1). If a resin is provided between the semiconductor chip and the wiring substrate, the wiring substrate is warped due to curing and shrinkage of the resin. In this case, in particular, there is a possibility of a short circuit when the wiring contacts the semiconductor chip, so that countermeasures have been demanded.
JP 2004-327920 A

本発明は、上述したような課題を解決するものであり、その目的は、配線基板と半導体チップとの接触を防止することができる半導体装置及びその製造方法を提供することにある。   The present invention solves the above-described problems, and an object of the present invention is to provide a semiconductor device capable of preventing contact between a wiring board and a semiconductor chip and a method for manufacturing the same.

（１）本発明に係る半導体装置は、
集積回路が形成され、前記集積回路が形成された面に、無機材料からなるパッシベーション膜及び電極並びに前記電極上に設けられたバンプを有する半導体チップと、
配線パターンを有し、前記半導体チップが、前記バンプと前記配線パターンが対向して電気的に接続されるように搭載され、前記半導体チップよりも大きくて前記半導体チップとオーバーラップする領域に開口が形成されない基板と、
前記パッシベーション膜と前記基板との間であって、前記電極よりも前記半導体チップの外縁近くに配置されてなる第１の樹脂成形体と、
前記半導体チップ及び前記基板に密着して設けられた、前記第１の樹脂成形体とは硬さが異なる第２の樹脂成形体と、
を含む。本発明によれば、第２の樹脂成形体が収縮したときに、第１の樹脂成形体によってパッシベーション膜と基板のギャップが確保される。
（２）この半導体装置において、
前記第１の樹脂成形体は、前記電極を囲む領域に、連続的に設けられていてもよい。
（３）この半導体装置において、
前記第１の樹脂成形体は、前記電極を囲む領域に、断続的に設けられていてもよい。
（４）この半導体装置において、
前記第１の樹脂成形体は、前記第２の樹脂成形体よりも柔らかくてもよい。これによれば、第１の樹脂成形体が半導体チップに与える衝撃を小さくすることができる。
（５）この半導体装置において、
前記第１の樹脂成形体は、前記第２の樹脂成形体よりも硬くてもよい。これによれば、パッシベーション膜と基板のギャップを確保する性能が高い。
（６）本発明に係る半導体装置の製造方法は、
集積回路が形成され、前記集積回路が形成された面に、電極及び前記電極上に設けられたバンプ並びに無機材料からなるパッシベーション膜を有する半導体チップと、
配線パターンが形成され、前記半導体チップよりも大きい基板と、
を用意し、
前記パッシベーション膜と前記基板の間に、第１の樹脂成形体及び樹脂前駆体を介在させて、前記半導体チップと前記基板を配置し、前記配線パターンと前記バンプを対向させて電気的に接続し、
前記樹脂前駆体を硬化させて第２の樹脂成形体にすること、
を含み、
前記第１の樹脂成形体を、前記電極よりも前記半導体チップの外縁近くに配置する。本発明によれば、樹脂前駆体が硬化するときに収縮しても、第１の樹脂成形体によってパッシベーション膜と基板のギャップが確保される。
（７）この半導体装置の製造方法において、
前記第１の樹脂成形体を前記半導体チップに設けた後に、前記半導体チップと前記基板の間に前記樹脂前駆体を設けてもよい。 (1) A semiconductor device according to the present invention includes:
A semiconductor chip having an integrated circuit formed on the surface on which the integrated circuit is formed, a passivation film made of an inorganic material and an electrode, and a bump provided on the electrode;
A wiring pattern is provided, and the semiconductor chip is mounted so that the bump and the wiring pattern are electrically connected to face each other, and an opening is formed in a region that is larger than the semiconductor chip and overlaps the semiconductor chip. A substrate that is not formed;
A first resin molded body disposed between the passivation film and the substrate and closer to the outer edge of the semiconductor chip than the electrodes;
A second resin molded body provided in close contact with the semiconductor chip and the substrate and having a hardness different from that of the first resin molded body;
including. According to the present invention, when the second resin molded body contracts, the gap between the passivation film and the substrate is secured by the first resin molded body.
(2) In this semiconductor device,
The first resin molded body may be continuously provided in a region surrounding the electrode.
(3) In this semiconductor device,
The first resin molded body may be provided intermittently in a region surrounding the electrode.
(4) In this semiconductor device,
The first resin molded body may be softer than the second resin molded body. According to this, the impact which the 1st resin molding gives to a semiconductor chip can be made small.
(5) In this semiconductor device,
The first resin molded body may be harder than the second resin molded body. According to this, the performance of ensuring the gap between the passivation film and the substrate is high.
(6) A method for manufacturing a semiconductor device according to the present invention includes:
A semiconductor chip having an integrated circuit formed thereon, a surface on which the integrated circuit is formed, an electrode, a bump provided on the electrode, and a passivation film made of an inorganic material;
A wiring pattern is formed, and a substrate larger than the semiconductor chip;
Prepare
The semiconductor chip and the substrate are disposed with the first resin molding and the resin precursor interposed between the passivation film and the substrate, and the wiring pattern and the bump are opposed to be electrically connected. ,
Curing the resin precursor into a second resin molded body;
Including
The first resin molded body is disposed closer to the outer edge of the semiconductor chip than the electrodes. According to the present invention, even if the resin precursor shrinks when cured, the first resin molded body ensures a gap between the passivation film and the substrate.
(7) In this method of manufacturing a semiconductor device,
After providing the first resin molded body on the semiconductor chip, the resin precursor may be provided between the semiconductor chip and the substrate.

以下に、本発明の実施の形態について図面を参照して説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図１は、本発明の実施の形態に係る半導体装置の一部断面図である。半導体装置は、基板１０を有する。基板１０は、ポリエチレンテレフタレートやポリイミド樹脂などの有機系材料で構成されていてもよいし、無機材料で構成されていてもよいし、これらの複合材料から構成されてもよい。基板１０は、テープであってもよいし、フィルムであってもよいし、フレキシブル基板であってもよい。基板１０には、配線パターン１２が形成されている。配線パターン１２は、導電体又はその積層体から構成され、電子部品間の電気的な接続のために使用される。基板１０は、一方の面のみ配線パターン１２が形成された片面基板であってもよいし、両面に配線パターンが形成された両面基板であってもよい。   FIG. 1 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention. The semiconductor device has a substrate 10. The substrate 10 may be composed of an organic material such as polyethylene terephthalate or polyimide resin, may be composed of an inorganic material, or may be composed of a composite material thereof. The substrate 10 may be a tape, a film, or a flexible substrate. A wiring pattern 12 is formed on the substrate 10. The wiring pattern 12 is composed of a conductor or a laminate thereof, and is used for electrical connection between electronic components. The substrate 10 may be a single-sided substrate in which the wiring pattern 12 is formed on only one surface, or may be a double-sided substrate in which the wiring pattern is formed on both sides.

半導体装置は、半導体チップ２０を有する。半導体チップ２０には、集積回路２２が形成されている。集積回路２２が形成された面（能動面）には、電極２４が形成され、電極２４上にバンプ２６が形成されている。バンプ２６は、アルミニウム又は銅、金等から形成されている。電極２４及びバンプ２６は、集積回路２２と電気的に接続されている。集積回路２２が形成された面には、無機材料（ＳｉＯ２又はＳｉＮ等）からなるパッシベーション膜２８も形成されている。パッシベーション膜２８には、電極２４を露出させる開口が形成されている。 The semiconductor device has a semiconductor chip 20. An integrated circuit 22 is formed on the semiconductor chip 20. An electrode 24 is formed on the surface (active surface) on which the integrated circuit 22 is formed, and a bump 26 is formed on the electrode 24. The bumps 26 are made of aluminum, copper, gold, or the like. The electrode 24 and the bump 26 are electrically connected to the integrated circuit 22. A passivation film 28 made of an inorganic material (SiO 2 or SiN or the like) is also formed on the surface on which the integrated circuit 22 is formed. In the passivation film 28, an opening for exposing the electrode 24 is formed.

半導体チップ２０は、バンプ２６と配線パターン１２が対向して電気的に接続されるように、基板１０に搭載されている。バンプ２６と配線パターン１２は、金属接合されていてもよいし、圧力がかかった状態で接触しているだけでもよいし、両者間に導電粒子が介在してもよいし、両者の共晶合金によって連結されていてもよい。配線パターン１２がバンプ２６にめり込んでいる場合（又はその逆）や、配線パターン１２が基板１０にめり込む場合もある。   The semiconductor chip 20 is mounted on the substrate 10 so that the bumps 26 and the wiring pattern 12 are electrically connected to face each other. The bumps 26 and the wiring pattern 12 may be metal-bonded, or may be in contact with each other under pressure, or conductive particles may be interposed between the two, or a eutectic alloy of both. It may be connected by. The wiring pattern 12 may be embedded in the bump 26 (or vice versa), or the wiring pattern 12 may be embedded in the substrate 10.

基板１０は、半導体チップ２０よりも大きい。詳しくは、半導体チップ２０の全体が基板１０とオーバーラップし、かつ、基板１０は、半導体チップ２０とのオーバーラップ領域１４からのはみ出し部分１６を有する。はみ出し部分１６は、オーバーラップ領域１４を囲むものであってもよいし、オーバーラップ領域１４を囲まないようにこれに隣接していてもよい。基板１０は、オーバーラップ領域１４には開口が形成されないが、はみ出し部分１６に開口が形成されていてもよいし、形成されていなくてもよい。   The substrate 10 is larger than the semiconductor chip 20. Specifically, the entire semiconductor chip 20 overlaps the substrate 10, and the substrate 10 has a protruding portion 16 from the overlap region 14 with the semiconductor chip 20. The protruding portion 16 may surround the overlap region 14 or may be adjacent to the overlap region 14 so as not to surround the overlap region 14. In the substrate 10, no opening is formed in the overlap region 14, but the opening may be formed in the protruding portion 16 or may not be formed.

半導体装置は、第１の樹脂成形体３０を有する。第１の樹脂成形体３０は、基板１０とパッシベーション膜２８の間であって、電極２４よりも半導体チップ２０の外縁近くに配置されている。第１の樹脂成形体３０は、パッシベーション膜２８に接触（密着）しているが、基板１０及び配線パターン１２とは離れていてもよい。図２は、本発明の実施の形態に係る半導体装置の、半導体チップの能動面を示す図である。図２に示す例では、第１の樹脂成形体３０は、電極２４及びバンプ２６を囲む領域に、連続的に設けられている。第１の樹脂成形体３０は、樹脂（ポリイミド、シリコーン変性ポリイミド、エポキシ、シリコーン変性エポキシ、ベンゾシクロブテン（ＢＣＢ；benzocyclobutene）、ポリベンゾオキサゾール（ＰＢＯ；polybenzoxazole）、フェノール等）から形成されている。   The semiconductor device has a first resin molded body 30. The first resin molded body 30 is disposed between the substrate 10 and the passivation film 28 and closer to the outer edge of the semiconductor chip 20 than the electrode 24. The first resin molded body 30 is in contact with (adhered to) the passivation film 28, but may be separated from the substrate 10 and the wiring pattern 12. FIG. 2 is a diagram showing the active surface of the semiconductor chip of the semiconductor device according to the embodiment of the present invention. In the example shown in FIG. 2, the first resin molded body 30 is continuously provided in a region surrounding the electrodes 24 and the bumps 26. The first resin molding 30 is formed of a resin (polyimide, silicone-modified polyimide, epoxy, silicone-modified epoxy, benzocyclobutene (BCB), polybenzoxazole (PBO), phenol, or the like).

図３は、本発明の実施の形態に係る半導体装置の、第１の樹脂成形体の変形例を示す図である。この変形例では、第１の樹脂成形体１３０は、電極２４及びバンプ２６を囲む領域に、断続的に設けられている。それ以外の点は、上述した点が該当する。本発明は、このような例も含む。さらに、図示しない例として、半導体チップ２０の平行な二辺に沿ってのみ第１の樹脂成形体を設けてもよい。例えば、半導体チップ２０が長方形である場合、その短辺に沿ってのみ第１の樹脂成形体を設けてもよいし、その長辺に沿ってのみ第１の樹脂成形体を設けてもよい。   FIG. 3 is a view showing a modification of the first resin molded body of the semiconductor device according to the embodiment of the present invention. In this modification, the first resin molded body 130 is intermittently provided in a region surrounding the electrodes 24 and the bumps 26. The points mentioned above correspond to other points. The present invention includes such an example. Furthermore, as an example not shown, the first resin molded body may be provided only along two parallel sides of the semiconductor chip 20. For example, when the semiconductor chip 20 is rectangular, the first resin molded body may be provided only along the short side, or the first resin molded body may be provided only along the long side.

半導体装置は、第２の樹脂成形体４０を有する。第２の樹脂成形体４０は、基板１０及び半導体チップ２０に密着して設けられている。第２の樹脂成形体４０は、基板１０と半導体チップ２０のギャップに設けられており、両者間の外側に至るようになっている。例えば、第２の樹脂成形体４０にはフィレットが形成されている。詳しくは、第２の樹脂成形体の一部は、基板１０のはみ出し部分１６の上面（半導体チップ２０が搭載される面）から、半導体チップ２０の側面（基板１０の上面から立ち上がる面）に至るように形成されている。第２の樹脂成形体４０は、基板１０及び半導体チップ２０のギャップを埋める封止材であり、両者を接着する接着剤であってもよい。第２の樹脂成形体４０は、第１の樹脂成形体３０とは硬さ（又はヤング率）が異なる。第２の樹脂成形体４０も、樹脂から形成されている。第１及び第２の樹脂成形体３０，４０は、構成物質の含有比率の違いによって硬さが異なっていてもよい。   The semiconductor device has a second resin molded body 40. The second resin molded body 40 is provided in close contact with the substrate 10 and the semiconductor chip 20. The 2nd resin molding 40 is provided in the gap of the board | substrate 10 and the semiconductor chip 20, and reaches the outer side between both. For example, a fillet is formed in the second resin molded body 40. Specifically, a part of the second resin molded body extends from the upper surface of the protruding portion 16 of the substrate 10 (the surface on which the semiconductor chip 20 is mounted) to the side surface of the semiconductor chip 20 (the surface rising from the upper surface of the substrate 10). It is formed as follows. The second resin molded body 40 is a sealing material that fills the gap between the substrate 10 and the semiconductor chip 20, and may be an adhesive that bonds them together. The second resin molded body 40 is different in hardness (or Young's modulus) from the first resin molded body 30. The 2nd resin molding 40 is also formed from resin. The first and second resin moldings 30 and 40 may have different hardnesses depending on the content ratio of the constituent substances.

半導体装置は、第３の樹脂成形体５０を有する。第３の樹脂成形体５０は、基板１０とパッシベーション膜２８の間であって、電極２４よりも半導体チップ２０の中央近くに配置されている。第３の樹脂成形体５０も、樹脂（ポリイミド、シリコーン変性ポリイミド、エポキシ、シリコーン変性エポキシ、ベンゾシクロブテン（ＢＣＢ；benzocyclobutene）、ポリベンゾオキサゾール（ＰＢＯ；polybenzoxazole）、フェノール等）から形成されている。第１及び第３の樹脂成形体３０，５０は、同一の材料から形成されていてもよい。   The semiconductor device has a third resin molded body 50. The third resin molded body 50 is disposed between the substrate 10 and the passivation film 28 and closer to the center of the semiconductor chip 20 than the electrode 24. The third resin molded body 50 is also formed from a resin (polyimide, silicone-modified polyimide, epoxy, silicone-modified epoxy, benzocyclobutene (BCB), polybenzoxazole (PBO), phenol, or the like). The 1st and 3rd resin moldings 30 and 50 may be formed from the same material.

本実施の形態によれば、基板１０が、半導体チップ２０とのオーバーラップ領域１４からのはみ出し部分１６を有する。基板１０には、半導体チップ２０が搭載された面が凹となるように反る力が加えられることがある。例えば、第２の樹脂成形体４０（例えばそのフィレット）が収縮することで、基板１０のはみ出し部分１６を、半導体チップ２０の側面に引き付ける力が加えられる。このとき、第１の樹脂成形体３０によってパッシベーション膜２８と基板１０のギャップが確保される。第１の樹脂成形体３０が第２の樹脂成形体４０よりも柔らかい場合、基板１０から半導体チップ２０（特のそのエッジ）に与える衝撃を吸収して小さくする性能が、第２の樹脂成形体４０よりも高い。第１の樹脂成形体３０が第２の樹脂成形体４０よりも硬い場合、パッシベーション膜２８と基板１０とのギャップを確保する性能が、第２の樹脂成形体４０よりも高い。   According to the present embodiment, the substrate 10 has the protruding portion 16 from the overlap region 14 with the semiconductor chip 20. A warping force may be applied to the substrate 10 so that the surface on which the semiconductor chip 20 is mounted becomes concave. For example, when the second resin molded body 40 (for example, its fillet) contracts, a force that attracts the protruding portion 16 of the substrate 10 to the side surface of the semiconductor chip 20 is applied. At this time, a gap between the passivation film 28 and the substrate 10 is secured by the first resin molding 30. When the first resin molded body 30 is softer than the second resin molded body 40, the second resin molded body is capable of absorbing and reducing the impact applied from the substrate 10 to the semiconductor chip 20 (particularly its edge). Higher than 40. When the first resin molded body 30 is harder than the second resin molded body 40, the performance of securing a gap between the passivation film 28 and the substrate 10 is higher than that of the second resin molded body 40.

次に、本発明に係る半導体装置の製造方法を説明する。本実施の形態では、上述した基板１０及び半導体チップ２０を用意する。また、半導体チップ２０には、上述した第１の樹脂成形体３０を形成しておき、必要であれば、第３の樹脂成形体５０も形成しておく。第１の樹脂成形体３０は、電極２４よりも半導体チップ２０の外縁近くに配置する。また、第１の樹脂成形体３０は、バンプ２６よりも低くなるように形成する。そして、半導体チップ２０を基板１０にフェースダウンボンディングして、配線パターン１２とバンプ２６を対向させて電気的に接続する。   Next, a method for manufacturing a semiconductor device according to the present invention will be described. In the present embodiment, the substrate 10 and the semiconductor chip 20 described above are prepared. In addition, the first resin molded body 30 described above is formed on the semiconductor chip 20, and a third resin molded body 50 is also formed if necessary. The first resin molded body 30 is disposed closer to the outer edge of the semiconductor chip 20 than the electrode 24. Further, the first resin molded body 30 is formed to be lower than the bumps 26. Then, the semiconductor chip 20 is face-down bonded to the substrate 10, and the wiring pattern 12 and the bumps 26 are opposed to each other and electrically connected.

本実施の形態では、パッシベーション膜２８と基板１０の間に、第１の樹脂成形体３０（既に硬化した状態）及び上述した第２の樹脂成形体４０の硬化前の状態である樹脂前駆体を介在させる。例えば、半導体チップ２０を基板１０に搭載してから、そのギャップに樹脂前駆体を注入してもよいし、予め基板１０に樹脂前駆体を設けておいてその上に半導体チップ２０を搭載してもよい。樹脂前駆体は、半導体チップ２０及び基板１０に密着するように配置する。樹脂前駆体は、絶縁性接着剤、絶縁性封止材又は異方性導電材料のいずれであってもよい。樹脂前駆体は、基板１０と半導体チップ２０のギャップから、両者間の外側に至るように設ける。例えば、樹脂前駆体を、フィレットを有するように設ける。その後、樹脂前駆体を硬化（重合又は架橋反応）させて第２の樹脂成形体４０にする。   In the present embodiment, a resin precursor that is in a state before curing of the first resin molded body 30 (already cured) and the second resin molded body 40 described above is provided between the passivation film 28 and the substrate 10. Intervene. For example, after the semiconductor chip 20 is mounted on the substrate 10, a resin precursor may be injected into the gap, or the resin precursor is previously provided on the substrate 10 and the semiconductor chip 20 is mounted thereon. Also good. The resin precursor is disposed so as to be in close contact with the semiconductor chip 20 and the substrate 10. The resin precursor may be any of an insulating adhesive, an insulating sealing material, or an anisotropic conductive material. The resin precursor is provided so as to extend from the gap between the substrate 10 and the semiconductor chip 20 to the outside between the two. For example, the resin precursor is provided so as to have a fillet. Thereafter, the resin precursor is cured (polymerization or crosslinking reaction) to form the second resin molded body 40.

本実施の形態では、基板１０が、半導体チップ２０とのオーバーラップ領域１４からのはみ出し部分１６を有しており、樹脂前駆体が硬化するときに収縮することで、基板１０には、半導体チップ２０が搭載された面が凹となるように反る力が加えられる。しかし、樹脂前駆体が硬化するときに、既に硬化している第１の樹脂成形体３０によってパッシベーション膜２８と基板１０のギャップが確保されるので、基板１０（特に配線パターン１２）と半導体チップ２０（特にそのエッジ）との接触を防止することができる。   In the present embodiment, the substrate 10 has a protruding portion 16 from the overlap region 14 with the semiconductor chip 20, and contracts when the resin precursor is cured, so that the substrate 10 includes the semiconductor chip. A warping force is applied so that the surface on which 20 is mounted becomes concave. However, when the resin precursor is cured, the gap between the passivation film 28 and the substrate 10 is secured by the already cured first resin molding 30, so that the substrate 10 (particularly the wiring pattern 12) and the semiconductor chip 20 are secured. Contact with (especially the edge) can be prevented.

本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び結果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。さらに、本発明は、実施の形態で説明した技術的事項のいずれかを限定的に除外した内容を含む。あるいは、本発明は、上述した実施の形態から公知技術を限定的に除外した内容を含む。   The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment. Furthermore, the present invention includes contents that exclude any of the technical matters described in the embodiments in a limited manner. Or this invention includes the content which excluded the well-known technique limitedly from embodiment mentioned above.

図１は、本発明の実施の形態に係る半導体装置の一部断面図である。FIG. 1 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention. 図２は、本発明の実施の形態に係る半導体装置の、半導体チップの能動面を示す図である。FIG. 2 is a diagram showing the active surface of the semiconductor chip of the semiconductor device according to the embodiment of the present invention. 図３は、本発明の実施の形態に係る半導体装置の、第１の樹脂成形体の変形例を示す図である。FIG. 3 is a view showing a modification of the first resin molded body of the semiconductor device according to the embodiment of the present invention.

符号の説明Explanation of symbols

１０…基板、 １２…配線パターン、 １４…オーバーラップ領域、 １６…はみ出し部分、 ２０…半導体チップ、 ２２…集積回路、 ２４…電極、 ２６…バンプ、 ２８…パッシベーション膜、 ３０…第１の樹脂成形体、 ４０…第２の樹脂成形体、 ５０…第３の樹脂成形体、 １３０…第１の樹脂成形体   DESCRIPTION OF SYMBOLS 10 ... Board | substrate, 12 ... Wiring pattern, 14 ... Overlapping area | region, 16 ... Overhang | projection part, 20 ... Semiconductor chip, 22 ... Integrated circuit, 24 ... Electrode, 26 ... Bump, 28 ... Passivation film, 30 ... 1st resin molding 40, second resin molding, 50 ... third resin molding, 130 ... first resin molding.

Claims (7)

集積回路が形成され、前記集積回路が形成された面に、無機材料からなるパッシベーション膜及び電極並びに前記電極上に設けられたバンプを有する半導体チップと、
配線パターンを有し、前記半導体チップが、前記バンプと前記配線パターンが対向して電気的に接続されるように搭載され、前記半導体チップよりも大きくて前記半導体チップとオーバーラップする領域に開口が形成されない基板と、
前記パッシベーション膜と前記基板との間であって、前記電極よりも前記半導体チップの外縁近くに配置されてなる第１の樹脂成形体と、
前記半導体チップ及び前記基板に密着して設けられた、前記第１の樹脂成形体とは硬さが異なる第２の樹脂成形体と、
を含む半導体装置。 A semiconductor chip having an integrated circuit formed on the surface on which the integrated circuit is formed, a passivation film made of an inorganic material and an electrode, and a bump provided on the electrode;
A wiring pattern is provided, and the semiconductor chip is mounted so that the bump and the wiring pattern are electrically connected to face each other, and an opening is formed in a region that is larger than the semiconductor chip and overlaps the semiconductor chip. A substrate that is not formed;
A first resin molded body disposed between the passivation film and the substrate and closer to the outer edge of the semiconductor chip than the electrodes;
A second resin molded body provided in close contact with the semiconductor chip and the substrate and having a hardness different from that of the first resin molded body;
A semiconductor device including: 請求項１に記載された半導体装置において、
前記第１の樹脂成形体は、前記電極を囲む領域に、連続的に設けられてなる半導体装置。 The semiconductor device according to claim 1,
The first resin molded body is a semiconductor device that is continuously provided in a region surrounding the electrode. 請求項１に記載された半導体装置において、
前記第１の樹脂成形体は、前記電極を囲む領域に、断続的に設けられてなる半導体装置。 The semiconductor device according to claim 1,
The first resin molded body is a semiconductor device provided intermittently in a region surrounding the electrode. 請求項１から３のいずれ１つに記載された半導体装置において、
前記第１の樹脂成形体は、前記第２の樹脂成形体よりも柔らかい半導体装置。 The semiconductor device according to any one of claims 1 to 3,
The first resin molded body is a semiconductor device that is softer than the second resin molded body. 請求項１から３のいずれか１つに記載された半導体装置において、
前記第１の樹脂成形体は、前記第２の樹脂成形体よりも硬い半導体装置。 The semiconductor device according to any one of claims 1 to 3,
The first resin molded body is a semiconductor device that is harder than the second resin molded body. 集積回路が形成され、前記集積回路が形成された面に、電極及び前記電極上に設けられたバンプ並びに無機材料からなるパッシベーション膜を有する半導体チップと、
配線パターンが形成され、前記半導体チップよりも大きい基板と、
を用意し、
前記パッシベーション膜と前記基板の間に、第１の樹脂成形体及び樹脂前駆体を介在させて、前記半導体チップと前記基板を配置し、前記配線パターンと前記バンプを対向させて電気的に接続し、
前記樹脂前駆体を硬化させて第２の樹脂成形体にすること、
を含み、
前記第１の樹脂成形体を、前記電極よりも前記半導体チップの外縁近くに配置する半導体装置の製造方法。 A semiconductor chip having an integrated circuit formed thereon, a surface on which the integrated circuit is formed, an electrode, a bump provided on the electrode, and a passivation film made of an inorganic material;
A wiring pattern is formed, and a substrate larger than the semiconductor chip;
Prepare
The semiconductor chip and the substrate are disposed with the first resin molding and the resin precursor interposed between the passivation film and the substrate, and the wiring pattern and the bump are opposed to be electrically connected. ,
Curing the resin precursor into a second resin molded body;
Including
A method of manufacturing a semiconductor device, wherein the first resin molded body is disposed closer to an outer edge of the semiconductor chip than the electrode. 請求項６に記載された半導体装置の製造方法において、
前記第１の樹脂成形体を前記半導体チップに設けた後に、前記半導体チップと前記基板の間に前記樹脂前駆体を設ける半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 6,
A method for manufacturing a semiconductor device, wherein the resin precursor is provided between the semiconductor chip and the substrate after the first resin molding is provided on the semiconductor chip.
JP2006074728A 2006-03-17 2006-03-17 Semiconductor device and method for manufacturing the same Withdrawn JP2007250998A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006074728A JP2007250998A (en) 2006-03-17 2006-03-17 Semiconductor device and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006074728A JP2007250998A (en) 2006-03-17 2006-03-17 Semiconductor device and method for manufacturing the same

Publications (1)

Publication Number Publication Date
JP2007250998A true JP2007250998A (en) 2007-09-27

Family

ID=38594946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006074728A Withdrawn JP2007250998A (en) 2006-03-17 2006-03-17 Semiconductor device and method for manufacturing the same

Country Status (1)

Country Link
JP (1) JP2007250998A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015140392A1 (en) * 2014-03-21 2015-09-24 Nokia Technologies Oy Flexible electronics apparatus and associated methods
US10321563B2 (en) 2014-08-29 2019-06-11 Nokia Technologies Oy Apparatus and associated methods for deformable electronics
US10393599B2 (en) 2014-10-16 2019-08-27 Nokia Technologies Oy Deformable apparatus and method
US10435289B2 (en) 2014-10-16 2019-10-08 Nokia Technoloiges Oy Deformable apparatus and method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015140392A1 (en) * 2014-03-21 2015-09-24 Nokia Technologies Oy Flexible electronics apparatus and associated methods
US10470304B2 (en) 2014-03-21 2019-11-05 Nokia Technologies Oy Flexible electronics apparatus and associated methods
US10321563B2 (en) 2014-08-29 2019-06-11 Nokia Technologies Oy Apparatus and associated methods for deformable electronics
US10393599B2 (en) 2014-10-16 2019-08-27 Nokia Technologies Oy Deformable apparatus and method
US10435289B2 (en) 2014-10-16 2019-10-08 Nokia Technoloiges Oy Deformable apparatus and method

Similar Documents

Publication Publication Date Title
TW200539359A (en) Semiconductor device and manufacturing method thereof, and liquid crystal module and semiconductor module having the same
US8334602B2 (en) Die package including encapsulated die and method of manufacturing the same
JP5598054B2 (en) Flexible substrate and circuit module including the flexible substrate
US20010031515A1 (en) Semiconductor device and method of manufacturing the same, circuit board and electronic instrument
JP2009033010A (en) Electronic device and method of manufacturing the same, and semiconductor device
JP2007250998A (en) Semiconductor device and method for manufacturing the same
JP3722223B2 (en) Semiconductor device and manufacturing method thereof, electronic module, and electronic apparatus
JP4645832B2 (en) Semiconductor device and manufacturing method thereof
JP2004349399A (en) Component mounting substrate
KR100608610B1 (en) PCB, manufacturing method thereof and semiconductor package using the same
JP2006229018A (en) Tape carrier substrate, its manufacturing method and semiconductor device
JP4052078B2 (en) Semiconductor device
JP5105103B2 (en) Semiconductor device
US8390115B2 (en) Wiring board and semiconductor device using the wiring board
JP2008277954A (en) Package device
JP5556007B2 (en) Electronic equipment
US7592672B2 (en) Grounding structure of semiconductor device including a conductive paste
JP2007067053A (en) Module with built-in component, and manufacturing method thereof
JP4688443B2 (en) Manufacturing method of semiconductor device
JP5146358B2 (en) Electronic equipment
JP2008227241A (en) Electronic device and its manufacturing method
JP2007019410A (en) Semiconductor device, and method of manufacturing electronic module
JP2007227608A (en) Semiconductor device and method of manufacturing semiconductor device
JP4692720B2 (en) Wiring substrate, semiconductor device and manufacturing method thereof
JP4835230B2 (en) Mounting structure of semiconductor device

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20080627

A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20090602