JP2007250675A - Circuit board and semiconductor device - Google Patents

Circuit board and semiconductor device Download PDF

Info

Publication number
JP2007250675A
JP2007250675A JP2006069797A JP2006069797A JP2007250675A JP 2007250675 A JP2007250675 A JP 2007250675A JP 2006069797 A JP2006069797 A JP 2006069797A JP 2006069797 A JP2006069797 A JP 2006069797A JP 2007250675 A JP2007250675 A JP 2007250675A
Authority
JP
Japan
Prior art keywords
circuit board
region
semiconductor element
semiconductor device
back surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006069797A
Other languages
Japanese (ja)
Inventor
Makoto Tsubonoya
誠 坪野谷
Tetsuya Fukushima
哲也 福島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2006069797A priority Critical patent/JP2007250675A/en
Publication of JP2007250675A publication Critical patent/JP2007250675A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board and a semiconductor device for preventing deformation and improving yields. <P>SOLUTION: The semiconductor device has the circuit board 11, where a semiconductor element 12 is mounted on the front and a back surface electrode 114 is formed on the rear, while at least the semiconductor element 12 is not sealed with resin. In the semiconductor device, a solder resist 118 having nearly the same thickness as that of the back surface electrode 114 is formed at a region where the back surface electrode 114 of the circuit board 11 is not formed. When the back surface electrode 114 has been formed near the outer periphery of the circuit board 11, a member is formed at a region surrounded by the back surface electrode 114. The solder resist 118 is formed also for a region sandwiched by the adjacent back surface electrodes 114. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は、回路基板及び半導体装置に関し、とくに回路基板の変形を防ぐための技術に関する。   The present invention relates to a circuit board and a semiconductor device, and more particularly to a technique for preventing deformation of the circuit board.

図７はトランスファモールド方式によって行われる半導体装置の樹脂封止工程の一例である。同図に示されるトランスファモールド装置７０は、半導体装置の製品外形に対応するキャビティ７１を構成する上下金型７２，７３と、エポキシ樹脂等のモールドレジン７４を加圧／溶融するプランジャ７５、モールドレジン７４の流路となるポット７６／ランナー７７／ゲート７８とを有している。   FIG. 7 shows an example of a resin sealing process of a semiconductor device performed by a transfer mold method. A transfer mold apparatus 70 shown in the figure includes upper and lower molds 72 and 73 that constitute a cavity 71 corresponding to the product outer shape of a semiconductor device, a plunger 75 that pressurizes / melts a mold resin 74 such as an epoxy resin, and a mold resin. It has a pot 76 / runner 77 / gate 78 serving as a flow path of 74.

トランスファモールド方式によって行われる樹脂封止に際しては、まずトランスファモールド装置７０のキャビティ７１内に、半導体素子１２の搭載及びワイヤーボンディングが施された回路基板１１を固定する（図７（ａ））。次にプランジャ７５によってポット７６に充填されているモールドレジン７４を加圧／溶融し、溶融状態のモールドレジン７４をキャビティ７１に送り込む（図７（ｂ））。次にモールドレジン７４を所定時間高温（１７０〜１９０℃）に保って硬化させ（図７（ｃ））、モールドレジン７４の硬化後に、金型７２，７３から回路基板１１を取り外す（図７（ｄ））。最後に不要部分が除去されて、樹脂封止が完了する。
特開平８−２５８６０号公報 特開２００４−９６１３４号公報 When resin sealing is performed by the transfer molding method, first, the circuit board 11 on which the semiconductor element 12 is mounted and wire-bonded is fixed in the cavity 71 of the transfer molding apparatus 70 (FIG. 7A). Next, the mold resin 74 filled in the pot 76 is pressurized / melted by the plunger 75, and the molten mold resin 74 is fed into the cavity 71 (FIG. 7B). Next, the mold resin 74 is cured at a high temperature (170 to 190 ° C.) for a predetermined time (FIG. 7C), and after the mold resin 74 is cured, the circuit board 11 is removed from the molds 72 and 73 (FIG. d)). Finally, unnecessary portions are removed, and resin sealing is completed.
JP-A-8-25860 JP 2004-96134 A

上記図７（ｂ）、（ｃ）に示す工程では、キャビティ７１に高圧充填されるモールドレジン７４によって、回路基板１１に高圧（例えば、６〜７ＭＰａ）が印加される。このため、回路基板１１が変形してしまうことがある。   In the steps shown in FIGS. 7B and 7C, a high pressure (for example, 6 to 7 MPa) is applied to the circuit board 11 by the mold resin 74 that is filled in the cavity 71 with a high pressure. For this reason, the circuit board 11 may be deformed.

すなわち、例えば、回路基板１１の裏面の側辺に沿ってのみ裏面電極が形成されている場合には、裏面電極が形成されていない部分と金型の間に空間ができてしまうため、モールドレジン７４から受ける圧力を、裏面電極の部分のみが支持することとなる。このため、例えば、電極が存在しない回路基板１１の中央部分が下に凸となるような形で回路基板１１が変形してしまう。ここでこのような回路基板１１の変形は、半導体装置１の製品外形の平坦性を損ない、製品の機能性や美感性を損なうこととなる。また、回路の断線や接続不良につながるおそれもあり、製造歩留まりにも影響する。   That is, for example, when the back electrode is formed only along the side of the back surface of the circuit board 11, a space is formed between the portion where the back electrode is not formed and the mold. Only the portion of the back electrode supports the pressure received from 74. For this reason, for example, the circuit board 11 is deformed in such a manner that the central portion of the circuit board 11 where no electrode is present protrudes downward. Here, such deformation of the circuit board 11 impairs the flatness of the product outer shape of the semiconductor device 1 and impairs the functionality and aesthetics of the product. In addition, there is a risk of circuit disconnection or connection failure, which affects the manufacturing yield.

本発明は以上のような観点に基づいてなされたもので、回路基板の変形を防ぐことが可能な回路基板及び半導体装置を提供することを目的とする。   The present invention has been made based on the above viewpoint, and an object thereof is to provide a circuit board and a semiconductor device capable of preventing deformation of the circuit board.

上記目的を達成するための本発明のうちの主たる発明は、半導体素子が搭載されてなる回路基板であって、裏面の一部の領域に電極が形成され、裏面の前記裏面電極が形成されていない領域に、前記裏面電極とほぼ同厚の部材が形成されてなることとする。   A main invention of the present invention for achieving the above object is a circuit board on which a semiconductor element is mounted, wherein an electrode is formed in a partial region of the back surface, and the back electrode on the back surface is formed. A member having the same thickness as that of the back electrode is formed in a non-existing region.

このように、回路基板の裏面に、裏面電極と同厚の部材を形成するようにすることで、モールドレジン７４から受ける圧力が部材によっても支持されることとなる。このため、回路基板の変形を防ぐことができる。   Thus, by forming a member having the same thickness as the back electrode on the back surface of the circuit board, the pressure received from the mold resin 74 is also supported by the member. For this reason, deformation of the circuit board can be prevented.

また、本発明の主たる発明の他の一つは、上記回路基板であって、前記裏面電極は、当該回路基板の裏面の外周近傍に形成されており、前記部材が、裏面の前記裏面電極よりも内周側の領域に形成されてなることとする。   Moreover, another one of the main inventions of the present invention is the circuit board, wherein the back electrode is formed in the vicinity of the outer periphery of the back surface of the circuit board, and the member is formed from the back electrode on the back surface. Is also formed in the inner peripheral region.

裏面電極が回路基板の外周近傍に形成された回路基板の場合には、例えば、このように裏面電極によって囲まれる裏面電極よりも内周側の領域に部材を形成するようにする。このような部分に部材を形成することで、モールドレジンから受ける圧力を部材によって確実に支持することができる。またモールドレジンから受ける圧力が分散され、回路基板が変形してしまうのを防ぐことができる。また裏面電極の部分にかかる圧力が緩和され、断線や接続不良を防ぐことができる。   In the case of a circuit board in which the back electrode is formed in the vicinity of the outer periphery of the circuit board, for example, the member is formed in a region on the inner peripheral side of the back electrode surrounded by the back electrode in this way. By forming the member in such a portion, the pressure received from the mold resin can be reliably supported by the member. Further, the pressure received from the mold resin is dispersed, and the circuit board can be prevented from being deformed. Further, the pressure applied to the back electrode portion is relieved, and disconnection and poor connection can be prevented.

また、本発明のうちの他の一つは、上記回路基板であって、複数の前記裏面電極が当該回路基板の裏面の外周に沿って形成されており、前記部材が、隣接する前記裏面電極に挟まれる領域にも形成されてなることとする。   Another aspect of the present invention is the circuit board, wherein the plurality of back electrodes are formed along the outer periphery of the back surface of the circuit board, and the members are adjacent to the back electrodes. It is also formed in a region sandwiched between the two.

このように、回路基板の裏面の外周に沿って複数の裏面電極が形成されている場合には、裏面電極よりも内側の領域だけでなく、隣接する裏面電極に挟まれる領域にも形成するようにする。そしてこのようにすることで、モールドレジン７４からの圧力を広域に分散させることができ、回路基板の変形や断線等も確実に防ぐことができる。   In this way, when a plurality of back electrodes are formed along the outer periphery of the back surface of the circuit board, they are formed not only in the area inside the back electrode but also in the area sandwiched between the adjacent back electrodes. To. And by doing in this way, the pressure from the mold resin 74 can be disperse | distributed to wide area, and a deformation | transformation, a disconnection, etc. of a circuit board can be prevented reliably.

なお、上記部材は、例えば、ソルダーレジストや銅箔などの導電体である。これらによって部材を形成することで、ソルダーレジストや配線パターンの形成工程において、これらと一緒に上記部材を形成できるので、上記部材を容易に形成することができる。   In addition, the said member is conductors, such as a soldering resist and copper foil, for example. By forming a member by these, since the said member can be formed together with these in the formation process of a soldering resist or a wiring pattern, the said member can be formed easily.

本発明によれば、回路基板の変形を防ぐことができる。   According to the present invention, deformation of the circuit board can be prevented.

以下、本発明の一実施形態につき詳細に説明する。図１Ａ乃至図１Ｃに本発明の一実施形態として説明する半導体装置１の構成を示している。図１Ａは、半導体装置１の表面側斜視図であり、図１Ｂは、半導体装置１を下面側斜視図である。図１Ｃは、半導体装置１の側面図である。図１Ｄは、図１ＡのＸ−Ｘ’線における半導体装置１の断面図である。これらの図に示すように、半導体装置１は略正方形状の扁平な回路基板１１と、回路基板１１の表面２に搭載される電子デバイスである扁平直方体状の半導体素子１２（ベアチップ）とを含んで構成されている。   Hereinafter, one embodiment of the present invention will be described in detail. 1A to 1C show a configuration of a semiconductor device 1 described as an embodiment of the present invention. 1A is a front perspective view of the semiconductor device 1, and FIG. 1B is a bottom perspective view of the semiconductor device 1. FIG. FIG. 1C is a side view of the semiconductor device 1. FIG. 1D is a cross-sectional view of the semiconductor device 1 taken along line X-X ′ of FIG. 1A. As shown in these drawings, the semiconductor device 1 includes a flat circuit board 11 having a substantially square shape, and a flat rectangular semiconductor element 12 (bare chip) which is an electronic device mounted on the surface 2 of the circuit board 11. It consists of

半導体素子１２が搭載される回路基板１１は、エポキシやポリエステル、ポリイミド等の樹脂を素材とするリジッド配線基板又はフレキシブル基板（ＦＰＣ）等の有機基板である。なお、本発明は回路基板１１がセラミック配線基板、金属配線基板、又はＳｉからなる実装基板などの無機基板である場合にも適用することができる。また本実施形態で説明する回路基板１１は単層構造であるものとするが、回路基板１１は多層構造であってもよい。上記Ｓｉからなる実装基板は、例えば、フレキシブル基板の樹脂の代わりにＳｉを採用するもので、半導体素子１２と熱膨張係数が一致し、熱応力が少ないものである。   The circuit board 11 on which the semiconductor element 12 is mounted is an organic board such as a rigid wiring board or a flexible board (FPC) made of a resin such as epoxy, polyester, or polyimide. The present invention can also be applied when the circuit board 11 is an inorganic substrate such as a ceramic wiring substrate, a metal wiring substrate, or a mounting substrate made of Si. The circuit board 11 described in the present embodiment is assumed to have a single layer structure, but the circuit board 11 may have a multilayer structure. The mounting substrate made of Si employs, for example, Si instead of the resin of the flexible substrate, and has the same thermal expansion coefficient as that of the semiconductor element 12 and has a low thermal stress.

回路基板１１の表面２には、回路基板１１の端面１１２に沿って複数のボンディングパッド１１１が形成されている。ボンディングパッド１１１は、例えば、下層から順にＮｉ／Ａｕ等の導体を無電解メッキ又は電解メッキすることにより形成されている。   A plurality of bonding pads 111 are formed along the end surface 112 of the circuit board 11 on the surface 2 of the circuit board 11. The bonding pad 111 is formed by, for example, electroless plating or electrolytic plating of a conductor such as Ni / Au in order from the lower layer.

回路基板１１の端面１１２には、この端面１１２側に開口する複数の貫通孔１１３（Via Hall）が形成されている。図２Ａに貫通孔１１３の周辺部分の拡大斜視図を示している。同図に示すように、貫通孔１１３の回路基板１１に平行な断面は、回路基板１１の端面１１２から所定長さの直線部分を有する略半円状（長孔状）である。貫通孔１１３の内側面には、下層から順にＮｉ／Ａｕ等の導電体によるメッキが施され、これによりボンディングパッド１１１は、回路基板１１の裏面３に形成された裏面電極１１４に電気的に接続されている。   A plurality of through holes 113 (Via Hall) are formed in the end surface 112 of the circuit board 11 so as to open to the end surface 112 side. FIG. 2A shows an enlarged perspective view of the peripheral portion of the through hole 113. As shown in the figure, the cross section of the through hole 113 parallel to the circuit board 11 is substantially semicircular (long hole shape) having a straight portion of a predetermined length from the end surface 112 of the circuit board 11. The inner surface of the through-hole 113 is plated with a conductor such as Ni / Au in order from the lower layer, whereby the bonding pad 111 is electrically connected to the back electrode 114 formed on the back surface 3 of the circuit board 11. Has been.

図１Ｂ乃至図１Ｄ、及び図３Ｂに示すように、回路基板１１の裏面３には、裏面電極１１４とほぼ同厚のソルダーレジスト１１８（部材）が、いずれの裏面電極１１４にも重ならないように、裏面電極１１４よりも内周側の正方形状の領域に形成されている。   As shown in FIG. 1B to FIG. 1D and FIG. 3B, the solder resist 118 (member) having substantially the same thickness as the back electrode 114 does not overlap any back electrode 114 on the back surface 3 of the circuit board 11. Further, it is formed in a square area on the inner peripheral side with respect to the back electrode 114.

ここでソルダーレジスト１１８は、半導体装置１の樹脂封止工程において回路基板１１の表面側から圧力が印加された場合に回路基板１１がその中央部分が下に凸となるように変形してしまうのを防ぐ役目を果たす。   Here, when a pressure is applied from the surface side of the circuit board 11 in the resin sealing process of the semiconductor device 1, the solder resist 118 is deformed so that the center part thereof is convex downward. Play a role in preventing.

すなわち、このような領域にソルダーレジスト１１８を形成しておくことで、トランスファモールド方式による樹脂封止に際し、モールドレジン（樹脂）から受ける圧力がソルダーレジスト１１８の部分によっても支持されることとなる。このため、モールドレジンから受ける圧力によって、回路基板１１が下に凸となるように変形してしまうのを防ぐことができる。また裏面電極１１４にかかる圧力が緩和されるため、断線や接続不良を防ぐことができる。   That is, by forming the solder resist 118 in such a region, the pressure received from the mold resin (resin) during the resin sealing by the transfer molding method is also supported by the solder resist 118 portion. For this reason, it can prevent that the circuit board 11 deform | transforms so that it may become convex by the pressure received from a mold resin. In addition, since the pressure applied to the back electrode 114 is relieved, disconnection and poor connection can be prevented.

ソルダーレジスト１１８の素材は、例えば、エポキシ樹脂であり、例えば、整面工程や印刷工程（印刷、露光、現像）を経ることによって形成することができる。すなわち、ソルダーレジスト１１８は、一般的なソルダーレジストの形成工程において形成することができる。またソルダーレジスト１１８に代えて、銅箔などの導電体を形成するようにしてもよい。この場合には回路基板１１に設けられる配線パターンの形成工程において同時に形成することができる。   The material of the solder resist 118 is, for example, an epoxy resin, and can be formed, for example, through a surface conditioning process or a printing process (printing, exposure, development). That is, the solder resist 118 can be formed in a general solder resist forming process. Further, instead of the solder resist 118, a conductor such as a copper foil may be formed. In this case, it can be formed simultaneously in the process of forming the wiring pattern provided on the circuit board 11.

図３Ａに回路基板１１の平面図を示している。同図に示すように、回路基板１１の表面２の中央の領域には、回路基板１１に搭載される半導体素子１２の平面形状に合わせた形状の素子搭載領域１１５が設けられている。なお、素子搭載領域１１５は必ず設けられるわけではなく、半田による接続に代えて半導体素子１２の搭載領域に接着剤が塗布されることもある。また素子搭載領域１１５に代えて、導体による配線パターンが形成されることもある。   FIG. 3A shows a plan view of the circuit board 11. As shown in the figure, an element mounting area 115 having a shape matching the planar shape of the semiconductor element 12 mounted on the circuit board 11 is provided in the central area of the surface 2 of the circuit board 11. Note that the element mounting region 115 is not necessarily provided, and an adhesive may be applied to the mounting region of the semiconductor element 12 instead of the connection by solder. In addition, instead of the element mounting region 115, a conductor wiring pattern may be formed.

ボンディングパッド１１１は、素子搭載領域１１５の周囲に設けられている。また、同図に示すように、ボンディングパッド１１１は、回路基板１１の端面１１２とその面を一致させるとともに回路基板１１の表面２の貫通孔１１３が形成されている部分を塞ぐように形成された第１の領域１１１１と、回路基板１１の端面１１２と一致することなく半導体素子１２の縁に沿って延出して形成され、第１の領域１１１１に連続する第２の領域１１１２とを有している。   The bonding pad 111 is provided around the element mounting region 115. Further, as shown in the figure, the bonding pad 111 is formed so that the end surface 112 of the circuit board 11 and the surface thereof coincide with each other and the portion of the surface 2 of the circuit board 11 where the through hole 113 is formed is blocked. The first region 1111 has a second region 1112 that extends along the edge of the semiconductor element 12 and does not coincide with the end surface 112 of the circuit board 11 and continues to the first region 1111. Yes.

図３Ａにおいて、ボンディングパッド１１１の部分に表記されている破線は、第１の領域１１１１と第２の領域１１１２との境界を表している。第２の領域１１１２は、必要本数のボンディングワイヤー２０を接合可能な形状及び面積に設定されている。ボンディングパッド１１１は、以上の構成によってその全体が略Ｌ字状を呈している。なお、図３Ａに示すボンディングパッド１１１の形態は一例に過ぎず、第１の領域１１１１や第２の領域１１１２の形状や大きさは、同図に示したものに限られない。   In FIG. 3A, a broken line written in the bonding pad 111 represents a boundary between the first region 1111 and the second region 1112. The second region 1112 is set to have a shape and an area capable of bonding the required number of bonding wires 20. The bonding pad 111 as a whole has a substantially L shape with the above configuration. Note that the form of the bonding pad 111 illustrated in FIG. 3A is merely an example, and the shape and size of the first region 1111 and the second region 1112 are not limited to those illustrated in FIG.

ここでボンディングパッド１１１の端面が回路基板１１の端面１１２と一致していると、ダイシング時の外力等によりボンディングパッド１１１が剥がれ易くなり、また回路基板１１のダイシング時にボンディングワイヤー２０が切断されてしまう可能性がある。しかしながら本実施形態の半導体装置１では、上記のようにボンディングパッド１１１の端面１１２に接する部分を第１の領域１１１１のみとし、ボンディングパッド１１１の端面１１２に露出する部分が少ないので、ボンディングパッド１１１の剥がれやボンディングワイヤー２０の切断等を防ぐことができる。具体的に説明すると、図３Ａに示すＬ字のボンディングパッド１１１は６つの側辺を有しているが、このうち半導体素子１２の外周側辺と平行で、回路基板１１の最も外周側に設けられている側辺が、半導体素子１２側に面するとともに半導体素子１２の外周側辺と平行に設けられている側辺の長に渡って設けられていない事が重要であり、これにより剥がれが生じやすいボンディングパッド１１の回路基板１１の端面に露出する部分が減って、ボンディングパッド１１１の剥がれやボンディングワイヤー２０の切断等を防ぐことができる。回路基板１１の表面２の角隅部にはインデックスマーク１１６が設けられている。   Here, if the end surface of the bonding pad 111 coincides with the end surface 112 of the circuit board 11, the bonding pad 111 is easily peeled off due to an external force or the like during dicing, and the bonding wire 20 is cut during dicing of the circuit board 11. there is a possibility. However, in the semiconductor device 1 of the present embodiment, the portion in contact with the end surface 112 of the bonding pad 111 is only the first region 1111 as described above, and the portion exposed to the end surface 112 of the bonding pad 111 is small. Peeling, cutting of the bonding wire 20 and the like can be prevented. More specifically, the L-shaped bonding pad 111 shown in FIG. 3A has six sides. Among these, the L-shaped bonding pad 111 is provided on the outermost side of the circuit board 11 in parallel with the outer side of the semiconductor element 12. It is important that the provided side is not provided over the length of the side that faces the semiconductor element 12 and is provided in parallel with the outer peripheral side of the semiconductor element 12. The portion of the bonding pad 11 that is likely to be exposed is less exposed on the end face of the circuit board 11, and peeling of the bonding pad 111 and cutting of the bonding wire 20 can be prevented. Index marks 116 are provided at corners of the surface 2 of the circuit board 11.

ボンディングワイヤー２０は、第２の領域１１１２に接合される。すなわち、貫通孔１１３の穿孔状態によっては、第１の領域１１１１にボンディングワイヤー２０を接合するための領域を確保することができないことがあるが、第２の領域１１１２を設けていることでボンディングワイヤーを接合するための領域が確実に確保される。また第２の領域１１１２にボンディングワイヤー２０を接合することで、表面の凹凸の影響などにより接合強度を充分確保できない可能性のある貫通孔１１３の直上にボンディングワイヤー２０を接合する必要がなく、ボンディングワイヤー２０をボンディングパッド１１１に確実に接合することができる。なお、別言すれば、第２の領域１１１２は、これに対応する電極パッド１２１とずれた位置に形成されており、ボンディングワイヤー２０が半導体素子１２の側辺に対して斜めに交叉する位置に形成されている。   The bonding wire 20 is bonded to the second region 1112. That is, depending on the perforated state of the through hole 113, there may be a case where a region for bonding the bonding wire 20 cannot be secured in the first region 1111, but the bonding wire is provided by providing the second region 1112. A region for joining the members is ensured. Further, by bonding the bonding wire 20 to the second region 1112, it is not necessary to bond the bonding wire 20 directly above the through hole 113, which may not be able to ensure sufficient bonding strength due to the influence of surface irregularities. The wire 20 can be reliably bonded to the bonding pad 111. In other words, the second region 1112 is formed at a position shifted from the corresponding electrode pad 121, and at a position where the bonding wire 20 obliquely crosses the side of the semiconductor element 12. Is formed.

図３Ｂに回路基板１１の裏面図を示している。回路基板１１の下面３の、ボンディングパッド１１１の第１の領域１１１１に対向する位置には、一部に切り欠きを有する略長方形状の複数の裏面電極１１４が設けられている。   FIG. 3B shows a back view of the circuit board 11. On the lower surface 3 of the circuit board 11, a plurality of substantially rectangular back electrodes 114 each having a notch are provided at positions facing the first region 1111 of the bonding pad 111.

なお、ソルダーレジストの形態は、図３Ｂに示すものに限られず、例えば、図３Ｃに示すように、隣接する裏面電極１１４の間の領域についてもソルダーレジスト１１８を形成するようにしてもよい。ソルダーレジスト１１８をこのような領域にも形成しておくことで、モールドレジンから受ける圧力をより一層分散させることができ、回路基板１１の変形をより確実に防ぐことができる。また裏面電極１１４にかかる圧力がさらに緩和されることとなるため、断線や接続不良をより確実に防ぐことができる。   The form of the solder resist is not limited to that shown in FIG. 3B. For example, as shown in FIG. 3C, the solder resist 118 may be formed also in the region between the adjacent back surface electrodes 114. By forming the solder resist 118 also in such a region, the pressure received from the mold resin can be further dispersed, and the deformation of the circuit board 11 can be prevented more reliably. In addition, since the pressure applied to the back electrode 114 is further relaxed, disconnection and poor connection can be prevented more reliably.

以上に説明した構成によって、回路基板１１の端面には、ボンディングパッド１１１の第１の領域１１１１の断面、貫通孔１１３の内側面の断面、及び裏面電極１１４の断面が露出する。   With the configuration described above, the cross section of the first region 1111 of the bonding pad 111, the cross section of the inner surface of the through hole 113, and the cross section of the back electrode 114 are exposed on the end surface of the circuit board 11.

ところで、回路基板１１は、例えば、複数の回路基板１１が形成された集合基板１１０から切り出されたものである。この場合の集合基板１１０の平面図を図４Ａに示している。同図に示すように、この例では隣接する位置に形成された回路基板１１のボンディングパッド１１１が連続して形成されている。また図４Ｂは、集合基板１１０の裏面図であるが、同図に示すように、隣接する位置に形成された回路基板１１の裏面電極１１４は連続している。このように、集合基板１１０の状態で隣接するボンディングパッド１１１や裏面電極１１４を連続して形成することで、回路パターンが簡素化され、パターン形成や貫通孔１１３の穿孔にかかる工数を減らすことができる。   By the way, the circuit board 11 is cut out from, for example, the collective board 110 on which the plurality of circuit boards 11 are formed. A plan view of the collective substrate 110 in this case is shown in FIG. 4A. As shown in the figure, in this example, the bonding pads 111 of the circuit board 11 formed at adjacent positions are continuously formed. FIG. 4B is a back view of the collective substrate 110. As shown in FIG. 4B, the back electrodes 114 of the circuit board 11 formed at adjacent positions are continuous. As described above, by continuously forming the bonding pads 111 and the back electrode 114 adjacent to each other in the state of the collective substrate 110, the circuit pattern is simplified, and the number of steps for pattern formation and drilling of the through holes 113 can be reduced. it can.

一方、集合基板１１０自体は、例えば、複数の集合基板１１０が形成された連続回路基板１２０から切り出されたものである。図５に連続回路基板１２０の一例（平面図）を示している。連続回路基板１２０は、例えば、基板樹脂の片面又は両面に銅（Ｃｕ）箔（Resin Coated Copper Foil）をラミネートするラミネート工程、貫通孔１１３が形成される部分のフォトエッチング工程、レーザー光照射等による孔あけ工程、レーザー光照射やプラズマ等のドライデスミア処理あるいは化学的処理によるウェットデスミア処理による樹脂残渣工程、表面に銅（Ｃｕ）メッキ（無電解／電解）等の処理を行う導体層形成工程、フォトエッチングによりパターニングすることにより回路を形成する回路形成工程などの、各種の工程を経ることにより製造される。   On the other hand, the collective substrate 110 itself is, for example, cut out from the continuous circuit substrate 120 on which a plurality of collective substrates 110 are formed. FIG. 5 shows an example (plan view) of the continuous circuit board 120. The continuous circuit board 120 is formed by, for example, a laminating process of laminating copper (Cu) foil (Resin Coated Copper Foil) on one or both sides of a substrate resin, a photo-etching process of a portion where the through hole 113 is formed, laser light irradiation, or the like. A conductor layer forming step for performing a drilling step, a resin residue step by dry desmear treatment such as laser light irradiation or plasma or wet desmear treatment by chemical treatment, copper (Cu) plating (electroless / electrolysis) on the surface, It is manufactured through various processes such as a circuit forming process for forming a circuit by patterning by photoetching.

一方、半導体素子１２の典型例は、半導体基板に、熱酸化法やＣＶＤ（Chemical Vapor Deposition）、スパッタ、リソグラフィ、不純物拡散等の各種前工程を行うことにより製造されたＣＭＯＳ（Complementary Metal Oxide Semiconductor）である。しかしながら、ＣＭＯＳに限らず、半導体素子１２は、例えば、バイＣＭＯＳ、ＭＯＳ、リニア（バイポーラ）ＩＣ等の他の集積回路であってもよい。また半導体素子１２はトランジスタ、ダイオードなどのディスクリートな素子であってもよい。   On the other hand, a typical example of the semiconductor element 12 is a CMOS (Complementary Metal Oxide Semiconductor) manufactured by performing various pre-processes such as thermal oxidation, CVD (Chemical Vapor Deposition), sputtering, lithography, and impurity diffusion on a semiconductor substrate. It is. However, the semiconductor element 12 is not limited to the CMOS, and may be another integrated circuit such as a bi-CMOS, MOS, or linear (bipolar) IC. The semiconductor element 12 may be a discrete element such as a transistor or a diode.

半導体素子１２の上面には、その周辺縁部に沿って所定形状の複数の電極パッド１２１が形成されている。各電極パッド１２１は、各電極パッド１２１に近接する位置に形成されているボンディングパッド１１１と、Ａｕ／Ａｌなどの導体線を用いたワイヤーボンディングによって接続されている。なお、ワイヤーボンディングの方法としては、ボールボンディング（Ball Bonding）や超音波接合法などが用いられる。   A plurality of electrode pads 121 having a predetermined shape are formed on the upper surface of the semiconductor element 12 along the peripheral edge. Each electrode pad 121 is connected to a bonding pad 111 formed at a position close to each electrode pad 121 by wire bonding using a conductor wire such as Au / Al. As a wire bonding method, ball bonding or ultrasonic bonding is used.

ところで、配線されたボンディングワイヤー２０の曲率が大きいと、ボンディングワイヤー２０の不良が生じ易くなる。そこで本実施形態の半導体装置１では、ボンディングパッド１１１の領域のうち電極パッド１２１の直近ではなく、ボンディングワイヤー２０を電極パッド１２１の直近から斜めにずれた位置にある第２の領域１１１２に接合するようにしている。これによりボンディングワイヤー２０の曲率の増大を緩和してボンディングワイヤー２０の過剰変形を防ぐことができる。そしてこのことにより本実施形態の半導体装置１は、回路基板１１のサイズにより近いサイズの半導体素子１２をボンディングワイヤー２０の曲率を増大させることなく搭載することが可能となる。   By the way, if the curvature of the wired bonding wire 20 is large, the bonding wire 20 is likely to be defective. Therefore, in the semiconductor device 1 of the present embodiment, the bonding wire 20 is bonded to the second region 1112 which is not in the immediate vicinity of the electrode pad 121 in the bonding pad 111 region but is obliquely shifted from the immediate vicinity of the electrode pad 121. I am doing so. As a result, an increase in the curvature of the bonding wire 20 can be mitigated and excessive deformation of the bonding wire 20 can be prevented. As a result, the semiconductor device 1 according to the present embodiment can mount the semiconductor element 12 having a size closer to the size of the circuit board 11 without increasing the curvature of the bonding wire 20.

半導体素子１２をＤＡＦ１３によって素子搭載領域１１５に接合する場合、ＤＡＦ１３としては、例えば、耐熱性及び接着強度を得るための熱硬化性樹脂としてエポキシ樹脂を７０〜８０％、保持力向上及びテープ製造の適正化を図るためのバインダー樹脂としてアクリルポリマーを１０〜１５％、ピックアップ性及びダイシング性を向上させるためのＵＶ硬化型樹脂としてアクリル樹脂を１０〜１５％を含む組成ものを用いる。   When the semiconductor element 12 is joined to the element mounting region 115 by the DAF 13, for example, the DAF 13 is 70 to 80% of an epoxy resin as a thermosetting resin for obtaining heat resistance and adhesive strength. A composition containing 10 to 15% of an acrylic polymer as a binder resin for optimization and a composition containing 10 to 15% of an acrylic resin as a UV curable resin for improving pickup property and dicing property is used.

なお、半導体素子１２をＤＡＦ１３により素子搭載領域１１５に接合するようにした場合、半導体素子１２を回路基板１１に押圧した際に半導体素子１２の周囲に接着剤が流出するようなことが無く、ボンディングパッド１１１の汚染、ボンディングワイヤー２０の接合不良、ボンディングパッド間のショートといった前述の問題を生じない。また回路基板１１表面の状態は個体ごとに異なるため、液状（ペースト状）の接着剤を用いた場合には、接着剤の量のコントロールが難しいが、ＤＡＦ１３ではそのような問題も生じない。さらに、ＤＡＦ１３の厚みは通常は高精度で一定であるため、回路基板１１に接合された半導体素子１２に殆ど傾きが無く、各電極パッド１２１と各電極パッド１２１が接続されるボンディングパッド１１１との間の距離の精度が確保され、ワイヤーボンディングによる製品間のばらつきが抑えられる。   When the semiconductor element 12 is bonded to the element mounting region 115 by the DAF 13, the adhesive does not flow out around the semiconductor element 12 when the semiconductor element 12 is pressed against the circuit board 11. The above-described problems such as contamination of the pad 111, bonding failure of the bonding wire 20, and short-circuit between bonding pads do not occur. Further, since the state of the surface of the circuit board 11 varies from individual to individual, it is difficult to control the amount of the adhesive when a liquid (paste-like) adhesive is used, but the DAF 13 does not cause such a problem. Furthermore, since the thickness of the DAF 13 is usually highly accurate and constant, the semiconductor element 12 bonded to the circuit board 11 has almost no inclination, and each electrode pad 121 and the bonding pad 111 to which each electrode pad 121 is connected are connected. The accuracy of the distance between them is ensured, and variation between products due to wire bonding is suppressed.

ＤＡＦ１３によって半導体素子１２を回路基板１１に接合する工程の一例を図６に示している。同図における（ａ）に示す工程では、ＤＡＦ１３（２０μｍ）を、複数の半導体素子１２が形成されたダイシング前の半導体基板１５の裏面に透明な基材１６（１００μｍ）とともに貼付している（貼付工程）。続く（ｂ）に示す工程では、ＤＡＦ１３にＵＶ照射を行って、ＤＡＦ１３の弾性率を向上させ、回路基板１１への接着性を向上させている。（ｃ）に示す工程では、ＤＡＦ１３及び基材１６とともに半導体基板１５をダイシングしている。なお、ＤＡＦ１３層が完全に切断されるようにするため、ダイシングはフルカットダイシングで行う。またピックアップ時にＤＡＦ１３を基材１６から剥がしやすくするためにダイシング深度は基材１６が２０〜３０μｍ切り込まれる程度としている。（ｄ）に示す工程では、ダイシング後の半導体素子１２をＤＡＦ１３ごと基材１６からピックアップし、例えば１２０℃に加温した回路基板１１上の素子搭載領域１１５に仮マウントしている。（ｅ）に示す工程では、半導体素子１２が仮マウントされた回路基板１１を例えば１６０℃に昇温（キュア処理）し、半導体素子１２を回路基板１１に接合している。   An example of the process of bonding the semiconductor element 12 to the circuit board 11 by the DAF 13 is shown in FIG. In the step shown in FIG. 5A, DAF 13 (20 μm) is pasted together with a transparent base material 16 (100 μm) on the back surface of the semiconductor substrate 15 before dicing on which a plurality of semiconductor elements 12 are formed (pasting). Process). In the subsequent step (b), the DAF 13 is irradiated with UV to improve the elastic modulus of the DAF 13 and improve the adhesion to the circuit board 11. In the step shown in (c), the semiconductor substrate 15 is diced together with the DAF 13 and the base material 16. Note that dicing is performed by full-cut dicing so that the DAF 13 layer is completely cut. Further, the dicing depth is set such that the base material 16 is cut by 20 to 30 μm so that the DAF 13 can be easily peeled off from the base material 16 during pick-up. In the step shown in (d), the semiconductor element 12 after dicing is picked up together with the DAF 13 from the base material 16 and temporarily mounted on the element mounting region 115 on the circuit board 11 heated to 120 ° C., for example. In step (e), the circuit board 11 on which the semiconductor element 12 is temporarily mounted is heated (cured) to, for example, 160 ° C., and the semiconductor element 12 is bonded to the circuit board 11.

一方、半導体素子１２を接着剤によって素子搭載領域１１５に接合する場合には、半導体素子１２の素子搭載領域１１５への搭載は、例えば、導電性エポキシ樹脂や銀ペースト樹脂などからなる接着剤をシリンジのシャワーノズルからスポット状にディスペンス塗布し、次に半導体素子１２を搭載してスクラブすることにより接着剤を均一に広げ、その後、接着剤を加熱硬化する、といった工程により行われる。   On the other hand, when the semiconductor element 12 is bonded to the element mounting region 115 with an adhesive, the semiconductor element 12 is mounted on the element mounting region 115 by using, for example, an adhesive made of conductive epoxy resin or silver paste resin as a syringe. The adhesive is spread uniformly by spot coating from the shower nozzle, and then scrubbing with the semiconductor element 12 mounted thereon, and then the adhesive is heated and cured.

なお、以上の工程を経て製造された回路基板１１、半導体素子１２、及びボンディングワイヤー２０の全体は、絶縁性樹脂の被覆工程を経て、エポキシ樹脂等の熱硬化性樹脂、又はポリイミド樹脂やポリフェニレンサルファイド等の熱可塑性樹脂によって樹脂封入される。樹脂封入は、例えば、トランスファモールド法やインジェクションモールド法等の金型モールド法、ポッティング法、シート接着法などによって行われる。なお、一般にはこのように樹脂封入が行われるが、樹脂封入は必ずしも行わなくてもよい。   The entire circuit board 11, semiconductor element 12, and bonding wire 20 manufactured through the above steps are subjected to an insulating resin coating step, and then a thermosetting resin such as epoxy resin, polyimide resin, or polyphenylene sulfide. The resin is encapsulated with a thermoplastic resin. The resin encapsulation is performed by, for example, a mold molding method such as a transfer molding method or an injection molding method, a potting method, a sheet bonding method, or the like. In general, resin encapsulation is performed in this manner, but resin encapsulation is not necessarily performed.

ところで、以上の実施形態の説明は、本発明の理解を容易にするためのものであり、本発明を限定するものではない。本発明はその趣旨を逸脱することなく、変更、改良され得ると共に本発明にはその等価物が含まれることは勿論である。   By the way, description of the above embodiment is for making an understanding of this invention easy, and does not limit this invention. It goes without saying that the present invention can be changed and improved without departing from the gist thereof, and that the present invention includes equivalents thereof.

例えば、回路基板１１の形状は、上述したものに限られず、ボンディングパッド１１１の第１の領域１１１１と第２の領域１１１２とが連続する部分に、図１Ａの破線円Ｃ１に示すように、第１の領域１１１１及び第２の領域１１１２の幅よりも細幅の括れを形成するようにしてもよい。このようにすることで、ボンディングパッド１１１とボンディングワイヤー２０を経路とする外部から半導体素子１２への水分の浸入を防ぐことができる。   For example, the shape of the circuit board 11 is not limited to the above-described one, and the first region 1111 and the second region 1112 of the bonding pad 111 are continuous with each other as shown by a broken line circle C1 in FIG. A narrower width than the width of the first region 1111 and the second region 1112 may be formed. By doing so, it is possible to prevent moisture from entering the semiconductor element 12 from the outside through the bonding pad 111 and the bonding wire 20.

また以上の実施形態では、ボンディングパッド１１１の第１の領域１１１１が回路基板１１の端面１１２に接していたが、例えば、図１Ａの破線円Ｃ２に示すように、第１の領域１１１１は必ずしも回路基板１１の端面１１２に接していなくてもよい。   In the above embodiment, the first region 1111 of the bonding pad 111 is in contact with the end face 112 of the circuit board 11. However, for example, the first region 1111 is not necessarily a circuit as shown by a dashed circle C2 in FIG. 1A. It does not have to be in contact with the end surface 112 of the substrate 11.

また半導体素子１２の回路基板１１への実装形態は、フェイスアップ、フェイスダウンのいずれの形態であってもよい。   Further, the mounting form of the semiconductor element 12 on the circuit board 11 may be either face-up or face-down.

本発明の一実施形態として説明する半導体装置１の表面側斜視図である。It is a surface side perspective view of semiconductor device 1 explained as one embodiment of the present invention. 本発明の一実施形態として説明する半導体装置１を裏面側斜視図である。It is a back surface side perspective view of semiconductor device 1 explained as one embodiment of the present invention. 本発明の一実施形態として説明する半導体装置１の側面図である。It is a side view of the semiconductor device 1 demonstrated as one Embodiment of this invention. 本発明の一実施形態として説明する半導体装置１の貫通孔１１３周辺部分の拡大斜視図である。It is an expansion perspective view of the peripheral part of the through-hole 113 of the semiconductor device 1 demonstrated as one Embodiment of this invention. 本発明の一実施形態として説明する回路基板１１の平面図である。It is a top view of the circuit board 11 demonstrated as one Embodiment of this invention. 本発明の一実施形態として説明する回路基板１１の裏面図である。It is a back view of the circuit board 11 demonstrated as one Embodiment of this invention. 本発明の一実施形態として説明する回路基板１１の裏面図である。It is a back view of the circuit board 11 demonstrated as one Embodiment of this invention. 本発明の一実施形態として説明する集合基板１１０の平面図である。It is a top view of the collective substrate 110 demonstrated as one Embodiment of this invention. 本発明の一実施形態として説明する集合基板１１０の裏面図である。It is a back view of the collective substrate 110 demonstrated as one Embodiment of this invention. 本発明の一実施形態として説明する連続回路基板１２０の平面図である。It is a top view of the continuous circuit board 120 demonstrated as one Embodiment of this invention. （ａ）〜（ｅ）は、本発明の一実施形態として説明する半導体素子１２を回路基板１１に接合する際の工程を示す図である。(A)-(e) is a figure which shows the process at the time of joining the semiconductor element 12 demonstrated as one Embodiment of this invention to the circuit board 11. FIG. （ａ）〜（ｄ）は、トランスファモールド方式による半導体装置の樹脂封止工程の一例を示す図である。(A)-(d) is a figure which shows an example of the resin sealing process of the semiconductor device by a transfer mold system.

符号の説明Explanation of symbols

１ 半導体装置
１１ 回路基板
１１１ ボンディングパッド
１１１１ 第１の領域
１１１２ 第２の領域
１１３ 貫通孔
１１４ 裏面電極
１１５ 素子搭載領域
１１６ インデックスマーク
１１８ ソルダーレジスト
１２ 半導体素子
１２１ 電極パッド
１３ ＤＡＦ
１５ 半導体基板
２０ ボンディングワイヤー DESCRIPTION OF SYMBOLS 1 Semiconductor device 11 Circuit board 111 Bonding pad 1111 1st area | region 1112 2nd area | region 113 Through-hole 114 Back surface electrode 115 Element mounting area
116 Index mark 118 Solder resist 12 Semiconductor element 121 Electrode pad 13 DAF
15 Semiconductor substrate 20 Bonding wire

Claims (7)

半導体素子が搭載されてなる回路基板であって、
裏面の一部の領域に電極が形成され、
裏面の前記裏面電極が形成されていない領域に、前記裏面電極とほぼ同厚の部材が形成されてなること
を特徴とする回路基板。 A circuit board on which a semiconductor element is mounted,
An electrode is formed on a part of the back surface,
A circuit board, wherein a member having substantially the same thickness as the back electrode is formed in a region of the back surface where the back electrode is not formed. 請求項１に記載の回路基板であって、
前記裏面電極は、当該回路基板の裏面の外周近傍に形成されており、
前記部材が、裏面の前記裏面電極よりも内周側の領域に形成されてなること
を特徴とする回路基板。 The circuit board according to claim 1,
The back electrode is formed near the outer periphery of the back surface of the circuit board,
The circuit board is characterized in that the member is formed in a region on the inner surface side of the back electrode on the back surface. 請求項２に記載の回路基板であって、
複数の前記裏面電極が当該回路基板の裏面の外周に沿って形成されており、
前記部材が、隣接する前記裏面電極に挟まれる領域にも形成されてなること
を特徴とする回路基板。 The circuit board according to claim 2,
A plurality of the back electrodes are formed along the outer periphery of the back surface of the circuit board;
The circuit board, wherein the member is formed also in a region sandwiched between the adjacent back electrodes. 請求項１に記載の回路基板であって、
前記部材はソルダーレジスト又は導電体からなること
を特徴とする回路基板。 The circuit board according to claim 1,
The circuit board is characterized in that the member is made of a solder resist or a conductor. 半導体素子と、
前記半導体素子が搭載される回路基板と、
を有し、
前記回路基板の裏面に電極が形成され、
前記回路基板の裏面の前記裏面電極が形成されていない領域に、前記裏面電極とほぼ同厚の部材が形成されていること
を特徴とする半導体装置。 A semiconductor element;
A circuit board on which the semiconductor element is mounted;
Have
An electrode is formed on the back surface of the circuit board,
A member having substantially the same thickness as the back electrode is formed in a region of the back surface of the circuit board where the back electrode is not formed. 請求項５に記載の半導体装置であって、
前記半導体素子が樹脂封止されてなること
を特徴とする半導体装置。 The semiconductor device according to claim 5,
A semiconductor device, wherein the semiconductor element is sealed with resin. 請求項５に記載の半導体装置であって、
前記回路基板には、
当該回路基板の端面に開口し当該回路基板を貫通する複数の貫通孔と、
前記各貫通孔を塞ぐように形成されるボンディングパッドと、
が形成され、
前記電極と前記ボンディングパッドとを電気的に接続するボンディングワイヤーが設けられ、
前記半導体素子及び前記ボンディングワイヤーが樹脂封止されてなること
を特徴とする半導体装置。

The semiconductor device according to claim 5,
In the circuit board,
A plurality of through holes that open in the end face of the circuit board and penetrate the circuit board;
A bonding pad formed so as to close each through hole;
Formed,
A bonding wire for electrically connecting the electrode and the bonding pad is provided;
The semiconductor device, wherein the semiconductor element and the bonding wire are sealed with resin.

JP2006069797A 2006-03-14 2006-03-14 Circuit board and semiconductor device Pending JP2007250675A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006069797A JP2007250675A (en) 2006-03-14 2006-03-14 Circuit board and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006069797A JP2007250675A (en) 2006-03-14 2006-03-14 Circuit board and semiconductor device

Publications (1)

Publication Number Publication Date
JP2007250675A true JP2007250675A (en) 2007-09-27

Family

ID=38594673

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006069797A Pending JP2007250675A (en) 2006-03-14 2006-03-14 Circuit board and semiconductor device

Country Status (1)

Country Link
JP (1) JP2007250675A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012101978A1 (en) * 2011-01-25 2012-08-02 株式会社村田製作所 Electronic component
JP2013222877A (en) * 2012-04-18 2013-10-28 Sharp Corp Semiconductor module

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0613479A (en) * 1992-06-29 1994-01-21 Kyocera Corp Housing package for surface mount electronic part
JPH06334061A (en) * 1993-05-19 1994-12-02 Ibiden Co Ltd Semiconductor mounting board
JP2002100701A (en) * 2000-09-22 2002-04-05 Sharp Corp Semiconductor device
JP2006261549A (en) * 2005-03-18 2006-09-28 Fujitsu Ltd Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0613479A (en) * 1992-06-29 1994-01-21 Kyocera Corp Housing package for surface mount electronic part
JPH06334061A (en) * 1993-05-19 1994-12-02 Ibiden Co Ltd Semiconductor mounting board
JP2002100701A (en) * 2000-09-22 2002-04-05 Sharp Corp Semiconductor device
JP2006261549A (en) * 2005-03-18 2006-09-28 Fujitsu Ltd Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012101978A1 (en) * 2011-01-25 2012-08-02 株式会社村田製作所 Electronic component
US20130301230A1 (en) * 2011-01-25 2013-11-14 Murata Manufacturing Co., Ltd. Electronic component
JP5704177B2 (en) * 2011-01-25 2015-04-22 株式会社村田製作所 Electronic components
US9343844B2 (en) 2011-01-25 2016-05-17 Murata Manufacturing Co., Ltd. Electronic component
JP2013222877A (en) * 2012-04-18 2013-10-28 Sharp Corp Semiconductor module

Similar Documents

Publication Publication Date Title
JP2001015679A (en) Semiconductor device and manufacture thereof
TWM382576U (en) Leadless integrated circuit package having high density contacts
JP2011124251A (en) Semiconductor device and method of manufacturing the same
JP2003017518A (en) Method for manufacturing hybrid integrated circuit device
JPH09199635A (en) Multilayer film for forming circuit substrate, multilayer circuit substrate using it, and package for semiconductor device
JP2958692B2 (en) Ball grid array semiconductor package member, method of manufacturing the same, and method of manufacturing ball grid array semiconductor package
JP4970388B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2005286057A (en) Circuit device and its manufacturing method
CN111261532A (en) Low RDSON three-dimensional stacking integrated packaging structure and preparation method thereof
US20050098869A1 (en) Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
JP2007250675A (en) Circuit board and semiconductor device
JP4776012B2 (en) Circuit board and semiconductor device
JP2008198916A (en) Semiconductor device and manufacturing method thereof
JP2016192447A (en) Semiconductor device
JP4852319B2 (en) Circuit board and semiconductor device
JP2010050288A (en) Resin-sealed semiconductor device and method of manufacturing the same
JP5857556B2 (en) Multi-chip composite lead frame and semiconductor device
JP3417292B2 (en) Semiconductor device
JP2020057771A (en) Module and method of manufacturing the same
JP2010021392A (en) Semiconductor device and its manufacturing method
JP2013110188A (en) Semiconductor device and manufacturing method of the same
JP2011238770A (en) Lead frame, semiconductor device, and method of manufacturing semiconductor device
JP5286948B2 (en) Substrate and electronic device manufacturing method
JP4881369B2 (en) Manufacturing method of semiconductor device
JP3382516B2 (en) Semiconductor package

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090218

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090901

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20110531

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110607

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110802

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20110823