JP2007242652A - Process for fabricating semiconductor device - Google Patents

Process for fabricating semiconductor device Download PDF

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JP2007242652A
JP2007242652A JP2006058872A JP2006058872A JP2007242652A JP 2007242652 A JP2007242652 A JP 2007242652A JP 2006058872 A JP2006058872 A JP 2006058872A JP 2006058872 A JP2006058872 A JP 2006058872A JP 2007242652 A JP2007242652 A JP 2007242652A
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sio
film
opening
etching
semiconductor device
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JP4864491B2 (en
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Hideaki Matsuzaki
秀昭 松崎
Masami Tokumitsu
雅美 徳光
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Nippon Telegraph and Telephone Corp
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<P>PROBLEM TO BE SOLVED: To provide a process for fabricating a semiconductor device in which parasitic capacitance can be reduced at a T-shaped electrode. <P>SOLUTION: A semiconductor crystal layer 12 is formed on a substrate 11, a first SiO<SB>2</SB>film 13 having a thickness of 50 nm is formed on the semiconductor crystal layer 12, a second SiO<SB>2</SB>film 14 having a thickness of 100 nm is formed on the SiO<SB>2</SB>film 13, and resist 15 having an opening 15a is formed. The SiO<SB>2</SB>films 14 and 13 directly under the opening 15a are then etched by first reactive ion etching, etching of the SiO<SB>2</SB>film 13 is not advanced, but etching of the SiO<SB>2</SB>film 14 is advanced in the lateral direction by second reactive ion etching to form a T-shaped opening in the SiO<SB>2</SB>films 13 and 14. After removing the resist 15, a T-shaped electrode 16 is formed in the T-shaped opening of the SiO<SB>2</SB>films 13 and 14. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明はＴ型電極を有する半導体装置、たとえばショットキ接合型の電界効果型トランジスタ（ＦＥＴ）を製造する半導体装置の製造方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor device having a T-type electrode, for example, a semiconductor device for manufacturing a Schottky junction field effect transistor (FET).

従来のＴ型電極を有する電界効果型トランジスタを製造する半導体装置の製造方法を図６、図７により説明する。まず、図６(ａ)に示すように、基板１上に半導体結晶層（ショットキ障壁層）２を形成し、半導体結晶層２上にキャップ層３を形成し、キャップ層３上にＳｉＯ２膜４を形成する。つぎに、図６(ｂ)に示すように、ＳｉＯ２膜４上にＳｉＮ膜５を形成する。つぎに、図６(ｃ)に示すように、ＳｉＮ膜５上に開口部６ａを有するレジスト６を形成する。つぎに、図６(ｄ)に示すように、エッチングを等方的に進行させて、ＳｉＮ膜５を除去したのち、エッチングを異方的に進行させて、ＳｉＯ２膜４を除去して、ＳｉＯ２膜４、ＳｉＮ膜５にＴ型開口部を形成する。つぎに、図７(ａ)に示すように、レジスト６を除去する。つぎに、図７(ｂ)に示すように、キャップ層３をリセスエッチングする。つぎに、図７(ｃ)に示すように、ＳｉＯ２膜４、ＳｉＮ膜５のＴ型開口部にゲート電極すなわちＴ型電極７を形成する。 A conventional method for manufacturing a semiconductor device for manufacturing a field effect transistor having a T-type electrode will be described with reference to FIGS. First, as shown in FIG. 6A, a semiconductor crystal layer (Schottky barrier layer) 2 is formed on a substrate 1, a cap layer 3 is formed on the semiconductor crystal layer 2, and an SiO 2 film is formed on the cap layer 3. 4 is formed. Next, as shown in FIG. 6B, a SiN film 5 is formed on the SiO 2 film 4. Next, as shown in FIG. 6C, a resist 6 having an opening 6 a is formed on the SiN film 5. Next, as shown in FIG. 6 (d), the etching is isotropically advanced to remove the SiN film 5, and then the etching is anisotropically advanced to remove the SiO 2 film 4. T-shaped openings are formed in the SiO 2 film 4 and the SiN film 5. Next, as shown in FIG. 7A, the resist 6 is removed. Next, as shown in FIG. 7B, the cap layer 3 is recess-etched. Next, as shown in FIG. 7C, a gate electrode, that is, a T-type electrode 7 is formed in the T-type opening of the SiO 2 film 4 and the SiN film 5.

この半導体装置の製造方法においては、ＳｉＯ２膜４、ＳｉＮ膜５のＴ型開口部を介してキャップ層３のリセスエッチングを実施し、露出した半導体結晶層２に接触するようにＴ型電極７を形成することで、寄生容量の低減と寄生抵抗の低減とを両立させている。
T. Enoki, H. Ito, K. Ikuta and Y. Ishii: Proc. Int. Conf. Indium Phosphideand Related Materials,1995, pp. 81-84 In this semiconductor device manufacturing method, recess etching of the cap layer 3 is performed through the T-type openings of the SiO 2 film 4 and the SiN film 5, and the T-type electrode 7 is brought into contact with the exposed semiconductor crystal layer 2. By forming this, both reduction of parasitic capacitance and reduction of parasitic resistance are achieved.
T. Enoki, H. Ito, K. Ikuta and Y. Ishii: Proc. Int. Conf. Indium Phosphideand Related Materials, 1995, pp. 81-84

しかし、このような半導体装置の製造方法においては、ＳｉＮ膜５は比誘電率が高い（〜７．５）ため、ゲート微細化の際には寄生容量の寄与が相対的に大きくなり、電界効果型トランジスタの高周波性能の向上が阻害されてしまう。   However, in such a method for manufacturing a semiconductor device, since the SiN film 5 has a high relative dielectric constant (˜7.5), the contribution of parasitic capacitance becomes relatively large at the time of gate miniaturization, and the field effect Improvement of the high-frequency performance of the type transistor is hindered.

本発明は上述の課題を解決するためになされたもので、Ｔ型電極部の寄生容量を小さくすることができる半導体装置の製造方法を提供することを目的とする。   The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can reduce the parasitic capacitance of a T-type electrode portion.

この目的を達成するため、本発明においては、半導体層上に第１のＳｉＯ２膜を形成し、上記第１のＳｉＯ２膜上に上記第１のＳｉＯ２膜とは化学組成の異なる第２のＳｉＯ２膜を形成し、上記第２のＳｉＯ２膜上に開口部を有するレジストを形成し、エッチングを異方的に進行させる第１の反応性イオンエッチングを行ない、上記レジストの上記開口部の直下の上記第２のＳｉＯ２膜、上記第１のＳｉＯ２膜を除去し、つぎにエッチングを等方的に進行させる第２の反応性イオンエッチングを行ない、上記第２のＳｉＯ２膜のエッチングを横方向に進行させることにより、上記第１、第２のＳｉＯ２膜にＴ型開口部を形成し、上記Ｔ型開口部にＴ型電極を形成する。 In order to achieve this object, in the present invention, a first SiO 2 film is formed on a semiconductor layer, and a second chemical composition different from that of the first SiO 2 film is formed on the first SiO 2 film. An SiO 2 film is formed, a resist having an opening is formed on the second SiO 2 film, a first reactive ion etching is performed to anisotropically proceed, and the opening of the resist is formed. The second SiO 2 film and the first SiO 2 film immediately below the first SiO 2 film are removed, and then a second reactive ion etching isotropically performed to perform etching of the second SiO 2 film. Etching proceeds in the lateral direction to form T-shaped openings in the first and second SiO 2 films, and to form T-shaped electrodes in the T-shaped openings.

また、半導体層上に第１のＳｉＯ２膜を形成し、上記第１のＳｉＯ２膜上に上記第１のＳｉＯ２膜とは化学組成の異なる第２のＳｉＯ２膜を形成し、上記第２のＳｉＯ２膜の上記開口部を有するレジストを形成し、エッチングを等方的に進行させる第３の反応性イオンエッチングを行ない、上記開口部の直下の第２のＳｉＯ２膜を除去するとともに、上記第２のＳｉＯ２膜のエッチングを横方向に進行させ、つぎにエッチングを異方的に進行させる第４の反応性イオンエッチングを行ない、上記開口部の直下の上記第１のＳｉＯ２膜を除去することにより、上記第１、第２のＳｉＯ２膜にＴ型開口部を形成し、上記Ｔ型開口部にＴ型電極を形成する。 In addition, a first SiO 2 film is formed on the semiconductor layer, a second SiO 2 film having a chemical composition different from that of the first SiO 2 film is formed on the first SiO 2 film, and the first SiO 2 film is formed. Forming a resist having the opening of the SiO 2 film 2 and performing a third reactive ion etching for isotropically proceeding to remove the second SiO 2 film immediately below the opening; Then, etching of the second SiO 2 film is performed in the lateral direction, and then fourth reactive ion etching is performed in which the etching proceeds anisotropically, and the first SiO 2 film immediately below the opening is performed. Is removed to form T-shaped openings in the first and second SiO 2 films, and T-shaped electrodes are formed in the T-shaped openings.

これらの場合、電界効果型トランジスタの半導体結晶層上に上記第１のＳｉＯ２膜を形成し、また上記Ｔ型開口部にゲート電極である上記Ｔ型電極を形成してもよい。 In these cases, the first SiO 2 film may be formed on the semiconductor crystal layer of the field effect transistor, and the T-type electrode as the gate electrode may be formed in the T-type opening.

また、電界効果型トランジスタの半導体結晶層上にキャップ層を形成し、上記キャップ層上に上記第１のＳｉＯ２膜を形成し、また上記第１、第２のＳｉＯ２膜に上記Ｔ型開口部を形成し、上記キャップ層をリセスエッチングしたのち、上記Ｔ型開口部にゲート電極である上記Ｔ型電極を形成してもよい。 Further, a cap layer is formed on the semiconductor crystal layer of the field effect transistor, the first SiO 2 film is formed on the cap layer, and the T-type opening is formed in the first and second SiO 2 films. After forming the portion and recess-etching the cap layer, the T-type electrode, which is a gate electrode, may be formed in the T-type opening.

本発明に係る半導体装置の製造方法においては、ＳｉＯ２膜の比誘電率はＳｉＮ膜の比誘電率よりも小さいから、Ｔ型電極部の寄生容量を小さくすることができ、またＴ型電極を形成するために異なる種類の絶縁膜を形成する必要がない。 In the method for manufacturing a semiconductor device according to the present invention, since the relative dielectric constant of the SiO 2 film is smaller than the relative dielectric constant of the SiN film, the parasitic capacitance of the T-type electrode portion can be reduced, and the T-type electrode can be reduced. There is no need to form different types of insulating films to form.

本発明に係るＴ型電極を有する電界効果型トランジスタを製造する半導体装置の製造方法を図１、図２により説明する。まず、図１(ａ)に示すように、基板１１上に半導体層である半導体結晶層（ショットキ障壁層、キャリア供給層、チャネル層から構成される結晶層）１２を形成し、半導体結晶層１２上に膜厚が５０ｎｍの第１のＳｉＯ２膜１３をスパッタ法により形成（堆積）し、連続して製膜条件（スパッタパワー、チャンバ内圧力など）を適宜変更してＳｉＯ２膜１３上に膜厚が１００ｎｍの第２のＳｉＯ２膜１４を形成（堆積）する。この結果、ＳｉＯ２膜１４はその組成において酸素欠損を生じており、ＳｉＯ２膜１４とＳｉＯ２膜１３とは化学組成が異なり、反応性イオンエッチング（ＲＩＥ）耐性が異なる。つぎに、図１(ｂ)に示すように、ＳｉＯ２膜１４上にレジストを塗布し、フォトリソグラフィ法または電子線描画によりゲートパタンを転写し、開口部１５ａを有するレジスト１５を形成する。このときのゲート長寸法を例えば５０ｎｍとする。つぎに、図１(ｃ)に示すように、エッチングを異方的に（垂直方向に）進行させる第１の反応性イオンエッチングを行ない、開口部１５ａの直下のＳｉＯ２膜１４、１３を除去する。つぎに、図２(ａ)に示すように、エッチングガスおよびチャンバ内圧力を変更して、エッチングを等方的に（横方向に）進行させる第２の反応性イオンエッチングを行ない、ＳｉＯ２膜１４のエッチングを横方向に進行させる。すなわち、ＳｉＯ２膜１４の反応性イオンエッチング耐性とＳｉＯ２膜１３の反応性イオンエッチング耐性とが異なることを利用することにより、ＳｉＯ２膜１３のエッチングを進行させずに、ＳｉＯ２膜１４のエッチングを横方向に進行させて、ＳｉＯ２膜１３、１４にＴ型開口部を形成する。つぎに、図２(ｂ)に示すように、レジスト１５を除去する。つぎに、図２(ｃ)に示すように、ＳｉＯ２膜１３、１４のＴ型開口部に例えば蒸着、リフトオフ法により金属からなるゲート電極すなわちＴ型電極１６を形成する。 A method of manufacturing a semiconductor device for manufacturing a field effect transistor having a T-type electrode according to the present invention will be described with reference to FIGS. First, as shown in FIG. 1A, a semiconductor crystal layer (crystal layer composed of a Schottky barrier layer, a carrier supply layer, and a channel layer) 12 which is a semiconductor layer is formed on a substrate 11, and the semiconductor crystal layer 12 is formed. A first SiO 2 film 13 having a thickness of 50 nm is formed (deposited) on the SiO 2 film 13 by sputtering, and continuously changes the film forming conditions (sputtering power, pressure in the chamber, etc.) on the SiO 2 film 13. A second SiO 2 film 14 having a thickness of 100 nm is formed (deposited). As a result, the SiO 2 film 14 has oxygen deficiency in its composition, and the SiO 2 film 14 and the SiO 2 film 13 have different chemical compositions and different reactive ion etching (RIE) resistance. Next, as shown in FIG. 1B, a resist is applied onto the SiO 2 film 14, and the gate pattern is transferred by photolithography or electron beam drawing to form a resist 15 having an opening 15a. The gate length dimension at this time is set to 50 nm, for example. Next, as shown in FIG. 1 (c), first reactive ion etching is performed in which the etching proceeds anisotropically (in the vertical direction) to remove the SiO 2 films 14 and 13 immediately below the opening 15a. To do. Next, as shown in FIG. 2 (a), by changing the etching gas and the pressure inside the chamber, (laterally) isotropically etching performs second reactive ion etching to proceed, SiO 2 film Etching 14 proceeds laterally. That is, by utilizing the fact that the reactive ion etching resistance of the SiO 2 film 14 and the reactive ion etching resistance of the SiO 2 film 13 are different from each other, the etching of the SiO 2 film 13 does not proceed and the SiO 2 film 14 is not etched. Etching is advanced in the lateral direction to form T-shaped openings in the SiO 2 films 13 and 14. Next, as shown in FIG. 2B, the resist 15 is removed. Next, as shown in FIG. 2C, a gate electrode made of metal, that is, a T-type electrode 16 is formed in the T-type openings of the SiO 2 films 13 and 14 by, for example, vapor deposition or lift-off.

この半導体装置の製造方法においては、ＳｉＯ２膜１３上にＳｉＯ２膜１４を形成しており、ＳｉＯ２膜の比誘電率は約４であり、ＳｉＮ膜の比誘電率の半分程度の値であることから、Ｔ型電極１６部の寄生容量を小さくすることができ、ゲート微細化の際にも寄生容量の寄与が大きくなることがないので、電界効果型トランジスタの高周波性能の向上が阻害されることがない。また、Ｔ型電極１６を形成するためにＳｉＯ２膜１３とＳｉＯ２膜１４とを形成しており、異なる種類の絶縁膜を形成する必要がないから、製造に必要な装置の削減、製造時間の短縮を簡便に実現することができる。また、Ｔ型電極１６をゲート電極として用いることで、寄生容量低減と寄生抵抗低減との両立が可能なゲート電極を得ることができ、微細化された電界効果型トランジスタの特性向上を図ることができる。 In this semiconductor device manufacturing method, the SiO 2 film 14 is formed on the SiO 2 film 13, and the relative dielectric constant of the SiO 2 film is about 4, which is about half the relative dielectric constant of the SiN film. As a result, the parasitic capacitance of the T-type electrode 16 can be reduced, and the contribution of the parasitic capacitance does not increase even when the gate is miniaturized, which hinders the improvement of the high-frequency performance of the field effect transistor. There is nothing to do. Further, since the SiO 2 film 13 and the SiO 2 film 14 are formed in order to form the T-type electrode 16 and it is not necessary to form different types of insulating films, the number of devices required for manufacturing is reduced and the manufacturing time is reduced. Can be easily achieved. In addition, by using the T-type electrode 16 as a gate electrode, a gate electrode capable of reducing both parasitic capacitance and parasitic resistance can be obtained, and characteristics of a miniaturized field effect transistor can be improved. it can.

つぎに、本発明に係る他のＴ型電極を有する電界効果型トランジスタを製造する半導体装置の製造方法を図３により説明する。まず、図１(ａ)で説明した工程を行なったのち、図３(ａ)に示すように、ＳｉＯ２膜１４上に開口部１５ａを有するレジスト１５を形成する。つぎに、図３(ｂ)に示すように、エッチングを等方的に進行させる第３の反応性イオンエッチングを行ない、開口部１５ａの直下のＳｉＯ２膜１４を除去するとともに、ＳｉＯ２膜１４のエッチングを横方向に進行させる。つぎに、図３(ｃ)に示すように、エッチングガスおよびチャンバ内圧力を変更して、エッチングを異方的に進行させる第４の反応性イオンエッチングを行ない、開口部１５ａの直下のＳｉＯ２膜１３を除去することにより、ＳｉＯ２膜１３、１４にＴ型開口部を形成する。つぎに、図２(ｂ)、(ｃ)で説明した工程を行なう。 Next, a method for manufacturing a semiconductor device for manufacturing a field effect transistor having another T-type electrode according to the present invention will be described with reference to FIG. First, after performing the process described in FIG. 1A, a resist 15 having an opening 15a is formed on the SiO 2 film 14 as shown in FIG. 3A. Next, as shown in FIG. 3B, the third reactive ion etching isotropically progressed to remove the SiO 2 film 14 immediately below the opening 15a and the SiO 2 film 14 Etching is performed in the lateral direction. Next, as shown in FIG. 3C, the fourth reactive ion etching is performed to change the etching gas and the pressure in the chamber to cause the etching to proceed anisotropically, and SiO 2 immediately below the opening 15a. By removing the film 13, T-shaped openings are formed in the SiO 2 films 13 and 14. Next, the steps described in FIGS. 2B and 2C are performed.

つぎに、本発明に係る他のＴ型電極を有する電界効果型トランジスタを製造する半導体装置の製造方法を図４、図５により説明する。まず、図４(ａ)に示すように、基板１１上に半導体結晶層１２を形成し、半導体結晶層１２上にキャップ層２１を形成し、キャップ層２１上（半導体結晶層１２上）にＳｉＯ２膜１３を形成し、ＳｉＯ２膜１３上にＳｉＯ２膜１４を形成する。つぎに、図４(ｂ)に示すように、ＳｉＯ２膜１４上に開口部１５ａを有するレジスト１５を形成する。つぎに、図４(ｃ)に示すように、エッチングを異方的に進行させる第３の反応性イオンエッチングを行ない、開口部１５ａの直下のＳｉＯ２膜１４、１３膜を除去する。つぎに、図５(ａ)に示すように、エッチングガスおよびチャンバ内圧力を変更して、エッチングを等方的に進行させる第４の反応性イオンエッチングを行ない、ＳｉＯ２膜１４のエッチングを横方向に進行させることにより、ＳｉＯ２膜１３、１４にＴ型開口部を形成する。つぎに、図５(ｂ)に示すように、レジスト１５を除去したのち、キャップ層２１をリセスエッチングする。つぎに、図５(ｃ)に示すように、ＳｉＯ２膜１３、１４のＴ型開口部に露出した半導体結晶層１２に接触するようにＴ型電極１６を形成する。 Next, a method of manufacturing a semiconductor device for manufacturing a field effect transistor having another T-type electrode according to the present invention will be described with reference to FIGS. First, as shown in FIG. 4A, the semiconductor crystal layer 12 is formed on the substrate 11, the cap layer 21 is formed on the semiconductor crystal layer 12, and the SiO 2 is formed on the cap layer 21 (on the semiconductor crystal layer 12). Two films 13 are formed, and a SiO 2 film 14 is formed on the SiO 2 film 13. Next, as shown in FIG. 4B, a resist 15 having an opening 15 a is formed on the SiO 2 film 14. Next, as shown in FIG. 4C, third reactive ion etching is performed to anisotropically advance the etching, and the SiO 2 films 14 and 13 immediately below the opening 15a are removed. Next, as shown in FIG. 5 (a), the etching gas and the pressure in the chamber are changed, and the fourth reactive ion etching isotropically advanced to perform etching of the SiO 2 film 14 laterally. By proceeding in the direction, T-shaped openings are formed in the SiO 2 films 13 and 14. Next, as shown in FIG. 5B, after removing the resist 15, the cap layer 21 is recess-etched. Next, as shown in FIG. 5C, a T-type electrode 16 is formed so as to be in contact with the semiconductor crystal layer 12 exposed in the T-type openings of the SiO 2 films 13 and 14.

なお、上述実施の形態においては、ゲート長を５０ｎｍとした場合について説明したが、ゲート長に依らず、寄生容量の寄与は一定であることから、ゲート長を短縮すればするほど、本発明の効果はより顕著になるので、ゲート長を２００ｎｍ以下にするのが望ましい。また、第１、第２のＳｉＯ２膜の厚みについては、Ｔ型電極用の金属の開口部の埋め込み状況がゲート長とのアスペクト比に依存することを勘案すると、可能な限り薄くすることが望ましいが、薄くなると寄生容量の増大を招くことから、電極埋め込み技術の許す限り厚くすることが素子性能向上の観点から要求される。実際のＴ型電極用の金属の開口部への埋め込みを考慮すると、第１のＳｉＯ２膜の膜厚はゲート長と同程度、第２のＳｉＯ２膜の膜厚はゲート長の３倍程度の膜厚とすることが望ましい。また、上述実施の形態においては、レジスト１５を除去したのち、キャップ層２１をリセスエッチングしたが、キャップ層２１をリセスエッチングしたのち、レジスト１５を除去してもよい。 In the above-described embodiment, the case where the gate length is 50 nm has been described. However, the contribution of the parasitic capacitance is constant regardless of the gate length, so that the shorter the gate length, the more the present invention. Since the effect becomes more remarkable, it is desirable that the gate length be 200 nm or less. In addition, the thickness of the first and second SiO 2 films can be made as thin as possible considering that the filling state of the opening of the metal for the T-type electrode depends on the aspect ratio with the gate length. Although it is desirable, since the parasitic capacitance increases when the thickness is reduced, the thickness is required to be as thick as the electrode embedding technique allows, from the viewpoint of improving the device performance. Considering the actual filling of the metal for the T-type electrode into the opening, the thickness of the first SiO 2 film is about the same as the gate length, and the thickness of the second SiO 2 film is about three times the gate length. It is desirable to set it as the film thickness. In the above-described embodiment, the cap layer 21 is recess-etched after removing the resist 15, but the resist 15 may be removed after the cap layer 21 is recess-etched.

本発明に係る半導体装置の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the semiconductor device which concerns on this invention. 本発明に係る半導体装置の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the semiconductor device which concerns on this invention. 本発明に係る他の半導体装置の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the other semiconductor device which concerns on this invention. 本発明に係る他の半導体装置の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the other semiconductor device which concerns on this invention. 本発明に係る他の半導体装置の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the other semiconductor device which concerns on this invention. 従来の半導体装置の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the conventional semiconductor device.

符号の説明Explanation of symbols

１１…基板
１２…半導体結晶層
１３…第１のＳｉＯ２膜
１４…第２のＳｉＯ２膜
１５…レジスト
１５ａ…開口部
１６…Ｔ型電極
２１…キャップ層 11 ... substrate 12 ... semiconductor crystal layer 13 ... first SiO 2 film 14 ... second SiO 2 film 15 ... resist 15a ... opening 16 ... T-type electrode 21 ... cap layer

Claims (4)

半導体層上に第１のＳｉＯ２膜を形成し、上記第１のＳｉＯ２膜上に上記第１のＳｉＯ２膜とは化学組成の異なる第２のＳｉＯ２膜を形成し、上記第２のＳｉＯ２膜上に開口部を有するレジストを形成し、エッチングを異方的に進行させる第１の反応性イオンエッチングを行ない、上記レジストの上記開口部の直下の上記第２のＳｉＯ２膜、上記第１のＳｉＯ２膜を除去し、つぎにエッチングを等方的に進行させる第２の反応性イオンエッチングを行ない、上記第２のＳｉＯ２膜のエッチングを横方向に進行させることにより、上記第１、第２のＳｉＯ２膜にＴ型開口部を形成し、上記Ｔ型開口部にＴ型電極を形成することを特徴とする半導体装置の製造方法。 The first SiO 2 film is formed on the semiconductor layer, the above first SiO 2 film to form a different second SiO 2 film having a chemical composition in the first SiO 2 film, the second A resist having an opening is formed on the SiO 2 film, and first reactive ion etching is performed to anisotropically advance the second SiO 2 film immediately below the opening of the resist. The first SiO 2 film is removed, and then the second reactive ion etching for isotropically proceeding etching is performed, and the etching of the second SiO 2 film is proceeded in the lateral direction, whereby the first 1. A method of manufacturing a semiconductor device, comprising: forming a T-type opening in the first SiO 2 film; and forming a T-type electrode in the T-type opening. 半導体層上に第１のＳｉＯ２膜を形成し、上記第１のＳｉＯ２膜上に上記第１のＳｉＯ２膜とは化学組成の異なる第２のＳｉＯ２膜を形成し、上記第２のＳｉＯ２膜の上記開口部を有するレジストを形成し、エッチングを等方的に進行させる第３の反応性イオンエッチングを行ない、上記開口部の直下の第２のＳｉＯ２膜を除去するとともに、上記第２のＳｉＯ２膜のエッチングを横方向に進行させ、つぎにエッチングを異方的に進行させる第４の反応性イオンエッチングを行ない、上記開口部の直下の上記第１のＳｉＯ２膜を除去することにより、上記第１、第２のＳｉＯ２膜にＴ型開口部を形成し、上記Ｔ型開口部にＴ型電極を形成することを特徴とする半導体装置の製造方法。 The first SiO 2 film is formed on the semiconductor layer, the above first SiO 2 film to form a different second SiO 2 film having a chemical composition in the first SiO 2 film, the second A resist having the opening of the SiO 2 film is formed, a third reactive ion etching isotropically proceeding to remove the second SiO 2 film immediately below the opening, and the above Etching of the second SiO 2 film is performed in the lateral direction, and then the fourth reactive ion etching is performed to anisotropically proceed to remove the first SiO 2 film immediately below the opening. Thus, a T-type opening is formed in the first and second SiO 2 films, and a T-type electrode is formed in the T-type opening. 電界効果型トランジスタの半導体結晶層上に上記第１のＳｉＯ２膜を形成し、また上記Ｔ型開口部にゲート電極である上記Ｔ型電極を形成することを特徴とする請求項１または２に記載の半導体装置の製造方法。 3. The first SiO 2 film is formed on a semiconductor crystal layer of a field effect transistor, and the T-type electrode which is a gate electrode is formed in the T-type opening. The manufacturing method of the semiconductor device of description. 電界効果型トランジスタの半導体結晶層上にキャップ層を形成し、上記キャップ層上に上記第１のＳｉＯ２膜を形成し、また上記第１、第２のＳｉＯ２膜に上記Ｔ型開口部を形成し、上記キャップ層をリセスエッチングしたのち、上記Ｔ型開口部にゲート電極である上記Ｔ型電極を形成することを特徴とする請求項１または２に記載の半導体装置の製造方法。 A cap layer is formed on the semiconductor crystal layer of the field effect transistor, the first SiO 2 film is formed on the cap layer, and the T-shaped opening is formed in the first and second SiO 2 films. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the T-type electrode which is a gate electrode is formed in the T-type opening after forming and recess-etching the cap layer. 4.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6169175A (en) * 1984-09-12 1986-04-09 Nec Corp Manufacture of semiconductor device
JPS63137481A (en) * 1986-11-28 1988-06-09 Nec Corp Manufacture of semiconductor device
JPH09330937A (en) * 1996-06-07 1997-12-22 Fujitsu Ltd Semiconductor device and its manufacture
JPH10270555A (en) * 1997-03-27 1998-10-09 Mitsubishi Electric Corp Semiconductor device and manufacture thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6169175A (en) * 1984-09-12 1986-04-09 Nec Corp Manufacture of semiconductor device
JPS63137481A (en) * 1986-11-28 1988-06-09 Nec Corp Manufacture of semiconductor device
JPH09330937A (en) * 1996-06-07 1997-12-22 Fujitsu Ltd Semiconductor device and its manufacture
JPH10270555A (en) * 1997-03-27 1998-10-09 Mitsubishi Electric Corp Semiconductor device and manufacture thereof

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