JP2007174134A - High-speed gate drive circuit - Google Patents

High-speed gate drive circuit Download PDF

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JP2007174134A
JP2007174134A JP2005367298A JP2005367298A JP2007174134A JP 2007174134 A JP2007174134 A JP 2007174134A JP 2005367298 A JP2005367298 A JP 2005367298A JP 2005367298 A JP2005367298 A JP 2005367298A JP 2007174134 A JP2007174134 A JP 2007174134A
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gate
voltage
power supply
capacitor
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JP4804142B2 (en
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Yuji Oyama
裕二 大山
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Toyo Electric Manufacturing Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To apply a high voltage temporarily to the gate of a switching device when the device is turned ON or OFF to enable a mirror period near a threshold voltage to pass away at a high speed so as to turn the device ON or OFF quickly and to enable an adequate bias voltage to be applied to the gate of the device while it is kept ON or OFF. <P>SOLUTION: A high-speed gate drive circuit is equipped with an ON-holding power supply 1 whose voltage is within the rated gate voltage of the switching device, a turn-ON power supply 2 whose voltage is above the rated gate voltage, and a turn-ON capacitor 7 which is charged with the turn-ON power supply 2. The turn-ON capacitor 7 which is charged up to just before a turn-ON voltage is released from the turn-ON power supply 2, the electric charge of the turn-ON capacitor 7 is applied to the gate of the semiconductor switching device to turn it ON at a high-speed, and the switching device is kept in an ON-state by the ON-holding power supply 1 after the device is turned ON. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、ＭＯＳＦＥＴ等の絶縁ゲート構造を持つ半導体スイッチの高速ゲート駆動回路に関するものである。   The present invention relates to a high-speed gate drive circuit for a semiconductor switch having an insulated gate structure such as a MOSFET.

ＭＯＳＦＥＴやＩＧＢＴなどの絶縁ゲート構造を持つ半導体スイッチング素子は、電圧駆動型の素子であるため、バイポーラトランジスタなどの電流駆動型の素子に比べて駆動電力が小さく、マイクロエレクトロニクスからパワーエレクトロニクスまで幅広い分野で広く利用されている。   Semiconductor switching elements with insulated gate structures such as MOSFETs and IGBTs are voltage-driven elements, so they have lower driving power than current-driven elements such as bipolar transistors, and can be used in a wide range of fields from microelectronics to power electronics. Widely used.

これらの絶縁ゲート型素子は、ゲートが他の端子に対して絶縁物で絶縁されており、ゲート端子からみると等価的にコンデンサが形成されている。図５は絶縁ゲート型素子の例としてＭＯＳＦＥＴの等価回路を示したものである。ゲート端子からみると内部配線等に存在する寄生抵抗Ｒｇと、ゲート−ソース間容量Ｃｇｓ、ゲート−ドレイン間容量ＣｇｄとによりＣＲ回路が形成されており、ゲート駆動回路はこれらのゲート容量を充放電させるための回路となる。   In these insulated gate type elements, the gate is insulated from other terminals by an insulator, and a capacitor is equivalently formed when viewed from the gate terminal. FIG. 5 shows an equivalent circuit of a MOSFET as an example of an insulated gate element. When viewed from the gate terminal, a CR circuit is formed by the parasitic resistance Rg existing in the internal wiring and the like, the gate-source capacitance Cgs, and the gate-drain capacitance Cgd, and the gate drive circuit charges and discharges these gate capacitances. It becomes a circuit for making it.

図６は従来のＭＯＳＦＥＴゲート駆動回路を示す図である。ゲートドライブ用電源３１に、直列接続したオン用スイッチ８とオフ用スイッチ９を並列に接続し、オン用スイッチ８とオフ用スイッチ９の接続点に駆動対象となるＦＥＴ１０のゲートを、ゲートドライブ用電源３１の負極端子にＦＥＴ１０のソースをそれぞれ接続する。ＦＥＴ１０をターンオンさせる場合、タイミング制御回路３２のＯＮ指令信号をＯＦＦ→ＯＮに変化させることで、タイミング制御回路３２はオフ用スイッチ９を開き、オン用スイッチ８を閉じる信号を出力する。これによりゲートドライブ用電源３１の電圧でゲート容量を充電しターンオンさせる。ターンオフさせる場合、それぞれのスイッチをターンオン時とは逆に動作させ、ゲート容量の電荷をゲート→オフ用スイッチ９→ソースの経路で放電させてターンオフさせる。通常のゲート駆動回路では、ゲートドライブ用電源３１の電圧は、ＦＥＴのデータシートで規定されたゲート電圧絶対最大定格以内で選択される。また、ゲート電圧の振動を抑制する目的で、ゲート駆動回路とＦＥＴのゲート間に直列にゲート抵抗ＲＧを挿入することもある。   FIG. 6 shows a conventional MOSFET gate drive circuit. An on switch 8 and an off switch 9 connected in series are connected in parallel to a gate drive power supply 31, and the gate of the FET 10 to be driven is connected to the connection point of the on switch 8 and the off switch 9 for gate drive. The source of the FET 10 is connected to the negative terminal of the power supply 31. When the FET 10 is turned on, the timing control circuit 32 opens the off switch 9 and outputs a signal to close the on switch 8 by changing the ON command signal of the timing control circuit 32 from OFF to ON. As a result, the gate capacitance is charged with the voltage of the gate drive power supply 31 and turned on. In the case of turning off, each switch is operated in reverse to the turn-on, and the gate capacitance is discharged through the gate → off switch 9 → source path to turn off. In a normal gate drive circuit, the voltage of the gate drive power supply 31 is selected within the absolute maximum rating of the gate voltage defined in the FET data sheet. In order to suppress the oscillation of the gate voltage, a gate resistor RG may be inserted in series between the gate drive circuit and the gate of the FET.

図７は従来のＭＯＳＦＥＴゲート駆動回路による駆動波形例である。前記図６のタイミング制御回路３２のＯＮ指令信号をＯＦＦ→ＯＮに変化させると、ＦＥＴ１０のゲート容量をゲートドライブ用電源３１で充電し始める。このとき、ゲート−ソース間電圧ＶＧＳは、スレッショルド電圧ＶＧＳ（ｔｈ）まで、ゲート容量と寄生抵抗Ｒｇの時定数で上昇する。ＶＧＳがＶＧＳ（ｔｈ）まで達すると、ＦＥＴ１０はターンオン動作を開始し、ドレイン電流ＩＤが流れ始める。ターンオン動作が始まると、ミラー効果によるゲート容量の増加分を充電し続け、再びＶＧＳが上昇し始めるとターンオン動作が終了しオン状態が保持される。次にオフ動作は、オフ用スイッチ９が閉じゲート容量の放電が始まるとＶＧＳが下降し始め、ＶＧＳ（ｔｈ）に達するとターンオフ動作が始まる。再びＶＧＳが下降し始めるとターンオフ動作が完了し、オフ状態が保持される。 FIG. 7 shows an example of a driving waveform by a conventional MOSFET gate driving circuit. When the ON command signal of the timing control circuit 32 in FIG. 6 is changed from OFF to ON, the gate capacity of the FET 10 starts to be charged by the gate drive power supply 31. At this time, the gate-source voltage V GS rises to the threshold voltage V GS (th) with the time constant of the gate capacitance and the parasitic resistance Rg. When V GS reaches V GS (th) , the FET 10 starts to turn on, and the drain current ID starts to flow. When the turn-on operation starts, the increase in the gate capacitance due to the Miller effect continues to be charged, and when V GS starts to rise again, the turn-on operation ends and the on state is maintained. Next, in the off operation, when the off switch 9 is closed and the discharge of the gate capacitance starts, V GS starts to fall, and when it reaches V GS (th) , the turn-off operation starts. When V GS begins to fall again, the turn-off operation is completed and the off state is maintained.

従来のゲート駆動回路では、前記のとおりＯＮ指令信号をＯＦＦ→ＯＮに変化させてから実際にターンオン動作を始めるまでの遅延時間ｔｄ（ＯＮ）と、ターンオンが始まりドレイン電流が飽和するまでの上昇時間ｔｒという２段階の遅れが生じる。また、ターンオフの場合も同様で、ＯＮ指令信号をＯＮ→ＯＦＦに変化させると、実際にターンオフ動作が始まるまでの遅延時間ｔｄ（ＯＦＦ）と、ターンオフ動作が始まりドレイン電流ＩＤが消失するまでの下降時間ｔｆという遅れが生じる。これらの遅れ時間は、半導体スイッチング素子のゲート容量、寄生抵抗Ｒｇ、振動抑制用ゲート抵抗ＲＧの各要素による時定数と、ゲートドライブ電源２０の電圧、およびミラー効果に影響するドレイン−ソース間電圧ＶＤＳに依存する。 In the conventional gate drive circuit, as described above, the delay time td (ON) from when the ON command signal is changed from OFF to ON until the actual turn-on operation is started, and the rise time until the drain current is saturated after the turn-on starts. A two-stage delay tr occurs. The same applies to the turn-off. When the ON command signal is changed from ON to OFF, the delay time td (OFF) until the turn-off operation actually starts and the drain current ID disappears until the turn-off operation starts. There is a delay of the fall time tf. These delay times are the time constant due to each element of the gate capacitance of the semiconductor switching element, the parasitic resistance Rg, and the vibration suppressing gate resistance RG, the voltage of the gate drive power supply 20, and the drain-source voltage V that affects the Miller effect. Depends on DS .

遅れ時間を短縮するには、これら遅れ要因を改善すればよいが、ゲート容量に関わる時定数については素子の製造プロセス等に依存するもので、回路設計者やユーザーにとっては改善不可能な領域である。また、ゲートドライブ電源３１の電圧を上げれば、スレッショルド電圧を通過するまでの時間を短縮でき効果があるが、その上限は素子のデータシートで規定されたゲート電圧の絶対最大定格までである。絶対最大定格以上の電圧を選択した場合は、ＦＥＴのオン保持中は定常的にゲートに過電圧が印加されることとなり現実的ではない。このように、従来のゲート駆動回路においてスイッチングの遅れ時間を短縮し、高速動作させることについては制約があった。 In order to shorten the delay time, these delay factors can be improved. However, the time constant related to the gate capacitance depends on the element manufacturing process, etc., and is in an area that cannot be improved by circuit designers and users. is there. Further, if the voltage of the gate drive power supply 31 is increased, the time until it passes through the threshold voltage can be shortened. However, the upper limit is up to the absolute maximum rating of the gate voltage defined in the data sheet of the element. When a voltage higher than the absolute maximum rating is selected, an overvoltage is constantly applied to the gate while the FET is kept on, which is not realistic. As described above, in the conventional gate drive circuit, there is a restriction on shortening the switching delay time and operating at high speed.

特許文献１では、前記図６のゲート駆動回路の低消費電力化に関する方法を開示している。特許文献１の発明では、前記図６のオン用スイッチ８とオフ用スイッチ９に相当するスイッチにＦＥＴなどの電圧駆動型素子を用い、これらのスイッチのバイアス電圧をターンオン（またはオフ）動作時とオン（またはオフ）保持期間とで変化させ、ゲート駆動回路の低消費電力化を図るものである。すなわち、駆動対象の半導体スイッチ素子のゲートを充放電する期間は、駆動用ＦＥＴのバイアス電圧を高くしオン抵抗の低い領域で使用し、オン・オフ保持期間はゲート電流がほとんど流れず、多少のオン抵抗増加は影響がないので、バイアス電圧を低くして使用することで低消費電力化を図る。
特開２００２−１６５４３５号公報 Patent Document 1 discloses a method related to low power consumption of the gate drive circuit of FIG. In the invention of Patent Document 1, voltage-driven elements such as FETs are used as switches corresponding to the on switch 8 and the off switch 9 in FIG. 6, and the bias voltage of these switches is set at the time of turn-on (or off) operation. The power consumption of the gate driving circuit is reduced by changing the ON (or OFF) holding period. That is, during the period for charging and discharging the gate of the semiconductor switch element to be driven, the bias voltage of the driving FET is increased and used in a region where the on-resistance is low, and the gate current hardly flows during the on / off holding period. Since the increase in on-resistance has no effect, lower power consumption is achieved by using a lower bias voltage.
JP 2002-165435 A

前記特許文献１による方法においても、図６のゲート駆動用電源３１に相当する電源の電圧は、駆動対象の半導体スイッチのゲート電圧絶対最大定格以下で選択せざるを得ず、ゲート駆動回路の低消費電力化に貢献できても、駆動対象の半導体スイッチ素子を高速でスイッチングさせることは期待できない。   Also in the method according to Patent Document 1, the voltage of the power supply corresponding to the gate drive power supply 31 in FIG. 6 must be selected below the absolute maximum rating of the gate voltage of the semiconductor switch to be driven. Even if it can contribute to power consumption, it cannot be expected that the semiconductor switch element to be driven is switched at high speed.

解決しようとする問題点は、ゲートドライブ用電源の電圧を高くすればするほど、ゲートのスレッショルド電圧を通過するまでの時間が短くなり高速スイッチングを実現できるが、絶対最大定格以上の電圧を選択すると、オンまたはオフ保持中は定常的にゲートに過電圧が印加されるため、その上限は絶対最大定格以内で制限されるという点である。   The problem to be solved is that the higher the voltage of the power supply for the gate drive, the shorter the time until it passes through the threshold voltage of the gate, so that high-speed switching can be realized, but if a voltage exceeding the absolute maximum rating is selected Since the overvoltage is constantly applied to the gate while it is on or off, the upper limit is limited within the absolute maximum rating.

本発明は、上記課題を解決するために、請求項１記載の高速ゲート駆動回路は、定格ゲート電圧内の電圧のオン保持用電源と、定格ゲート電圧を越えた電圧のターンオン用電源と、該ターンオン用電源により充電されるターンオン用コンデンサを有し、ターンオン直前までに充電した該ターンオン用コンデンサを前記ターンオン用電源から開放し、前記ターンオン用コンデンサの電荷を半導体スイッチング素子のゲートに印加して高速ターンオンし、ターンオン後は前記オン保持用電源でオン状態を保持する事を特徴とする。   In order to solve the above-mentioned problems, the present invention provides a high-speed gate drive circuit according to claim 1, wherein a power supply for holding on a voltage within a rated gate voltage, a power supply for turning on a voltage exceeding the rated gate voltage, A turn-on capacitor charged by a turn-on power source is provided, the turn-on capacitor charged immediately before turn-on is released from the turn-on power source, and the charge of the turn-on capacitor is applied to the gate of the semiconductor switching element at high speed. The turn-on is performed, and after the turn-on, the on-hold power supply holds the on state.

請求項２記載の高速ゲート駆動回路は、定格ゲート電圧内の電圧のオフ保持用電源と、定格ゲート電圧を越えた電圧のターンオフ用電源と、該ターンオフ用電源により充電されるターンオフ用コンデンサを有し、ターンオン期間中に充電した該ターンオフ用コンデンサをターンオフ直前に前記ターンオフ用電源から開放し、前記ターンオフ用コンデンサの電荷を前記半導体スイッチング素子のゲートに印加して高速ターンオフし、ターンオフ後は前記オフ保持用電源でオフ状態を保持する事を特徴とする。   The high-speed gate driving circuit according to claim 2 includes a power supply for holding off the voltage within the rated gate voltage, a power supply for turning off the voltage exceeding the rated gate voltage, and a turn-off capacitor charged by the power supply for turning off. Then, the turn-off capacitor charged during the turn-on period is released from the turn-off power supply immediately before turn-off, the charge of the turn-off capacitor is applied to the gate of the semiconductor switching element, and the turn-off capacitor is turned off at high speed. It is characterized in that it is kept off by a holding power source.

本発明の高速ゲート駆動回路は、ターンオン（オフ）時に高電圧電源で充電したコンデンサの電荷を駆動対象のゲート容量に流し込むことにより、スレッショルド電圧を高速で通過させる事ができるため、高速でターンオン（オフ）でき、その後は絶対最大定格内のゲート電圧でオン（オフ）状態を保持するため、ゲートに定常的に過電圧を印加しなくてもよいという利点がある。   The high-speed gate drive circuit of the present invention allows the threshold voltage to pass at high speed by flowing the charge of the capacitor charged by the high-voltage power supply into the gate capacitance to be driven at the time of turn-on (off). Since the ON (off) state is maintained at the gate voltage within the absolute maximum rating after that, there is an advantage that it is not necessary to constantly apply an overvoltage to the gate.

ターンオン（オフ）時に、ゲートのスレッショルド電圧を高速で通過させるという目的と、オン（オフ）保持中はゲートに過電圧を印加しないという目的を、従来のゲート駆動回路に若干の回路を追加することで実現した。   By adding a few circuits to the conventional gate drive circuit, the purpose of passing the threshold voltage of the gate at high speed when turning on (off) and the purpose of not applying an overvoltage to the gate while holding on (off) It was realized.

図１は、本発明の請求項１による高速ゲート駆動回路の実施例を示す図である。図１の回路は、駆動対象のＦＥＴ１０と、ターンオン時において一時的に絶対最大定格以上の正バイアス電圧をＦＥＴ１０のゲートに供給するターンオン回路と、オン保持中において絶対最大定格内の正バイアス電圧を供給するオン保持回路と、ＦＥＴ１０のゲート容量を充放電させる充放電用スイッチ群と、これらスイッチのタイミング制御を行うタイミング制御回路から構成される。   FIG. 1 is a diagram showing an embodiment of a high-speed gate driving circuit according to claim 1 of the present invention. The circuit shown in FIG. 1 includes an FET 10 to be driven, a turn-on circuit that temporarily supplies a positive bias voltage that is higher than the absolute maximum rating to the gate of the FET 10 at the time of turn-on, and a positive bias voltage that is within the absolute maximum rating while the switch is on. An ON holding circuit to be supplied, a charging / discharging switch group for charging / discharging the gate capacitance of the FET 10, and a timing control circuit for controlling the timing of these switches.

ターンオン回路は、オフ保持中にターンオン用電源２から充電抵抗３、充電スイッチ４、充電ダイオード５を介してターンオン用コンデンサ７を充電し、ＯＮ指令信号のタイミングでオン用スイッチ８を介してＦＥＴ１０のゲート容量を充電する回路である。ターンオン用電源２は、ターンオン直前に充電スイッチ４によりターンオン用コンデンサ７から開放される。ターンオン用電源２の電圧は、ＦＥＴ１０のゲート絶対最大定格以上の電圧に設定する。オン保持回路は絶対最大定格内に設定したオン保持用電源１から、オン保持用ダイオード６を介してターンオン用コンデンサ７を充電し、この電圧がＦＥＴ１０のスレッショルド電圧以下に低下することを防止している。ゲートの充放電用スイッチ群は、オン用スイッチ８とオフ用スイッチ９とからなり、図６の同符号のものと同一の動作をするものである。 The turn-on circuit charges the turn-on capacitor 7 from the power supply 2 for turn-on through the charging resistor 3, the charge switch 4, and the charging diode 5 while holding off, and the FET 10 is turned on via the switch 8 for turning on at the timing of the ON command signal. This is a circuit for charging the gate capacitance. The turn-on power supply 2 is released from the turn-on capacitor 7 by the charge switch 4 immediately before the turn-on. The voltage of the turn-on power supply 2 is set to a voltage equal to or higher than the gate absolute maximum rating of the FET 10. The on-hold circuit charges the turn-on capacitor 7 from the on-hold power source 1 set within the absolute maximum rating via the on-hold diode 6 to prevent this voltage from dropping below the threshold voltage of the FET 10. Yes. The charging / discharging switch group of the gate includes an on switch 8 and an off switch 9, and performs the same operation as that of the same symbol in FIG.

図２は図１の高速ゲート駆動回路の動作タイミングを示すチャートである。図２を用いて図１の回路の動作を詳細に説明する。
図２のＯＮ指令信号は正論理信号で図１のタイミング制御回路１１に入力される信号である。図２のＳＣＨ１、Ｓ１、Ｓ２は、それぞれ図１の充電スイッチ４、オン用スイッチ８、オフ用スイッチ９の状態を示すものであり、正論理で動作するものである。図２のＶＣ１は図１のターンオン用コンデンサ７の電圧を示すものであり、電圧レベルＶＤ２は図１のターンオン用電源２の電圧を示し、ＶＤ１は同じくオン保持用電源１の電圧を示す。図２のＶＧＳは、図１のＦＥＴ１０のゲート−ソース間電圧を示すものであり、電圧レベルは前記のＶＣ１と同一である。図２のＦＥＴは、図１のＦＥＴ１０の状態を示すものである。 FIG. 2 is a chart showing the operation timing of the high-speed gate drive circuit of FIG. The operation of the circuit of FIG. 1 will be described in detail with reference to FIG.
The ON command signal shown in FIG. 2 is a positive logic signal that is input to the timing control circuit 11 shown in FIG. S CH1, S 1, S 2 in FIG. 2, the charging switch 4 of FIG. 1, respectively, on switch 8, which shows the OFF switch 9, and operates in positive logic. V C1 in FIG. 2 indicates the voltage of the turn-on capacitor 7 in FIG. 1, the voltage level V D2 indicates the voltage of the turn-on power source 2 in FIG. 1, and V D1 similarly indicates the voltage of the on-hold power source 1. Show. V GS in FIG. 2 indicates the gate-source voltage of the FET 10 in FIG. 1, and the voltage level is the same as V C1 described above. The FET of FIG. 2 shows the state of the FET 10 of FIG.

所望のタイミングでＯＮ指令信号を０→１へ変化させると、ＳＣＨ１はオン→オフになり、図１のターンオン用コンデンサ７はターンオン用電源から解放される。このタイミングからわずかに遅れてＳ１がオフ→オンになり、図１のターンオン用コンデンサ７の電荷がＦＥＴ１０のゲートへ転送され始め、ＶＧＳの電圧が急激に上昇しＦＥＴ１０を高速にターンオンさせる。この際、図１のターンオン用コンデンサ７の充電電荷（ＶＤ２とＣ１の積）とＦＥＴ１０のゲート総電荷量を同程度〜２倍程度に設定すると、電荷の転送に伴いＶＣ１は低下し、ＶＤ１を下回るとオン保持用ダイオード６が導通し、ＶＧＳをＶＤ１に保持するためオン状態が維持される。 When the ON command signal is changed from 0 to 1 at a desired timing, SCH1 is turned from ON to OFF, and the turn-on capacitor 7 in FIG. 1 is released from the turn-on power source. The S 1 with a slight delay from the timing is off → on, the charge of the turn-on capacitor 7 in FIG. 1 starts to be transferred to the gate of FET10, voltage V GS is turning sharply elevated FET10 fast. At this time, if the charge (the product of V D2 and C 1 ) of the turn-on capacitor 7 in FIG. 1 and the total gate charge of the FET 10 are set to about the same or twice, V C1 decreases as the charge is transferred. When V D1 falls below V D1 , the on-holding diode 6 conducts, and V GS is held at V D1 , so that the on state is maintained.

図１、図２の実施例では、ターンオン用コンデンサの容量を適切に設定することにより、一時的にゲート−ソース間に高い正バイアス電圧を印加することで高速ターンオンを実現し、なおかつターンオン後は適切なオン保持電圧を印加できるものである。高速ターンオンを実現することで、駆動対象のＦＥＴ等のターンオン損失が低減でき、またパルスパワー電源などパルス電圧の高速立上りを要求される用途において、実用上大いに役立つ。   In the embodiment of FIGS. 1 and 2, by setting the capacitance of the turn-on capacitor appropriately, a high positive bias voltage is temporarily applied between the gate and the source to realize high-speed turn-on, and after turn-on, An appropriate on-hold voltage can be applied. By realizing the high-speed turn-on, the turn-on loss of the FET to be driven can be reduced, and it is greatly useful in practice in applications that require a high-speed rise of the pulse voltage such as a pulse power supply.

図３は本発明の請求項２による高速ゲート駆動回路の実施例を示す図である。図３は実施例１の回路に請求項２の実施例を追加したものであり、ターンオンとターンオフを高速化するための高速ゲート駆動回路である。
図３の回路は、駆動対象のＦＥＴ１０と、ターンオン時において一時的に絶対最大定格以上の正バイアス電圧をＦＥＴ１０のゲートに供給するターンオン回路と、オン保持中において絶対最大定格内の正バイアス電圧を供給するオン保持回路と、ターンオフ時において一時的に絶対最大定格以上の逆バイアス電圧をＦＥＴ１０のゲートに供給するターンオフ回路と、オフ保持中に絶対最大定格内の逆バイアス電圧を供給するオフ保持回路と、ＦＥＴ１０のゲート容量を充放電させる充放電用スイッチ群と、これらスイッチのタイミング制御を行うタイミング制御回路から構成される。 FIG. 3 is a diagram showing an embodiment of a high-speed gate driving circuit according to claim 2 of the present invention. FIG. 3 is a circuit in which the embodiment of claim 2 is added to the circuit of the embodiment 1, and is a high-speed gate drive circuit for speeding up the turn-on and turn-off.
The circuit of FIG. 3 includes an FET 10 to be driven, a turn-on circuit that temporarily supplies a positive bias voltage higher than the absolute maximum rating to the gate of the FET 10 at turn-on, and a positive bias voltage within the absolute maximum rating during ON-holding. An on-hold circuit for supplying, a turn-off circuit for temporarily supplying a reverse bias voltage exceeding the absolute maximum rating to the gate of the FET 10 at the time of turn-off, and an off-hold circuit for supplying a reverse bias voltage within the absolute maximum rating during off-holding And a charging / discharging switch group for charging / discharging the gate capacitance of the FET 10, and a timing control circuit for controlling the timing of these switches.

ターンオン回路のターンオン用電源２、充電抵抗３、充電スイッチ４、充電ダイオード５、ターンオン用コンデンサ７、オン用スイッチ８、オン保持回路のオン保持用電源１、オン保持用ダイオード６の各部品は実施例１の図１と同一であり、動作も同一なので説明を省略する。ターンオフ回路は、オン保持中にターンオフ用電源２２から充電抵抗２３、充電スイッチ２４、充電ダイオード２５を介してターンオフ用コンデンサ２７を充電し、ＯＮ指令信号のオフのタイミングでオフ用スイッチ９を介してＦＥＴ１０のゲート容量を放電・負の電圧に充電する回路である。ターンオフ用電源２２は、ターンオフ直前に充電スイッチ２４によりターンオフ用コンデンサ２７から開放される。ターンオフ用電源２１の電圧は、ＦＥＴ１０のゲート絶対最大定格以上の電圧に設定する。オフ保持回路は絶対最大定格内に設定したオフ保持用電源２１から、オフ保持用ダイオード２６を介してターンオフ用コンデンサ２７を充電し、この電圧がＦＥＴ１０のスレッショルド電圧以上になることを防止している。   The turn-on circuit power supply 2, charging resistor 3, charging switch 4, charging diode 5, turn-on capacitor 7, turn-on switch 8, on-holding circuit on-holding power source 1, on-holding diode 6 are implemented. Since it is the same as FIG. 1 of Example 1 and the operation is the same, the description is omitted. The turn-off circuit charges the turn-off capacitor 27 from the turn-off power source 22 through the charging resistor 23, the charge switch 24, and the charging diode 25 while the power is on, and the turn-off circuit passes through the turn-off switch 9 at the turn-off timing of the turn-on command signal. This is a circuit for discharging the gate capacitance of the FET 10 to a negative voltage. The turn-off power supply 22 is released from the turn-off capacitor 27 by the charge switch 24 immediately before the turn-off. The voltage of the turn-off power supply 21 is set to a voltage equal to or higher than the gate absolute maximum rating of the FET 10. The off-holding circuit charges the turn-off capacitor 27 from the off-holding power supply 21 set within the absolute maximum rating via the off-holding diode 26, and prevents this voltage from exceeding the threshold voltage of the FET 10. .

図４は図３の高速ゲート駆動回路の動作タイミングを示すチャートである。図４を用いて図３の回路の動作を詳細に説明する。
図４のＯＮ指令信号、ＳＣＨ１、Ｓ１、Ｓ２、ＶＣ１は、実施例１の図２の記号と同一であり、ＳＣＨ２は図３の充電スイッチ２４の状態を示すものである。図４のＶＣ２は、図３のターンオフ用コンデンサ２７の電圧を示すものであり、電圧レベルＶＤ４、ＶＤ３はそれぞれ図３のターンオフ用電源２２、オフ保持用電源２１の電圧を示す。図４のＶＧＳはＦＥＴ１０のゲート−ソース間電圧を示すものであり、電圧レベルＶＤ２、ＶＤ１はそれぞれターンオン用電源２、オン保持用電源１の電圧である。図４のＦＥＴは、図３のＦＥＴ１０の状態を示すものである。 FIG. 4 is a chart showing the operation timing of the high-speed gate driving circuit of FIG. The operation of the circuit of FIG. 3 will be described in detail with reference to FIG.
The ON command signals S CH1 , S 1 , S 2 , and V C1 in FIG. 4 are the same as the symbols in FIG. 2 of the first embodiment, and S CH2 indicates the state of the charge switch 24 in FIG. V C2 of FIG. 4 shows the voltage of the turn-off capacitor 27 of FIG. 3, the turn-off power source 22 for the voltage level V D4, V D3 respectively Figure 3 shows the voltage of the off-holding power source 21. V GS is the gate of FET10 in Figure 4 - is indicative of the source voltage, the voltage level V D2, V D1 each turn-on power source 2, the voltage of the on-hold power supply 1. The FET of FIG. 4 shows the state of the FET 10 of FIG.

オン保持中、所望のタイミングでＯＮ指令信号を１→０へ変化させると、ＳＣＨ２はオン→オフになり、図３の充電が完了したターンオフ用コンデンサ２７は、ターンオフ用電源２２から開放される。このタイミングからわずかに遅れてＳ２がオフ→オンになり、図３のターンオフ用コンデンサ２７の負の電荷がＦＥＴ１０のゲートへ転送され始め、ＶＧＳの電圧が急激に下降しＦＥＴ１０を高速にターンオフさせる。この際、図３のターンオフ用コンデンサ２７の充電電荷（ＶＤ４とＣ２の積）とＦＥＴ１０のゲート総電荷量を同程度〜２倍程度に設定すると、電荷の転送に伴いＶＣ２は低下し、ＶＤ３を下回るとオフ保持用ダイオード２６が導通し、ＶＧＳを−ＶＤ３に保持するためオフ状態が維持される。 When the ON command signal is changed from 1 to 0 at a desired timing while the ON state is maintained, SCH2 is turned ON to OFF, and the turn-off capacitor 27 in FIG. . S 2 is turned off → on with a slight delay from this timing, the negative charge of the turn-off capacitor 27 in FIG. 3 starts to be transferred to the gate of the FET 10, the voltage of V GS drops rapidly, and the FET 10 is turned off at high speed. Let At this time, if the charge (the product of V D4 and C 2 ) of the turn-off capacitor 27 in FIG. 3 and the total gate charge of the FET 10 are set to about the same or about twice, V C2 decreases as the charge is transferred. When the voltage drops below V D3 , the off-holding diode 26 is turned on, and V GS is held at −V D3 , so that the off state is maintained.

図３、図４の実施例では、ターンオフ用コンデンサの容量を適切に設定することにより、一時的にゲート−ソース間に高い逆バイアス電圧を印加することで高速ターンオフを実現し、なおかつターンオフ後は適切なオフ保持電圧を印加できるものである。高速ターンオフを実現することで、駆動対象のＦＥＴ等のターンオフ損失が低減でき、実用上大いに役立つ。 In the embodiment of FIGS. 3 and 4, by setting the capacitance of the turn-off capacitor appropriately, a high reverse bias voltage is temporarily applied between the gate and the source to realize high-speed turn-off, and after turn-off, An appropriate off-holding voltage can be applied. By realizing high-speed turn-off, the turn-off loss of the FET to be driven can be reduced, which is very useful in practice.

インバータ等のスイッチング素子駆動用に適用することで、スイッチング損失を低減できる。また、パルスパワー電源等のパルスの高速立上りを要求される装置のスイッチング素子駆動方法として適用しても有効である。   Switching loss can be reduced by applying to driving a switching element such as an inverter. Further, the present invention is also effective when applied as a switching element driving method for a device that requires high-speed rising of a pulse such as a pulse power supply.

請求項１の高速ゲート駆動回路の実施例を示した回路図である。（実施例１）FIG. 3 is a circuit diagram showing an embodiment of a high-speed gate driving circuit according to claim 1. Example 1 図１の回路の動作タイミングを示したチャートである。（実施例１）2 is a chart showing operation timing of the circuit of FIG. 1. Example 1 請求項２の高速ゲート駆動回路の実施例を示した回路図である。（実施例２）FIG. 3 is a circuit diagram showing an embodiment of a high-speed gate driving circuit according to claim 2. (Example 2) 図２の回路の動作タイミングを示したチャートである。（実施例２）3 is a chart showing operation timing of the circuit of FIG. 2. (Example 2) ＭＯＳＦＥＴの等価回路を示した図である。It is the figure which showed the equivalent circuit of MOSFET. 従来のゲート駆動回路を示した回路図である。It is a circuit diagram showing a conventional gate drive circuit. 従来のゲート駆動波形例を示した図ある。It is the figure which showed the example of the conventional gate drive waveform.

符号の説明Explanation of symbols

１ オン保持用電源
２ ターンオン用電源
３ 充電抵抗
４ 充電スイッチ
５ 充電ダイオード
６ オン保持用ダイオード
７ ターンオン用コンデンサ
８ オン用スイッチ
９ オフ用スイッチ
１０ ＦＥＴ
１１ タイミング制御回路
２１ オフ保持用電源
２２ ターンオフ用電源
２３ 充電抵抗
２４ 充電スイッチ
２５ 充電ダイオード
２６ オフ保持用ダイオード
２７ ターンオフ用コンデンサ
２８ タイミング制御回路
３１ ゲートドライブ電源
３２ タイミング制御回路 DESCRIPTION OF SYMBOLS 1 Power supply for ON 2 Power supply for turn ON 3 Charging resistor 4 Charging switch 5 Charging diode 6 Diode for holding ON 7 Capacitor for turn ON 8 Switch for ON 9 Switch for OFF 10 FET
DESCRIPTION OF SYMBOLS 11 Timing control circuit 21 Turn-off power supply 22 Turn-off power supply 23 Charging resistor 24 Charge switch 25 Charging diode 26 Off-hold diode 27 Turn-off capacitor 28 Timing control circuit 31 Gate drive power supply 32 Timing control circuit

Claims (2)

ＭＯＳＦＥＴ等の絶縁ゲート構造を持つ半導体スイッチング素子を駆動するゲート駆動回路において、定格ゲート電圧内の電圧のオン保持用電源と、定格ゲート電圧を越えた電圧のターンオン用電源と、該ターンオン用電源により充電されるターンオン用コンデンサを有し、ターンオン直前までに充電した該ターンオン用コンデンサを前記ターンオン用電源から開放し、前記コンデンサの電荷を半導体スイッチング素子のゲートに印加して高速ターンオンし、ターンオン後は前記オン保持用電源でオン状態を保持する事を特徴とする高速ゲート駆動回路。
In a gate drive circuit for driving a semiconductor switching element having an insulated gate structure such as a MOSFET, a power supply for holding on a voltage within the rated gate voltage, a power supply for turning on a voltage exceeding the rated gate voltage, and the power supply for turning on It has a turn-on capacitor to be charged, releases the turn-on capacitor charged immediately before the turn-on from the turn-on power supply, applies a charge of the capacitor to the gate of the semiconductor switching element, and turns on at high speed. A high-speed gate driving circuit, wherein the on-hold power supply holds an on state.
ＭＯＳＦＥＴ等の絶縁ゲート構造を持つ半導体スイッチング素子を駆動するゲート駆動回路において、定格ゲート電圧内の電圧のオフ保持用電源と、定格ゲート電圧を越えた電圧のターンオフ用電源と、該ターンオフ用電源により充電されるターンオフ用コンデンサを有し、ターンオン期間中に充電した該コンデンサをターンオフ直前に前記ターンオフ用電源から開放し、前記ターンオフ用コンデンサの電荷を前記半導体スイッチング素子のゲートに印加して高速ターンオフし、ターンオフ後は前記オフ保持用電源でオフ状態を保持する事を特徴とする高速ゲート駆動回路。 In a gate drive circuit for driving a semiconductor switching element having an insulated gate structure such as a MOSFET, a power supply for holding off the voltage within the rated gate voltage, a power supply for turning off the voltage exceeding the rated gate voltage, and the power supply for turning off A turn-off capacitor to be charged is provided, and the capacitor charged during the turn-on period is released from the turn-off power supply immediately before the turn-off, and the charge of the turn-off capacitor is applied to the gate of the semiconductor switching element for fast turn-off. The high-speed gate driving circuit is characterized in that the off state is maintained by the off-holding power source after the turn-off.
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