JP2007149792A - Semiconductor wafer and manufacturing method of semiconductor device - Google Patents

Semiconductor wafer and manufacturing method of semiconductor device Download PDF

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JP2007149792A
JP2007149792A JP2005339542A JP2005339542A JP2007149792A JP 2007149792 A JP2007149792 A JP 2007149792A JP 2005339542 A JP2005339542 A JP 2005339542A JP 2005339542 A JP2005339542 A JP 2005339542A JP 2007149792 A JP2007149792 A JP 2007149792A
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electrode pad
semiconductor
layer
wiring layer
semiconductor wafer
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Takeshi Matsumoto
健 松本
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract

<P>PROBLEM TO BE SOLVED: To avoid electric leakage caused by a winding abnormality of an electrode pad of a PCM and a bump on the electrode pad generated in accordance with a dicing process. <P>SOLUTION: The electrode pad is formed only of the lowermost layer or a lower-layer wiring layer by using a process where the wiring layer is formed in multilayers on a scribe. The bumps are formed on the electrode pad to a degree that no protective film projects on the electrode pad. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は半導体拡散工程の評価用にスクライブ領域にプロセス・コントロール・モジュールが形成された半導体ウエハと、この半導体ウエハから切り出してチップ状に分割して製造される半導体装置の製造方法に関するものである。   The present invention relates to a semiconductor wafer having a process control module formed in a scribe region for evaluation of a semiconductor diffusion process, and a method of manufacturing a semiconductor device cut out from the semiconductor wafer and divided into chips. .

本発明の半導体装置、特に半導体装置に使用される電極パッドについて従来例を説明する前に本技術の背景について説明する。
半導体装置は図７（ａ）に示すように、ウエハ１上に、拡散工程と呼ばれる製造工程を経ることで多数の半導体装置２の形成を行い、その後に、図７（ｂ）に示すようにウエハ１から半導体装置２をチップ状に切り出し、パッケージングされる。３はスクライブ領域と呼ばれる「切り代」部分である。 The background of the present technology will be described before a conventional example of a semiconductor device of the present invention, particularly an electrode pad used in the semiconductor device.
As shown in FIG. 7A, the semiconductor device forms a large number of semiconductor devices 2 on a wafer 1 through a manufacturing process called a diffusion process, and thereafter, as shown in FIG. 7B. The semiconductor device 2 is cut out from the wafer 1 into chips and packaged. Reference numeral 3 denotes a “cutting margin” portion called a scribe area.

半導体装置２の拡散工程の出来映え評価としてのプロセス・コントロール・モジュール（Process・Control・Module、以下、ＰＣＭと称す）４が、図７（ｃ）に示すようにスクライブ領域３に形成されている。ＰＣＭ４の測定によって得られたデータを収集管理し、結果を拡散工程にフィードバックすることにより、デバイスや拡散工程を最適に維持管理して、歩留と品質を向上させている。   As shown in FIG. 7C, a process control module (hereinafter referred to as PCM) 4 is formed in the scribe region 3 as an evaluation of the workmanship of the diffusion process of the semiconductor device 2. By collecting and managing data obtained by measurement of PCM4 and feeding back the results to the diffusion process, the device and the diffusion process are optimally maintained and managed to improve yield and quality.

図８（ａ）はこのスクライブ領域３に形成されたＰＣＭ４の電極パッドの断面を示したもので、ウエハ１の上に、第１層電極パッド５、第２層電極パッド６、第３層電極パッド７の３層の電極パッドを重ねた状態で形成されており、各層上に第１層保護膜５ａ、第２層保護膜６ａ、第３層保護膜７ａが形成されている。   FIG. 8A shows a cross section of the electrode pad of the PCM 4 formed in the scribe region 3. The first layer electrode pad 5, the second layer electrode pad 6, the third layer electrode are formed on the wafer 1. The pad 7 is formed in a state where three electrode pads are overlapped, and a first layer protective film 5a, a second layer protective film 6a, and a third layer protective film 7a are formed on each layer.

さらに、図８（ｂ）は別の例で、図８（ａ）で示したＰＣＭ４の第３層電極パッド７にバンプ８を形成した状態を示している。通常、このバンプ８は無電解めっきで形成される。   Further, FIG. 8B shows another example in which bumps 8 are formed on the third-layer electrode pads 7 of the PCM 4 shown in FIG. 8A. Usually, the bumps 8 are formed by electroless plating.

図９（ａ），図９（ｂ）は図８（ｂ）で示したＰＣＭ４付きのウエハ１から半導体装置２をチップ状に切り出すダイシング工程を示している。
図９（ａ）に仮想線で示すダイシングカッター９を用いてスクライブ領域３（同時にＰＣＭ４や３層の電極パッド）をカットして、図９（ｂ）に示すようにウエハ１からチップ状の半導体装置２を切り出している。 FIGS. 9A and 9B show a dicing process for cutting the semiconductor device 2 into chips from the wafer 1 with the PCM 4 shown in FIG. 8B.
A scribe region 3 (PCM 4 or three-layer electrode pad at the same time) is cut using a dicing cutter 9 indicated by a virtual line in FIG. 9A, and a chip-like semiconductor is formed from the wafer 1 as shown in FIG. 9B. The apparatus 2 is cut out.

なお、（特許文献１）にはバンプを保護膜以下の高さにして形成する技術が記載されている。
特開２００４−１７９６３５公報 Incidentally, (Patent Document 1) describes a technique for forming bumps with a height equal to or lower than that of the protective film.
JP 2004-179635 A

しかしながら、図８（ａ），図８（ｂ）に示す従来のＰＣＭ付きの半導体ウエハには、以下に示す２点の問題がある。
図１０（ａ）に示すようにダイシングカッター９を用いてスクライブ領域３（同時にＰＣＭ４や３層の電極パッド）をカットする。しかしそのダイシングカッター９がずれた場合、図１０（ｂ）のように電極パッド、特に第３層電極パッド７が捲れ上がる異常が発生する。 However, the conventional semiconductor wafer with PCM shown in FIGS. 8A and 8B has the following two problems.
As shown in FIG. 10A, the scribe region 3 (PCM 4 and three layers of electrode pads at the same time) is cut using a dicing cutter 9. However, when the dicing cutter 9 is displaced, an abnormality occurs in which the electrode pad, particularly the third layer electrode pad 7 is rolled up as shown in FIG.

このように半導体装置２を切り出す時に導電性のある第３層電極パッド７が捲れ上がると、後の組立工程でパッケージングを行った場合、この「捲れ上がった電極パッド」部分より電気的なリークなどが発生するおそれがある。   When the conductive third-layer electrode pad 7 is rolled up when the semiconductor device 2 is cut out in this way, when packaging is performed in a later assembly process, an electrical leakage occurs from the “swollen electrode pad” portion. May occur.

図１１（ａ），図１１（ｂ）は図９（ａ），図９（ｂ）と同様に図８（ｂ）で示した３層の電極パッドを重ねたＰＣＭの電極パッド上にバンプ８を形成したものをダイシングした時のフローについて示したものである。   11A and 11B show bumps 8 on the electrode pads of the PCM in which the three-layer electrode pads shown in FIG. 8B are overlaid as in FIGS. 9A and 9B. It shows the flow when dicing the one formed.

図１０では電極パッド上にバンプ８が形成されていない場合ダイシングであったが、図１１（ａ）に示すように電極パッド上にバンプ８が形成されている場合には、ダイシングカッター９による切断位置がずれた場合には、図１１（ｂ）に示すようにエッジ部分にバンプ８の一部が残留する異常が発生する。   In FIG. 10, the dicing is performed when the bump 8 is not formed on the electrode pad. However, when the bump 8 is formed on the electrode pad as shown in FIG. When the position is shifted, an abnormality in which a part of the bump 8 remains at the edge portion as shown in FIG. 11B occurs.

このようにバンプ８がエッジ部分に残留すると、後の組立工程でパッケージングを行った場合、この「残留したバンプ」部分より電気的なリークなどが発生するおそれがある。
図１０におけるダイシングに伴う第３層電極パッド７の捲れ上がりや、図１１におけるダイシングに伴うエッジ部分でのバンプ８の残留を解消するためには、図１２（ａ）に示すように幅広のダイシングカッター９を用いてスクライブ領域３（同時にＰＣＭ４や３層の電極パッド、バンプ８）をカットして、図１２（ｂ）に示すように、第３層電極パッド７の捲れ上がりや、エッジ部分でのバンプ８の残留がない半導体装置２を切り出すことができるが、この場合には、ダイシングカッター９の幅、すなわち「切り代」の幅を大きくするために、その広くした分だけスクライブ領域３の幅を広くする必要がある。そうするとウエハ中のスクライブ領域３の面積が広くなり、逆に半導体装置２を形成する面積が小さくなり、半導体装置の取れ数が減ってしまう別の問題がある。 If the bumps 8 remain in the edge portion in this way, when packaging is performed in a later assembly process, there is a possibility that electrical leakage or the like may occur from the “remaining bump” portion.
In order to eliminate the rolling-up of the third-layer electrode pad 7 due to dicing in FIG. 10 and the remaining of the bumps 8 at the edge portion due to dicing in FIG. 11, wide dicing as shown in FIG. Cut the scribe region 3 (PCM 4 and the three-layer electrode pads and bumps 8 at the same time) using the cutter 9, and as shown in FIG. However, in this case, in order to increase the width of the dicing cutter 9, that is, the width of the “cutting margin”, the scribe region 3 is increased by the increased width. It is necessary to widen the width. This increases the area of the scribe region 3 in the wafer, conversely reduces the area where the semiconductor device 2 is formed, and reduces the number of semiconductor devices that can be taken.

本発明は、ダイシングに伴って「捲れ上がった電極パッド」や「残留したバンプ」が発生せず、加えて半導体装置の取れ数を落とすことの無い構造のＰＣＭ付き半導体ウエハ、ならびに半導体装置の製造方法を提供することを目的とする。   The present invention provides a semiconductor wafer with PCM having a structure that does not cause “swelled electrode pads” and “remaining bumps” with dicing, and does not reduce the number of semiconductor devices, and the manufacture of the semiconductor devices. It aims to provide a method.

本発明の半導体ウエハは、半導体拡散工程の評価用にスクライブ領域にプロセス・コントロール・モジュールが形成された半導体ウエハであって、プロセス・コントロール・モジュールは、ウエハの上に形成された多層の配線層のうちで最上層の配線層よりも下層の配線層だけで電極パッドを形成したことを特徴とする。また、前記電極パッドの上に保護膜からはみ出ない程度にバンプを形成したことを特徴とする。   The semiconductor wafer of the present invention is a semiconductor wafer in which a process control module is formed in a scribe region for evaluation of a semiconductor diffusion process, and the process control module has a multilayer wiring layer formed on the wafer. Of these, the electrode pad is formed only with the lower wiring layer than the uppermost wiring layer. Further, a bump is formed on the electrode pad so as not to protrude from the protective film.

また、本発明の半導体ウエハは、半導体拡散工程の評価用にスクライブ領域にプロセス・コントロール・モジュールが形成された半導体ウエハであって、プロセス・コントロール・モジュールは、ウエハの上に形成された多層の配線層のうちで少なくとも最上層の配線層を取り除いて露出した下層の配線層を電極パッドとしたことを特徴とする。また、前記電極パッドの上に保護膜からはみ出ない程度にバンプを形成したことを特徴とする。   The semiconductor wafer of the present invention is a semiconductor wafer in which a process control module is formed in a scribe region for evaluation of a semiconductor diffusion process, and the process control module is a multilayer wafer formed on the wafer. The lower wiring layer exposed by removing at least the uppermost wiring layer among the wiring layers is used as an electrode pad. Further, a bump is formed on the electrode pad so as not to protrude from the protective film.

また、本発明の半導体装置の製造方法は、半導体拡散工程の評価用にスクライブ領域にプロセス・コントロール・モジュールが形成された半導体ウエハを製造し、この半導体ウエハから半導体装置を切り出すに際し、プロセス・コントロール・モジュールは、ウエハの上に形成された多層の配線層のうちで最上層の配線層よりも下層の配線層だけで電極パッドを形成し、前記スクライブ領域の位置を切断することを特徴とする。また、前記電極パッドの上に保護膜からはみ出ない程度にバンプを形成し、前記スクライブ領域の位置を切断することを特徴とする。   In addition, the semiconductor device manufacturing method of the present invention manufactures a semiconductor wafer having a process control module formed in a scribe region for evaluation of a semiconductor diffusion process, and cuts out the semiconductor device from the semiconductor wafer. The module is characterized in that an electrode pad is formed only with a wiring layer lower than the uppermost wiring layer among the multilayer wiring layers formed on the wafer, and the position of the scribe region is cut. . Further, a bump is formed on the electrode pad so as not to protrude from the protective film, and the position of the scribe region is cut.

また、本発明の半導体装置の製造方法は、半導体拡散工程の評価用にスクライブ領域にプロセス・コントロール・モジュールが形成された半導体ウエハを製造し、この半導体ウエハから半導体装置を切り出すに際し、プロセス・コントロール・モジュールは、ウエハの上に形成された多層の配線層のうちで少なくとも最上層の配線層を取り除いて露出した下層の配線層を電極パッドとし、前記スクライブ領域の位置を切断することを特徴とする。また、前記電極パッドの上に保護膜からはみ出ない程度にバンプを形成し、前記スクライブ領域の位置を切断することを特徴とする。   In addition, the semiconductor device manufacturing method of the present invention manufactures a semiconductor wafer having a process control module formed in a scribe region for evaluation of a semiconductor diffusion process, and cuts out the semiconductor device from the semiconductor wafer. The module is characterized in that at least the uppermost wiring layer of the multilayer wiring layers formed on the wafer is removed and an exposed lower wiring layer is used as an electrode pad, and the position of the scribe region is cut. To do. Further, a bump is formed on the electrode pad so as not to protrude from the protective film, and the position of the scribe region is cut.

この構成によると、従来の構造の問題点であった、ダイシングの際「捲れ上がった電極パッド」や「残留したバンプ」が発生しなくなる。加えて従来の問題点であったスクライブ領域を広くすることで半導体装置の取れ数を落とすことについての対策も可能となる。   According to this configuration, “swelled electrode pads” and “remaining bumps” are not generated during dicing, which is a problem of the conventional structure. In addition, it is possible to take measures against the reduction of the number of semiconductor devices by widening the scribe region, which has been a problem in the past.

本発明の各実施の形態を図１〜図６に基づいて説明する。
なお、図７〜図１２と同様の作用を成すものには同一の符号を付けて説明する。
（実施の形態１）
図１と図２は本発明の（実施の形態１）を示す。 Embodiments of the present invention will be described with reference to FIGS.
In addition, the same code | symbol is attached | subjected and demonstrated to what comprises the effect | action similar to FIGS.
(Embodiment 1)
1 and 2 show (Embodiment 1) of the present invention.

図１（ａ）〜図１（ｃ）は半導体ウエハの前記スクライブ領域３に形成されたＰＣＭの電極パッドの形状およびそのダイシング工程のフローについて示したものである。本例は３層で配線層を形成した場合の半導体装置を示したものである。   FIG. 1A to FIG. 1C show the shape of the PCM electrode pad formed in the scribe region 3 of the semiconductor wafer and the flow of the dicing process. This example shows a semiconductor device in which a wiring layer is formed of three layers.

図１（ａ）に示すように、ＰＣＭ４の電極パッドは第１層電極パッド５のみで形成しており、第２層および第３層の電極パッドは形成しない形状になっている。その後、図１（ｂ）に示すようにダイシングカッター９を用いてスクライブ領域３（同時にＰＣＭ４や電極パッド）をカットして図１（ｃ）に示すように半導体装置２を切り出す。   As shown in FIG. 1A, the electrode pad of the PCM 4 is formed by only the first layer electrode pad 5, and the second and third layer electrode pads are not formed. After that, as shown in FIG. 1B, the scribe region 3 (PCM 4 and electrode pad at the same time) is cut using a dicing cutter 9 to cut out the semiconductor device 2 as shown in FIG.

ここで、ダイシングカッター９が図２（ａ）に示すようにずれた場合には、図２（ｂ）に示すように第１層電極パッド５が捲れ上がる異常が発生するが、この実施の形態の場合には、第２，３層の電極パッドを形成していない上に第１，第２，第３層の保護膜５ａ，６ａ，７ａの厚みがあるため、捲れ上がった第１層電極パッド５の先端が半導体装置２の表面上に露出しない。したがって、後の組立工程でパッケージングを行った場合に、この「捲れ上がった電極パッド」部分より電気的なリークなどが発生しない。   Here, when the dicing cutter 9 is displaced as shown in FIG. 2A, an abnormality in which the first layer electrode pad 5 is rolled up as shown in FIG. 2B occurs. In this case, the second and third layer electrode pads are not formed and the thicknesses of the first, second and third layer protective films 5a, 6a and 7a are increased. The tip of the pad 5 is not exposed on the surface of the semiconductor device 2. Therefore, when packaging is performed in the subsequent assembly process, no electrical leakage or the like occurs from the “swelled electrode pad” portion.

なお、この実施の形態では３層で配線層を形成した半導体ウエハの場合を例に挙げて説明したが、配線層の数が３層に限定されるものではなく、ウエハ１の上に形成された多層の配線層のうちで最上層の配線層よりも下層の配線層だけで電極パッドを形成したＰＣＭ付きの半導体ウエハであると言える。このことは以下の実施の形態においても同様である。   In this embodiment, the case of a semiconductor wafer in which three wiring layers are formed has been described as an example. However, the number of wiring layers is not limited to three, and is formed on the wafer 1. It can be said that this is a semiconductor wafer with PCM in which electrode pads are formed only by a wiring layer lower than the uppermost wiring layer among the multilayer wiring layers. The same applies to the following embodiments.

（実施の形態２）
図３〜図５は本発明の（実施の形態２）を示す。
この（実施の形態２）の半導体ウエハは、図１（ａ）に示した（実施の形態１）の第１層電極パッド５の上に、図３（ａ）に示すようにバンプ８を無電解めっきなどで形成してＰＣＭを形成したものである。その他は（実施の形態１）と同じであって、図１（ｂ）に相当する図３（ｂ）においてダイシングカッター９を用いてスクライブ領域３（同時にＰＣＭ４や電極パッドやバンプ８）をカットして、図３（ｃ）に示すように半導体装置２を切り出す。 (Embodiment 2)
3 to 5 show (Embodiment 2) of the present invention.
The semiconductor wafer of this (Embodiment 2) has no bumps 8 on the first layer electrode pad 5 of (Embodiment 1) shown in FIG. 1A as shown in FIG. The PCM is formed by electrolytic plating or the like. Others are the same as in the first embodiment, and in FIG. 3 (b) corresponding to FIG. 1 (b), the scribe region 3 (PCM 4, electrode pads, and bumps 8) is cut using the dicing cutter 9. Then, the semiconductor device 2 is cut out as shown in FIG.

なお、ここでバンプ８の厚みは、上面の位置が第３層保護膜７ａよりも低くなるように形成されている。
このように構成したため、図４（ａ）に示すようにダイシングカッター９の位置がずれた場合には、残留した一部のバンプ８が半導体装置２のエッジ部分に残留するが、第２，３層の電極パッドを形成していない上に第１，第２，第３層の保護膜の厚みがあるため、残留したバンプ８が半導体装置２の表面上に露出しない。 Here, the thickness of the bump 8 is formed so that the position of the upper surface is lower than that of the third layer protective film 7a.
With this configuration, when the position of the dicing cutter 9 is shifted as shown in FIG. 4A, some remaining bumps 8 remain on the edge portion of the semiconductor device 2, but the second and third The remaining bumps 8 are not exposed on the surface of the semiconductor device 2 due to the thickness of the first, second and third layer protective films on which the electrode pads of the layers are not formed.

したがって、残留した一部のバンプ８が半導体装置２のエッジ部分に残留しても、後の組立工程でパッケージングを行った場合、この「残留したバンプ」部分より電気的なリークなどが発生するおそれがない。   Therefore, even if some of the remaining bumps 8 remain on the edge portion of the semiconductor device 2, when packaging is performed in a later assembly process, electrical leakage or the like occurs from the “remaining bump” portion. There is no fear.

図５は従来例との比較図で、図５（ａ）は図９（ａ）に示した従来のＰＣＭ付き半導体ウエハを示し、図５（ｂ）は（実施の形態２）の構造のＰＣＭ付き半導体ウエハを示している。   FIG. 5 is a comparison diagram with the conventional example, FIG. 5 (a) shows the conventional semiconductor wafer with PCM shown in FIG. 9 (a), and FIG. 5 (b) shows the PCM having the structure of (Embodiment 2). The attached semiconductor wafer is shown.

この図５（ａ）と図５（ｂ）を比較して分かるように、第１層電極パッド５やバンプ８を残さないように幅広のダイシングカッター９を用いてスクライブ領域３（同時にＰＣＭ４や３層の電極パッド、バンプ８）をカットする場合にも、図５（ｂ）に示した（実施の形態２）の構造の場合には、バンプ８自体が図５（ａ）に示した従来例に比べて幅が狭いため、ウエハ中のスクライブ領域３の面積が図５（ａ）に示した従来例に比べて小さくなり、半導体装置２を形成する面積が多くなり、半導体装置の取れ数減少の対策になる。   As can be seen by comparing FIG. 5A and FIG. 5B, the scribe region 3 (PCM 4 and 3 at the same time) is used by using a wide dicing cutter 9 so as not to leave the first electrode pad 5 and the bump 8. Even when the electrode pad of the layer, bump 8) is cut, in the case of the structure of (Embodiment 2) shown in FIG. 5B, the bump 8 itself is the conventional example shown in FIG. The width of the scribe region 3 in the wafer is smaller than that of the conventional example shown in FIG. 5A, the area for forming the semiconductor device 2 is increased, and the number of semiconductor devices that can be taken is reduced. It will be a countermeasure.

なお、図３（ａ）に示した構造は、電極パッドの上方に、前記電極パッドよりも上層に形成された保護膜の厚みで形成される段差を形成し、さらに前記電極パッドの上に前記段差からはみ出ない程度にバンプを形成したものであるということもできる。   In the structure shown in FIG. 3A, a step formed by the thickness of a protective film formed above the electrode pad is formed above the electrode pad, and the step is further formed on the electrode pad. It can also be said that bumps are formed so as not to protrude from the step.

（実施の形態３）
図６（ａ）は本発明の（実施の形態３）を示す。
図１（ａ）で示したＰＣＭ付き半導体ウエハの場合には、第１層電極パッド５のみで形成しており、第２層および第３層の電極パッドは形成しない形状の電極パッドであって、第１層電極パッド５の面上から第３層保護膜７ａの上面までの段差は、第１，第２，第３層の保護膜５ａ，６ａ，７ａの厚み分だけであったが、この（実施の形態３）の場合には、第２層電極パッドならびに第３層電極パッドは形成しないが、開口部分において第２層配線層６ｂで段差を形成し、同様に第３層配線層７ｂで段差を形成しているため、第１，第２，第３層の保護膜５ａ，６ａ，７ａの厚み分に、第２層配線層６ｂの厚みと、第３層配線層７ｂの厚み分だけ高くできる。 (Embodiment 3)
FIG. 6A shows (Embodiment 3) of the present invention.
In the case of the semiconductor wafer with PCM shown in FIG. 1 (a), the electrode pad is formed only by the first layer electrode pad 5, and the second and third layer electrode pads are not formed. The step from the surface of the first layer electrode pad 5 to the upper surface of the third layer protective film 7a was only the thickness of the first, second and third layer protective films 5a, 6a and 7a. In the case of this (Embodiment 3), the second layer electrode pad and the third layer electrode pad are not formed, but a step is formed in the second layer wiring layer 6b in the opening, and the third layer wiring layer is similarly formed. Since the step is formed at 7b, the thickness of the second-layer wiring layer 6b and the thickness of the third-layer wiring layer 7b are equal to the thicknesses of the first, second, and third-layer protective films 5a, 6a, and 7a. Can be higher by the minute.

そのため、ダイシング工程で半導体装置２の切り出しに伴って、図２（ｂ）と同じように第１層電極パッド５が捲れ上がる異常が発生しても、捲れ上がった第１層電極パッド５の先端が半導体装置２の表面上にさらに露出し難くなり、後の組立工程でパッケージングを行った場合、この「残留したバンプ」部分より電気的なリークなどが発生するおそれが更に少なくなる。   For this reason, even if an abnormality occurs in which the first layer electrode pad 5 is rolled up as the semiconductor device 2 is cut out in the dicing process, the tip of the rolled up first layer electrode pad 5 is generated. However, when the packaging is performed in the subsequent assembly process, the possibility of electrical leakage or the like is further reduced from this “remaining bump” portion.

また、図６（ａ）の構造は、電極パッドの上方に、前記電極パッドよりも上層に形成された保護膜の厚みと配線層の厚みで形成される段差を形成したものであるということもできる。   In addition, the structure in FIG. 6A is a structure in which a step formed by the thickness of the protective film formed above the electrode pad and the thickness of the wiring layer is formed above the electrode pad. it can.

なお、この実施の形態では３層の配線層のうちの最上層を含めた上層の何層かを連続除去して最下層の配線層を電極パッドとしたが、最上層の第３層配線層を除去して第２層配線層を露出させて電極パッドとすることもでき、ウエハの上に形成された多層の配線層のうちで少なくとも最上層の配線層を取り除いて露出した下層の配線層を電極パッドとしたものが効果的であると言える。   In this embodiment, some of the upper layers including the uppermost layer of the three wiring layers are continuously removed and the lowermost wiring layer is used as the electrode pad. The second wiring layer can be exposed to form an electrode pad, and at least the uppermost wiring layer of the multilayer wiring layers formed on the wafer is removed to expose the lower wiring layer It can be said that an electrode pad is effective.

（実施の形態４）
図６（ｂ）は本発明の（実施の形態４）を示す。
図１（ａ）で示したＰＣＭ付き半導体ウエハの場合には、第１層電極パッド５のみで形成しており、第２層および第３層の電極パッドは形成しない形状の電極パッドであって、第１層電極パッド５の面上から第３層保護膜７ａの上面までの段差は、第１，第２，第３層の保護膜５ａ，６ａ，７ａの厚み分だけであったが、この（実施の形態４）の場合には、第２層電極パッドならびに第３層電極パッドは形成しないが、開口部分において第２層配線層６ｂで段差を形成し、同様に第３層配線層７ｂで段差を形成しているため、第１，第２，第３層の保護膜５ａ，６ａ，７ａの厚み分に、第２層配線層６ｂの厚みと、第３層配線層７ｂの厚み分だけ高くできる。 (Embodiment 4)
FIG. 6B shows (Embodiment 4) of the present invention.
In the case of the semiconductor wafer with PCM shown in FIG. 1 (a), the electrode pad is formed only by the first layer electrode pad 5, and the second and third layer electrode pads are not formed. The step from the surface of the first layer electrode pad 5 to the upper surface of the third layer protective film 7a was only the thickness of the first, second and third layer protective films 5a, 6a and 7a. In the case of this (Embodiment 4), the second layer electrode pad and the third layer electrode pad are not formed, but a step is formed in the second layer wiring layer 6b in the opening, and the third layer wiring layer is similarly formed. Since the step is formed at 7b, the thickness of the second-layer wiring layer 6b and the thickness of the third-layer wiring layer 7b are equal to the thicknesses of the first, second, and third-layer protective films 5a, 6a, and 7a. Can be higher by the minute.

そのため、ダイシング工程で半導体装置２の切り出しに伴って残留したバンプ８の一部が半導体装置２のエッジ部分に残留しても残留したバンプ８が半導体装置２の表面上にさらに露出し難くなり、後の組立工程でパッケージングを行った場合、この「残留したバンプ」部分より電気的なリークなどが発生するおそれが更に少なくなる。換言すれば、高膜厚のバンプ８を形成してもバンプ頭が段差より高くならないので、図３の場合よりも高膜厚のバンプ８の形成が可能となる。   For this reason, even if a part of the bump 8 remaining in the dicing process due to the cutting out of the semiconductor device 2 remains on the edge portion of the semiconductor device 2, the remaining bump 8 is more difficult to be exposed on the surface of the semiconductor device 2. When packaging is performed in a later assembly process, the possibility of electrical leakage or the like is further reduced from this “remaining bump” portion. In other words, even if the bump 8 having a high film thickness is formed, the bump head does not become higher than the step, and therefore, the bump 8 having a higher film thickness can be formed than in the case of FIG.

また、図６（ｂ）の構造は、電極パッドの上方に、前記電極パッドよりも上層に形成された保護膜の厚みと配線層の厚みで形成される段差を形成し、さらに前記電極パッドの上に前記段差からはみ出ない程度にバンプを形成したものであるということもできる。   In the structure of FIG. 6B, a step formed by the thickness of the protective film formed above the electrode pad and the thickness of the wiring layer is formed above the electrode pad. It can also be said that bumps are formed so as not to protrude from the step.

なお、この実施の形態では３層の配線層のうちの最上層を含めた上層の何層かを連続除去して最下層の配線層を電極パッドとしたが、最上層の第３層配線層を除去して第２層配線層を露出させて電極パッドとすることもでき、ウエハの上に形成された多層の配線層のうちで少なくとも最上層の配線層を取り除いて露出した下層の配線層を電極パッドとしたものが効果的であると言える。   In this embodiment, some of the upper layers including the uppermost layer of the three wiring layers are continuously removed and the lowermost wiring layer is used as the electrode pad. The second wiring layer can be exposed to form an electrode pad, and at least the uppermost wiring layer of the multilayer wiring layers formed on the wafer is removed to expose the lower wiring layer It can be said that an electrode pad is effective.

本発明はダイシング工程において半導体装置の品質を低下させることのない優れたＰＣＭを得ることができ、アナログデバイスなどの拡散工程有する半導体製造プロセスの更なる歩留と品質の向上に寄与できる。   The present invention can obtain an excellent PCM without degrading the quality of a semiconductor device in a dicing process, and can contribute to further yield and quality improvement of a semiconductor manufacturing process having a diffusion process such as an analog device.

本発明の（実施の形態１）の半導体ウエハ要部断面図と半導体装置の製造方法の工程図Sectional view of essential part of semiconductor wafer and process diagram of manufacturing method of semiconductor device of (Embodiment 1) of the present invention 同実施の形態においてダイシング工程の切断位置がずれた場合の断面図Sectional drawing when the cutting position of the dicing process is shifted in the same embodiment 本発明の（実施の形態２）の半導体ウエハ要部断面図と半導体装置の製造方法の工程図Sectional view of essential part of semiconductor wafer and process diagram of manufacturing method of semiconductor device of (Embodiment 2) of the present invention 同実施の形態においてダイシング工程の切断位置がずれた場合の断面図Sectional drawing when the cutting position of the dicing process is shifted in the same embodiment 従来例と同実施の形態との比較説明の断面図Sectional drawing of comparative explanation between the conventional example and the same embodiment 本発明の（実施の形態３）（実施の形態４）の半導体ウエハの要部断面図Sectional drawing of the principal part of the semiconductor wafer of (Embodiment 3) (Embodiment 4) of this invention 一般的な半導体ウエハ平面図とダイシング工程説明図ならびにＰＣＭを示す拡大平面図General plan view of semiconductor wafer, explanatory diagram of dicing process and enlarged plan view showing PCM 第１の従来例の半導体ウエハのＰＣＭ部分断面図と第２の従来例の半導体ウエハＰＣＭ部分の断面図PCM partial sectional view of the first conventional semiconductor wafer and sectional view of the second conventional semiconductor wafer PCM portion ダイシング工程の説明図Explanatory drawing of dicing process 従来例においてダイシング工程の切断位置がずれた場合の断面図Sectional view when the cutting position of the dicing process is shifted in the conventional example 電極パッドにバンプを付けた従来例においてダイシング工程の切断位置がずれた場合の断面図Sectional view when the cutting position of the dicing process is shifted in the conventional example with bumps on the electrode pad 電極パッドにバンプを付けた従来例において幅広のダイシングカッターで実施するダイシング工程の断面図Sectional view of the dicing process performed with a wide dicing cutter in the conventional example with bumps on the electrode pads

符号の説明Explanation of symbols

１ ウエハ
２ 半導体装置
３ スクライブ領域
４ プロセス・コントロール・モジュール（ＰＣＭ）
５ 第１層電極パッド
５ａ 第１層保護膜
６ 第２層電極パッド
６ａ 第２層保護膜
６ｂ 第２層配線層
７ 第３層電極パッド
７ａ 第３層保護膜
７ｂ 第３層配線層
８ バンプ
９ ダイシングカッター 1 Wafer 2 Semiconductor Device 3 Scribe Area 4 Process Control Module (PCM)
5 1st layer electrode pad 5a 1st layer protective film 6 2nd layer electrode pad 6a 2nd layer protective film 6b 2nd layer wiring layer 7 3rd layer electrode pad 7a 3rd layer protective film 7b 3rd layer wiring layer 8 Bump 9 Dicing cutter

Claims (16)

半導体拡散工程の評価用にスクライブ領域にプロセス・コントロール・モジュールが形成された半導体ウエハであって、
プロセス・コントロール・モジュールは、ウエハの上に形成された多層の配線層のうちで最上層の配線層よりも下層の配線層だけで電極パッドを形成した
半導体ウエハ。 A semiconductor wafer having a process control module formed in a scribe region for evaluation of a semiconductor diffusion process,
The process control module is a semiconductor wafer in which electrode pads are formed only by a wiring layer lower than the uppermost wiring layer among the multilayer wiring layers formed on the wafer. 前記電極パッドの上に保護膜からはみ出ない程度にバンプを形成した請求項１記載の半導体ウエハ。   The semiconductor wafer according to claim 1, wherein bumps are formed on the electrode pads so as not to protrude from the protective film. 前記電極パッドの上方に、前記電極パッドよりも上層に形成された保護膜の厚みで形成される段差を形成した請求項１記載の半導体ウエハ。   The semiconductor wafer according to claim 1, wherein a step formed by a thickness of a protective film formed in an upper layer than the electrode pad is formed above the electrode pad. 前記電極パッドの上方に、前記電極パッドよりも上層に形成された保護膜の厚みで形成される段差を形成し、前記電極パッドの上に前記段差からはみ出ない程度にバンプを形成した請求項１記載の半導体ウエハ。   2. A step formed by a thickness of a protective film formed above the electrode pad is formed above the electrode pad, and a bump is formed on the electrode pad so as not to protrude from the step. The semiconductor wafer as described. 半導体拡散工程の評価用にスクライブ領域にプロセス・コントロール・モジュールが形成された半導体ウエハであって、
プロセス・コントロール・モジュールは、ウエハの上に形成された多層の配線層のうちで少なくとも最上層の配線層を取り除いて露出した下層の配線層を電極パッドとした
半導体ウエハ。 A semiconductor wafer having a process control module formed in a scribe region for evaluation of a semiconductor diffusion process,
The process control module is a semiconductor wafer in which at least the uppermost wiring layer of the multilayer wiring layers formed on the wafer is removed and the lower wiring layer exposed is used as an electrode pad. 前記電極パッドの上に保護膜からはみ出ない程度にバンプを形成した請求項５記載の半導体ウエハ。   The semiconductor wafer according to claim 5, wherein bumps are formed on the electrode pads so as not to protrude from the protective film. 前記電極パッドの上方に、前記電極パッドよりも上層に形成された配線層と保護膜の厚みで形成される段差を形成した請求項５記載の半導体ウエハ。   The semiconductor wafer according to claim 5, wherein a step formed by a thickness of a wiring layer and a protective film formed above the electrode pad is formed above the electrode pad. 前記電極パッドの上方に、前記電極パッドよりも上層に形成された配線層と保護膜の厚みで形成される段差を形成し、前記段差からはみ出ない程度に前記電極パッドの上にバンプを形成した請求項５記載の半導体ウエハ。   A step formed by the thickness of the wiring layer formed above the electrode pad and the thickness of the protective film is formed above the electrode pad, and a bump is formed on the electrode pad so as not to protrude from the step. The semiconductor wafer according to claim 5. 半導体拡散工程の評価用にスクライブ領域にプロセス・コントロール・モジュールが形成された半導体ウエハを製造し、この半導体ウエハから半導体装置を切り出すに際し、
プロセス・コントロール・モジュールは、ウエハの上に形成された多層の配線層のうちで最上層の配線層よりも下層の配線層だけで電極パッドを形成し、前記スクライブ領域の位置を切断する
半導体装置の製造方法。 When manufacturing a semiconductor wafer having a process control module formed in a scribe region for evaluation of a semiconductor diffusion process, and cutting out a semiconductor device from this semiconductor wafer,
A process control module is a semiconductor device in which an electrode pad is formed only by a wiring layer lower than the uppermost wiring layer among multilayer wiring layers formed on a wafer, and the position of the scribe region is cut Manufacturing method. 前記電極パッドの上に保護膜からはみ出ない程度にバンプを形成し、前記スクライブ領域の位置を切断する
請求項９記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 9, wherein bumps are formed on the electrode pads so as not to protrude from a protective film, and the positions of the scribe regions are cut. 前記電極パッドの上方に、前記電極パッドよりも上層に形成された保護膜の厚みで形成される段差を形成し、前記スクライブ領域の位置を切断する
請求項９記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 9, wherein a step formed by a thickness of a protective film formed above the electrode pad is formed above the electrode pad, and the position of the scribe region is cut. 前記電極パッドの上方に、前記電極パッドよりも上層に形成された保護膜の厚みで形成される段差を形成し、前記電極パッドの上に前記段差からはみ出ない程度にバンプを形成し、前記スクライブ領域の位置を切断する
請求項９記載の半導体装置の製造方法。 A step formed by a thickness of a protective film formed above the electrode pad is formed above the electrode pad, a bump is formed on the electrode pad so as not to protrude from the step, and the scribe is formed. The method for manufacturing a semiconductor device according to claim 9, wherein the position of the region is cut. 半導体拡散工程の評価用にスクライブ領域にプロセス・コントロール・モジュールが形成された半導体ウエハを製造し、この半導体ウエハから半導体装置を切り出すに際し、
プロセス・コントロール・モジュールは、ウエハの上に形成された多層の配線層のうちで少なくとも最上層の配線層を取り除いて露出した下層の配線層を電極パッドとし、前記スクライブ領域の位置を切断する
半導体装置の製造方法。 When manufacturing a semiconductor wafer having a process control module formed in a scribe region for evaluation of a semiconductor diffusion process, and cutting out a semiconductor device from this semiconductor wafer,
The process control module is a semiconductor that cuts the position of the scribe region by using, as an electrode pad, a lower wiring layer exposed by removing at least the uppermost wiring layer from among the multilayer wiring layers formed on the wafer. Device manufacturing method. 前記電極パッドの上に保護膜からはみ出ない程度にバンプを形成し、前記スクライブ領域の位置を切断する
請求項１３記載の半導体装置の製造方法。 14. The method of manufacturing a semiconductor device according to claim 13, wherein bumps are formed on the electrode pads so as not to protrude from a protective film, and the positions of the scribe regions are cut. 前記電極パッドの上方に、前記電極パッドよりも上層に形成された配線層と保護膜の厚みで形成される段差を形成し、前記スクライブ領域の位置を切断する
請求項１３記載の半導体装置の製造方法。 The semiconductor device manufacturing method according to claim 13, wherein a step formed by a thickness of a protective layer and a wiring layer formed above the electrode pad is formed above the electrode pad, and the position of the scribe region is cut. Method. 前記電極パッドの上方に、前記電極パッドよりも上層に形成された配線層と保護膜の厚みで形成される段差を形成し、前記段差からはみ出ない程度に前記電極パッドの上にバンプを形成し、前記スクライブ領域の位置を切断する
請求項１３記載の半導体装置の製造方法。 A step formed by the thickness of the wiring layer formed above the electrode pad and the protective film is formed above the electrode pad, and a bump is formed on the electrode pad to the extent that it does not protrude from the step. The method of manufacturing a semiconductor device according to claim 13, wherein the position of the scribe region is cut.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011249478A (en) * 2010-05-25 2011-12-08 Rohm Co Ltd Semiconductor device, manufacturing method for the same and semiconductor wafer

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JPS62261139A (en) * 1986-05-07 1987-11-13 Nippon Denso Co Ltd Semiconductor device
JP2001308036A (en) * 2000-04-25 2001-11-02 Hitachi Ltd Method for manufacturing semiconductor device
JP2004179635A (en) * 2002-11-11 2004-06-24 Seiko Epson Corp Electronic element and its manufacturing method, circuit board and its manufacturing method, and electronic device and its manufacturing method

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Publication number Priority date Publication date Assignee Title
JPS62261139A (en) * 1986-05-07 1987-11-13 Nippon Denso Co Ltd Semiconductor device
JP2001308036A (en) * 2000-04-25 2001-11-02 Hitachi Ltd Method for manufacturing semiconductor device
JP2004179635A (en) * 2002-11-11 2004-06-24 Seiko Epson Corp Electronic element and its manufacturing method, circuit board and its manufacturing method, and electronic device and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011249478A (en) * 2010-05-25 2011-12-08 Rohm Co Ltd Semiconductor device, manufacturing method for the same and semiconductor wafer

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