JP2007123566A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

Info

Publication number
JP2007123566A
JP2007123566A JP2005313883A JP2005313883A JP2007123566A JP 2007123566 A JP2007123566 A JP 2007123566A JP 2005313883 A JP2005313883 A JP 2005313883A JP 2005313883 A JP2005313883 A JP 2005313883A JP 2007123566 A JP2007123566 A JP 2007123566A
Authority
JP
Japan
Prior art keywords
layer
solder
substrate
semiconductor device
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005313883A
Other languages
Japanese (ja)
Other versions
JP4765099B2 (en
Inventor
Yuji Iizuka
祐二 飯塚
Yoshinari Ikeda
良成 池田
Yoko Kakigi
洋子 柿木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Holdings Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Holdings Ltd filed Critical Fuji Electric Holdings Ltd
Priority to JP2005313883A priority Critical patent/JP4765099B2/en
Publication of JP2007123566A publication Critical patent/JP2007123566A/en
Application granted granted Critical
Publication of JP4765099B2 publication Critical patent/JP4765099B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H01L2224/32505—Material outside the bonding interface, e.g. in the bulk of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/8381—Soldering or alloying involving forming an intermetallic compound at the bonding interface

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device formed of a semiconductor chip soldered on a good conductor keeping a joint soldered using a lead-free Sn-based solder high in reliability, not only in an initial phase but also in an actual use after a high-temperature operation history, and to provide its manufacturing method. <P>SOLUTION: In the semiconductor device that the semiconductor chip is mounted on a board equipped with a metal by solder-bonding, the above solder is Pb-free Sn-based solder. An Sn-based solder layer between the semiconductor chip and the metal, and the surface of the metal, have a bonding layer structure that is successively composed of, starting from the Sn-based solder layer, the Sn-based solder layer, an Ni/Sn layer, a Cu/Ni/Sn layer, a Cu/Ni layer, and a Cu layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明はパワーデバイス、高周波用途のスイッチングＩＣなどの各種半導体チップが良伝導体上にはんだ接合された半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device in which various semiconductor chips such as a power device and a switching IC for high frequency use are soldered on a good conductor and a method for manufacturing the same.

電力変換用途のスイッチングデバイスとして用いられるパワーデバイスや高周波スイッチング用途のパワーＩＣなどは半導体モジュールの形に組み立てられるものが多い。このような半導体モジュールの従来の組み立て構造は図５に示すように、銅（以下Ｃｕと略）などの良伝導体の材質で作られた支持基板１０１およびヒートシンク１０２にの上に、絶縁基板の両表面に形成されたはんだ接合を可能にする金属部を有する配線基板１０３の裏面をはんだ接合し、この配線基板１０３の表面の金属配線（金属部）１０６には、前記各用途の半導体チップ１０４をはんだ接合（はんだ接合は図示を省略）により搭載して、単体のモジュール１００を形成する。前記配線基板１０３の上下両面における前記はんだ接合は、通常、同じはんだ材を用いて同時にはんだ接合される。この半導体モジュール１００は、前記半導体チップ１０４から、そのチップ１０４の表面電極に一端が固着されたアルミワイヤ１０５が引き出され、他端は、前記配線基板１０３内の回路配線などから引き出された所定の電極パッド１０７上に固着され、さらに接続される図示しない引き出し端子を介して、外部に引き出され所定のスイッチング機能を奏する半導体モジュールとして構成される。   Many power devices used as switching devices for power conversion and power ICs for high-frequency switching are assembled in the form of semiconductor modules. As shown in FIG. 5, a conventional assembly structure of such a semiconductor module is formed on an insulating substrate on a support substrate 101 and a heat sink 102 made of a good conductor material such as copper (hereinafter abbreviated as Cu). The back surface of the wiring substrate 103 having a metal portion that enables solder bonding formed on both surfaces is soldered, and the metal wiring (metal portion) 106 on the surface of the wiring substrate 103 is connected to the semiconductor chip 104 for each application. Are mounted by solder bonding (solder bonding is not shown) to form a single module 100. The solder bonding on the upper and lower surfaces of the wiring substrate 103 is usually performed simultaneously using the same solder material. In the semiconductor module 100, an aluminum wire 105 having one end fixed to the surface electrode of the chip 104 is drawn out from the semiconductor chip 104, and the other end is drawn out from a circuit wiring or the like in the wiring board 103. The semiconductor module is configured as a semiconductor module that is fixed on the electrode pad 107 and is drawn to the outside via a lead terminal (not shown) that is further connected to perform a predetermined switching function.

前述のような半導体モジュール構造の場合、半導体チップ１０４、配線基板１０３、支持基板１０１などの各主要部材を相互に信頼性高く強固に結合する目的で、はんだ接合が通常行われる。近年は環境問題への対策から鉛フリーはんだとしてＳｎＡｇ、ＳｎＡｇＣｕ、ＳｎＣｕ、ＳｎＢｉ、ＳｎＺｎ、ＳｎＳｂなどのいずれもＳｎリッチな組成の合金が用いられるようになりつつある。高放熱性と良伝導性（良導電性）の観点から、支持基板および配線基板上のチップ接合部を構成する各材料としては銅材が広く用いられている。しかし、銅は前述の鉛フリーはんだとの反応傾向が高く、合金を作りやすい。さらに、はんだ接合時に接合界面に形成されるＳｎＣｕ合金層は、半導体モジュールの実使用時の通電による温度上昇履歴により次第に成長して層厚が過大になりやすいという特徴がある。
また、前述のはんだ接合時に形成される前記ＳｎＣｕ合金層については、適度な厚みを持っていることがはんだ接合層の密着性の観点からは必要な要件であるが、他方では銅より硬度が高いものの脆性傾向の高い機械的性質をも有している。加えて前記ＳｎＣｕ合金層は合金形成時の体積変化のため接合部に応力ひずみが発生するので、前述のように実使用中における高温履歴により合金層が過大に成長すると、はんだ接合層に初期クラックを導入した場合と同様の理由により、所定の期間経過後にはんだ接合層が破壊されるという結果をもたらし、半導体モジュールの信頼性を損なう要因となることが判明した。従って、はんだの濡れ性などの接合安定性と接合後のＳｎＣｕ合金化反応の進行抑制を目的として、Ｎｉめっき等で被接合材（銅基板または銅層）を被覆するのが一般的になりつつある。 In the case of the semiconductor module structure as described above, solder bonding is usually performed for the purpose of bonding the main members such as the semiconductor chip 104, the wiring substrate 103, and the support substrate 101 with high reliability and strength. In recent years, Sn-rich alloys such as SnAg, SnAgCu, SnCu, SnBi, SnZn, and SnSb have been used as lead-free solders as countermeasures for environmental problems. From the viewpoint of high heat dissipation and good conductivity (good conductivity), a copper material is widely used as each material constituting the chip bonding portion on the support substrate and the wiring substrate. However, copper has a high reaction tendency with the aforementioned lead-free solder, and it is easy to make an alloy. Furthermore, the SnCu alloy layer formed at the joint interface at the time of solder joining has a feature that the layer thickness is likely to grow excessively due to a temperature rise history due to energization during actual use of the semiconductor module.
In addition, the SnCu alloy layer formed at the time of the above-described solder bonding has an appropriate thickness from the viewpoint of the adhesion of the solder bonding layer, but on the other hand, the hardness is higher than that of copper. It also has mechanical properties that are highly brittle. In addition, since the SnCu alloy layer generates stress strain in the joint due to volume change during alloy formation, if the alloy layer grows excessively due to high temperature history during actual use as described above, initial cracks will form in the solder joint layer. For the same reason as in the case of introducing, it has been found that the result is that the solder joint layer is destroyed after a predetermined period of time, which is a factor that impairs the reliability of the semiconductor module. Therefore, it is becoming common to coat the material to be joined (copper substrate or copper layer) with Ni plating or the like for the purpose of suppressing the progress of the SnCu alloying reaction after joining, such as solder wettability. is there.

一方、このようなはんだ接合に関する公知技術として、はんだ付け性、耐熱信頼性を高めるめっきを施した銅または銅合金に関する発明が知られている（特許文献１）。この特許文献１には、たとえば、厚さ０．０５〜１．０μｍのＮｉまたはＮｉ合金めっきを施し、次いで厚さ０．０３〜１．０μｍのＣｕめっきを施し、最表面に厚さ０．１５〜３．０μｍであるめっき厚さのＳｎまたはＳｎ合金めっきを施した後、少なくとも一回以上の加熱処理を行う製造方法の記載が見られる（特許文献１の請求項９）。
特開２００３−２９３１８７号公報 On the other hand, as a known technique related to such solder joining, an invention relating to copper or copper alloy plated with a soldering property and a heat-resistant reliability is known (Patent Document 1). In this Patent Document 1, for example, Ni or Ni alloy plating with a thickness of 0.05 to 1.0 μm is applied, then Cu plating with a thickness of 0.03 to 1.0 μm is applied, and a thickness of 0. There is a description of a manufacturing method in which at least one heat treatment is performed after Sn or Sn alloy plating having a plating thickness of 15 to 3.0 μm is performed (claim 9 of Patent Document 1).
JP 2003-293187 A

しかしながら、高温動作する半導体デバイスについては、はんだ接合部の工程を示す図６（ａ）と図６（ｂ）の断面図から、図６（ａ）のように、Ｎｉめっき１０９で被覆された銅基材１０８を加熱処理なしに図６（ｂ）のようにＳｎ系のはんだ１１２で接合すると、Ｎｉ自体の溶出やＳｎの侵食によるＮｉめっき層の目減り（図６（ｂ）の鎖線で示すＮｉ層１０９から実線で示す１１０へ）、およびＳｎとの反応により、脆弱性のあるＮｉＳｎ合金層１１１の成膜、成長が生じるので、Ｎｉめっき膜１０９を被着させてもなお、十分な信頼性が得られない場合も多いという問題を抱えている。
本発明は以上述べた点に鑑みて成されたものであり、本発明の目的は、半導体チップが良伝導体上にはんだ接合された半導体装置について、初期だけでなく、実使用中における高温動作履歴後においても、Ｓｎを主成分とする鉛フリーはんだを用いたはんだ接合部の信頼性を高くできる半導体装置およびその製造方法を提供することである。 However, for semiconductor devices that operate at high temperatures, from the cross-sectional views of FIG. 6 (a) and FIG. 6 (b) showing the solder joint process, as shown in FIG. 6 (a), copper coated with Ni plating 109 is used. When the base material 108 is joined by the Sn-based solder 112 as shown in FIG. 6B without heat treatment, the Ni plating layer is reduced due to elution of Ni itself or Sn erosion (Ni shown by the chain line in FIG. 6B). From the layer 109 to 110 shown by a solid line) and the reaction with Sn, the NiSn alloy layer 111 having a fragility is formed and grown. Therefore, even if the Ni plating film 109 is deposited, sufficient reliability is obtained. There is a problem that there are many cases that cannot be obtained.
The present invention has been made in view of the above points, and an object of the present invention is not only in the initial stage but also in high temperature operation during actual use of a semiconductor device in which a semiconductor chip is soldered onto a good conductor. It is to provide a semiconductor device and a method of manufacturing the same that can increase the reliability of a solder joint using lead-free solder containing Sn as a main component even after the history.

特許請求の範囲の請求項１記載の本発明によれば、半導体チップが金属部を有する基板上にはんだを用いた接合により搭載される半導体装置において、前記はんだがＰｂフリーのＳｎ系はんだであり、前記半導体チップと前記金属部の間のＳｎ系はんだ層と前記金属部の表面とが前記Ｓｎ系はんだ層側から、順次Ｓｎ系はんだ層とＮｉ／Ｓｎ層とＣｕ／Ｎｉ／Ｓｎ層とＣｕ／Ｎｉ層とＣｕ層とで構成される接合層構造を有する半導体装置とすることにより、前記本発明は達成される。
特許請求の範囲の請求項２記載の本発明によれば、前記金属部がＣｕ、Ａｌを含む良伝導体材料から選ばれる少なくともいずれか一種類の材料である請求項１記載の半導体装置とすることが好ましい。
特許請求の範囲の請求項３記載の本発明によれば、前記金属部を有する基板が、絶縁基板の表面に形成される金属配線パターンを含む金属部を有する基板である請求項１または２記載の半導体装置とすることが好適である。 According to the first aspect of the present invention, in a semiconductor device in which a semiconductor chip is mounted on a substrate having a metal portion by bonding using solder, the solder is Pb-free Sn-based solder. The Sn solder layer between the semiconductor chip and the metal part and the surface of the metal part are sequentially formed from the Sn solder layer side, the Sn solder layer, the Ni / Sn layer, the Cu / Ni / Sn layer, and the Cu. The present invention is achieved by forming a semiconductor device having a bonding layer structure composed of a / Ni layer and a Cu layer.
According to the present invention as set forth in claim 2, the semiconductor device according to claim 1, wherein the metal portion is at least one kind of material selected from good conductor materials including Cu and Al. It is preferable.
According to the present invention as set forth in claim 3, the substrate having the metal portion is a substrate having a metal portion including a metal wiring pattern formed on a surface of an insulating substrate. The semiconductor device is preferably used.

特許請求の範囲の請求項４記載の本発明によれば、前記金属部を有する基板が金属基板からなる請求項１または２記載の半導体装置とすることもできる。
特許請求の範囲の請求項５記載の本発明によれば、半導体チップをはんだを用いた接合により、基板の金属部上に搭載する半導体装置の製造方法において、表面側からＮｉ層とＣｕ層とをこの順に有する金属部を備える基板に所定の加熱処理を加えることにより、Ｃｕ／Ｎｉ層とＣｕ層とをこの順に有する金属部を備える基板に変えてから、Ｓｎを主成分とするＰｂフリーはんだ材を用いて半導体チップを前記金属部のＣｕ／Ｎｉ層の上にはんだ接合する半導体装置の製造方法とすることにより、前記本発明の目的は達成される。
特許請求の範囲の請求項６記載の本発明によれば、前記金属部を備える基板に所定の加熱処理を加えた後、前記金属部の最表面にＡｕ、Ｉｎ、Ｓｂから選ばれる少なくとも一種類を用いた金属層を形成し、前記半導体チップをはんだ接合する請求項５記載の半導体装置の製造方法とすることが好ましい。 According to a fourth aspect of the present invention, the substrate having the metal part may be a semiconductor device according to the first or second aspect.
According to the present invention of claim 5, in a method of manufacturing a semiconductor device in which a semiconductor chip is mounted on a metal part of a substrate by bonding using solder, a Ni layer and a Cu layer are formed from the surface side. Pb-free solder containing Sn as a main component after changing to a substrate having a metal part having a Cu / Ni layer and a Cu layer in this order by applying a predetermined heat treatment to the substrate having a metal part having the order of The object of the present invention can be achieved by using a material for manufacturing a semiconductor device in which a semiconductor chip is solder-bonded onto the Cu / Ni layer of the metal part.
According to the present invention of claim 6, at least one selected from Au, In, and Sb is applied to the outermost surface of the metal portion after a predetermined heat treatment is applied to the substrate including the metal portion. 6. A method of manufacturing a semiconductor device according to claim 5, wherein a metal layer is formed using solder and the semiconductor chip is soldered.

特許請求の範囲の請求項７記載の本発明によれば、前記金属部の最表面にＡｕ、Ｉｎ、Ｓｂから選ばれる少なくとも一種類を用いた金属層を形成した後、前記半導体チップをはんだ接合する前に、前記金属層上にＳｎまたはＳｎ合金層を形成する請求項６記載の半導体装置の製造方法とすることが好適である。   According to the present invention of claim 7, after forming a metal layer using at least one selected from Au, In, and Sb on the outermost surface of the metal part, the semiconductor chip is soldered The semiconductor device manufacturing method according to claim 6, wherein an Sn or Sn alloy layer is formed on the metal layer before performing.

本発明によれば、半導体チップが良伝導体上にはんだ接合された半導体装置について、初期だけでなく、実使用中における高温動作履歴後においても、Ｓｎを主成分とする鉛フリーはんだを用いたはんだ接合部の信頼性を高くする半導体装置およびその製造方法を提供することができる。   According to the present invention, for a semiconductor device in which a semiconductor chip is solder-bonded on a good conductor, lead-free solder mainly composed of Sn is used not only in the initial stage but also after a high-temperature operation history during actual use. It is possible to provide a semiconductor device that increases the reliability of a solder joint and a manufacturing method thereof.

図５は一般的な半導体装置の断面図であるが、本発明の半導体装置にかかる一実施例の断面図とマクロ的な外観は変らないので、以下の本発明の説明に使用することとする。図１、図２、図３、図４は、それぞれ、本発明の半導体装置およびその製造方法にかかり、前記図５に示す半導体装置において、半導体チップ１０４をはんだ接合するために搭載する配線基板１０３上の金属部１０６およびこの金属部１０６に半導体チップ１０４をはんだ接合した場合のはんだ接合部近傍の拡大断面図を示す。本発明の半導体装置は前記半導体チップの下のはんだ接合部近傍の層構成が従来技術とは異なるので、この部分を詳細に説明するために前記図１乃至図４に拡大断面図として示した。本発明の半導体装置を構成するはんだ接合部分にかかる相互の接合部材は、前記図５に示すような半導体チップ１０４と配線基板１０３の場合だけでなく、半導体チップと金属支持基板、前記半導体チップと配線基板を接続する配線体（アルミワイヤ）等、いずれの部材の組み合わせであってもよく、一方の接合表面がＣｕを主成分とする金属であって、Ｎｉ表面層を有し、はんだ材がＳｎを主成分とする鉛フリーはんだであるときに本発明はその効果を発揮する。   FIG. 5 is a cross-sectional view of a general semiconductor device, but the cross-sectional view of one embodiment according to the semiconductor device of the present invention and the macroscopic appearance are not changed, and will be used for the following description of the present invention. . 1, 2, 3, and 4 respectively relate to a semiconductor device and a manufacturing method thereof according to the present invention. In the semiconductor device shown in FIG. 5, a wiring substrate 103 that is mounted for solder bonding a semiconductor chip 104. The upper metal part 106 and an enlarged cross-sectional view of the vicinity of the solder joint when the semiconductor chip 104 is soldered to the metal part 106 are shown. Since the semiconductor device of the present invention has a layer structure near the solder joint under the semiconductor chip, which is different from that of the prior art, this portion is shown as an enlarged cross-sectional view in FIGS. The mutual joining members applied to the solder joints constituting the semiconductor device of the present invention are not only the case of the semiconductor chip 104 and the wiring board 103 as shown in FIG. 5, but also the semiconductor chip, the metal supporting board, and the semiconductor chip. Any combination of members such as a wiring body (aluminum wire) for connecting a wiring board may be used, and one bonding surface is a metal mainly composed of Cu, has a Ni surface layer, and a solder material The present invention exhibits its effect when it is a lead-free solder containing Sn as a main component.

本発明は、本発明の要旨を超えない限り、下記の実施例の説明のみに限定されるものではない。本発明では、図１（ａ）に示すように、被接合材である金属部はＣｕ若しくはＣｕ合金、及びＣｕを含有する複合材などの基材１からなり、Ｎｉ（ニッケル）層２により被膜される（金属部がＣｕの場合を図示）。この場合、Ｎｉ層２は蒸着、スパッタ、めっきのいずれでも良く、無電解Ｎｉ−Ｐ（リン）、Ｎｉ−Ｂ（ホウ素）若しくは電解Ｎｉめっきであることが望ましい。また、Ｃｕを含有する合金、複合材などの場合、単一層のめっきだけでは被膜欠陥が生じやすい場合がある。そのような場合は下地層としてＮｉ、Ｃｒ（クロム）、Ｐｄ（パラジウム）、Ａｌ（アルミニウム）、Ａｌ−Ｓｉ（シリコン）などの下地被膜を形成した上で最表面にＮｉ被膜を成膜することが望ましい。図１（ｃ）に示すように、はんだ接合層３はＳｎ（スズ）Ａｇ（銀）、ＳｎＡｇＣｕ、ＳｎＢｉ（ビスマス）、ＳｎＣｕ、ＳｎＺｎ（亜鉛）、ＳｎＳｂ（アンチモン）などのＳｎを主体とした鉛フリーのはんだを用いる。上述の構成の場合、はんだ接合により、通常、接合界面にはＮｉ／Ｓｎ系の化合物（Ｎｉ３Ｓｎ４など）を生じるが、本発明では、予め良伝導体層（銅層）パタン１を表面に形成した前記配線基板１０３に、図１（ａ）に示すように、Ｎｉめっき層２を形成してＣｕ層（基材）１とＮｉめっき層２との二層にした後、高温加熱処理することを特徴としており、その結果、図１（ｂ）に示すように、基板の銅層１からＮｉめっき層２に銅が拡散されてＣｕ／Ｎｉ層２−１が形成される。また、被接合材の界面付近にＮｉとＣｕが存在するので、はんだとの接合反応の際にはＳｎ、Ｎｉの反応により生成するＮｉＳｎ系の化合物に加えて、Ｎｉ被膜中に存在するＣｕが反応界面に析出するため、図１（ｃ）に示すように、Ｃｕ／Ｎｉ／Ｓｎ系の三元成分の層４が生じる。従来、Ｃｕ層１０８にＮｉめっき後の高温加熱処理がない場合、前記図６に示したように、Ｎｉ層１０９は加熱時効によりはんだ接合層３に溶出するともにＮｉＳｎ系の合金層１１１の成長を促進するため、温度上昇を伴う実機への通電時において接合界面の脆化傾向を進展させ、その結果、はんだ接合の延展性を低下させると共に金属疲労傾向を増大させる結果となっていた。この場合は、接合層内部の脆性破壊傾向を加速させる要因となっていた。これに対し、本発明では、図１に示すように銅を含むＣｕ／Ｎｉ／Ｓｎ系の層４が生じ安定なバリアメタルとして作用するので、接合層界面のＮｉＳｎ系の合金層１０の成長を抑制することができ、接合層の経時脆化の影響が低減され、信頼性を向上させることができるのである。なお、被接合材は半導体チップそのものでも可能で、バンプ状に形成された銅、ニッケル層を含む被膜部及びそれらの拡散を防ぐＷ（タングステン）、Ｔｉ（チタン）、Ａｌなどの下地電極層（ＵＢＭ：Ｕｎｄｅｒ Ｂｕｍｐ Ｍｅｔａｌ）があればＣｕ、Ｎｉの拡散による不都合は生じないので、同様の作用を期待できる。 The present invention is not limited to the description of the following examples unless it exceeds the gist of the present invention. In the present invention, as shown in FIG. 1 (a), the metal part to be joined consists of a base material 1 such as Cu or a Cu alloy and a composite material containing Cu, and is coated with a Ni (nickel) layer 2. (The case where the metal part is Cu is illustrated). In this case, the Ni layer 2 may be vapor deposition, sputtering, or plating, and is preferably electroless Ni—P (phosphorus), Ni—B (boron), or electrolytic Ni plating. Further, in the case of an alloy, a composite material, or the like containing Cu, a film defect may easily occur only by a single layer plating. In such a case, a Ni film is formed on the outermost surface after forming a base film such as Ni, Cr (chromium), Pd (palladium), Al (aluminum), or Al-Si (silicon) as the base layer. Is desirable. As shown in FIG. 1 (c), the solder joint layer 3 is a lead mainly composed of Sn such as Sn (tin) Ag (silver), SnAgCu, SnBi (bismuth), SnCu, SnZn (zinc), SnSb (antimony). Use free solder. In the case of the above-described configuration, a Ni / Sn-based compound (Ni 3 Sn 4 or the like) is usually generated at the bonding interface by solder bonding, but in the present invention, the good conductor layer (copper layer) pattern 1 is applied to the surface in advance. As shown in FIG. 1 (a), the Ni plating layer 2 is formed on the wiring board 103 formed in step 2 to form a Cu layer (base material) 1 and a Ni plating layer 2, and then a high temperature heat treatment is performed. As a result, as shown in FIG. 1B, copper is diffused from the copper layer 1 to the Ni plating layer 2 of the substrate to form a Cu / Ni layer 2-1. In addition, since Ni and Cu exist near the interface of the material to be joined, in addition to the NiSn-based compound produced by the reaction of Sn and Ni during the joining reaction with the solder, Cu present in the Ni coating is also present. Since it precipitates at the reaction interface, a Cu / Ni / Sn ternary component layer 4 is formed as shown in FIG. Conventionally, when the Cu layer 108 is not subjected to high-temperature heat treatment after Ni plating, as shown in FIG. 6, the Ni layer 109 is eluted into the solder joint layer 3 by heating aging, and the NiSn-based alloy layer 111 grows. In order to promote, the tendency of the joint interface to become brittle at the time of energization of the actual machine accompanied by a temperature rise, and as a result, the ductility of the solder joint is lowered and the tendency of metal fatigue is increased. In this case, it has become a factor that accelerates the brittle fracture tendency inside the bonding layer. On the other hand, in the present invention, as shown in FIG. 1, a Cu / Ni / Sn-based layer 4 containing copper is generated and acts as a stable barrier metal, so that the growth of the NiSn-based alloy layer 10 at the bonding layer interface is increased. Thus, the influence of embrittlement of the bonding layer with time can be reduced, and the reliability can be improved. Note that the material to be bonded can be a semiconductor chip itself, and a coating part including copper and a nickel layer formed in a bump shape, and a base electrode layer (such as W (tungsten), Ti (titanium), and Al for preventing diffusion thereof) Since there is no inconvenience due to diffusion of Cu and Ni if UBM (Under Bump Metal) is present, the same effect can be expected.

本発明の半導体装置の製造方法にかかる一実施例について、銅層または銅基板などを基材とする良伝導体上に半導体チップを鉛フリーのＳｎ系はんだを用いて、はんだ接合する前後の工程を中心にして以下詳細に説明する。銅若しくは銅合金からなる良伝導体（銅層または銅を基材）１の表面に電解めっきによりＮｉ層２を形成する。図１（ａ）は銅層１の表面にＮｉメッキ層２を形成したことを断面図により示した図である。Ｎｉ層２の厚みは５μｍ以下であるとよい。その後、還元雰囲気の加熱炉で４００〜８００℃の加熱処理を５〜３０分間行いＮｉ層２と良伝導体１の相互拡散を進展させる。低温（４００〜６００℃程度）加熱処理時においては結晶粒内を浸透した緩やかな相互拡散が進展するが、特に高温（６００℃〜８００℃）加熱処理時においては良伝導体１及びＮｉ層２は再結晶化が進行し、結晶粒の粗大化が進行する。結晶粒が粗粒化すると共にＮｉ層２の粒界近傍に良伝導体１のＣｕ成分の拡散が促進され、一部の拡散Ｃｕが最表面近傍に析出し、Ｃｕ／Ｎｉ合金層２−１が形成される（図１（ｂ））。被膜強度などの膜状態に対する影響としては前者の低温加熱処理の方が望ましいが、後者の高温加熱処理でも、最大結晶粒径が２〜３μｍ程度までの粗大化にとどまっていれば、はんだ接合した後の脆化の影響を前記低温加熱処理と比較しても信頼性に及ぼす影響は些少であるので、問題なく、高温加熱処理の方が処理時間を短かくできる分、より好ましいと言える。この状態でＳｎ３．５Ａｇなどの鉛フリーはんだ３との接合（最大加熱温度２４０〜３００℃）を行なうと、安定相であるＣｕ／Ｎｉ／Ｓｎ層（たとえば、η’−（Ｃｕ，Ｎｉ）６Ｓｎ５などを含む層）４が表面に形成される（図１（ｃ））。この図１（ｃ）では元のＣｕ／Ｎｉ２−１に相当する領域を鎖線で示し、新しいＣｕ／Ｎｉ層を２−２で示した。図１（ｃ）によれば、鎖線で示す元のＣｕ／Ｎｉ２−１の最表面はＣｕ／Ｎｉ／Ｓｎ層４であり、その上のはんだ層３側にはごく薄いＮｉ／Ｓｎ層１０が形成されているが、Ｃｕ／Ｎｉ／Ｓｎ層４により、層の成長が抑制されているので影響は小さい。 About the Example concerning the manufacturing method of the semiconductor device of this invention, the process before and behind solder-joining a semiconductor chip on the good conductor which makes a copper layer or a copper substrate the base material using lead-free Sn type solder The details will be described below. An Ni layer 2 is formed on the surface of a good conductor (copper layer or copper base material) 1 made of copper or a copper alloy by electrolytic plating. FIG. 1A is a sectional view showing that the Ni plating layer 2 is formed on the surface of the copper layer 1. The thickness of the Ni layer 2 is preferably 5 μm or less. Thereafter, a heat treatment at 400 to 800 ° C. is performed for 5 to 30 minutes in a heating furnace in a reducing atmosphere to promote the mutual diffusion of the Ni layer 2 and the good conductor 1. During the low temperature (about 400 to 600 ° C.) heat treatment, slow interdiffusion that penetrates the crystal grains progresses, but particularly during the high temperature (600 ° C. to 800 ° C.) heat treatment, the good conductor 1 and the Ni layer 2. Recrystallization proceeds and crystal grain coarsening proceeds. As the crystal grains become coarser, the diffusion of the Cu component of the good conductor 1 is promoted near the grain boundary of the Ni layer 2, and a part of the diffused Cu precipitates near the outermost surface, and the Cu / Ni alloy layer 2-1 Is formed (FIG. 1B). The former low-temperature heat treatment is preferable as an effect on the film state such as film strength, but the latter high-temperature heat treatment is soldered if the maximum crystal grain size is limited to about 2 to 3 μm. Even if the influence of the subsequent embrittlement is compared with the low-temperature heat treatment, the influence on the reliability is insignificant. Therefore, there is no problem, and it can be said that the high-temperature heat treatment is more preferable because the treatment time can be shortened. When joining with lead-free solder 3 such as Sn3.5Ag (maximum heating temperature of 240 to 300 ° C.) in this state, a Cu / Ni / Sn layer (for example, η ′-(Cu, Ni) 6 ) that is a stable phase. A layer containing Sn 5 or the like) 4 is formed on the surface (FIG. 1C). In FIG. 1C, a region corresponding to the original Cu / Ni2-1 is indicated by a chain line, and a new Cu / Ni layer is indicated by 2-2. According to FIG.1 (c), the outermost surface of the original Cu / Ni2-1 shown with a chain line is the Cu / Ni / Sn layer 4, and a very thin Ni / Sn layer 10 is formed on the solder layer 3 side thereon. Although formed, the growth of the layer is suppressed by the Cu / Ni / Sn layer 4, so the influence is small.

前記実施例１の場合、良伝導体（Ｃｕ層またはＣｕ基板）１とＮｉ層２からなる基板の高温または低温の加熱処理後においては、はんだ接合界面を形成する最表面には銅とニッケルの双方が露出した状態となるが、特に銅の酸化傾向が腐食に及ぼす影響が強いので、加熱処理後の部材管理を通常の雰囲気内で行なうと、はんだ接合の際の濡れ性を劣化させる要因となる。実施例２では、図２の表面にＮｉめっきされた良伝導体１の断面図に示すように、酸化防止保護膜としてＡｕめっき層５を、前記図１（ａ）に示すＣｕ／Ｎｉ膜基板の加熱処理後の前記図１（ｂ）の基板に成膜する。Ａｕ（金）めっき層５はフラッシュめっきであればよく、膜厚は０．０５μｍ程度の薄膜で良い。この場合、Ａｕ層５はんだ接合前の基板表面に耐食性を付与すると共に濡れ性を保持することができ、また、はんだ接合の際にＡｕは界面近傍に残留することなく、はんだ層全体に均一にＡｕが分散するため、実質的には接合後の層構成は実施例１と同様のものとなる。また、Ａｕめっき層５に代えて、接合活性傾向が高いＩｎ（インジウム）、Ｓｂ等を成膜しても良い。Ｉｎ、Ｓｂ等は下地部分との界面反応に先んじてはんだとの液相拡散により、前記Ａｕと同様にはんだ層全体に分散するので、悪影響のある合金層を形成することなく、Ａｕめっき層と同様の効果が期待できる。   In the case of Example 1, after the heat treatment of the substrate composed of the good conductor (Cu layer or Cu substrate) 1 and the Ni layer 2 at high or low temperature, copper and nickel are formed on the outermost surface forming the solder joint interface. Although both are exposed, the copper oxidation tendency has a strong influence on corrosion, so if you manage the parts after heat treatment in a normal atmosphere, it is a factor that degrades the wettability during soldering Become. In Example 2, as shown in the cross-sectional view of the good conductor 1 plated with Ni on the surface of FIG. 2, the Au plating layer 5 is used as an antioxidant protective film, and the Cu / Ni film substrate shown in FIG. A film is formed on the substrate shown in FIG. The Au (gold) plating layer 5 may be flash plating, and may be a thin film having a thickness of about 0.05 μm. In this case, the corrosion resistance can be imparted to the substrate surface before the solder bonding of the Au layer 5 and the wettability can be maintained, and Au does not remain in the vicinity of the interface at the time of soldering, and is uniformly distributed over the entire solder layer. Since Au is dispersed, the layer structure after bonding is substantially the same as that of the first embodiment. Further, in place of the Au plating layer 5, In (indium), Sb, or the like having a high bonding activity tendency may be formed. In, Sb, etc. are dispersed throughout the solder layer in the same manner as Au by liquid phase diffusion with the solder prior to the interfacial reaction with the base portion, so that an Au plating layer can be formed without forming an adverse alloy layer. Similar effects can be expected.

図３に実施例３の良伝導体の断面図を示す。良伝導体（基板）６はアルミニウム（Ａｌ）膜で、３〜５μｍ程度の厚みを有する。このアルミニウム膜の上に下地Ｎｉ膜７を無電解めっきで３μｍ程度成膜し、その上に電解めっきによりＣｕ層８を０．５〜２μｍ形成する。更に最表面に０．５〜２μｍ程度Ｎｉめっき２を施した（図３（ａ））後、前述の加熱処理とＡｕめっき膜形成を行なえば、Ｎｉ膜の最表面にＣｕ層８が拡散してＣｕ層の両界面にＣｕ／Ｎｉ層２−１がそれぞれ形成される（図３（ｂ））。この基板上に半導体チップをＳｎ３．５ＡｇなどのＳｎを主成分とする鉛フリーはんだ３を用いてはんだ接合を行なうと、図３（ｃ）に示すように、前述の実施例と同様の接合層構成を含む層（はんだ３、Ｎｉ／Ｓｎ層１０、Ｃｕ／Ｎｉ／Ｓｎ層４、Ｃｕ／Ｎｉ層２−１、Ｃｕ層８、Ｃｕ／Ｎｉ層２−１、Ｎｉ層２、Ａｌ層６）が形成される。この場合、下地のＮｉめっき層２は接合後も一部が残存していることが望ましく、表面側の膜（Ｃｕ層８、Ｎｉ膜２）より厚みを大きくとることで、供給Ｃｕ分が拡散して表面側のＮｉ膜７に一部が分散した段階でもＮｉリッチなまま残存し、Ａｌ側の界面付近の層構成が変化しないものとした。   FIG. 3 shows a cross-sectional view of the good conductor of Example 3. The good conductor (substrate) 6 is an aluminum (Al) film and has a thickness of about 3 to 5 μm. A base Ni film 7 is formed on the aluminum film by about 3 μm by electroless plating, and a Cu layer 8 is formed by 0.5-2 μm on the aluminum film by electrolytic plating. Further, after Ni plating 2 is applied to the outermost surface by about 0.5 to 2 μm (FIG. 3A), the Cu layer 8 diffuses on the outermost surface of the Ni film if the above heat treatment and Au plating film formation are performed. Thus, Cu / Ni layers 2-1 are formed on both interfaces of the Cu layer, respectively (FIG. 3B). When a semiconductor chip is solder-bonded on this substrate using lead-free solder 3 containing Sn as a main component such as Sn3.5Ag, as shown in FIG. Layers including configuration (solder 3, Ni / Sn layer 10, Cu / Ni / Sn layer 4, Cu / Ni layer 2-1, Cu layer 8, Cu / Ni layer 2-1, Ni layer 2, Al layer 6) Is formed. In this case, it is desirable that a part of the underlying Ni plating layer 2 remains even after the bonding, and by supplying a larger thickness than the surface side film (Cu layer 8, Ni film 2), the supplied Cu component is diffused. Thus, even when part of the Ni film 7 on the surface side is dispersed, it remains Ni-rich and the layer configuration near the Al-side interface remains unchanged.

前述の実施例１、２では、リードフレーム基板材等に多い銅＋Ｎｉめっき部材、配線基板上に形成される導電配線材などへの応用が可能だが、現在配線基板などの上に搭載される半導体チップの表面側の電極は、ワイヤボンディングが可能なようにアルミニウム膜の形成が通常であり、敢えて、半導体チップの表面側電極膜にはんだ接合を行なうためには、その上にさらに電解または無電解Ｎｉめっき膜が形成されるので、通電動作時には最も高温負荷が掛かるところとなる。そのため、実施例３によれば、実機信頼性を向上させるために安定した界面状態を保持する効果が期待できる。   In the first and second embodiments described above, it can be applied to a copper + Ni plating member, which is often used as a lead frame substrate material, and a conductive wiring material formed on a wiring substrate. However, a semiconductor currently mounted on a wiring substrate or the like. The electrode on the surface side of the chip is usually formed with an aluminum film so that wire bonding is possible. In order to perform solder bonding to the electrode film on the surface side of the semiconductor chip, it is further electrolyzed or electrolessly formed thereon. Since the Ni plating film is formed, the highest temperature load is applied during the energization operation. Therefore, according to the third embodiment, an effect of maintaining a stable interface state can be expected in order to improve actual machine reliability.

前記実施例１、２、３に加え、フローはんだ実装のように溶融はんだ材に浸漬させるような接合を行う場合は、前記図１（ａ）に示す銅基材１表面にＮｉめっき膜２形成された金属部材に実施例１と同様の加熱処理を施して、図１（ｂ）のようにＣｕ／Ｎｉ層２−１とした後、Ａｕ膜５を形成した後に、Ｓｎを主成分とする鉛フリーはんだめっき９を行うと、前述のようにＡｕ層は分散して消える（図４（ａ））。はんだ接合時の反応ではんだめっき層９とＮｉ、Ｃｕを含む下地界面の相互拡散によりＮｉ／Ｓｎ層１０とＣｕ／Ｎｉ／Ｓｎ層４が生成される（図４（ｂ））。一方、基板部材のはんだめっき９の最表面（鎖線で示す）は、はんだ３と同種の合金界面となるので液相状態で流動して部材の旧最表面下部の成分と混合する。すなわち、はんだ実装の際の溶融はんだ材の組成不均一などの品質上の影響を受けることなく、接合条件に依存せず安定してバリアメタル層４をＮｉ膜の境界表面付近に形成するため、実機の製造品質を均質化し、結果、信頼性を向上させることができる。なお、この場合、はんだめっき９とＣｕ／Ｎｉ層２−１に挟み込まれるＡｕ、Ｉｎ、Ｓｂは無くてもかまわない。あるいははんだめっき後の基板を放置することがある場合に、腐食を防ぐために最表面にＡｕ膜を成膜してもかまわない。   In addition to the first, second, and third embodiments, in the case of performing the joining so as to be immersed in the molten solder material as in the flow solder mounting, the Ni plating film 2 is formed on the surface of the copper base material 1 shown in FIG. After the heat treatment similar to that of Example 1 was performed on the formed metal member to form the Cu / Ni layer 2-1 as shown in FIG. 1B, the Au film 5 was formed, and then Sn was the main component. When lead-free solder plating 9 is performed, the Au layer is dispersed and disappears as described above (FIG. 4A). The Ni / Sn layer 10 and the Cu / Ni / Sn layer 4 are generated by the mutual diffusion of the solder plating layer 9 and the base interface containing Ni and Cu by the reaction at the time of soldering (FIG. 4B). On the other hand, the outermost surface (indicated by a chain line) of the solder plating 9 of the board member becomes an alloy interface of the same kind as the solder 3 and flows in a liquid phase state and mixes with the components at the lower part of the former outermost surface of the member. That is, in order to stably form the barrier metal layer 4 in the vicinity of the boundary surface of the Ni film without being influenced by the quality such as non-uniform composition of the molten solder material at the time of solder mounting, regardless of the joining conditions, It is possible to homogenize the manufacturing quality of the actual machine and improve the reliability as a result. In this case, there may be no Au, In, and Sb sandwiched between the solder plating 9 and the Cu / Ni layer 2-1. Alternatively, in the case where the substrate after solder plating may be left untreated, an Au film may be formed on the outermost surface in order to prevent corrosion.

本発明の半導体装置の製造方法にかかるはんだ接合部近傍のはんだと金属部の拡大断面図である（その１）。It is an expanded sectional view of the solder and metal part of the solder joint part vicinity concerning the manufacturing method of the semiconductor device of this invention (the 1). 本発明の半導体装置の製造方法にかかるはんだ接合部近傍のはんだと金属部の拡大断面図である（その２）。It is an expanded sectional view of the solder and metal part of the solder joint vicinity concerning the manufacturing method of the semiconductor device of this invention (the 2). 本発明の半導体装置の製造方法にかかるはんだ接合部近傍のはんだと金属部の拡大断面図である（その３）。It is an expanded sectional view of the solder and metal part of the solder joint vicinity concerning the manufacturing method of the semiconductor device of this invention (the 3). 本発明の半導体装置の製造方法にかかるはんだ接合部近傍のはんだと金属部の拡大断面図である（その４）。It is an expanded sectional view of the solder and metal part of the solder joint part vicinity concerning the manufacturing method of the semiconductor device of this invention (the 4). 一般的な半導体装置の組み立て構造の断面図である。It is sectional drawing of the assembly structure of a general semiconductor device. 従来の半導体装置の製造方法にかかる、はんだ接合部近傍のはんだと金属部の拡大断面図である。It is an expanded sectional view of the solder and metal part of a solder joint part vicinity concerning the manufacturing method of the conventional semiconductor device.

符号の説明Explanation of symbols

１、… Ｃｕ層、Ｃｕ基材、
２、… Ｎｉ皮膜、
２−１、… Ｃｕ／Ｎｉ層
３、… はんだ層、
４、… Ｃｕ／Ｎｉ／Ｓｎ層
５、… Ａｕ膜、
６、… Ａｌ層
７、… Ｎｉ層
８、… Ｃｕ層
９、… はんだめっき層
１０、… Ｎｉ／Ｓｎ層。


1, ... Cu layer, Cu base material,
2, Ni film,
2-1, ... Cu / Ni layer 3, ... solder layer,
4, Cu / Ni / Sn layer 5, Au film,
6, ... Al layer 7, ... Ni layer 8, ... Cu layer 9, ... Solder plating layer 10, ... Ni / Sn layer.


Claims (7)

半導体チップが金属部を有する基板上にはんだを用いた接合により搭載される半導体装置において、前記はんだがＰｂフリーのＳｎ系はんだであり、前記半導体チップと前記金属部の間のＳｎ系はんだ層と前記金属部の表面とが前記Ｓｎ系はんだ層側から、順次Ｓｎ系はんだ層とＮｉ／Ｓｎ層とＣｕ／Ｎｉ／Ｓｎ層とＣｕ／Ｎｉ層とＣｕ層とで構成される接合層構造を有することを特徴とする半導体装置。 In a semiconductor device in which a semiconductor chip is mounted on a substrate having a metal part by bonding using solder, the solder is Pb-free Sn solder, and an Sn solder layer between the semiconductor chip and the metal part; The surface of the metal part has a joining layer structure composed of an Sn-based solder layer, a Ni / Sn layer, a Cu / Ni / Sn layer, a Cu / Ni layer, and a Cu layer sequentially from the Sn-based solder layer side. A semiconductor device. 前記金属部がＣｕ、Ａｌを含む良伝導体材料から選ばれる少なくともいずれか一種類の材料であることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the metal portion is at least one kind of material selected from good conductor materials containing Cu and Al. 前記金属部を有する基板が、絶縁基板の表面に形成される金属配線パターンを含む金属部を有する基板であることを特徴とする請求項１または２記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the substrate having the metal part is a substrate having a metal part including a metal wiring pattern formed on a surface of an insulating substrate. 前記金属部を有する基板が金属基板からなることを特徴とする請求項１または２記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the substrate having the metal part is made of a metal substrate. 半導体チップをはんだ材を用いた接合により、基板の金属部上に搭載する半導体装置の製造方法において、表面側からＮｉ層とＣｕ層とをこの順に有する金属部を備える基板に所定の加熱処理を加えることにより、Ｃｕ／Ｎｉ層とＣｕ層とをこの順に有する金属部を備える基板に変えてから、Ｓｎを主成分とするＰｂフリーはんだ材を用いて半導体チップを前記金属部のＣｕ／Ｎｉ層の上にはんだ接合することを特徴とする半導体装置の製造方法。 In a manufacturing method of a semiconductor device in which a semiconductor chip is mounted on a metal part of a substrate by bonding using a solder material, a predetermined heat treatment is performed on a substrate including a metal part having a Ni layer and a Cu layer in this order from the surface side. By adding a Cu / Ni layer and a Cu layer to a substrate having a metal part in this order, the semiconductor chip is made of a Cu / Ni layer of the metal part using a Pb-free solder material mainly composed of Sn. A method for manufacturing a semiconductor device, comprising: solder bonding on a substrate. 前記金属部を備える基板に所定の加熱処理を加えた後、前記金属部の最表面にＡｕ、Ｉｎ、Ｓｂから選ばれる少なくとも一種類を用いた金属層を形成し、前記半導体チップをはんだ接合することを特徴とする請求項５記載の半導体装置の製造方法。 After a predetermined heat treatment is applied to the substrate having the metal part, a metal layer using at least one selected from Au, In, and Sb is formed on the outermost surface of the metal part, and the semiconductor chip is soldered 6. A method of manufacturing a semiconductor device according to claim 5, wherein: 前記金属部の最表面にＡｕ、Ｉｎ、Ｓｂから選ばれる少なくとも一種類を用いた金属層を形成した後、前記半導体チップをはんだ接合する前に、前記金属層上にＳｎまたはＳｎ合金層を形成することを特徴とする請求項６記載の半導体装置の製造方法。
After forming a metal layer using at least one selected from Au, In, and Sb on the outermost surface of the metal part, an Sn or Sn alloy layer is formed on the metal layer before soldering the semiconductor chip. The method of manufacturing a semiconductor device according to claim 6.
JP2005313883A 2005-10-28 2005-10-28 Semiconductor device and manufacturing method thereof Expired - Fee Related JP4765099B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005313883A JP4765099B2 (en) 2005-10-28 2005-10-28 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005313883A JP4765099B2 (en) 2005-10-28 2005-10-28 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2007123566A true JP2007123566A (en) 2007-05-17
JP4765099B2 JP4765099B2 (en) 2011-09-07

Family

ID=38147079

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005313883A Expired - Fee Related JP4765099B2 (en) 2005-10-28 2005-10-28 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP4765099B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011001818A1 (en) * 2009-07-01 2011-01-06 株式会社日立製作所 Semiconductor device and method for manufacturing semiconductor device
WO2013140936A1 (en) * 2012-03-22 2013-09-26 株式会社日立製作所 Semiconductor element, semiconductor device, method for manufacturing semiconductor device, and connection material
US8957522B2 (en) 2012-09-19 2015-02-17 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method of semiconductor device
JP2017130547A (en) * 2016-01-20 2017-07-27 トヨタ自動車株式会社 Semiconductor device manufacturing method
WO2022093783A1 (en) * 2020-10-30 2022-05-05 Wolfspeed, Inc. Transistor packages with improved die attach

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000138320A (en) * 1998-11-02 2000-05-16 Nec Corp Semiconductor element mounting substrate or heat sink and its manufacture and jointed body of the substrate or the heat sink with semiconductor element
JP2001011612A (en) * 1999-06-28 2001-01-16 Sumitomo Metal Mining Co Ltd Target material, electrode material, and packaging parts
JP2003293187A (en) * 2002-03-29 2003-10-15 Dowa Mining Co Ltd Copper or copper alloy subjected to plating and method for manufacturing the same
JP2004080060A (en) * 2003-11-28 2004-03-11 Ngk Spark Plug Co Ltd Package for electronic component and its manufacturing method
JP2005026612A (en) * 2003-07-02 2005-01-27 Denso Corp Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000138320A (en) * 1998-11-02 2000-05-16 Nec Corp Semiconductor element mounting substrate or heat sink and its manufacture and jointed body of the substrate or the heat sink with semiconductor element
JP2001011612A (en) * 1999-06-28 2001-01-16 Sumitomo Metal Mining Co Ltd Target material, electrode material, and packaging parts
JP2003293187A (en) * 2002-03-29 2003-10-15 Dowa Mining Co Ltd Copper or copper alloy subjected to plating and method for manufacturing the same
JP2005026612A (en) * 2003-07-02 2005-01-27 Denso Corp Semiconductor device
JP2004080060A (en) * 2003-11-28 2004-03-11 Ngk Spark Plug Co Ltd Package for electronic component and its manufacturing method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011001818A1 (en) * 2009-07-01 2011-01-06 株式会社日立製作所 Semiconductor device and method for manufacturing semiconductor device
WO2013140936A1 (en) * 2012-03-22 2013-09-26 株式会社日立製作所 Semiconductor element, semiconductor device, method for manufacturing semiconductor device, and connection material
JP2013197427A (en) * 2012-03-22 2013-09-30 Hitachi Ltd Semiconductor element, semiconductor device, semiconductor device manufacturing method and connection material
US8957522B2 (en) 2012-09-19 2015-02-17 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method of semiconductor device
JP2017130547A (en) * 2016-01-20 2017-07-27 トヨタ自動車株式会社 Semiconductor device manufacturing method
WO2022093783A1 (en) * 2020-10-30 2022-05-05 Wolfspeed, Inc. Transistor packages with improved die attach

Also Published As

Publication number Publication date
JP4765099B2 (en) 2011-09-07

Similar Documents

Publication Publication Date Title
US10930614B2 (en) Chip arrangements
US8580621B2 (en) Solder interconnect by addition of copper
US8092621B2 (en) Method for inhibiting growth of nickel-copper-tin intermetallic layer in solder joints
WO2010047139A1 (en) Solder alloy and semiconductor device
US20110042815A1 (en) Semiconductor device and on-vehicle ac generator
TW201323131A (en) Method for suppressing kirkendall voids formation at the interface between solder and Cu pad
JP5614507B2 (en) Sn-Cu lead-free solder alloy
JP6287759B2 (en) Semiconductor device and manufacturing method thereof
WO2012053178A1 (en) Semiconductor junction structure and method for manufacturing semiconductor junction structure
US10328533B2 (en) Hybrid lead-free solder wire
JP2011138968A (en) Method for soldering surface-mount component, and surface-mount component
TW201213552A (en) Bi-Sn-BASED HIGH-TEMPERATURE SOLDER ALLOY
JP4765099B2 (en) Semiconductor device and manufacturing method thereof
JP2003230980A (en) Leadless solder alloy, solder ball and electronic member having solder bump
JP2006066716A (en) Semiconductor device
US20230126663A1 (en) Layer structure and chip package that includes the layer structure
JP2005032834A (en) Joining method of semiconductor chip and substrate
CN115881673A (en) Layer structure, chip package, method for forming the same, and solder material
JP2015205345A (en) Method for soldering surface-mount component and surface-mount component
JP2007031740A (en) Electronic component, and its manufacturing method
JP2003223945A (en) LEAD PIN WITH Au-Ge SYSTEM BRAZING MATERIAL
JP2007103462A (en) Bonding structure of terminal pad and solder, semiconductor device having the same, and its manufacturing method
JP2014123745A (en) Power module for automobile
JP6543890B2 (en) High temperature solder alloy
WO2001076335A1 (en) Mounting structure of electronic device and method of mounting electronic device

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20080204

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080916

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20081216

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20090219

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20091112

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110204

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110215

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110408

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20110422

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110510

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110523

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 4765099

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140624

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees