JP2007103619A - Soi基板の製造方法 - Google Patents
Soi基板の製造方法 Download PDFInfo
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- JP2007103619A JP2007103619A JP2005290705A JP2005290705A JP2007103619A JP 2007103619 A JP2007103619 A JP 2007103619A JP 2005290705 A JP2005290705 A JP 2005290705A JP 2005290705 A JP2005290705 A JP 2005290705A JP 2007103619 A JP2007103619 A JP 2007103619A
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- Prior art keywords
- substrate
- silicon
- region
- soi
- oxide layer
- Prior art date
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- 239000000758 substrate Substances 0.000 title claims abstract description 108
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 46
- 239000010703 silicon Substances 0.000 claims abstract description 46
- 239000013078 crystal Substances 0.000 claims abstract description 9
- 239000001301 oxygen Substances 0.000 claims description 27
- 229910052760 oxygen Inorganic materials 0.000 claims description 27
- 238000000137 annealing Methods 0.000 claims description 21
- -1 oxygen ions Chemical class 0.000 claims description 18
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 238000002513 implantation Methods 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 abstract description 3
- 239000012212 insulator Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 19
- 229910052814 silicon oxide Inorganic materials 0.000 description 19
- 229910052581 Si3N4 Inorganic materials 0.000 description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 14
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000008719 thickening Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 206010067482 No adverse event Diseases 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
【解決手段】 シリコン単結晶からなるシリコン基板1中に酸化層19が部分的に埋め込まれたSOI基板23の製造方法において、シリコン基板中に酸素イオンを注入して酸化層19を形成する前に、シリコン基板1の酸化層19(17)に対応する領域の表面高さが他の領域の表面高さよりも高い段差8を形成する。この方法によれば、製品のSOI基板23のSOI領域とバルク領域の間の表面段差が無く、かつ、BOX層エッジ部の基板表面突き出しが無いことによる基板表面の空洞が無い部分SOI基板を形成させることができる。
【選択図】 図1
Description
3 レジスト膜
5 SOI領域
7 バルク(Bulk)領域
9,13,15 シリコン酸化膜
11 シリコン窒化膜
19 BOX層
21 シリコン酸化層
23 SOI基板
Claims (4)
- シリコン単結晶からなるシリコン基板中に酸化層が部分的に埋め込まれたSOI基板の製造方法において、前記シリコン基板中に酸素イオンを注入して前記酸化層を形成する前に、前記シリコン基板の前記酸化層に対応する領域の表面高さが他の領域の表面高さよりも高い段差を形成することを特徴とするSOI基板の製造方法。
- 前記段差は、前記シリコン基板の前記酸化層に対応する領域の表面にレジスト膜を形成し、該レジスト膜以外の領域の前記シリコン基板表面をドライエッチングにより除去して形成することを特徴とする請求項1に記載のSOI基板の製造方法。
- 前記段差を形成してから前記酸素イオンを注入するまでの間、前記段差の表面に始めに酸化膜を形成後、窒化膜を形成し、前記他の領域の前記窒化膜の上にマスク酸化膜を形成することを特徴とする請求項1に記載のSOI基板の製造方法。
- 前記酸素イオンの注入後は、前記酸化層に対応する領域の前記窒化膜を除去する第1の除去工程と、前記第1の除去工程の後に前記シリコン基板を酸化性雰囲気で熱処理して前記シリコン基板中に前記酸化層を形成し、かつ前記シリコン基板の前記酸化層に対応する領域の表面に表面酸化層を形成するアニール工程と、前記アニール工程の後に前記シリコン基板上の前記窒化膜、前記表面酸化層及び前記マスク酸化膜を除去する第2の除去工程とを含むことを特徴とする請求項3に記載のSOI基板の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005290705A JP5239117B2 (ja) | 2005-10-04 | 2005-10-04 | Soi基板の製造方法 |
US11/541,385 US7632735B2 (en) | 2005-10-04 | 2006-09-29 | Process for manufacturing silicon-on-insulator substrate |
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Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005290705A JP5239117B2 (ja) | 2005-10-04 | 2005-10-04 | Soi基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007103619A true JP2007103619A (ja) | 2007-04-19 |
JP5239117B2 JP5239117B2 (ja) | 2013-07-17 |
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JP2005290705A Active JP5239117B2 (ja) | 2005-10-04 | 2005-10-04 | Soi基板の製造方法 |
Country Status (2)
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US (1) | US7632735B2 (ja) |
JP (1) | JP5239117B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011029618A (ja) * | 2009-06-25 | 2011-02-10 | Sumco Corp | Simoxウェーハの製造方法、simoxウェーハ |
FR2972564B1 (fr) * | 2011-03-08 | 2016-11-04 | S O I Tec Silicon On Insulator Tech | Procédé de traitement d'une structure de type semi-conducteur sur isolant |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6376377A (ja) * | 1986-09-18 | 1988-04-06 | Nec Corp | 半導体集積回路装置の製造方法 |
JPH07193204A (ja) * | 1993-12-27 | 1995-07-28 | Nippon Steel Corp | 半導体基板の製造方法 |
JPH09246507A (ja) * | 1996-03-05 | 1997-09-19 | Citizen Watch Co Ltd | 半導体装置およびその製造方法 |
JP2004193185A (ja) * | 2002-12-09 | 2004-07-08 | Sumitomo Mitsubishi Silicon Corp | Soi基板の製造方法及びsoi基板 |
JP2005268511A (ja) * | 2004-03-18 | 2005-09-29 | Siltronic Japan Corp | Soi基板の製造方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6949420B1 (en) * | 2004-03-12 | 2005-09-27 | Sony Corporation | Silicon-on-insulator (SOI) substrate having dual surface crystallographic orientations and method of forming same |
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2005
- 2005-10-04 JP JP2005290705A patent/JP5239117B2/ja active Active
-
2006
- 2006-09-29 US US11/541,385 patent/US7632735B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6376377A (ja) * | 1986-09-18 | 1988-04-06 | Nec Corp | 半導体集積回路装置の製造方法 |
JPH07193204A (ja) * | 1993-12-27 | 1995-07-28 | Nippon Steel Corp | 半導体基板の製造方法 |
JPH09246507A (ja) * | 1996-03-05 | 1997-09-19 | Citizen Watch Co Ltd | 半導体装置およびその製造方法 |
JP2004193185A (ja) * | 2002-12-09 | 2004-07-08 | Sumitomo Mitsubishi Silicon Corp | Soi基板の製造方法及びsoi基板 |
JP2005268511A (ja) * | 2004-03-18 | 2005-09-29 | Siltronic Japan Corp | Soi基板の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP5239117B2 (ja) | 2013-07-17 |
US7632735B2 (en) | 2009-12-15 |
US20070077718A1 (en) | 2007-04-05 |
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