JP2007059514A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2007059514A
JP2007059514A JP2005240941A JP2005240941A JP2007059514A JP 2007059514 A JP2007059514 A JP 2007059514A JP 2005240941 A JP2005240941 A JP 2005240941A JP 2005240941 A JP2005240941 A JP 2005240941A JP 2007059514 A JP2007059514 A JP 2007059514A
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Prior art keywords
semiconductor device
resin
resin protrusion
electrical connection
semiconductor chip
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JP2005240941A
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JP4720992B2 (en
Inventor
Yasuo Yamazaki
康男 山▲崎▼
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Seiko Epson Corp
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Seiko Epson Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device superior in mounting property for manufacturing a highly reliable electronic module. <P>SOLUTION: The semiconductor device is provided with a semiconductor chip 10 having a plurality of electrodes 14, a plurality of resin projections 20 formed on a face 15 where the electrodes 14 of the semiconductor chip 10 are formed, and electric connections 30 which are electrically connected to the electrodes 14 and formed on one of the resin projections 20. Each resin projection 20 comprises a first resin projection 21 formed in a shape extending along a virtual straight line 100 extending in a radial shape from the center of the face 15, and a second resin projection 22 which is arranged in a region outside the first resin projection 21 and crosses the virtual straight line 100. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置に関する。   The present invention relates to a semiconductor device.

配線基板に半導体装置が実装されたタイプの電子モジュールが知られている。信頼性の高い電子モジュールを製造するためには、配線基板の配線パターンと半導体装置の配線とを電気的に接続させることが重要である。   An electronic module of a type in which a semiconductor device is mounted on a wiring board is known. In order to manufacture a highly reliable electronic module, it is important to electrically connect the wiring pattern of the wiring board and the wiring of the semiconductor device.

本発明の目的は、実装性の高い半導体装置を提供することにある。
特開平２−２７２７３７号公報 An object of the present invention is to provide a semiconductor device with high mountability.
JP-A-2-272737

（１）本発明に係る半導体装置は、複数の電極を有する半導体チップと、
前記半導体チップの前記電極が形成された面上に形成された複数の樹脂突起と、
前記電極と電気的に接続されてなり、いずれかの前記樹脂突起上に形成された電気的接続部と、
を含み、
前記複数の樹脂突起は、前記面の中心部から放射状に延びる仮想直線に沿って延びる形状をなす第１の樹脂突起と、前記第１の樹脂突起よりも外側の領域に配置された、前記仮想直線と交差する第２の樹脂突起とを含む。本発明によると、実装性に優れた半導体装置を提供することができる。
（２）この半導体装置において、
前記面は矩形をなし、
前記第２の樹脂突起は、前記面の対角線と交差していてもよい。
（３）この半導体装置において、
前記第２の樹脂突起は、前記対角線と直交する方向に延びる形状をなしていてもよい。
（４）この半導体装置において、
前記第２の樹脂突起は、前記仮想直線と直交する方向に延びる形状をなしていてもよい。
（５）この半導体装置において、
前記第２の樹脂突起は、前記面の四隅に配置されていてもよい。 (1) A semiconductor device according to the present invention includes a semiconductor chip having a plurality of electrodes,
A plurality of resin protrusions formed on the surface of the semiconductor chip on which the electrodes are formed;
An electrical connection portion that is electrically connected to the electrode and formed on any of the resin protrusions;
Including
The plurality of resin protrusions are arranged in a first resin protrusion having a shape extending along a virtual straight line extending radially from the center of the surface, and the virtual protrusion disposed in a region outside the first resin protrusion. A second resin protrusion intersecting with the straight line. According to the present invention, a semiconductor device excellent in mountability can be provided.
(2) In this semiconductor device,
The surface is rectangular;
The second resin protrusion may intersect with a diagonal line of the surface.
(3) In this semiconductor device,
The second resin protrusion may have a shape extending in a direction orthogonal to the diagonal line.
(4) In this semiconductor device,
The second resin protrusion may have a shape extending in a direction orthogonal to the virtual line.
(5) In this semiconductor device,
The second resin protrusion may be disposed at four corners of the surface.

以下、本発明を適用した実施の形態について図面を参照して説明する。ただし、本発明は以下の実施の形態に限定されるものではない。また、本発明は、以下の実施の形態及び変形例を自由に組み合わせたものを含むものとする。   Embodiments to which the present invention is applied will be described below with reference to the drawings. However, the present invention is not limited to the following embodiments. The present invention includes any combination of the following embodiments and modifications.

図１（Ａ）〜図１（Ｃ）は、本発明を適用した実施の形態に係る半導体装置１について説明するための図である。ここで、図１（Ａ）及び図１（Ｂ）は、半導体装置１の上視図である。ただし、図１（Ｂ）では、簡単のため、電極１４及び配線３２（電気的接続部３０）を省略してある。また、図１（Ｃ）は、図１（Ａ）のIC−IC線断面の一部拡大図である。   FIG. 1A to FIG. 1C are diagrams for explaining a semiconductor device 1 according to an embodiment to which the present invention is applied. Here, FIG. 1A and FIG. 1B are top views of the semiconductor device 1. However, in FIG. 1B, for simplicity, the electrode 14 and the wiring 32 (electrical connection portion 30) are omitted. FIG. 1C is a partially enlarged view of a cross section taken along the line IC-IC in FIG.

本実施の形態に係る半導体装置は、図１（Ａ）〜図１（Ｃ）に示すように、半導体チップ１０を含む。半導体チップ１０は、例えばシリコンチップであってもよい。半導体チップ１０には、集積回路１２が形成されていてもよい（図１（Ｃ）参照）。集積回路１２の構成は特に限定されないが、例えば、トランジスタ等の能動素子や、抵抗、コイル、コンデンサ等の受動素子を含んでいてもよい。半導体チップ１０の集積回路１２が形成された面（能動面）は長方形をなしていてもよい（図１（Ａ）及び図１（Ｂ）参照）。ただし、半導体チップ１０の能動面は、正方形をなしていてもよい（図示せず）。   The semiconductor device according to the present embodiment includes a semiconductor chip 10 as shown in FIGS. 1 (A) to 1 (C). The semiconductor chip 10 may be a silicon chip, for example. An integrated circuit 12 may be formed on the semiconductor chip 10 (see FIG. 1C). The configuration of the integrated circuit 12 is not particularly limited, and may include, for example, an active element such as a transistor or a passive element such as a resistor, a coil, or a capacitor. The surface (active surface) on which the integrated circuit 12 of the semiconductor chip 10 is formed may be rectangular (see FIGS. 1A and 1B). However, the active surface of the semiconductor chip 10 may be square (not shown).

半導体チップ１０は、図１（Ａ）及び図１（Ｃ）に示すように、複数の電極１４を有する。電極１４は、半導体チップ１０の能動面に形成されていてもよい。電極１４は、半導体チップ１０の能動面の辺に沿って配列されていてもよい。半導体チップ１０の能動面が長方形をなす場合、電極１４は、その２つの長辺（のみ）に沿って配列されていてもよい。ただし、半導体装置は、半導体チップ１０の能動面の短辺に沿って配列された電極をさらに含んでいてもよい（図示せず）。電極１４は、半導体チップ１０の１つの辺に沿って一列に配列されていてもよい。ただし、電極１４は、１つの辺に沿って複数列に配列されていてもよい（図示せず）。なお、半導体チップ１０における電極１４が形成された面を、面１５と称してもよい。そして、面１５は、矩形（長方形又は正方形）をなしていてもよい。   As shown in FIGS. 1A and 1C, the semiconductor chip 10 has a plurality of electrodes 14. The electrode 14 may be formed on the active surface of the semiconductor chip 10. The electrodes 14 may be arranged along the sides of the active surface of the semiconductor chip 10. When the active surface of the semiconductor chip 10 is rectangular, the electrodes 14 may be arranged along the two long sides (only). However, the semiconductor device may further include an electrode arranged along the short side of the active surface of the semiconductor chip 10 (not shown). The electrodes 14 may be arranged in a line along one side of the semiconductor chip 10. However, the electrodes 14 may be arranged in a plurality of rows along one side (not shown). The surface on which the electrode 14 is formed in the semiconductor chip 10 may be referred to as a surface 15. The surface 15 may be rectangular (rectangular or square).

電極１４は、集積回路１２と電気的に接続されていてもよい。あるいは、集積回路１２に電気的に接続されていない導電体を含めて、電極１４と称してもよい。電極１４は、半導体チップの内部配線（電極）の一部であってもよい。電極１４は、アルミニウム又は銅等の金属で形成されていてもよい。半導体チップ１０にはパッシベーション膜１６が形成されていてもよく、このとき、電極１４は、パッシベーション膜１６からの露出領域であってもよい（図１（Ｃ）参照）。なお、パッシベーション膜は、例えば、ＳｉＯ２やＳｉＮ等の無機絶縁膜であってもよい。あるいは、パッシベーション膜１６は、ポリイミド樹脂などの有機絶縁膜であってもよい。 The electrode 14 may be electrically connected to the integrated circuit 12. Alternatively, a conductor that is not electrically connected to the integrated circuit 12 may be referred to as the electrode 14. The electrode 14 may be a part of the internal wiring (electrode) of the semiconductor chip. The electrode 14 may be formed of a metal such as aluminum or copper. A passivation film 16 may be formed on the semiconductor chip 10, and at this time, the electrode 14 may be an exposed region from the passivation film 16 (see FIG. 1C). The passivation film may be an inorganic insulating film such as SiO 2 or SiN. Alternatively, the passivation film 16 may be an organic insulating film such as a polyimide resin.

本実施の形態に係る半導体装置は、図１（Ａ）〜図１（Ｃ）に示すように、複数の樹脂突起２０を含む。樹脂突起２０は、半導体チップ１０上に形成されてなる。樹脂突起２０は、半導体チップ１０の電極１４が形成された面（面１５）上に形成されてなる。樹脂突起２０は、パッシベーション膜１６上に形成されていてもよい。樹脂突起２０は、電極１４を避けて（オーバーラップしないように）形成されていてもよい。   The semiconductor device according to the present embodiment includes a plurality of resin protrusions 20 as shown in FIGS. The resin protrusion 20 is formed on the semiconductor chip 10. The resin protrusion 20 is formed on the surface (surface 15) on which the electrode 14 of the semiconductor chip 10 is formed. The resin protrusion 20 may be formed on the passivation film 16. The resin protrusion 20 may be formed avoiding the electrode 14 (so as not to overlap).

樹脂突起２０は、図１（Ａ）及び図１（Ｂ）に示すように、面１５の中心部から放射状に延びる仮想直線１００に沿って延びる形状をなす第１の樹脂突起２１と、第１の樹脂突起２１よりも外側の領域に配置された第２の樹脂突起２２とを含む。第１の樹脂突起２１は、面１５の中心部から放射状に延びる形状をなしていると言ってもよい。そして、第２の樹脂突起２２は、仮想直線１００と交差してなる。第２の樹脂突起２２の形状は特に限定されるものではない。第２の樹脂突起２２は、例えば、仮想直線１００と交差する方向に延びる形状をなしていてもよい。このとき、第２の樹脂突起２２は、仮想直線１００と直交する方向に延びる形状をなしていてもよい。第２の樹脂突起２２は、図１（Ａ）及び図１（Ｂ）に示すように、半導体チップ１０の面１５の四隅に配置されていてもよい。ただし、第２の樹脂突起２２は、面１５の４つの角のうち、１〜３個の角付近のみに配置されていてもよい。第２の樹脂突起２２は、面１５の対角線と交差していてもよい。このとき、第２の樹脂突起２２は、面１５の対角線と直交する方向に延びる形状をなしていてもよい。第２の樹脂突起２２は、図１（Ｂ）に示すように、面１５の４個の角のうち最も近接する角を構成する２辺と交差する方向に延びる形状をなしていてもよい。言い換えると、第２の樹脂突起２２は、面１５の４辺のうち最も近接する２辺に交差する方向に延びる形状をなしていてもよい。なお、第１及び第２の樹脂突起２１，２２は、同じ高さをなしていてもよい。あるいは、第２の樹脂突起２２は、第１の樹脂突起２１よりも高さが低くなっていてもよい。例えば、後述する電気的接続部３０が、第２の樹脂突起２２上に形成されていない場合には、第２の樹脂突起２２を、第１の樹脂突起２１よりも低くなるように形成してもよい。ここで、樹脂突起２０の「高さ」とは、半導体チップ１０の面１５を基準とした、樹脂突起２０の最も高い部分の高さを指していてもよい。なお、本実施の形態に係る半導体装置は、半導体チップ１０の面１５（能動面）の辺に沿って延びる樹脂突起をさらに含んでいてもよい（図示せず）。   As shown in FIGS. 1A and 1B, the resin protrusion 20 includes a first resin protrusion 21 having a shape extending along a virtual straight line 100 extending radially from the center of the surface 15, and a first resin protrusion 21. 2nd resin protrusion 22 arrange | positioned in the area | region outside the resin protrusion 21 of this. It may be said that the first resin protrusion 21 has a shape extending radially from the center of the surface 15. The second resin protrusion 22 intersects the virtual straight line 100. The shape of the second resin protrusion 22 is not particularly limited. For example, the second resin protrusion 22 may have a shape extending in a direction intersecting the virtual straight line 100. At this time, the second resin protrusion 22 may have a shape extending in a direction orthogonal to the virtual straight line 100. The second resin protrusions 22 may be disposed at the four corners of the surface 15 of the semiconductor chip 10 as shown in FIGS. 1 (A) and 1 (B). However, the second resin protrusion 22 may be disposed only in the vicinity of 1 to 3 corners of the four corners of the surface 15. The second resin protrusion 22 may intersect the diagonal line of the surface 15. At this time, the second resin protrusion 22 may have a shape extending in a direction orthogonal to the diagonal line of the surface 15. As shown in FIG. 1B, the second resin protrusion 22 may have a shape extending in a direction intersecting with two sides constituting the closest corner among the four corners of the surface 15. In other words, the second resin protrusion 22 may have a shape that extends in a direction intersecting two closest sides of the four sides of the surface 15. Note that the first and second resin protrusions 21 and 22 may have the same height. Alternatively, the second resin protrusion 22 may be lower in height than the first resin protrusion 21. For example, when an electrical connection portion 30 to be described later is not formed on the second resin protrusion 22, the second resin protrusion 22 is formed to be lower than the first resin protrusion 21. Also good. Here, the “height” of the resin protrusion 20 may refer to the height of the highest portion of the resin protrusion 20 with respect to the surface 15 of the semiconductor chip 10. The semiconductor device according to the present embodiment may further include a resin protrusion (not shown) extending along the side of the surface 15 (active surface) of the semiconductor chip 10.

樹脂突起２０の材料は特に限定されず、既に公知となっているいずれかの材料を適用してもよい。例えば、樹脂突起２０は、ポリイミド樹脂、シリコーン変性ポリイミド樹脂、エポキシ樹脂、シリコーン変性エポキシ樹脂、ベンゾシクロブテン（ＢＣＢ；benzocyclobutene）、ポリベンゾオキサゾール（ＰＢＯ；polybenzoxazole）、フェノール樹脂等の樹脂で形成されていてもよい。   The material of the resin protrusion 20 is not particularly limited, and any known material may be applied. For example, the resin protrusion 20 is formed of a resin such as polyimide resin, silicone-modified polyimide resin, epoxy resin, silicone-modified epoxy resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or phenol resin. May be.

本実施の形態に係る半導体装置は、図１（Ａ）及び図１（Ｃ）に示すように、電気的接続部３０を含む。電気的接続部３０は、電極１４と電気的に接続されてなる。電気的接続部３０は、いずれかの樹脂突起２０上に形成されてなる。電気的接続部３０は、第１の樹脂突起２１上に形成されていてもよい。このとき、第２の樹脂突起２２上には、電気的接続部３０が形成されていなくてもよい。あるいは、電気的接続部３０は、第１及び第２の樹脂突起２１，２２上に形成されていてもよい。ただし、電気的接続部３０は、第１及び第２の樹脂突起２１，２２上に形成されていなくてもよい。このときは、電気的接続部３０は、図示しない他の樹脂突起上のみに形成されていてもよい。例えば、電気的接続部３０は、図示しない、半導体チップ１０の面１５の辺と平行に延びる樹脂突起上のみに形成されていてもよい。このとき、該樹脂突起は、第１及び第２の樹脂突起２１，２２と同じ高さをなしていてもよい。あるいは、該樹脂突起は、第１及び第２の樹脂突起２１，２２よりも高さが高くなっていてもよい。   As shown in FIGS. 1A and 1C, the semiconductor device according to the present embodiment includes an electrical connection portion 30. The electrical connection unit 30 is electrically connected to the electrode 14. The electrical connection portion 30 is formed on one of the resin protrusions 20. The electrical connection portion 30 may be formed on the first resin protrusion 21. At this time, the electrical connection portion 30 may not be formed on the second resin protrusion 22. Alternatively, the electrical connection portion 30 may be formed on the first and second resin protrusions 21 and 22. However, the electrical connection portion 30 may not be formed on the first and second resin protrusions 21 and 22. At this time, the electrical connection portion 30 may be formed only on another resin protrusion (not shown). For example, the electrical connection portion 30 may be formed only on a resin protrusion (not shown) extending in parallel with the side of the surface 15 of the semiconductor chip 10. At this time, the resin protrusion may have the same height as the first and second resin protrusions 21 and 22. Alternatively, the resin protrusion may be higher in height than the first and second resin protrusions 21 and 22.

電気的接続部３０は、電極１４と電気的に接続されていてもよい。例えば、電気的接続部３０は、電極１４上から引き出されて樹脂突起２０上に至るように形成された配線３２の一部（樹脂突起２０とオーバーラップする領域）を指していてもよい。このとき、電気的接続部３０は、配線３２のうち、外部端子として利用される部分を指していてもよい。   The electrical connection unit 30 may be electrically connected to the electrode 14. For example, the electrical connection portion 30 may indicate a part of the wiring 32 formed so as to be drawn from the electrode 14 and reach the resin protrusion 20 (a region overlapping with the resin protrusion 20). At this time, the electrical connection portion 30 may indicate a portion of the wiring 32 that is used as an external terminal.

配線３２（電気的接続部３０）の構造及び材料は、特に限定されるものではない。例えば、配線３２は、単層で形成されていてもよい。あるいは、配線３２は、複数層で形成されていてもよい。このとき、配線３２は、チタン又はチタンタングステンによって形成された第１の層と、金によって形成された第２の層とを含んでいてもよい（図示せず）。また、配線３２は、樹脂突起２０の両側で、半導体チップ１０（パッシベーション膜１６）と接触するように形成されていてもよい。   The structure and material of the wiring 32 (electrical connection part 30) are not particularly limited. For example, the wiring 32 may be formed of a single layer. Alternatively, the wiring 32 may be formed of a plurality of layers. At this time, the wiring 32 may include a first layer formed of titanium or titanium tungsten and a second layer formed of gold (not shown). The wiring 32 may be formed on both sides of the resin protrusion 20 so as to be in contact with the semiconductor chip 10 (passivation film 16).

本実施の形態に係る半導体装置１は、以上の構成をなしていてもよい。半導体装置１によると、実装性に優れた半導体装置を提供することができる。すなわち、半導体装置１によると、信頼性の高い電子モジュール１０００（図３参照）を、効率よく製造することが可能になる。以下、その効果について説明する。   The semiconductor device 1 according to the present embodiment may have the above configuration. According to the semiconductor device 1, a semiconductor device excellent in mountability can be provided. That is, according to the semiconductor device 1, it is possible to efficiently manufacture the highly reliable electronic module 1000 (see FIG. 3). Hereinafter, the effect will be described.

半導体装置１を配線基板４０に実装する方法は特に限定されないが、図２（Ａ）〜図２（Ｃ）を参照して、その一例について説明する。はじめに、配線基板４０について説明する。配線基板４０は、ベース基板４２と配線パターン４４とを含んでいてもよい。ベース基板４２の材料は特に限定されず、有機系又は無機系のいずれの材料であってもよく、これらの複合構造からなるものであってもよい。ベース基板４２として、無機系の材料から形成された基板を利用してもよい。このとき、ベース基板４２は、セラミックス基板やガラス基板であってもよい。ベース基板４２がガラス基板である場合、配線基板４０は、電気光学パネル（液晶パネル・エレクトロルミネッセンスパネル等）の一部であってもよい。配線パターン４４は、ＩＴＯ（Indium Tin Oxide）、Ｃｒ、Ａｌなどの金属膜、金属化合物膜、又は、それらの複合膜によって形成されていてもよい。このとき、配線パターン４４は、液晶を駆動する電極（走査電極、信号電極、対向電極等）に電気的に接続されていてもよい。あるいは、ベース基板４２は、ポリエチレンテレフタレート（ＰＥＴ）からなる基板又はフィルムであってもよい。あるいは、ベース基板４２としてポリイミド樹脂からなるフレキシブル基板を使用してもよい。フレキシブル基板としてFPC(Flexible Printed Circuit)や、TAB(Tape Automated Bonding)技術で使用されるテープを使用してもよい。このとき、配線パターン４４は、例えば、銅（Ｃｕ）、クロム（Ｃｒ）、チタン（Ｔｉ）、ニッケル（Ｎｉ）、チタンタングステン（Ｔｉ−Ｗ）のうちのいずれかを積層して形成されていてもよい。そして、配線パターン４４は、電気的接続部４５を含む。電気的接続部４５は、配線パターン４４のうち、他の部材との電気的な接続に利用される部分である。また、配線パターン４４は、その一部がベース基板４２の内側を通るように形成されていてもよい（図示せず）。   A method for mounting the semiconductor device 1 on the wiring board 40 is not particularly limited, but an example thereof will be described with reference to FIGS. 2 (A) to 2 (C). First, the wiring board 40 will be described. The wiring substrate 40 may include a base substrate 42 and a wiring pattern 44. The material of the base substrate 42 is not particularly limited, and may be any organic or inorganic material, or may be composed of a composite structure thereof. As the base substrate 42, a substrate formed of an inorganic material may be used. At this time, the base substrate 42 may be a ceramic substrate or a glass substrate. When the base substrate 42 is a glass substrate, the wiring substrate 40 may be a part of an electro-optical panel (liquid crystal panel, electroluminescence panel, etc.). The wiring pattern 44 may be formed of a metal film such as ITO (Indium Tin Oxide), Cr, or Al, a metal compound film, or a composite film thereof. At this time, the wiring pattern 44 may be electrically connected to an electrode (scanning electrode, signal electrode, counter electrode, etc.) that drives the liquid crystal. Alternatively, the base substrate 42 may be a substrate or film made of polyethylene terephthalate (PET). Alternatively, a flexible substrate made of polyimide resin may be used as the base substrate 42. As the flexible substrate, a tape used in FPC (Flexible Printed Circuit) or TAB (Tape Automated Bonding) technology may be used. At this time, the wiring pattern 44 is formed by, for example, laminating any one of copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni), and titanium tungsten (Ti-W). Also good. The wiring pattern 44 includes an electrical connection portion 45. The electrical connection portion 45 is a portion used for electrical connection with other members in the wiring pattern 44. Further, the wiring pattern 44 may be formed so that a part thereof passes inside the base substrate 42 (not shown).

以下、配線基板４０に半導体装置１を搭載する工程について説明する。はじめに、図２（Ａ）に示すように、半導体装置１を配線基板４０上に配置して、半導体装置１の電気的接続部３０（樹脂突起２０）と配線基板４０の配線パターン４４（電気的接続部４５）とが対向するように位置合わせをする。このとき、半導体装置１と配線基板４０との間に接着剤５０を設けておいてもよい。接着剤５０は、図２（Ａ）に示すように、配線基板４０上に設けてもよい。接着剤５０は、例えば、フィルム状の接着剤を利用してもよい。あるいは、接着剤５０として、ペースト状の接着剤を利用してもよい。接着剤５０は、絶縁性の接着剤であってもよい。接着剤５０は、樹脂系接着剤であってもよい。その後、図２（Ｂ）に示すように、半導体装置１と配線基板４０とを押圧する。本工程で、樹脂突起２０によって、接着剤５０を流動させてもよい（図２（Ｂ）参照）。そして、電気的接続部３０と配線パターン４４（電気的接続部４５）とを接触させる（図２（Ｃ）参照）。本工程は、加熱環境下で行ってもよい。これにより、接着剤５０の流動性を高めることができる。なお、本工程では、半導体チップ１０と配線基板４０とによって樹脂突起２０を押しつぶして、樹脂突起２０を弾性変形させてもよい（図２（Ｃ）参照）。これにより、樹脂突起２０の弾性力によって、電気的接続部３０と電気的接続部４５（配線パターン４４）とを押し付けることができるため、電気的な接続信頼性の高い電子モジュールを製造することができる。そして、接着剤５０を硬化させて、図２（Ｃ）に示すように、接着層５２を形成してもよい。接着層５２によって、半導体チップ１０と配線基板４０との間隔を維持してもよい。すなわち、接着層５２によって、樹脂突起２０が弾性変形した状態を維持してもよい。例えば、樹脂突起２０が弾性変形した状態で接着剤５０を硬化させることで、樹脂突起２０が弾性変形した状態を維持することができる。   Hereinafter, a process of mounting the semiconductor device 1 on the wiring board 40 will be described. First, as shown in FIG. 2A, the semiconductor device 1 is disposed on the wiring substrate 40, and the electrical connection portion 30 (resin protrusion 20) of the semiconductor device 1 and the wiring pattern 44 (electrical) of the wiring substrate 40 are displayed. Positioning is performed so that the connection portion 45) faces the connection portion 45). At this time, an adhesive 50 may be provided between the semiconductor device 1 and the wiring substrate 40. The adhesive 50 may be provided on the wiring board 40 as shown in FIG. As the adhesive 50, for example, a film adhesive may be used. Alternatively, a paste adhesive may be used as the adhesive 50. The adhesive 50 may be an insulating adhesive. The adhesive 50 may be a resin adhesive. Thereafter, as shown in FIG. 2B, the semiconductor device 1 and the wiring board 40 are pressed. In this step, the adhesive 50 may be caused to flow by the resin protrusion 20 (see FIG. 2B). And the electrical connection part 30 and the wiring pattern 44 (electrical connection part 45) are made to contact (refer FIG.2 (C)). This step may be performed in a heating environment. Thereby, the fluidity | liquidity of the adhesive agent 50 can be improved. In this step, the resin protrusion 20 may be crushed by the semiconductor chip 10 and the wiring substrate 40 to elastically deform the resin protrusion 20 (see FIG. 2C). Thereby, since the electrical connection part 30 and the electrical connection part 45 (wiring pattern 44) can be pressed by the elastic force of the resin protrusion 20, an electronic module with high electrical connection reliability can be manufactured. it can. Then, the adhesive 50 may be cured to form the adhesive layer 52 as shown in FIG. The distance between the semiconductor chip 10 and the wiring substrate 40 may be maintained by the adhesive layer 52. That is, the adhesive protrusion 52 may maintain the state where the resin protrusion 20 is elastically deformed. For example, by curing the adhesive 50 in a state where the resin protrusion 20 is elastically deformed, the state where the resin protrusion 20 is elastically deformed can be maintained.

以上の工程によって、半導体装置１を、配線基板４０に実装してもよい。さらに、検査工程などを経て、図３に示す電子モジュール１０００を製造してもよい。電子モジュール１０００は、表示デバイスであってもよい。表示デバイスは、例えば液晶表示デバイスやＥＬ（Electrical Luminescence）表示デバイスであってもよい。そして、半導体装置１（半導体チップ１０）は、表示デバイスを制御するドライバＩＣであってもよい。   The semiconductor device 1 may be mounted on the wiring board 40 through the above steps. Further, the electronic module 1000 shown in FIG. 3 may be manufactured through an inspection process or the like. The electronic module 1000 may be a display device. The display device may be, for example, a liquid crystal display device or an EL (Electrical Luminescence) display device. The semiconductor device 1 (semiconductor chip 10) may be a driver IC that controls the display device.

半導体装置１は、特に限られる訳ではないが、上述のような、電気的接続部３０を電気的接続部４５と対向させて電気的に接続させる実装方式に適している。なぜなら、この実装方式によると、樹脂突起２０の弾性力によって、電気的接続部３０と電気的接続部４５とが押し付けられ、両者の電気的な接続信頼性を維持することができるためである。ただし、信頼性の高い電子モジュール１０００を製造するためには、すべての電気的接続部３０を、均一な押圧力で、電気的接続部４５に押し付けることが好ましい。特に、半導体装置１を配線基板４０に実装する工程で、予め、半導体装置１と配線基板４０との間に接着剤５０を設けておく場合には、樹脂突起２０によって接着剤５０を流動させることになる。このときに、すべての電気的接続部３０と配線基板４０との間から均一に接着剤を排出させることができれば、すべての電気的接続部３０と電気的接続部４５とを、均一な力で押し付けることができる。   The semiconductor device 1 is not particularly limited, but is suitable for a mounting method in which the electrical connection portion 30 is electrically connected to face the electrical connection portion 45 as described above. This is because, according to this mounting method, the electrical connection portion 30 and the electrical connection portion 45 are pressed by the elastic force of the resin protrusion 20, and the electrical connection reliability of both can be maintained. However, in order to manufacture the highly reliable electronic module 1000, it is preferable to press all the electrical connection portions 30 against the electrical connection portion 45 with a uniform pressing force. In particular, when the adhesive 50 is provided between the semiconductor device 1 and the wiring substrate 40 in the step of mounting the semiconductor device 1 on the wiring substrate 40, the adhesive 50 is caused to flow by the resin protrusion 20. become. At this time, if the adhesive can be uniformly discharged from between all the electrical connection portions 30 and the wiring board 40, all the electrical connection portions 30 and the electrical connection portions 45 can be connected with a uniform force. Can be pressed.

しかし、通常、半導体チップ１０の中央付近では、接着剤５０は、様々な方向に流動し、互いに流動性を阻害するような方向の流れが生じる可能性がある。そのため、半導体チップ１０の中央付近では、電気的接続部３０と電気的接続部４５との間から、接着剤５０が排出されにくくなることがある。これに対して、半導体チップ１０の周縁部付近（角部付近）では、接着剤５０が、互いに阻害するように流動する事態が発生しにくい。そのため、半導体チップ１０の中央付近では、周縁部付近（特に、面１５の角部付近）に較べて、電気的接続部３０と配線基板４０との間の接着剤５０が除去されにくい。これが顕著になれば、半導体チップ１０の中央付近と周縁付近とで、電気的接続部３０と電気的接続部４５とを均一に押し付けることが困難になることが予想される。すなわち、電気的接続部３０と電気的接続部４５との間の押圧力にばらつきが生じることが予想される。   However, normally, the adhesive 50 flows in various directions near the center of the semiconductor chip 10, and there is a possibility that a flow in a direction that inhibits fluidity occurs. Therefore, the adhesive 50 may be difficult to be discharged from between the electrical connection portion 30 and the electrical connection portion 45 near the center of the semiconductor chip 10. On the other hand, in the vicinity of the periphery of the semiconductor chip 10 (near the corner), it is difficult for the adhesive 50 to flow so as to inhibit each other. Therefore, the adhesive 50 between the electrical connection portion 30 and the wiring board 40 is less likely to be removed near the center of the semiconductor chip 10 than in the vicinity of the peripheral portion (particularly, near the corner portion of the surface 15). If this becomes conspicuous, it is expected that it will be difficult to press the electrical connection portion 30 and the electrical connection portion 45 uniformly near the center and the periphery of the semiconductor chip 10. That is, it is expected that the pressing force between the electrical connection portion 30 and the electrical connection portion 45 varies.

ところで、先に説明したように、半導体装置１は、第１及び第２の樹脂突起２１，２２を含む。第１の樹脂突起２１は、面１５の中心部から放射状に延びる仮想直線１００に沿って延びる形状をなす。そのため、接着剤５０は、第１の樹脂突起２１によって流れが制御され、第１の樹脂突起２１に沿って、半導体チップ１０の外側に向かって流動する。そのため、半導体チップ１０の中央部で、接着剤５０が、相互に流れを阻害する方向に流動することを防止することができる。すなわち、半導体チップ１０の中央付近で、電気的接続部３０と配線基板４０との間の接着剤５０の排出性を高めることができる。同時に、第２の樹脂突起２２は、第１の樹脂突起２１の外側の領域に形成されてなり、かつ、仮想直線１００と交差してなる。そのため、半導体チップ１０の角部付近（周縁部付近）で、電気的接続部３０と配線基板４０との間の接着剤５０の排出性を低下させることができる。この２つの作用によって、すべての電気的接続部３０と配線基板４０との間の、接着剤５０の排出性を均一に近づけることができる。そのため、すべての電気的接続部３０と電気的接続部４５とを、均一な押圧力で押し付けることができ、信頼性の高い電子モジュールを形成することができる。   Incidentally, as described above, the semiconductor device 1 includes the first and second resin protrusions 21 and 22. The first resin protrusion 21 has a shape extending along a virtual straight line 100 extending radially from the center of the surface 15. Therefore, the flow of the adhesive 50 is controlled by the first resin protrusion 21, and flows toward the outside of the semiconductor chip 10 along the first resin protrusion 21. Therefore, it is possible to prevent the adhesive 50 from flowing in a direction that inhibits the flow in the center portion of the semiconductor chip 10. That is, the discharge property of the adhesive 50 between the electrical connection portion 30 and the wiring substrate 40 can be improved near the center of the semiconductor chip 10. At the same time, the second resin protrusion 22 is formed in a region outside the first resin protrusion 21 and intersects the virtual straight line 100. Therefore, the discharge property of the adhesive 50 between the electrical connection portion 30 and the wiring substrate 40 can be reduced near the corner portion (near the peripheral portion) of the semiconductor chip 10. By these two actions, the dischargeability of the adhesive 50 between all the electrical connection portions 30 and the wiring board 40 can be made close to each other. Therefore, all the electrical connection portions 30 and the electrical connection portions 45 can be pressed with a uniform pressing force, and a highly reliable electronic module can be formed.

すなわち、本実施の形態に係る半導体装置によると、信頼性の高い電子モジュールを、効率よく製造することが可能な半導体装置を提供することができる。   That is, according to the semiconductor device according to the present embodiment, a semiconductor device capable of efficiently manufacturing a highly reliable electronic module can be provided.

図４は、本発明を適用した実施の形態の変形例に係る半導体装置２について説明するための図である。本実施の形態に係る半導体装置は、第２の樹脂突起２５を含む。第２の樹脂突起２５は、図４に示すように、L字型をなしていてもよい。このとき、第２の樹脂突起２５は、両端を結ぶ仮想直線が、面１５の４つの角のうち第２の樹脂突起２５に最も近接した角を構成する２つの辺と交差する形状をなしていてもよい。この実施の形態によっても、実装性に優れた半導体装置を提供することができる。   FIG. 4 is a diagram for explaining a semiconductor device 2 according to a modification of the embodiment to which the present invention is applied. The semiconductor device according to the present embodiment includes a second resin protrusion 25. The second resin protrusion 25 may have an L shape as shown in FIG. At this time, the second resin protrusion 25 has a shape in which an imaginary straight line connecting both ends intersects two sides constituting the corner closest to the second resin protrusion 25 among the four corners of the surface 15. May be. Also according to this embodiment, a semiconductor device excellent in mountability can be provided.

なお、本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び効果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。   In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation is possible. For example, the present invention includes substantially the same configuration as the configuration described in the embodiment (for example, a configuration having the same function, method, and result, or a configuration having the same purpose and effect). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

図１（Ａ）〜図１（Ｃ）は、本発明を適用した実施の形態に係る半導体装置について説明するための図である。1A to 1C are diagrams for describing a semiconductor device according to an embodiment to which the present invention is applied. 図２（Ａ）〜図２（Ｃ）は、本発明を適用した実施の形態に係る半導体装置について説明するための図である。2A to 2C are diagrams for describing a semiconductor device according to an embodiment to which the present invention is applied. 図３は、本発明を適用した実施の形態に係る半導体装置について説明するための図である。FIG. 3 is a diagram for explaining a semiconductor device according to an embodiment to which the present invention is applied. 図４は、本発明を適用した実施の形態の変形例に係る半導体装置について説明するための図である。FIG. 4 is a diagram for explaining a semiconductor device according to a modification of the embodiment to which the present invention is applied.

符号の説明Explanation of symbols

１…半導体装置、 ２…半導体装置、 １０…半導体チップ、 １２…集積回路、 １４…電極、 １５…面、 １６…パッシベーション膜、 ２０…樹脂突起、 ２１…第１の樹脂突起、 ２２…第２の樹脂突起、 ２５…第２の樹脂突起、 ３０…電気的接続部、 ３２…配線、 ４０…配線基板、 ４２…ベース基板、 ４４…配線パターン、 ４５…電気的接続部、 ５０…接着剤、 ５２…接着層、 １００…仮想直線   DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Semiconductor device, 10 ... Semiconductor chip, 12 ... Integrated circuit, 14 ... Electrode, 15 ... Surface, 16 ... Passivation film, 20 ... Resin protrusion, 21 ... 1st resin protrusion, 22 ... 2nd 25 ... second resin projection, 30 ... electrical connection, 32 ... wiring, 40 ... wiring substrate, 42 ... base substrate, 44 ... wiring pattern, 45 ... electrical connection, 50 ... adhesive, 52 ... Adhesive layer, 100 ... Virtual straight line

Claims (5)

複数の電極を有する半導体チップと、
前記半導体チップの前記電極が形成された面上に形成された複数の樹脂突起と、
前記電極と電気的に接続されてなり、いずれかの前記樹脂突起上に形成された電気的接続部と、
を含み、
前記複数の樹脂突起は、前記面の中心部から放射状に延びる仮想直線に沿って延びる形状をなす第１の樹脂突起と、前記第１の樹脂突起よりも外側の領域に配置された、前記仮想直線と交差する第２の樹脂突起とを含む半導体装置。 A semiconductor chip having a plurality of electrodes;
A plurality of resin protrusions formed on the surface of the semiconductor chip on which the electrodes are formed;
An electrical connection portion that is electrically connected to the electrode and formed on any of the resin protrusions;
Including
The plurality of resin protrusions are arranged in a first resin protrusion having a shape extending along a virtual straight line extending radially from the center of the surface, and the virtual protrusion disposed in a region outside the first resin protrusion. A semiconductor device including a second resin protrusion intersecting with a straight line. 請求項１記載の半導体装置において、
前記面は矩形をなし、
前記第２の樹脂突起は、前記面の対角線と交差してなる半導体装置。 The semiconductor device according to claim 1,
The surface is rectangular;
The second resin protrusion is a semiconductor device formed by intersecting a diagonal line of the surface. 請求項２記載の半導体装置において、
前記第２の樹脂突起は、前記対角線と直交する方向に延びる形状をなす半導体装置。 The semiconductor device according to claim 2,
The second resin protrusion is a semiconductor device having a shape extending in a direction orthogonal to the diagonal line. 請求項１から請求項３のいずれかに記載の半導体装置において、
前記第２の樹脂突起は、前記仮想直線と直交する方向に延びる形状をなす半導体装置。 The semiconductor device according to any one of claims 1 to 3,
The second resin protrusion is a semiconductor device having a shape extending in a direction orthogonal to the virtual straight line. 請求項１から請求項４のいずれかに記載の半導体装置において、
前記第２の樹脂突起は、前記面の四隅に配置されてなる半導体装置。 The semiconductor device according to any one of claims 1 to 4,
The second resin protrusion is a semiconductor device arranged at four corners of the surface.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05144823A (en) * 1991-11-15 1993-06-11 Tanaka Kikinzoku Kogyo Kk High density bump forming method
WO1999065075A1 (en) * 1998-06-12 1999-12-16 Hitachi, Ltd. Semiconductor device and method for manufacturing the same
JP2001110831A (en) * 1999-10-07 2001-04-20 Seiko Epson Corp External connecting protrusion and its forming method, semiconductor chip, circuit board and electronic equipment

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05144823A (en) * 1991-11-15 1993-06-11 Tanaka Kikinzoku Kogyo Kk High density bump forming method
WO1999065075A1 (en) * 1998-06-12 1999-12-16 Hitachi, Ltd. Semiconductor device and method for manufacturing the same
JP2001110831A (en) * 1999-10-07 2001-04-20 Seiko Epson Corp External connecting protrusion and its forming method, semiconductor chip, circuit board and electronic equipment

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