JP2007019329A - Semiconductor device and method for detecting short circuit across terminal - Google Patents

Semiconductor device and method for detecting short circuit across terminal Download PDF

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JP2007019329A
JP2007019329A JP2005200530A JP2005200530A JP2007019329A JP 2007019329 A JP2007019329 A JP 2007019329A JP 2005200530 A JP2005200530 A JP 2005200530A JP 2005200530 A JP2005200530 A JP 2005200530A JP 2007019329 A JP2007019329 A JP 2007019329A
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circuit
short
terminals
terminal
semiconductor device
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JP4412250B2 (en
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Toshiro Isomura
俊郎 磯村
Masato Kobayashi
正人 小林
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Toyota Motor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To solve problems that the arrangement of disconnected terminals between adjacent terminals to detect the short circuit of the adjacent terminals and providing a short-circuit detection circuit between the adjacent terminals in a conventinal semiconductor device disturbs downsizing, and complicates the constitution of the semiconductor device. <P>SOLUTION: The semiconductor device 1 comprises a semiconductor element 10 having a terminal group 11 comprising a plurality of terminals 11a, 11b and 11c, and a substrate 20 connected to the semiconductor element through the terminal group. Wiring 31 for detecting the short circuit of the terminals is arranged between at least two adjacent terminals in the terminal group, the wiring for detecting the short circuit is connected to a detecting circuit 33 and to ground potential, and the detecting circuit determines the presence or absence of a short circuit between terminals by a change in the potential of the wiring for detecting the short circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、複数の端子からなる端子群を有する半導体素子と、該半導体素子と前記端子群を介して接続される基板とを備えた半導体装置およびその端子間短絡検出方法に関する。   The present invention relates to a semiconductor device including a semiconductor element having a terminal group composed of a plurality of terminals, and a substrate connected to the semiconductor element via the terminal group, and a method for detecting a short circuit between the terminals.

近年、半導体素子を基板に実装して構成される半導体装置の小型化が進んでいるが、半導体装置の小型化が進むにつれて、半導体素子としてＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）やＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）の需要が増大するとともに、これらのＣＳＰやＢＧＡにおけるボール端子間ピッチの狭ピッチ化が進んでいる。また、リードピン端子タイプの半導体素子においても、リードピン端子の狭ピッチ化が進んでいる。
このように、ボール端子間ピッチやリードピン端子間ピッチが狭くなるのにつれて、端子間に短絡が生じる恐れが増加するため、隣接する端子間に短絡が生じた場合でも半導体装置に重大な故障が発生しないように、各ボール端子やリードピン端子の配置を考慮して半導体素子の設計を行っている。 In recent years, a semiconductor device configured by mounting a semiconductor element on a substrate has been miniaturized. However, as the semiconductor device is further miniaturized, a CSP (Chip Size Package) or a BGA (Ball Grid Array) is used as the semiconductor element. As demand increases, the pitch between ball terminals in these CSPs and BGAs is becoming narrower. Further, lead pin terminals are also becoming narrower in the lead pin terminal type semiconductor element.
In this way, as the pitch between the ball terminals and the pitch between the lead pin terminals becomes narrower, the risk of a short circuit between the terminals increases. Therefore, the semiconductor element is designed in consideration of the arrangement of each ball terminal and lead pin terminal.

また、前述のＣＳＰやＢＧＡに構成される半導体素子１１０の場合、図１３に示すように、短絡が生じると半導体装置に重大な故障が発生する等といったように、短絡が生じると好ましくない端子間（例えば信号系端子１１１と電源系端子１１２との間）に未接続端子１１３を配置して、両端子１１１・１１２を分離し、該両端子１１１・１１２間が短絡しないように構成することも行われる。
さらに、特許文献１に示すように、半導体素子内部に、該半導体素子の各端子間に接続される短絡検出回路を設けて、隣接する端子間の短絡の有無を判断するように構成した半導体装置もある。
特開２００１−６６３４０号公報 Further, in the case of the semiconductor element 110 configured as the CSP or BGA described above, as shown in FIG. 13, when a short circuit occurs, a serious failure occurs in the semiconductor device. An unconnected terminal 113 may be arranged (for example, between the signal system terminal 111 and the power system terminal 112) to separate both terminals 111 and 112 so that the terminals 111 and 112 are not short-circuited. Done.
Furthermore, as shown in Patent Document 1, a semiconductor device configured to provide a short-circuit detection circuit connected between the terminals of the semiconductor element inside the semiconductor element so as to determine the presence or absence of a short-circuit between adjacent terminals. There is also.
JP 2001-66340 A

しかし、前述のように、短絡が生じると好ましくない端子間に未接続端子１１３を配置した構成では、例えば図１３に示すように、信号系端子１１１の５端子と、電源系端子１１２の５端子とを分離するのに、未接続端子１１３が５端子必要となってしまうといったように、半導体素子１１０に必要な端子数が増大してしまって、半導体装置の小型化を阻害する要因となってしまう。
また、特許文献１のように、隣接する端子間にそれぞれ短絡検出回路を設けた場合、特にＣＳＰやＢＧＡでは、ある端子に隣接する端子の数が多くなるので（最大で８本）、端子間に接続される短絡検出回路の数が多くなって回路構成が複雑になったり、故障モード影響解析（ＦＭＥＡ；Ｆａｉｌｕｒｅ Ｍｏｄｅ ａｎｄ Ｅｆｆｅｃｔ Ａｎａｌｙｓｉｓ）を考慮する必要があったりする。
そこで、本発明においては、半導体装置の小型化を阻害することなく、かつ回路構成を複雑にすることなく、隣接する端子間の短絡を検出することができる半導体装置およびその端子間短絡検出方法を提供するものである。 However, as described above, in the configuration in which the unconnected terminals 113 are arranged between terminals which are not desirable when a short circuit occurs, for example, as shown in FIG. 13, 5 terminals of the signal system terminal 111 and 5 terminals of the power system terminal 112 As a result, the number of terminals required for the semiconductor element 110 increases such that five unconnected terminals 113 are required to separate the two, which becomes a factor that hinders downsizing of the semiconductor device. End up.
In addition, when a short circuit detection circuit is provided between adjacent terminals as in Patent Document 1, especially in CSP and BGA, the number of terminals adjacent to a certain terminal increases (maximum of 8). The number of short-circuit detection circuits connected to the circuit increases, and the circuit configuration becomes complicated, or it is necessary to consider failure mode influence analysis (FMEA) (Failure Mode and Effect Analysis).
Therefore, in the present invention, there is provided a semiconductor device capable of detecting a short circuit between adjacent terminals and a method for detecting a short circuit between the terminals without hindering miniaturization of the semiconductor device and without complicating a circuit configuration. It is to provide.

上記課題を解決する半導体装置およびその端子間短絡検出方法は、以下の特徴を有する。
即ち、請求項１記載の如く、複数の端子からなる端子群を有する半導体素子と、該半導体素子と前記端子群を介して接続される基板とを備えた半導体装置であって、前記端子群における、少なくとも２つの隣り合う端子の間に、該端子の短絡検出用配線を配置した。
これにより、一つまたは少数の検出回路にて、複数の隣接する端子間の短絡を検出することが可能となり、半導体素子に未接続端子等の余分な端子を配置する必要もないので、半導体素子の面積を小さくすることができ、半導体装置を小型化することが可能となる。 A semiconductor device that solves the above problems and a method of detecting a short circuit between terminals have the following characteristics.
A semiconductor device comprising: a semiconductor element having a terminal group consisting of a plurality of terminals; and a substrate connected to the semiconductor element via the terminal group, wherein The short-circuit detection wiring of the terminal is disposed between at least two adjacent terminals.
This makes it possible to detect a short circuit between a plurality of adjacent terminals with one or a small number of detection circuits, and it is not necessary to arrange extra terminals such as unconnected terminals in the semiconductor element. The area of the semiconductor device can be reduced, and the semiconductor device can be downsized.

また、請求項２記載の如く、前記短絡検出用配線は短絡検出用の検出回路に接続され、該短絡検出用配線および検出回路の何れか一方を前記半導体素子に設け、何れか他方を前記基板に設けた。
これにより、短絡検出用配線および検出回路を、基板および半導体素子へ分散して配置することができ、半導体装置を全体的に小型化することができる。 The short-circuit detection wiring is connected to a detection circuit for short-circuit detection, and one of the short-circuit detection wiring and the detection circuit is provided in the semiconductor element, and the other is connected to the substrate. Provided.
Thereby, the short-circuit detection wiring and the detection circuit can be distributed and arranged on the substrate and the semiconductor element, and the semiconductor device can be downsized as a whole.

また、請求項３記載の如く、前記短絡検出用配線は短絡検出用の検出回路に接続され、該短絡検出用配線および検出回路の両方を、前記半導体素子または基板に設けた。
これにより、例えば短絡検出用配線と検出回路とを別々の部材に設けた場合のように、短絡検出用配線と検出回路との間で断線が発生する等といったような不具合が生じることがなく信頼性の高い短絡検出機能を発揮することができる。 According to a third aspect of the present invention, the short-circuit detection wiring is connected to a short-circuit detection circuit, and both the short-circuit detection wiring and the detection circuit are provided on the semiconductor element or the substrate.
As a result, for example, when the short-circuit detection wiring and the detection circuit are provided on separate members, there is no problem such as a disconnection between the short-circuit detection wiring and the detection circuit. High performance short circuit detection function can be exhibited.

また、請求項４記載の如く、前記短絡検出用配線は接地電位に接続されており、前記検出回路は、短絡検出用配線の電位変化により端子間の短絡の有無を判断する。
これにより、簡単な回路にて確実に短絡の有無を検出することが可能となり、半導体装置の小型化を阻害することもない。 According to a fourth aspect of the present invention, the short circuit detection wiring is connected to a ground potential, and the detection circuit determines whether or not there is a short circuit between the terminals based on a potential change of the short circuit detection wiring.
As a result, it is possible to reliably detect the presence or absence of a short circuit with a simple circuit and does not hinder downsizing of the semiconductor device.

また、請求項５記載の如く、前記短絡検出用配線には、電流源から微少電流が印加されており、前記検出回路は、短絡検出用配線の電位変化により端子間の短絡の有無を判断する。
これにより、短絡が発生した端子が接地電位にある端子であったとしても、端子間の短絡を適切に検出することが可能となる。 According to a fifth aspect of the present invention, a minute current is applied to the short-circuit detection wiring from a current source, and the detection circuit determines the presence or absence of a short circuit between the terminals based on a potential change of the short-circuit detection wiring. .
Thereby, even if the terminal where the short circuit occurs is a terminal at the ground potential, it is possible to appropriately detect the short circuit between the terminals.

また、請求項６記載の如く、複数の端子からなる端子群を有する半導体素子と、該半導体素子と前記端子群を介して接続される基板とを備えた半導体装置において、前記端子群における、少なくとも２つの隣り合う端子の間に、該端子の短絡検出用配線を配置し、前記短絡検出用配線を接地電圧に接続し、該短絡検出用配線の電位変化により端子間の短絡の有無を判断する。
これにより、簡単な回路で構成することが可能な一つまたは少数の検出回路にて、複数の隣接する端子間の短絡を検出することが可能となり、半導体素子に未接続端子等の余分な端子を配置する必要もないので、半導体素子の面積を小さくすることができ、半導体装置を小型化することが可能となる。 According to a sixth aspect of the present invention, in a semiconductor device comprising a semiconductor element having a terminal group consisting of a plurality of terminals, and a substrate connected to the semiconductor element via the terminal group, at least in the terminal group, A short-circuit detection wire for the terminal is arranged between two adjacent terminals, the short-circuit detection wire is connected to a ground voltage, and the presence / absence of a short-circuit between the terminals is determined by a potential change of the short-circuit detection wire. .
This makes it possible to detect a short circuit between a plurality of adjacent terminals with one or a small number of detection circuits that can be configured with a simple circuit, and extra terminals such as unconnected terminals in the semiconductor element. Therefore, the area of the semiconductor element can be reduced and the semiconductor device can be miniaturized.

また、請求項７記載の如く、複数の端子からなる端子群を有する半導体素子と、該半導体素子と前記端子群を介して接続される基板とを備えた半導体装置において、前記端子群における、少なくとも２つの隣り合う端子の間に、該端子の短絡検出用配線を配置し、前記短絡検出用配線に、電流源から微少電流を印加して、該短絡検出用配線の電位変化により端子間の短絡の有無を判断する。
これにより、簡単な回路で構成することが可能な一つまたは少数の検出回路にて、複数の隣接する端子間の短絡を検出することが可能となり、半導体素子に未接続端子等の余分な端子を配置する必要もないので、半導体素子の面積を小さくすることができ、半導体装置を小型化することが可能となる。
また、短絡が発生した端子が接地電位にある端子であったとしても、端子間の短絡を適切に検出することができる。 According to a seventh aspect of the present invention, in a semiconductor device comprising a semiconductor element having a terminal group composed of a plurality of terminals, and a substrate connected to the semiconductor element via the terminal group, at least in the terminal group, A short-circuit detection wiring for the terminal is arranged between two adjacent terminals, a small current is applied to the short-circuit detection wiring from a current source, and a short circuit between the terminals is caused by a potential change of the short-circuit detection wiring. Determine the presence or absence.
This makes it possible to detect a short circuit between a plurality of adjacent terminals with one or a small number of detection circuits that can be configured with a simple circuit, and extra terminals such as unconnected terminals in the semiconductor element. Therefore, the area of the semiconductor element can be reduced and the semiconductor device can be miniaturized.
Moreover, even if the terminal where the short circuit occurs is a terminal at the ground potential, it is possible to appropriately detect the short circuit between the terminals.

本発明によれば、一つまたは少数の検出回路にて、複数の隣接する端子間の短絡を検出することが可能となり、半導体素子に未接続端子等の余分な端子を配置する必要もないので、半導体素子の面積を小さくすることができ、半導体装置を小型化することが可能となる。   According to the present invention, it is possible to detect a short circuit between a plurality of adjacent terminals with one or a small number of detection circuits, and it is not necessary to arrange extra terminals such as unconnected terminals in the semiconductor element. The area of the semiconductor element can be reduced, and the semiconductor device can be reduced in size.

次に、本発明を実施するための形態を、添付の図面を用いて説明する。   Next, modes for carrying out the present invention will be described with reference to the accompanying drawings.

図１および図２に示す半導体装置１は、複数の第１類端子１１ａ、複数の第２類端子１１ｂ、および複数の第３類端子１１ｃからなる端子群１１を有する半導体素子１０と、該半導体素子１０と前記端子群１１を介して接続される基板２０とを備えている。
前記端子群１１は半導体素子１０の実装面１０ａに配置されており、例えば、該端子群１１における複数の第１類端子１１ａは信号系端子として用いられ、第２類端子１１ｂは電源系端子として用いられ、第３類端子はその他の用途の端子として用いられる。
ここで、前記半導体素子１０は、半導体チップを樹脂モールドしたものをいう。 A semiconductor device 1 shown in FIGS. 1 and 2 includes a semiconductor element 10 having a terminal group 11 including a plurality of first class terminals 11a, a plurality of second class terminals 11b, and a plurality of third class terminals 11c, and the semiconductor An element 10 and a substrate 20 connected via the terminal group 11 are provided.
The terminal group 11 is disposed on the mounting surface 10a of the semiconductor element 10. For example, a plurality of first class terminals 11a in the terminal group 11 are used as signal system terminals, and a second class terminal 11b is used as a power system terminal. The third type terminal is used as a terminal for other purposes.
Here, the semiconductor element 10 is a semiconductor chip obtained by resin molding.

本例の半導体装置１の場合、例えば、互いに短絡すると重大な故障を引き起こす等、短絡すると好ましくないと考えられる、第１類端子１１ａと第２類端子１１ｂとの間の短絡を検出するようにしており、隣接する第１類端子１１ａと第２類端子１１ｂとの間に、短絡検出用配線３１を配置している。   In the case of the semiconductor device 1 of the present example, for example, a short circuit between the first class terminal 11a and the second class terminal 11b, which is considered to be undesirable when the short circuit is caused, for example, causes a serious failure if they are short-circuited with each other, is detected. The short-circuit detection wiring 31 is arranged between the adjacent first class terminal 11a and second class terminal 11b.

短絡検出用配線３１の一端側は検出用抵抗３２を介して接地電位に接続され、他端側は検出回路３３を介して接地電位に接続されている。
前記短絡検出用配線３１、検出用抵抗３２、および検出回路３３は、基板２０側に形成されている。 One end side of the short-circuit detection wiring 31 is connected to the ground potential via the detection resistor 32, and the other end side is connected to the ground potential via the detection circuit 33.
The short-circuit detection wiring 31, the detection resistor 32, and the detection circuit 33 are formed on the substrate 20 side.

図３に示すように、例えば短絡検出用配線３１は、基板２０の最上層に形成される絶縁層である保護膜層２１の上層に形成されている。該保護膜層２１の下層には導電層であるパターン層２２が形成されており、該パターン層２２は、前記検出用抵抗３２および検出回路３３と接続される検出用パターン２２ａと接続されている。そして、該検出用パターＭ２２ａと前記短絡検出用配線３１とが、適宜箇所にて電気的に接続されている。   As shown in FIG. 3, for example, the short circuit detection wiring 31 is formed in an upper layer of the protective film layer 21 which is an insulating layer formed in the uppermost layer of the substrate 20. A pattern layer 22 which is a conductive layer is formed under the protective film layer 21, and the pattern layer 22 is connected to a detection pattern 22 a connected to the detection resistor 32 and the detection circuit 33. . The detection pattern M22a and the short-circuit detection wiring 31 are electrically connected at appropriate places.

また、図４に示すように、前記検出用パターン２２ａを第１類端子１１ａと第２類端子１１ｂとの間に配線し、該検出用パターン２２ａ形成部分の保護膜層２１を除去して、該検出用パターン２２ａを露出させることで、検出用パターン２２ａを直接短絡検出用配線３１として用いることもできる。   Further, as shown in FIG. 4, the detection pattern 22a is wired between the first class terminal 11a and the second class terminal 11b, and the protective film layer 21 in the detection pattern 22a forming portion is removed, By exposing the detection pattern 22a, the detection pattern 22a can be directly used as the short-circuit detection wiring 31.

図５に示すように、前記検出回路３３は、例えばコンパレータ３３ａにて構成されている。コンパレータ３３ａは、短絡検出用配線３１の電位が、予め設定されている閾値ｔｈよりも高いか低いかを判断して出力するものであり、短絡検出用配線３１の電位が閾値ｔｈよりも低ければ第１類端子１１ａと第２類端子１１ｂとの間に短絡が生じていない正常状態であるとの判断が行われ、短絡検出用配線３１の電位が閾値ｔｈよりも高ければ第１類端子１１ａと第２類端子１１ｂとの間に短絡が生じている状態であるとの判断が行われる。   As shown in FIG. 5, the detection circuit 33 is composed of, for example, a comparator 33a. The comparator 33a determines whether or not the potential of the short-circuit detection wiring 31 is higher or lower than a preset threshold th, and if the potential of the short-circuit detection wiring 31 is lower than the threshold th. If it is determined that there is no short circuit between the first class terminal 11a and the second class terminal 11b, and the potential of the short circuit detection wiring 31 is higher than the threshold th, the first class terminal 11a. And a second type terminal 11b are judged to be in a short-circuit state.

つまり、短絡検出用配線３１は検出用抵抗３２を介して接地されているため、第１類端子１１ａと第２類端子１１ｂとが短絡していない正常時においては、該短絡検出用配線３１の電位は接地電位（０Ｖ）に固定されている。
一方、図６に示すように、隣接する第１類端子１１ａと第２類端子１１ｂとが短絡した状態となると、短絡した第１類端子１１ａ、第２類端子１１ｂおよび短絡検出用配線３１がともに短絡した状態となり、短絡検出用配線３１の電位は短絡した端子の電位（接地電位よりも高い）となる。 That is, since the short-circuit detection wiring 31 is grounded via the detection resistor 32, the first-class terminal 11a and the second-class terminal 11b are not short-circuited and are normally connected. The potential is fixed at the ground potential (0 V).
On the other hand, as shown in FIG. 6, when the adjacent first class terminal 11a and second class terminal 11b are short-circuited, the short-circuited first class terminal 11a, second class terminal 11b, and short-circuit detection wiring 31 are provided. Both are short-circuited, and the potential of the short-circuit detection wiring 31 becomes the potential of the short-circuited terminal (higher than the ground potential).

そして、コンパレータ３３ａの閾値ｔｈは、接地電位よりも僅かに高い電位に設定されている。ここで、閾値ｔｈとして設定される「接地電位よりも僅かに高い電位」とは、接地電位よりも高い電位であって、かつ短絡検出用配線３１の電位が接地電位となっている正常状態のときに、ノイズ等の影響により短絡が生じていると誤った判断を行わない程度のできるだけ低い電位のことをいう。   The threshold th of the comparator 33a is set to a potential slightly higher than the ground potential. Here, the “slightly higher potential than the ground potential” set as the threshold th is a potential that is higher than the ground potential and the potential of the short-circuit detection wiring 31 is the ground potential. Sometimes it refers to a potential as low as possible so that it is not erroneously determined that a short circuit has occurred due to noise or the like.

従って、第１類端子１１ａと第２類端子１１ｂとの間で短絡が生じていないときには、短絡検出用配線３１の電位はコンパレータ３３ａの閾値ｔｈよりも低い接地電位を示し、該コンパレータ３３ａからは短絡が生じていない正常状態である旨を示す信号が出力され、第１類端子１１ａと第２類端子１１ｂとの間で短絡が生じているときには、短絡検出用配線３１の電位はコンパレータ３３ａの閾値ｔｈよりも高い短絡した端子の電位を示し、該コンパレータ３３ａからは短絡が生じている状態である旨を示す信号が出力されることとなる。   Therefore, when there is no short circuit between the first class terminal 11a and the second class terminal 11b, the potential of the short circuit detection wiring 31 shows a ground potential lower than the threshold th of the comparator 33a. When a signal indicating that a short circuit has not occurred and a normal state is output and a short circuit has occurred between the first class terminal 11a and the second class terminal 11b, the potential of the short circuit detection wiring 31 is equal to that of the comparator 33a. A short-circuited terminal potential higher than the threshold th is output, and a signal indicating that a short-circuit has occurred is output from the comparator 33a.

このように、半導体装置１に設けた短絡を検出するための検出回路３３により、短絡検出用配線３１の電位変化を検出することで、隣接する第１類端子１１ａと第２類端子１１ｂとの間に短絡が生じているか否かをの判断を行うことが可能となっている。
特に、短絡検出用配線３１は、半導体素子１０の実装面１０ａに配置される複数の第１類端子１１ａと複数の第２類端子１１ｂとの境界部分、すなわち隣接する各第１類端子１１ａと各第２類端子１１ｂとの間に連続的に配線されているので、一つの検出回路３３にて、全ての隣接する第１類端子１１ａと第２類端子１１ｂとの間の短絡を検出することが可能となっている。
また、半導体素子１０の実装面１０ａに未接続端子等の余分な端子を配置する必要もないので、半導体素子１０の面積を小さくすることができ、半導体装置１を小型化することが可能である。 As described above, the detection circuit 33 for detecting a short circuit provided in the semiconductor device 1 detects the potential change of the short circuit detection wiring 31 to thereby detect the adjacent first class terminal 11a and second class terminal 11b. It is possible to determine whether a short circuit has occurred between them.
In particular, the short-circuit detection wiring 31 includes a boundary portion between the plurality of first class terminals 11a and the plurality of second class terminals 11b arranged on the mounting surface 10a of the semiconductor element 10, that is, adjacent first class terminals 11a. Since it is continuously wired between each second class terminal 11b, a short circuit between all adjacent first class terminals 11a and second class terminals 11b is detected by one detection circuit 33. It is possible.
Further, since there is no need to arrange extra terminals such as unconnected terminals on the mounting surface 10a of the semiconductor element 10, the area of the semiconductor element 10 can be reduced, and the semiconductor device 1 can be miniaturized. .

また、半導体装置１には、複数の短絡検出用配線３１および検出回路３３を設けて、隣接する第１類端子１１ａと第２類端子１１ｂとの間の短絡、および隣接する第２類端子１１ａと第３類端子１１ｂとの間の短絡を検出する等といったように、複数系統の短絡検出回路を構成することもできる。
この場合でも、短絡検出回路の系統数に応じた極少数（本例の場合２つ）の検出回路３３を設けるだけでよいので、半導体装置１を小型化することができる。
さらに、検出回路３３は、接地された短絡検出用配線３１の電位変化をコンパレータ３３ａにより検出して短絡の有無を判断するようにしているので、簡単な回路にて確実に短絡の有無を検出することが可能となっており、半導体装置１の小型化を阻害することもない。 Further, the semiconductor device 1 is provided with a plurality of short-circuit detection wirings 31 and a detection circuit 33, and a short circuit between the adjacent first class terminal 11a and the second class terminal 11b and an adjacent second class terminal 11a. A short circuit detection circuit of a plurality of systems can also be configured, such as detecting a short circuit between the first terminal 11b and the third class terminal 11b.
Even in this case, it is only necessary to provide a very small number (two in this example) of detection circuits 33 corresponding to the number of systems of the short circuit detection circuit, so that the semiconductor device 1 can be reduced in size.
Further, since the detection circuit 33 detects the potential change of the grounded short-circuit detection wiring 31 by the comparator 33a and determines the presence or absence of the short circuit, the simple circuit reliably detects the presence or absence of the short circuit. Therefore, the size reduction of the semiconductor device 1 is not hindered.

また、図７、図８に示すように、前記短絡検出用配線３１は半導体素子１０側に設けることもできる。
この場合、図９に示すように、短絡検出用配線３１は、半導体素子１０の実装面１０ａを構成する保護膜１０ｂの表面上に形成し、該短絡検出用配線３１と半導体素子１０内部の配線層１０ｃとをコンタクト部１０ｄにて接続する。
同様に、前記検出回路３３も半導体素子１０内部に形成することができる。 As shown in FIGS. 7 and 8, the short-circuit detection wiring 31 can be provided on the semiconductor element 10 side.
In this case, as shown in FIG. 9, the short circuit detection wiring 31 is formed on the surface of the protective film 10 b constituting the mounting surface 10 a of the semiconductor element 10, and the short circuit detection wiring 31 and the wiring inside the semiconductor element 10 are formed. The layer 10c is connected to the contact portion 10d.
Similarly, the detection circuit 33 can also be formed inside the semiconductor element 10.

このように、短絡検出用配線３１および検出回路３３を、共に半導体素子１０内または基板２０内に設けているので、例えば短絡検出用配線３１と検出回路３３とを別々の部材に設けた場合のように、短絡検出用配線３１と検出回路３３との間で断線が発生する等といったような不具合が生じることがなく信頼性の高い短絡検出機能を発揮することができる。   Thus, since both the short-circuit detection wiring 31 and the detection circuit 33 are provided in the semiconductor element 10 or the substrate 20, for example, when the short-circuit detection wiring 31 and the detection circuit 33 are provided in separate members, As described above, it is possible to exhibit a highly reliable short-circuit detection function without causing a problem such as disconnection between the short-circuit detection wiring 31 and the detection circuit 33.

このように、短絡検出用配線３１および検出回路３３を半導体素子１０側に設けた場合でも、半導体素子１０内部に一つの検出回路３３を設けるだけで、全ての隣接する第１類端子１１ａと第２類端子１１ｂとの間の短絡を検出することができるため、半導体素子１０が大型化することはなく、半導体装置１の小型化を阻害することはない。   As described above, even when the short-circuit detection wiring 31 and the detection circuit 33 are provided on the semiconductor element 10 side, all the adjacent first-type terminals 11a and the first adjacent terminals 11a are connected to each other only by providing one detection circuit 33 inside the semiconductor element 10. Since a short circuit with the second class terminal 11b can be detected, the semiconductor element 10 does not increase in size and does not hinder downsizing of the semiconductor device 1.

さらに、短絡検出用配線３１および検出回路３３は、その一方を基板２０側へ設けて、他方を半導体素子１０側へ設けることも可能である。
この場合、基板２０側へ設けられる短絡検出用配線３１または検出回路３３と、半導体素子１０側へ設けられる検出回路３３または短絡検出用配線３１とは、半導体素子１０の基板２０への実装時に、前記第３類端子１１ｃ等を介して電気的に接続することができる。
このように、短絡検出用配線３１および検出回路３３の一方を基板２０側へ設けて、他方を半導体素子１０側へ設けることで、短絡検出用の配線・回路を基板２０および半導体素子１０へ分散して配置することができ、半導体装置１を全体的に小型化することができる。 Further, one of the short-circuit detection wiring 31 and the detection circuit 33 can be provided on the substrate 20 side, and the other can be provided on the semiconductor element 10 side.
In this case, the short-circuit detection wiring 31 or the detection circuit 33 provided on the substrate 20 side and the detection circuit 33 or the short-circuit detection wiring 31 provided on the semiconductor element 10 side are mounted when the semiconductor element 10 is mounted on the substrate 20. It can be electrically connected via the third class terminal 11c and the like.
Thus, by providing one of the short-circuit detection wiring 31 and the detection circuit 33 on the substrate 20 side and the other on the semiconductor element 10 side, the short-circuit detection wiring / circuit is distributed to the substrate 20 and the semiconductor element 10. The semiconductor device 1 can be downsized as a whole.

また、短絡検出用配線３１は、前述のように複数の第１類端子１１ａと複数の第２類端子１１ｂとの境界部分に設けるだけでなく、図１０に示すように短絡検出用配線をマトリクス状に配線して、端子群１１を構成する全ての隣接する端子間に短絡検出用配線３１が配置されるようにすることもできる。
また、短絡検出用配線３１は、全ての端子間に配線せずに、適宜必要な箇所のみに配線することも可能である。
このように、短絡検出用配線３１を適宜必要な箇所に配線する場合も、該短絡検出用配線３１は基板２０側または半導体素子１０側の何れにも配線することができる。 Further, the short-circuit detection wiring 31 is not only provided at the boundary between the plurality of first-class terminals 11a and the plurality of second-class terminals 11b as described above, but the short-circuit detection wiring is arranged in a matrix as shown in FIG. It is also possible to arrange the short circuit detection wiring 31 between all adjacent terminals constituting the terminal group 11.
Further, the short-circuit detection wiring 31 can be wired only where necessary as appropriate without wiring between all terminals.
As described above, even when the short-circuit detection wiring 31 is appropriately wired at a necessary location, the short-circuit detection wiring 31 can be wired on either the substrate 20 side or the semiconductor element 10 side.

また、前記図５に示した、短絡検出用配線３１を接地電位に固定し、該短絡検出用配線３１の電位変化をコンパレータ３３ａにて検出するように構成した半導体装置１では、短絡した端子が接地電位を有する端子であった場合、その短絡を検出することができない。
しかし、半導体装置１を次のように構成することで、接地電位を有する端子の短絡も検出することが可能となる。 In the semiconductor device 1 shown in FIG. 5 in which the short-circuit detection wiring 31 is fixed to the ground potential and the potential change of the short-circuit detection wiring 31 is detected by the comparator 33a, the short-circuited terminal has If the terminal has a ground potential, the short circuit cannot be detected.
However, by configuring the semiconductor device 1 as follows, it is possible to detect a short circuit of a terminal having a ground potential.

すなわち、図１１に示すように、短絡検出用配線３１の一端側を、検出用抵抗３２を介して接地電位に接続するとともに、他端側に電流源３５を接続して、該短絡検出用配線３１に、例えば数μＡ〜数十μＡ程度の微少電流を流すように構成しておき、検出回路３３にて短絡検出用配線３１の電位変化を検出することで、端子間の短絡の有無を判断することができる。   That is, as shown in FIG. 11, one end side of the short-circuit detection wiring 31 is connected to the ground potential via the detection resistor 32, and the current source 35 is connected to the other end side to connect the short-circuit detection wiring. 31 is configured so that a very small current of, for example, about several μA to several tens of μA flows, and the presence or absence of a short circuit between the terminals is determined by detecting the potential change of the short circuit detection wiring 31 by the detection circuit 33. can do.

この場合、電流源３５から短絡検出用配線３１へ印加される電圧は、短絡を検出する対象となっている端子（本例の場合第１類端子１１ａおよび第２類端子１１ｂ）が有する電圧よりも大きな電圧となっている。
また、検出回路３３におけるコンパレータ３３ａに設定される閾値ｔｈは、電流源３５と抵抗３２との積で求められる電圧と、各端子の最大電圧との間の電圧値に設定されている。 In this case, the voltage applied from the current source 35 to the short-circuit detection wiring 31 is greater than the voltage of the terminals (first class terminal 11a and second class terminal 11b in this example) that are targets for detecting a short circuit. Is also a large voltage.
The threshold th set in the comparator 33a in the detection circuit 33 is set to a voltage value between the voltage obtained by the product of the current source 35 and the resistor 32 and the maximum voltage of each terminal.

そして、コンパレータ３３ａに入力される電圧値が閾値ｔｈよりも高ければ正常状態である旨を示す信号が出力され、入力される電圧値が閾値ｔｈよりも低ければ短絡が生じている状態である旨を示す信号が出力されるように構成している。
これにより、端子間に短絡が生じていない正常状態のときは、コンパレータ３３ａには閾値ｔｈよりも高い電流源３５の電圧が入力されて、検出回路３３からは正常状態である旨の信号が出力され、端子間に短絡が生じているときは、コンパレータ３３ａには閾値ｔｈよりも低い短絡している端子の電圧が入力されて、検出回路３３からは短絡が生じている旨の信号が出力されることとなる。
短絡が発生した端子が接地電位にある端子であったとしても、コンパレータ３３ａには閾値ｔｈよりも低い電圧値が入力されるので、端子間の短絡を適切に検出することが可能となっている。 If the voltage value input to the comparator 33a is higher than the threshold value th, a signal indicating that the state is normal is output, and if the input voltage value is lower than the threshold value th, a short circuit has occurred. A signal indicating that is output.
Thus, in a normal state in which no short circuit occurs between the terminals, the voltage of the current source 35 higher than the threshold th is input to the comparator 33a, and a signal indicating that the normal state is output from the detection circuit 33. When a short circuit occurs between the terminals, the voltage of the shorted terminal lower than the threshold th is input to the comparator 33a, and a signal indicating that a short circuit has occurred is output from the detection circuit 33. The Rukoto.
Even if the terminal where the short circuit occurs is a terminal at the ground potential, a voltage value lower than the threshold value th is input to the comparator 33a, so that it is possible to appropriately detect a short circuit between the terminals. .

また、短絡検出用配線３１および検出回路３３による短絡検出機能は、ＣＳＰやＢＧＡのようにボール端子を備えた半導体装置のみでなく、リードピン端子を備えた半導体素子により構成される半導体装置に対しても適用することができる。
例えば、図１２に示す半導体装置１においては、リードピン端子５１を備えた半導体素子５０が基板２０に実装されており、該半導体素子５０の隣接する各リードピン端子５１間に、それぞれ短絡検出用配線３１が配線されている。
この場合も、図２等に示した半導体装置１の場合と同様に、短絡検出用配線３１の一端側は検出用抵抗３２を介して接地電位に接続され、他端側は検出回路３３を介して接地電位に接続されている。 Further, the short-circuit detection function by the short-circuit detection wiring 31 and the detection circuit 33 is not limited to a semiconductor device having a ball terminal, such as a CSP or a BGA, but to a semiconductor device constituted by a semiconductor element having a lead pin terminal. Can also be applied.
For example, in the semiconductor device 1 shown in FIG. 12, the semiconductor element 50 including the lead pin terminals 51 is mounted on the substrate 20, and the short-circuit detection wiring 31 is provided between the adjacent lead pin terminals 51 of the semiconductor element 50. Is wired.
Also in this case, as in the case of the semiconductor device 1 shown in FIG. 2 and the like, one end side of the short-circuit detection wiring 31 is connected to the ground potential via the detection resistor 32, and the other end side is connected via the detection circuit 33. Connected to ground potential.

このように、リードピン端子５１を備えた半導体素子５０の場合においても、ボール端子を備えたＣＳＰやＢＧＡの場合と同様に、隣接する端子間の短絡を検出することが可能である。
これにより、リードピン端子５１間のピッチが狭い場合でも半導体装置１の信頼性を確保することができ、該半導体装置１の小型化を図ることが可能になる。 As described above, even in the case of the semiconductor element 50 including the lead pin terminal 51, it is possible to detect a short circuit between adjacent terminals as in the case of a CSP or BGA including a ball terminal.
Thereby, even when the pitch between the lead pin terminals 51 is narrow, the reliability of the semiconductor device 1 can be ensured, and the semiconductor device 1 can be downsized.

本発明にかかる、短絡検出用配線および検出回路を備えた半導体装置を示す斜視図である。It is a perspective view which shows the semiconductor device provided with the wiring for short circuit detection, and a detection circuit concerning this invention. 同じく半導体装置を示す底面図である。It is a bottom view which similarly shows a semiconductor device. 短絡検出用配線を基板の保護膜上に形成した半導体装置を示す側面断面図である。It is side surface sectional drawing which shows the semiconductor device which formed the wiring for short circuit detection on the protective film of a board | substrate. 基板のパターン層を短絡検出用配線として用いた半導体装置を示す側面断面図である。It is side surface sectional drawing which shows the semiconductor device which used the pattern layer of the board | substrate as wiring for short circuit detection. 検出回路をコンパレータにて構成した半導体装置を示す底面図である。It is a bottom view which shows the semiconductor device which comprised the detection circuit with the comparator. 隣接する端子間に短絡が生じている状態を示す底面図である。It is a bottom view which shows the state in which the short circuit has arisen between the adjacent terminals. 短絡検出用配線が形成された半導体素子を示す底面図である。It is a bottom view which shows the semiconductor element in which the wiring for short circuit detection was formed. 半導体素子側に短絡検出用配線を形成した半導体装置を示す側面図である。It is a side view which shows the semiconductor device which formed the wiring for a short circuit detection in the semiconductor element side. 短絡検出用配線が形成された半導体素子を示す側面断面図である。It is side surface sectional drawing which shows the semiconductor element in which the wiring for short circuit detection was formed. 短絡検出用配線を全ての隣接端子間にマトリクス状に配置した半導体装置を示す底面図である。It is a bottom view which shows the semiconductor device which has arrange | positioned the wiring for short circuit detection in the matrix form between all the adjacent terminals. 短絡検出用配線に電流源からの微少電流を印加して、短絡検出用配線の電位変化により端子間の短絡の有無を判断するように構成した半導体装置を示す底面図である。It is a bottom view showing a semiconductor device configured to apply a minute current from a current source to a short-circuit detection wiring and determine whether or not there is a short circuit between terminals based on a potential change of the short-circuit detection wiring. リードピン端子を備えた半導体素子の、隣接する各リードピン端子間に、それぞれ短絡検出用配線を配線した半導体装置を示す平面図である。It is a top view which shows the semiconductor device which wired the wiring for short circuit detection between each adjacent lead pin terminal of the semiconductor element provided with the lead pin terminal. 信号系端子と電源系端子との間に未接続端子を配置した従来の半導体装置を示す底面図である。It is a bottom view which shows the conventional semiconductor device which has arrange | positioned the unconnected terminal between the signal system terminal and the power supply system terminal.

符号の説明Explanation of symbols

１ 半導体装置
１０ 半導体素子
１０ａ 実装面
１１ 端子群
１１ａ 第１類端子
１１ｂ 第２類端子
１１ｃ 第３類端子
２０ 基板
３１ 短絡検出用配線
３２ 検出用抵抗
３３ 検出回路
３３ａ コンパレータ DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Semiconductor element 10a Mounting surface 11 Terminal group 11a 1st class terminal 11b 2nd class terminal 11c 3rd class terminal 20 Board | substrate 31 Short circuit detection wiring 32 Detection resistance 33 Detection circuit 33a Comparator

Claims (7)

複数の端子からなる端子群を有する半導体素子と、
該半導体素子と前記端子群を介して接続される基板とを備えた半導体装置であって、
前記端子群における、少なくとも２つの隣り合う端子の間に、該端子の短絡検出用配線を配置したことを特徴とする半導体装置。 A semiconductor element having a terminal group consisting of a plurality of terminals;
A semiconductor device comprising the semiconductor element and a substrate connected via the terminal group,
A semiconductor device, wherein a short-circuit detection wiring of the terminal is arranged between at least two adjacent terminals in the terminal group. 前記短絡検出用配線は短絡検出用の検出回路に接続され、
該短絡検出用配線および検出回路の何れか一方を前記半導体素子に設け、何れか他方を前記基板に設けたことを特徴とする請求項１に記載の半導体装置。 The short-circuit detection wiring is connected to a detection circuit for short-circuit detection,
2. The semiconductor device according to claim 1, wherein one of the short-circuit detection wiring and the detection circuit is provided on the semiconductor element, and the other is provided on the substrate. 前記短絡検出用配線は短絡検出用の検出回路に接続され、
該短絡検出用配線および検出回路の両方を、前記半導体素子または基板に設けたことを特徴とする請求項１に記載の半導体装置。 The short-circuit detection wiring is connected to a detection circuit for short-circuit detection,
2. The semiconductor device according to claim 1, wherein both the short-circuit detection wiring and the detection circuit are provided on the semiconductor element or the substrate. 前記短絡検出用配線は接地電位に接続されており、
前記検出回路は、短絡検出用配線の電位変化により端子間の短絡の有無を判断することを特徴とする請求項２または請求項３に記載の半導体装置。 The short-circuit detection wiring is connected to a ground potential,
The semiconductor device according to claim 2, wherein the detection circuit determines whether or not there is a short circuit between terminals based on a potential change of a short circuit detection wiring. 前記短絡検出用配線には、電流源から微少電流が印加されており、
前記検出回路は、短絡検出用配線の電位変化により端子間の短絡の有無を判断することを特徴とする請求項２または請求項３に記載の半導体装置。 A minute current is applied to the short-circuit detection wiring from a current source,
The semiconductor device according to claim 2, wherein the detection circuit determines whether or not there is a short circuit between terminals based on a potential change of a short circuit detection wiring. 複数の端子からなる端子群を有する半導体素子と、該半導体素子と前記端子群を介して接続される基板とを備えた半導体装置において、
前記端子群における、少なくとも２つの隣り合う端子の間に、該端子の短絡検出用配線を配置し、
前記短絡検出用配線を接地電圧に接続し、
該短絡検出用配線の電位変化により端子間の短絡の有無を判断する、
ことを特徴とする半導体装置の端子間短絡検出方法。 In a semiconductor device comprising a semiconductor element having a terminal group consisting of a plurality of terminals, and a substrate connected to the semiconductor element via the terminal group,
In the terminal group, between the at least two adjacent terminals, the short-circuit detection wiring of the terminal is disposed,
Connecting the short-circuit detection wiring to a ground voltage;
Judging the presence or absence of a short circuit between the terminals by the potential change of the short circuit detection wiring,
A method of detecting a short circuit between terminals of a semiconductor device. 複数の端子からなる端子群を有する半導体素子と、該半導体素子と前記端子群を介して接続される基板とを備えた半導体装置において、
前記端子群における、少なくとも２つの隣り合う端子の間に、該端子の短絡検出用配線を配置し、
前記短絡検出用配線に、電流源から微少電流を印加して、
該短絡検出用配線の電位変化により端子間の短絡の有無を判断する、
ことを特徴とする半導体装置の端子間短絡検出方法。

In a semiconductor device comprising a semiconductor element having a terminal group consisting of a plurality of terminals, and a substrate connected to the semiconductor element via the terminal group,
In the terminal group, between the at least two adjacent terminals, the short-circuit detection wiring of the terminal is disposed,
Apply a minute current from the current source to the short-circuit detection wiring,
Judging the presence or absence of a short circuit between the terminals based on the potential change of the short circuit detection wiring,
A method of detecting a short circuit between terminals of a semiconductor device.

JP2005200530A 2005-07-08 2005-07-08 Semiconductor device and method for detecting short circuit between terminals thereof Expired - Fee Related JP4412250B2 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7906946B2 (en) 2007-03-29 2011-03-15 Denso Corporation Semiconductor integrated circuit device for providing series regulator
KR101045036B1 (en) 2007-04-09 2011-06-30 요코가와 덴키 가부시키가이샤 Ic tester
WO2011148802A1 (en) * 2010-05-27 2011-12-01 日本精機株式会社 Control circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7906946B2 (en) 2007-03-29 2011-03-15 Denso Corporation Semiconductor integrated circuit device for providing series regulator
KR101045036B1 (en) 2007-04-09 2011-06-30 요코가와 덴키 가부시키가이샤 Ic tester
WO2011148802A1 (en) * 2010-05-27 2011-12-01 日本精機株式会社 Control circuit

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