JP2007011947A - Power source regulator circuit - Google Patents

Power source regulator circuit Download PDF

Info

Publication number
JP2007011947A
JP2007011947A JP2005194884A JP2005194884A JP2007011947A JP 2007011947 A JP2007011947 A JP 2007011947A JP 2005194884 A JP2005194884 A JP 2005194884A JP 2005194884 A JP2005194884 A JP 2005194884A JP 2007011947 A JP2007011947 A JP 2007011947A
Authority
JP
Japan
Prior art keywords
voltage
type mosfet
terminal
power supply
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2005194884A
Other languages
Japanese (ja)
Inventor
Emiko Yoshida
絵美子 吉田
Koichi Notoya
晃一 能登谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Priority to JP2005194884A priority Critical patent/JP2007011947A/en
Publication of JP2007011947A publication Critical patent/JP2007011947A/en
Withdrawn legal-status Critical Current

Links

Images

Landscapes

  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power source regulator circuit wherein fluctuation of an output voltage is small even without adding a capacitor to an output terminal. <P>SOLUTION: This power source regulator circuit has: a P-type MOSFET 1 connected to between an input power source terminal 10 and the output terminal 20; resistors R1, R2 connected to between the output terminal 20 and a ground terminal 30; a comparator 3 comparing a feedback voltage Vfb obtained by dividing the output voltage Vout of the output terminal 20 by the resistors R1, R2 and a reference voltage Vref generated by a reference voltage generation circuit 2, and changing a voltage inputted to a gate terminal of the P-type MOSFET 1 such that the feedback voltage Vfb accords with the reference voltage Vref; an N-type MOSFET 4 connected to the P-type MOSFET 1 in parallel, turning off when the output voltage Vout is a prescribed voltage, and turning on when the output voltage Vout falls; and a constant voltage generation circuit 5A generating a gate voltage of the N-type MOSFET 4. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、電源レギュレータ回路に関し、特に入力電源電圧を降圧して所定の出力電圧を発生する電源レギュレータ回路に関する。   The present invention relates to a power supply regulator circuit, and more particularly to a power supply regulator circuit that generates a predetermined output voltage by stepping down an input power supply voltage.

ＣＭＯＳ型ＬＳＩの素子数の増加に伴い、ＣＭＯＳ型ＬＳＩの発熱が大きな問題となっている。その対策の１つとして、ＣＭＯＳ型ＬＳＩ内部の動作電圧を下げることが有効である。一方、ＣＭＯＳ型ＬＳＩの入出力部は、外部とのインターフェースの仕様上、従来の動作電圧を使用しなければならない場合がある。そこで、ＣＭＯＳ型ＬＳＩの入出力部へは、従来の高い電圧で供給される電源電圧をそのまま与え、ＣＭＯＳ型ＬＳＩ内部回路へは、この電源電圧を降圧して低い電圧を与えることが行われる。そのため、ＣＭＯＳ型ＬＳＩの内部に、入力電源電圧を降圧して所定の出力電圧を発生する電源レギュレータ回路を組み込むことがある。   With the increase in the number of elements of a CMOS LSI, heat generation of the CMOS LSI has become a big problem. As one of the countermeasures, it is effective to lower the operating voltage inside the CMOS LSI. On the other hand, the input / output unit of the CMOS LSI may need to use a conventional operating voltage due to the specifications of the interface with the outside. Therefore, a conventional power supply voltage supplied at a high voltage is directly applied to the input / output section of the CMOS LSI, and a low voltage is applied to the CMOS LSI internal circuit by stepping down the power supply voltage. Therefore, a power supply regulator circuit that steps down the input power supply voltage and generates a predetermined output voltage may be incorporated in the CMOS LSI.

ＣＭＯＳ型ＬＳＩに組み込まれる電源レギュレータ回路として、Ｐ型ＭＯＳＦＥＴのソース端子を入力電源端子に接続し、ドレイン端子に抵抗負荷を接続して、このドレイン端子の電圧を出力電圧Ｖｏｕｔとする回路が用いられる。   As a power supply regulator circuit incorporated in a CMOS type LSI, a circuit is used in which a source terminal of a P-type MOSFET is connected to an input power supply terminal, a resistance load is connected to the drain terminal, and the voltage at the drain terminal is used as the output voltage Vout. .

この電源レギュレータ回路では、上述の負荷抵抗をＰ型ＭＯＳＦＥＴのドレイン端子と接地端子との間に直列に接続した２つの抵抗Ｒ１、Ｒ２とし、この抵抗Ｒ１、Ｒ２で出力電圧Ｖｏｕｔを分圧した電圧を帰還電圧Ｖｆｂとして、基準電圧Ｖｒｅｆと比較する比較器を設け、この比較器の出力をＰ型ＭＯＳＦＥＴのゲート端子に入力する回路構成がとられる。   In this power supply regulator circuit, the load resistor described above is two resistors R1 and R2 connected in series between the drain terminal and the ground terminal of the P-type MOSFET, and a voltage obtained by dividing the output voltage Vout by the resistors R1 and R2. Is provided as a feedback voltage Vfb, and a comparator for comparing with the reference voltage Vref is provided, and the output of this comparator is input to the gate terminal of the P-type MOSFET.

このような構成の電源レギュレータ回路において、比較器がＶｆｂ＝ＶｒｅｆとなるようにＰ型ＭＯＳＦＥＴのゲート電圧を変化させることにより出力電圧Ｖｏｕｔを制御することが行われる。このような帰還制御を行うことにより、Ｐ型ＭＯＳＦＥＴのドレイン端子からＶｏｕｔ＝Ｖｒｅｆ×（１＋Ｒ１／Ｒ２）となる一定の出力電圧が得られる。   In the power supply regulator circuit having such a configuration, the output voltage Vout is controlled by changing the gate voltage of the P-type MOSFET so that the comparator satisfies Vfb = Vref. By performing such feedback control, a constant output voltage Vout = Vref × (1 + R1 / R2) is obtained from the drain terminal of the P-type MOSFET.

ただし、このような帰還制御には次のような問題がある。それは、帰還経路に抵抗Ｒ１、Ｒ２が存在するため、その抵抗値が帰還速度を決定する１つの要因になることである。   However, such feedback control has the following problems. That is, since the resistors R1 and R2 exist in the feedback path, the resistance value is one factor that determines the feedback speed.

例えば、モバイル用途のＬＳＩでは低消費電力が要求されるので、抵抗に流れる電流を少なくするため、抵抗Ｒ１、Ｒ２の抵抗値を１ＭΩ以上にすることがある。このような場合、電源レギュレータ回路の負荷電流が急激に増加して出力電圧Ｖｏｕｔが急激に低下すると、電源レギュレータ回路の比較器が出力電圧Ｖｏｕｔを元に戻そうとするが、抵抗Ｒ１、Ｒ２と寄生容量のために帰還電圧Ｖｆｂの変化が遅く、また、比較器が所望の電圧を出力するまでの時間が長い場合もあり、出力電圧Ｖｏｕｔの回復に長い時間を要する。   For example, since low power consumption is required in an LSI for mobile use, the resistance values of the resistors R1 and R2 may be set to 1 MΩ or more in order to reduce the current flowing through the resistors. In such a case, when the load current of the power supply regulator circuit increases rapidly and the output voltage Vout decreases rapidly, the comparator of the power supply regulator circuit tries to restore the output voltage Vout, but the resistors R1 and R2 Due to the parasitic capacitance, the change in the feedback voltage Vfb is slow, and it may take a long time for the comparator to output a desired voltage, and it takes a long time to recover the output voltage Vout.

そこで、電源レギュレータ回路の負荷電流が急激に変化しても出力電圧Ｖｏｕｔが急激に変化しないように、電源レギュレータ回路の出力端子、すなわちＰ型ＭＯＳＦＥＴのドレイン端子にコンデンサを付加することが行われる（例えば、特許文献１参照。）
このコンデンサの付加により、出力電圧Ｖｏｕｔの変動を小さくすることができるが、抵抗Ｒ１、Ｒ２の抵抗値が１ＭΩ以上であるような場合や、Ｖｏｕｔの負荷電流が数十μＡである場合、十分な出力電圧変動抑制効果を得るには、コンデンサの容量を１μＦ程度の大容量にしなければならない。 Therefore, a capacitor is added to the output terminal of the power supply regulator circuit, that is, the drain terminal of the P-type MOSFET so that the output voltage Vout does not change suddenly even if the load current of the power supply regulator circuit changes suddenly ( For example, see Patent Document 1.)
By adding this capacitor, the fluctuation of the output voltage Vout can be reduced. However, when the resistance values of the resistors R1 and R2 are 1 MΩ or more, or when the load current of Vout is several tens of μA, it is sufficient. In order to obtain the output voltage fluctuation suppressing effect, the capacitance of the capacitor must be as large as about 1 μF.

しかし、このような大容量のコンデンサをＬＳＩの内部に形成するには膨大な面積を必要とし、ＬＳＩのチップサイズを考慮すると、現実的には、ＬＳＩの内部にこのコンデンサを形成することができないという問題があった。また、このコンデンサを外付け部品としてＬＳＩの外部端子に接続するようにすると、ＬＳＩを搭載する基板の部品点数の増加、基板作成工程の増加を招くという問題があった。
特開２００４−３４１８７７号公報 （第９ページ、図４） However, in order to form such a large-capacity capacitor inside the LSI, an enormous area is required, and considering the chip size of the LSI, it is practically impossible to form this capacitor inside the LSI. There was a problem. Further, if this capacitor is connected as an external component to the external terminal of the LSI, there is a problem that the number of parts of the board on which the LSI is mounted is increased and the board production process is increased.
JP 2004-341877 A (9th page, FIG. 4)

そこで、本発明の目的は、出力端子にコンデンサを付加しなくても出力電圧の変動が小さい電源レギュレータ回路を提供することにある。   Accordingly, an object of the present invention is to provide a power supply regulator circuit in which fluctuation of the output voltage is small without adding a capacitor to the output terminal.

本発明の一態様によれば、入力電源端子にソース端子が接続され、出力端子にドレイン端子が接続されるＰ型ＭＯＳＦＥＴと、前記出力端子と接地端子との間に接続される第１および第２の抵抗と、前記出力端子の出力電圧を前記第１および第２の抵抗で分圧した帰還電圧と基準電圧とを比較し、前記帰還電圧が前記基準電圧と一致するよう前記Ｐ型ＭＯＳＦＥＴのゲート端子へ入力する電圧を変化させる比較器とを備え、前記Ｐ型ＭＯＳＦＥＴに並列に接続され、前記出力電圧が所定の電圧のときはオフしていて、前記出力電圧が低下したときにオンするＮ型ＭＯＳＦＥＴを有することを特徴とする電源レギュレータ回路が提供される。   According to one aspect of the present invention, a P-type MOSFET having a source terminal connected to the input power supply terminal and a drain terminal connected to the output terminal, and the first and second terminals connected between the output terminal and the ground terminal. 2 and a feedback voltage obtained by dividing the output voltage of the output terminal by the first and second resistors, and a reference voltage, and the P-type MOSFET of the P-type MOSFET is matched so that the feedback voltage matches the reference voltage. A comparator for changing a voltage input to the gate terminal, connected in parallel to the P-type MOSFET, and turned off when the output voltage is a predetermined voltage and turned on when the output voltage is lowered. A power supply regulator circuit comprising an N-type MOSFET is provided.

本発明によれば、負荷電流が急激に増加して出力電圧が下がるとＮ型ＭＯＳＦＥＴが速やかに導通して負荷電流を供給するので、出力電圧の変動を小さくすることができる。   According to the present invention, when the load current suddenly increases and the output voltage decreases, the N-type MOSFET quickly conducts and supplies the load current, so that fluctuations in the output voltage can be reduced.

以下、本発明の実施例を図面を参照して説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図１は、本発明の実施例１に係る電源レギュレータ回路の構成の例を示す回路図である。   1 is a circuit diagram showing an example of the configuration of a power regulator circuit according to a first embodiment of the present invention.

本実施例の電源レギュレータ回路は、入力電源端子１０にソース端子が接続され、出力端子２０にドレイン端子が接続されるＰ型ＭＯＳＦＥＴ１と、入力電源端子１０と接地端子３０とに接続されて基準電圧Ｖｒｅｆを生成する基準電圧生成回路２と、出力端子２０と接地端子３０との間に直列に接続され、出力電圧Ｖｏｕｔを分圧した帰還電圧Ｖｆｂを生成する抵抗Ｒ１および抵抗Ｒ２と、反転入力（−）端子に入力された基準電圧Ｖｒｅｆの値と、非反転入力（＋）端子に入力された帰還電圧Ｖｆｂの値とを比較し、その差分に応じた電圧をＰ型ＭＯＳＦＥＴ１のゲート端子へ入力する比較器３とからなる従来の電源レギュレータ回路に、Ｐ型ＭＯＳＦＥＴ１に並列に接続されて、入力電源端子１０にドレイン端子が接続され、出力端子２０にソース端子が接続されるＮ型ＭＯＳＦＥＴ４を設け、さらに、入力電源端子１０と接地端子３０とに接続されてＮ型ＭＯＳＦＥＴ４のゲート端子へ与える定電圧を生成する定電圧生成回路５Ａを備えた構成を有する。   The power supply regulator circuit of this embodiment is connected to a P-type MOSFET 1 having a source terminal connected to the input power supply terminal 10 and a drain terminal connected to the output terminal 20, and to a reference voltage connected to the input power supply terminal 10 and the ground terminal 30. A reference voltage generation circuit 2 that generates Vref, a resistor R1 and a resistor R2 that are connected in series between the output terminal 20 and the ground terminal 30, generate a feedback voltage Vfb obtained by dividing the output voltage Vout, and an inverting input ( The value of the reference voltage Vref input to the −) terminal is compared with the value of the feedback voltage Vfb input to the non-inverting input (+) terminal, and a voltage corresponding to the difference is input to the gate terminal of the P-type MOSFET 1. Is connected in parallel to the P-type MOSFET 1 and has a drain terminal connected to the input power supply terminal 10 and an output terminal. An N-type MOSFET 4 whose source terminal is connected to 0 is provided, and a constant voltage generation circuit 5A that is connected to the input power supply terminal 10 and the ground terminal 30 and generates a constant voltage to be applied to the gate terminal of the N-type MOSFET 4 is provided. It has a configuration.

定電圧生成回路５Ａは、出力電圧Ｖｏｕｔが所定の電圧であるときのＮ型ＭＯＳＦＥＴ４のゲート−ソース間電圧Ｖｇｓが、Ｎ型ＭＯＳＦＥＴ４のしきい値電圧Ｖｔｈより小さくなる（Ｖｇｓ＜Ｖｔｈ）ような定電圧を発生する。したがって、出力電圧Ｖｏｕｔが所定の電圧である通常動作時には、Ｎ型ＭＯＳＦＥＴ４はオフしている。   The constant voltage generation circuit 5A is configured such that the gate-source voltage Vgs of the N-type MOSFET 4 when the output voltage Vout is a predetermined voltage is smaller than the threshold voltage Vth of the N-type MOSFET 4 (Vgs <Vth). Generate voltage. Therefore, the N-type MOSFET 4 is off during normal operation when the output voltage Vout is a predetermined voltage.

このように通常はＮ型ＭＯＳＦＥＴ４がオフしているため、本実施例の電源レギュレータ回路も、従来の電源レギュレータ回路と同様、Ｖｏｕｔ＝Ｖｒｅｆ×（１＋Ｒ１／Ｒ２）で決定される出力電圧Ｖｏｕｔを出力する。   As described above, since the N-type MOSFET 4 is normally off, the power supply regulator circuit of this embodiment also outputs the output voltage Vout determined by Vout = Vref × (1 + R1 / R2), similarly to the conventional power supply regulator circuit. To do.

出力端子２０に接続される負荷を流れる負荷電流が急激に増加すると、出力電圧Ｖｏｕｔが低下し、出力電圧Ｖｏｕｔを抵抗Ｒ１および抵抗Ｒ２で分圧した帰還電圧Ｖｆｂも低下する。そのため、比較器３は、Ｐ型ＭＯＳＦＥＴ１を流れる電流が増加するようＰ型ＭＯＳＦＥＴ１のゲート電圧を下げようとする。しかし、抵抗Ｒ１および抵抗Ｒ２による帰還時間が大きいため、Ｐ型ＭＯＳＦＥＴ１を流れる電流の増加の割合は小さい。   When the load current flowing through the load connected to the output terminal 20 suddenly increases, the output voltage Vout decreases, and the feedback voltage Vfb obtained by dividing the output voltage Vout by the resistors R1 and R2 also decreases. Therefore, the comparator 3 tries to lower the gate voltage of the P-type MOSFET 1 so that the current flowing through the P-type MOSFET 1 increases. However, since the feedback time by the resistors R1 and R2 is long, the rate of increase in the current flowing through the P-type MOSFET 1 is small.

一方、出力電圧Ｖｏｕｔが低下して、Ｎ型ＭＯＳＦＥＴ４のゲート−ソース間電圧Ｖｇｓが、Ｎ型ＭＯＳＦＥＴ４のしきい値電圧Ｖｔｈ以上（Ｖｇｓ≧Ｖｔｈ）になると、Ｎ型ＭＯＳＦＥＴ４がオンし、負荷電流を供給するようになる。このとき、Ｎ型ＭＯＳＦＥＴ４には常に一定のゲート電圧が印加されているため、Ｎ型ＭＯＳＦＥＴ４は急速に導通し、負荷電流を急速に供給する。   On the other hand, when the output voltage Vout decreases and the gate-source voltage Vgs of the N-type MOSFET 4 becomes equal to or higher than the threshold voltage Vth of the N-type MOSFET 4 (Vgs ≧ Vth), the N-type MOSFET 4 is turned on and the load current is reduced. Come to supply. At this time, since a constant gate voltage is always applied to the N-type MOSFET 4, the N-type MOSFET 4 conducts rapidly and supplies a load current rapidly.

このようなＮ型ＭＯＳＦＥＴ４による高速な電流補強により、出力電圧Ｖｏｕｔの大幅な電圧低下を抑えることができる。   Such a high-speed current reinforcement by the N-type MOSFET 4 can suppress a significant voltage drop of the output voltage Vout.

図２に、負荷電流が急激の増加した場合の本実施例の出力電圧Ｖｏｕｔと、比較例としてＮ型ＭＯＳＦＥＴ４を有さない従来の電源レギュレータ回路の出力電圧Ｖｏｕｔのシミュレーションによる波形を示す。   FIG. 2 shows waveforms obtained by simulating the output voltage Vout of this embodiment when the load current increases rapidly and the output voltage Vout of a conventional power supply regulator circuit that does not have the N-type MOSFET 4 as a comparative example.

図２に示すように、Ｎ型ＭＯＳＦＥＴ４を有さない従来の電源レギュレータ回路の場合、負荷電流が急激に増加すると、出力電圧Ｖｏｕｔは大きく低下し、また、元の電圧に回復するまでの時間が長い。それに対して、本実施例の電源レギュレータ回路の場合、負荷電流が急激に増加すると、Ｎ型ＭＯＳＦＥＴ４がオンするまでの間は出力電圧Ｖｏｕｔが低下するが、Ｎ型ＭＯＳＦＥＴ４がオンすると、出力電圧Ｖｏｕｔは急速に回復する。   As shown in FIG. 2, in the case of a conventional power supply regulator circuit that does not have the N-type MOSFET 4, when the load current increases rapidly, the output voltage Vout greatly decreases and the time until the original voltage is restored long. On the other hand, in the power supply regulator circuit of this embodiment, when the load current increases rapidly, the output voltage Vout decreases until the N-type MOSFET 4 is turned on, but when the N-type MOSFET 4 is turned on, the output voltage Vout Recovers rapidly.

したがって、従来の電源レギュレータ回路に比べて、本実施例の電源レギュレータ回路の出力電圧Ｖｏｕｔの変動は小さく抑えられる。   Therefore, the fluctuation of the output voltage Vout of the power supply regulator circuit of the present embodiment can be suppressed as compared with the conventional power supply regulator circuit.

このような本実施例によれば、電源レギュレータ回路の負荷電流が急激に増加して、電源レギュレータ回路の出力電圧が下がると、Ｐ型ＭＯＳＦＥＴに並列に接続したＮ型ＭＯＳＦＥＴが速やかに導通して負荷電流を供給するので、電源レギュレータ回路の出力電圧の変動を小さくすることができる。   According to this embodiment, when the load current of the power supply regulator circuit increases rapidly and the output voltage of the power supply regulator circuit decreases, the N-type MOSFET connected in parallel to the P-type MOSFET quickly conducts. Since the load current is supplied, fluctuations in the output voltage of the power regulator circuit can be reduced.

図３は、本発明の実施例２に係る電源レギュレータ回路の構成の例を示す回路図である。   FIG. 3 is a circuit diagram showing an example of the configuration of the power regulator circuit according to the second embodiment of the present invention.

本実施例の電源レギュレータ回路が実施例１の電源レギュレータ回路と異なる点は、定電圧生成回路５Ｂが基準電圧生成回路２に接続されていることである。   The power regulator circuit of this embodiment is different from the power regulator circuit of the first embodiment in that the constant voltage generation circuit 5B is connected to the reference voltage generation circuit 2.

その他の回路構成は実施例１と同じであり、その動作も実施例１と同じである。そこで、図３において、図１に示す回路要素と同じ回路要素には図１と同じ符号を付し、ここではその詳細な説明を省略する。   Other circuit configurations are the same as those in the first embodiment, and their operations are also the same as those in the first embodiment. Therefore, in FIG. 3, the same circuit elements as those shown in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and detailed description thereof is omitted here.

本実施例の定電圧生成回路５Ｂは基準電圧生成回路２に接続されており、Ｎ型ＭＯＳＦＥＴ４のゲート端子へ入力する定電圧を基準電圧生成回路２の出力である基準電圧Ｖｒｅｆから生成する。この基準電圧Ｖｒｅｆは、入力電源端子１０へ入力される入力電源に電圧変動があっても一定電圧を出力するよう基準電圧生成回路２により制御されている。したがって、定電圧生成回路５Ｂへ入力される基準電圧Ｖｒｅｆは安定している。   The constant voltage generation circuit 5B of this embodiment is connected to the reference voltage generation circuit 2 and generates a constant voltage input to the gate terminal of the N-type MOSFET 4 from the reference voltage Vref that is the output of the reference voltage generation circuit 2. The reference voltage Vref is controlled by the reference voltage generation circuit 2 so as to output a constant voltage even when the input power supply input to the input power supply terminal 10 has a voltage fluctuation. Therefore, the reference voltage Vref input to the constant voltage generation circuit 5B is stable.

一方、実施例１の定電圧生成回路５Ａは入力電源端子１０に接続されて、入力電源電圧からＮ型ＭＯＳＦＥＴ４のゲート端子へ入力する定電圧を生成している。そのため、定電圧生成回路５Ｂへ入力される入力電源電圧は変動する。したがって、実施例１の定電圧生成回路５Ａには、基準電圧生成回路２と同様、入力電源の電圧変動を抑制する制御が必要となる。   On the other hand, the constant voltage generation circuit 5A according to the first embodiment is connected to the input power supply terminal 10 and generates a constant voltage input from the input power supply voltage to the gate terminal of the N-type MOSFET 4. Therefore, the input power supply voltage input to the constant voltage generation circuit 5B varies. Therefore, like the reference voltage generation circuit 2, the constant voltage generation circuit 5A according to the first embodiment needs to be controlled to suppress voltage fluctuations of the input power supply.

これに対して、本実施例の定電圧生成回路５Ｂでは、電圧レベルが安定している基準電圧ＶｒｅｆからＮ型ＭＯＳＦＥＴ４のゲート端子へ入力する定電圧を生成するため、実施例１の定電圧生成回路５Ａと異なり、入力電源の電圧変動を抑制する制御が不要となる。そのため、本実施例の定電圧生成回路５Ｂは、実施例１の定電圧生成回路５Ａに比べて、回路を簡素化することができる。   On the other hand, the constant voltage generation circuit 5B according to the present embodiment generates a constant voltage that is input to the gate terminal of the N-type MOSFET 4 from the reference voltage Vref having a stable voltage level. Unlike the circuit 5A, the control for suppressing the voltage fluctuation of the input power supply becomes unnecessary. Therefore, the constant voltage generation circuit 5B according to the present embodiment can be simplified in comparison with the constant voltage generation circuit 5A according to the first embodiment.

このような本実施例によれば、Ｎ型ＭＯＳＦＥＴのゲート端子へ入力する電圧を電圧レベルが安定している基準電圧Ｖｒｅｆから生成するため、Ｎ型ＭＯＳＦＥＴのゲート端子へ入力する電圧を定電圧に制御する回路を簡単に構成することができる。   According to the present embodiment, the voltage input to the gate terminal of the N-type MOSFET is generated from the reference voltage Vref whose voltage level is stable, so that the voltage input to the gate terminal of the N-type MOSFET is a constant voltage. The circuit to be controlled can be configured easily.

図４は、本発明の実施例３に係る電源レギュレータ回路の構成の例を示す回路図である。   FIG. 4 is a circuit diagram showing an example of the configuration of the power supply regulator circuit according to the third embodiment of the present invention.

本実施例の電源レギュレータ回路が実施例１の電源レギュレータ回路と異なる点は、Ｎ型ＭＯＳＦＥＴ４のゲート端子へ入力する電圧を定電圧生成回路５Ａから入力するのではなく、ゲート電圧入力端子４０から入力する点である。   The power regulator circuit of this embodiment is different from the power regulator circuit of the first embodiment in that the voltage input to the gate terminal of the N-type MOSFET 4 is not input from the constant voltage generation circuit 5A but input from the gate voltage input terminal 40. It is a point to do.

その他の回路構成は実施例１と同じであり、その動作も実施例１と同じである。そこで、図４において、図１に示す回路要素と同じ回路要素には図１と同じ符号を付し、ここではその詳細な説明を省略する。   Other circuit configurations are the same as those in the first embodiment, and their operations are also the same as those in the first embodiment. Therefore, in FIG. 4, the same circuit elements as those shown in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and detailed description thereof is omitted here.

本実施例のゲート電圧入力端子４０は、電源レギュレータ回路の外部からＮ型ＭＯＳＦＥＴ４のゲート端子へ、出力電圧Ｖｏｕｔが所定の電圧であるときのＮ型ＭＯＳＦＥＴ４のゲート−ソース間電圧Ｖｇｓが、Ｎ型ＭＯＳＦＥＴ４のしきい値電圧Ｖｔｈより小さくなる（Ｖｇｓ＜Ｖｔｈ）ような電圧を入力する端子である。   The gate voltage input terminal 40 of this embodiment is such that the gate-source voltage Vgs of the N-type MOSFET 4 when the output voltage Vout is a predetermined voltage from the outside of the power supply regulator circuit to the gate terminal of the N-type MOSFET 4 is N-type. This is a terminal for inputting a voltage lower than the threshold voltage Vth of the MOSFET 4 (Vgs <Vth).

実施例１の定電圧生成回路５Ａあるいは実施例２の定電圧生成回路５Ｂは、電源レギュレータ回路の内部に予め作られているため、その出力電圧は固定である。したがって、Ｎ型ＭＯＳＦＥＴ４を流れる電流量も固定されている。   Since the constant voltage generation circuit 5A of the first embodiment or the constant voltage generation circuit 5B of the second embodiment is made in advance in the power supply regulator circuit, its output voltage is fixed. Therefore, the amount of current flowing through the N-type MOSFET 4 is also fixed.

これに対して、本実施例では、Ｎ型ＭＯＳＦＥＴ４のゲート端子へ入力する電圧をゲート電圧入力端子４０により変更することができる。これにより、出力端子４０に接続される負荷に流れる電流の大きさに応じて、Ｎ型ＭＯＳＦＥＴ４に流す電流量を自由に制御することができる。   On the other hand, in this embodiment, the voltage input to the gate terminal of the N-type MOSFET 4 can be changed by the gate voltage input terminal 40. Thereby, according to the magnitude | size of the electric current which flows into the load connected to the output terminal 40, the electric current amount which flows into N type MOSFET4 can be controlled freely.

このような本実施例によれば、Ｎ型ＭＯＳＦＥＴのゲート端子へ入力する電圧を電源レギュレータの外部から制御することができるので、Ｎ型ＭＯＳＦＥＴに流す電流量の制御の自由度を広げることができる。   According to this embodiment, since the voltage input to the gate terminal of the N-type MOSFET can be controlled from the outside of the power supply regulator, the degree of freedom in controlling the amount of current flowing through the N-type MOSFET can be expanded. .

本発明の実施例１に係る電源レギュレータ回路の構成の例を示す回路図。1 is a circuit diagram showing an example of a configuration of a power supply regulator circuit according to Embodiment 1 of the present invention. 本発明の実施例１に係る電源レギュレータ回路の動作の例を示すシミュレーション波形図。FIG. 4 is a simulation waveform diagram showing an example of the operation of the power regulator circuit according to the first embodiment of the present invention. 本発明の実施例２に係る電源レギュレータ回路の構成の例を示す回路図。The circuit diagram which shows the example of a structure of the power supply regulator circuit which concerns on Example 2 of this invention. 本発明の実施例３に係る電源レギュレータ回路の構成の例を示す回路図。FIG. 6 is a circuit diagram illustrating an example of a configuration of a power regulator circuit according to a third embodiment of the present invention.

符号の説明Explanation of symbols

１ Ｐ型ＭＯＳＦＥＴ
２ 基準電圧生成回路
３ 比較器
４ Ｎ型ＭＯＳＦＥＴ
５Ａ、５Ｂ 定電圧生成回路
１０ 入力電源端子
２０ 出力端子
３０ 接地端子
４０ ゲート電圧入力端子
Ｒ１、Ｒ２ 抵抗 1 P-type MOSFET
2 Reference voltage generation circuit 3 Comparator 4 N-type MOSFET
5A, 5B Constant voltage generation circuit 10 Input power supply terminal 20 Output terminal 30 Ground terminal 40 Gate voltage input terminals R1, R2 Resistance

Claims (5)

入力電源端子にソース端子が接続され、出力端子にドレイン端子が接続されるＰ型ＭＯＳＦＥＴと、
前記出力端子と接地端子との間に接続される第１および第２の抵抗と、
前記出力端子の出力電圧を前記第１および第２の抵抗で分圧した帰還電圧と基準電圧とを比較し、前記帰還電圧が前記基準電圧と一致するよう前記Ｐ型ＭＯＳＦＥＴのゲート端子へ入力する電圧を変化させる比較器と
を備え、
前記Ｐ型ＭＯＳＦＥＴに並列に接続され、前記出力電圧が所定の電圧のときはオフしていて、前記出力電圧が低下したときにオンするＮ型ＭＯＳＦＥＴを有すること
を特徴とする電源レギュレータ回路。 A P-type MOSFET having a source terminal connected to the input power supply terminal and a drain terminal connected to the output terminal;
First and second resistors connected between the output terminal and a ground terminal;
A feedback voltage obtained by dividing the output voltage of the output terminal by the first and second resistors is compared with a reference voltage, and input to the gate terminal of the P-type MOSFET so that the feedback voltage matches the reference voltage. A comparator for changing the voltage,
A power supply regulator circuit comprising an N-type MOSFET connected in parallel to the P-type MOSFET and turned off when the output voltage is a predetermined voltage and turned on when the output voltage drops. 前記Ｎ型ＭＯＳＦＥＴのしきい値電圧より低い一定電圧を生成して前記Ｎ型ＭＯＳＦＥＴのゲート端子へ入力する定電圧生成生回路を有することを特徴とする請求項１に記載の電源レギュレータ回路。   2. The power supply regulator circuit according to claim 1, further comprising a constant voltage generation circuit that generates a constant voltage lower than a threshold voltage of the N-type MOSFET and inputs the constant voltage to a gate terminal of the N-type MOSFET. 前記定電圧生成回路は、前記入力電圧端子へ接続されることを特徴とする請求項２に記載の電源レギュレータ回路。   The power supply regulator circuit according to claim 2, wherein the constant voltage generation circuit is connected to the input voltage terminal. 前記定電圧生成回路は、前記基準電圧が入力されることを特徴とする請求項２に記載の電源レギュレータ回路。   The power supply regulator circuit according to claim 2, wherein the reference voltage is input to the constant voltage generation circuit. 前記Ｎ型ＭＯＳＦＥＴのゲート端子へ前記Ｎ型ＭＯＳＦＥＴのしきい値電圧より低い一定電圧を入力する端子を有することを特徴とする請求項１に記載の電源レギュレータ回路。   2. The power supply regulator circuit according to claim 1, further comprising a terminal for inputting a constant voltage lower than a threshold voltage of the N-type MOSFET to the gate terminal of the N-type MOSFET.
JP2005194884A 2005-07-04 2005-07-04 Power source regulator circuit Withdrawn JP2007011947A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005194884A JP2007011947A (en) 2005-07-04 2005-07-04 Power source regulator circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005194884A JP2007011947A (en) 2005-07-04 2005-07-04 Power source regulator circuit

Publications (1)

Publication Number Publication Date
JP2007011947A true JP2007011947A (en) 2007-01-18

Family

ID=37750305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005194884A Withdrawn JP2007011947A (en) 2005-07-04 2005-07-04 Power source regulator circuit

Country Status (1)

Country Link
JP (1) JP2007011947A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103021317A (en) * 2012-12-14 2013-04-03 京东方科技集团股份有限公司 Drive circuit and display screen
US9059703B2 (en) 2013-08-29 2015-06-16 Kabushiki Kaisha Toshiba Switch circuit
CN105404341A (en) * 2014-09-12 2016-03-16 南车株洲电力机车研究所有限公司 Device and system for power output voltage sampling feedback
JP2016143394A (en) * 2015-02-05 2016-08-08 ローム株式会社 Linear power supply and electronic device using the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103021317A (en) * 2012-12-14 2013-04-03 京东方科技集团股份有限公司 Drive circuit and display screen
US9059703B2 (en) 2013-08-29 2015-06-16 Kabushiki Kaisha Toshiba Switch circuit
CN105404341A (en) * 2014-09-12 2016-03-16 南车株洲电力机车研究所有限公司 Device and system for power output voltage sampling feedback
JP2016143394A (en) * 2015-02-05 2016-08-08 ローム株式会社 Linear power supply and electronic device using the same
WO2016125412A1 (en) * 2015-02-05 2016-08-11 ローム株式会社 Linear power supply and electronic apparatus using same
US10168720B2 (en) 2015-02-05 2019-01-01 Rohm Co., Ltd. Linear power supply and electronic apparatus using same
KR102057379B1 (en) 2015-02-05 2019-12-18 로무 가부시키가이샤 Linear power supplies and electronic devices using them

Similar Documents

Publication Publication Date Title
CN107305400B (en) Reference voltage generating circuit and DCDC converter having the same
KR102470562B1 (en) Regulator with enhanced slew rate
JP3710469B1 (en) Power supply device and portable device
JP2010079873A (en) Constant-voltage circuit device
US9651958B2 (en) Circuit for regulating startup and operation voltage of an electronic device
JP6660238B2 (en) Bandgap reference circuit and DCDC converter having the same
US20180188753A1 (en) Reduction of output undershoot in low-current voltage regulators
JP5867012B2 (en) Constant voltage circuit
JP2008276566A (en) Constant voltage power supply circuit
JP2011039887A (en) Band gap reference circuit
WO2016059954A1 (en) Light-emitting element driving device, light-emitting device, and vehicle
CN117155123B (en) Transient jump overshoot suppression circuit suitable for LDO and control method thereof
JP4855197B2 (en) Series regulator circuit
JP4592408B2 (en) Power circuit
JP6721231B2 (en) Power supply circuit
CN110134171B (en) Negative voltage follower circuit
KR102444199B1 (en) Voltage compensation circuit including low dropout regulators and operation method therof
JP2007011947A (en) Power source regulator circuit
JP2008099481A (en) Charge pump circuit
JP4077429B2 (en) Booster circuit
TW201338411A (en) Initial voltage generation circuit and method of generating an initial voltage
JP2007140755A (en) Voltage regulator
JP2013232760A (en) Output driver circuit
CN115268554A (en) Low dropout regulator
JP2013130937A (en) Constant voltage circuit and electronic equipment

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20081007