JP2006310894A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2006310894A
JP2006310894A JP2006224406A JP2006224406A JP2006310894A JP 2006310894 A JP2006310894 A JP 2006310894A JP 2006224406 A JP2006224406 A JP 2006224406A JP 2006224406 A JP2006224406 A JP 2006224406A JP 2006310894 A JP2006310894 A JP 2006310894A
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film
wiring
insulating film
interlayer insulating
lower electrode
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Akihiro Kajita
明広 梶田
Masaki Yamada
雅基 山田
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Toshiba Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a MIM-type capacitor with satisfactory properties is formed on a semiconductor substrate, and which is manufactured, without having to add special manufacturing processes, and to provide its manufacturing method. <P>SOLUTION: A MIM capacitor 11 (constituted of a lower electrode film 8a, a capacitor insulating film 9a, and an upper electrode film 10a) formed on a lower interlayer insulating film 3, can dispense with connection holes for the upper electrode, by being formed with a height same as that of a plug 14a connecting between a lower layer wiring 6 and an upper wiring 14c. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、キャパシタを搭載した半導体装置であって、特にアナログ/デジタル混載型半導体装置及びその製造方法に関するものである。 The present invention relates to a semiconductor device mounted with a capacitor, and more particularly to an analog / digital mixed semiconductor device and a method for manufacturing the same.

近年、製品のコンパクト化、高速化に伴い、いくつかのＬＳＩ（Ｌａｒｇｅ Ｓｃａｌｅ Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔ）を一纏めにしたシステムＬＳＩが用いられ、さらに、通信技術の発達が目覚しい現在、特にアナログとデジタルが混載されたアナログ/デジタル混載型ＬＳＩの開発が盛んに行われている。 In recent years, system LSIs that combine several LSIs (Large Scale Integrated Circuits) have been used as products have become more compact and faster, and in addition, the development of communication technology has been remarkable, especially analog and digital have been mixed. Analog / digital mixed LSIs are actively developed.

アナログ回路構成のためには高精度で電圧依存性のない安定した特性を有するキャパシタが求められている。   For an analog circuit configuration, a capacitor having a stable characteristic with high accuracy and no voltage dependency is required.

従来から、キャパシタは不純物がドーピングされたｐｏｌｙ−Ｓｉとｐｏｌｙ−Ｓｉの電極間にＯＮＯ膜が挟まれたようなＰＩＰ（Ｐｏｌｙｓｉｌｉｃｏｎ Ｉｎｓｕｌａｔｏｒ Ｐｏｌｙｓｉｌｉｃｏｎ）型キャパシタが用いられている。   Conventionally, a PIP (Polysilicon Insulator Polysilicon) type capacitor in which an ONO film is sandwiched between poly-Si and poly-Si electrodes doped with impurities has been used.

しかし、ＰＩＰ型キャパシタは電圧係数及び温度係数が高いため電圧及び温度の依存性があり、また、Ｐｏｌｙ−Ｓｉの抵抗が大きいためＬＳＩが安定した動作を行うことができないという問題が発生していた。   However, the PIP capacitor has a voltage and temperature dependency due to its high voltage coefficient and temperature coefficient, and there is a problem that the LSI cannot operate stably due to the large resistance of Poly-Si. .

そこで、このような問題を改善するために、電圧係数及び電気抵抗がＰｏｌｙ−Ｓｉより低い金属を電極に用い、多層配線層内に形成できることで寄生容量も抑えられるような電極構造としてＭＩＭ（Ｍｅｔａｌ Ｉｎｓｕｌａｔｏｒ Ｍｅｔａｌ）型キャパシタが注目されている（例えば、特許文献１参照）。   Therefore, in order to improve such a problem, a metal structure having a voltage coefficient and electrical resistance lower than that of Poly-Si is used as an electrode and can be formed in a multilayer wiring layer, so that an electrode structure that can suppress parasitic capacitance is MIM (Metal Insulator Metal) type capacitors are attracting attention (see, for example, Patent Document 1).

ＭＩＭ型キャパシタの構造を図１２〜図１４に示す製造工程を参照しながら説明する。 図１２（ａ）に示すように、第1の層間絶縁膜１０３には第1の配線層１０６（配線１０５とバリアメタル膜１０４からなる。）が形成されている。さらに、前記第１の層間絶縁膜１０３上には配線層に用いられている金属（例えばＣｕ）の拡散及び酸化防止のためバリア膜１０７が形成されている。   The structure of the MIM type capacitor will be described with reference to the manufacturing steps shown in FIGS. As shown in FIG. 12A, a first wiring layer 106 (consisting of a wiring 105 and a barrier metal film 104) is formed in the first interlayer insulating film 103. Further, a barrier film 107 is formed on the first interlayer insulating film 103 to prevent diffusion of metal (for example, Cu) used for the wiring layer and oxidation.

次に、図１２（ｂ）に示すように、前記バリア膜１０７上に下部電極金属１０８、誘電体膜１０９、上部電極金属１１０を順次堆積する。   Next, as shown in FIG. 12B, a lower electrode metal 108, a dielectric film 109 and an upper electrode metal 110 are sequentially deposited on the barrier film 107.

次に図１２（ｃ）に示すように、前記上部電極金属１１０上にレジストパターンを形成し（図示せず）、前記レジストパターンをマスクとして前記上部電極金属１１０及び誘電体膜１０９をエッチング後、前記レジストパターンをアッシングにより除去する。その結果、上部電極膜１１０ａ及びキャパシタ絶縁膜１０９ａが形成される。   Next, as shown in FIG. 12C, a resist pattern is formed on the upper electrode metal 110 (not shown), and the upper electrode metal 110 and the dielectric film 109 are etched using the resist pattern as a mask. The resist pattern is removed by ashing. As a result, the upper electrode film 110a and the capacitor insulating film 109a are formed.

次に図１３（ｄ）に示すように、前記上部電極膜１１０ａ及び前記下部電極金属１０８上にレジストパターンを形成し（図示せず）、前記レジストパターンをマスクとして前記下部電極金属１０８をエッチング後、前記レジストパターンをアッシングにより除去する。これにより、下部電極膜１０８ａ、キャパシタ絶縁膜１０９ａ、上部電極膜１１０ａからなるＭＩＭ型キャパシタ１１１が形成される。   Next, as shown in FIG. 13D, a resist pattern is formed on the upper electrode film 110a and the lower electrode metal 108 (not shown), and the lower electrode metal 108 is etched using the resist pattern as a mask. The resist pattern is removed by ashing. Thereby, the MIM type capacitor 111 including the lower electrode film 108a, the capacitor insulating film 109a, and the upper electrode film 110a is formed.

次に図１３（ｅ）に示すように、前記第１の層間絶縁膜１０３上に第2の層間絶縁膜１１２を堆積する。   Next, as shown in FIG. 13E, a second interlayer insulating film 112 is deposited on the first interlayer insulating film 103.

次に図１３（ｆ）に示すように、前記第２の層間絶縁膜１１２をＣＭＰ（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｌｉｓｈ）法によって平坦化する。   Next, as shown in FIG. 13F, the second interlayer insulating film 112 is planarized by a CMP (Chemical Mechanical Polish) method.

次に図１４（ｇ）に示すように、前記第２の層間絶縁膜１１２上にレジストパターンを形成し（図示せず）、前記レジストパターンをマスクとして、前記第２の層間絶縁膜１１２をエッチング後、前記レジストパターンをアッシングにより除去する。前記第２の層間絶縁膜１１２に形成された接続孔は、配線用接続孔１１２ａ、下部電極用接続孔１１２ｂ及び上部電極用接続孔１１２ｃを形成している。   Next, as shown in FIG. 14G, a resist pattern is formed on the second interlayer insulating film 112 (not shown), and the second interlayer insulating film 112 is etched using the resist pattern as a mask. Thereafter, the resist pattern is removed by ashing. The connection holes formed in the second interlayer insulating film 112 form wiring connection holes 112a, lower electrode connection holes 112b, and upper electrode connection holes 112c.

次に図１４（ｈ）に示すように、前記第２の層間絶縁膜１１２上にレジストパターンを形成し（図示せず）、前記レジストパターンをマスクとして、前記第２の層間絶縁膜１１２をエッチング後、前記レジストパターンをアッシングにより除去する。これによって、前記第２の層間絶縁膜に第２の配線溝１１２ｄ、下部電極用配線溝１１２ｅ、上部電極用配線溝１１２ｆが形成される。   Next, as shown in FIG. 14H, a resist pattern is formed on the second interlayer insulating film 112 (not shown), and the second interlayer insulating film 112 is etched using the resist pattern as a mask. Thereafter, the resist pattern is removed by ashing. As a result, a second wiring groove 112d, a lower electrode wiring groove 112e, and an upper electrode wiring groove 112f are formed in the second interlayer insulating film.

次に図１４（ｉ）に示すように、全ての前記接続孔及び配線溝の表面部分にバリアメタル膜１１３を形成、続けてＣｕ層１１４を堆積し、前記Ｃｕ層１１４をＣＭＰ法により平坦化する。以上により、第２の配線層（第２の配線１１４ｄと配線用プラグ１１４ａからなる。）と、下部電極配線層（下部電極用配線１１４ｅと下部電極用プラグ１１４ｂとからなる。）と、上部電極配線層（上部電極用配線１１４ｆと上部電極用プラグ１１４ｃとからなる。）が形成される。
特開平１０−１２８１９（図１） Next, as shown in FIG. 14 (i), a barrier metal film 113 is formed on the surface portions of all the connection holes and wiring grooves, a Cu layer 114 is subsequently deposited, and the Cu layer 114 is planarized by CMP. To do. As described above, the second wiring layer (consisting of the second wiring 114d and the wiring plug 114a), the lower electrode wiring layer (consisting of the lower electrode wiring 114e and the lower electrode plug 114b), and the upper electrode. A wiring layer (consisting of upper electrode wiring 114f and upper electrode plug 114c) is formed.
JP-A-10-12819 (FIG. 1)

しかし従来の製造工程においては、図１４（ｇ）に示すように、配線用接続孔１１２ａ、ＭＩＭ型キャパシタ１１１の下部電極用接続孔１１２ｂ、上部電極用接続孔１１２ｃはそれぞれ異なる深さの接続孔を形成しなければならない。 However, in the conventional manufacturing process, as shown in FIG. 14G, the wiring connection hole 112a, the lower electrode connection hole 112b of the MIM capacitor 111, and the upper electrode connection hole 112c have different depths. Must be formed.

これらの接続孔を同時に形成すると、最も深い配線用接続孔１１２ａの形成が完了するまでの間に、ＭＩＭ型キャパシタ１１１の下部電極膜１０８ａ及び上部電極膜１１０ａのオーバーエッチングがおこり、キャパシタのリーク特性が悪化する問題が発生する。   When these connection holes are formed simultaneously, over-etching of the lower electrode film 108a and the upper electrode film 110a of the MIM capacitor 111 occurs until the formation of the deepest wiring connection hole 112a is completed, and the leakage characteristics of the capacitor The problem of worsening occurs.

また、上記問題を回避するために、前記３種類の接続孔を同時ではなく、別々に形成することで解決はされるが、製造工程数が大幅に増大する。   Further, in order to avoid the above problem, the three types of connection holes can be solved separately rather than simultaneously, but the number of manufacturing steps is greatly increased.

そこで、本発明はＭＩＭ型キャパシタの電極膜の毀損を防ぎつつ、複数の接続孔を同時に形成することができ、延いては製造工程数の増大を抑えることが可能な半導体装置及びその製造方法について提案する。   Therefore, the present invention relates to a semiconductor device capable of simultaneously forming a plurality of connection holes while preventing damage to the electrode film of the MIM capacitor, and thus a method of manufacturing the semiconductor device capable of suppressing an increase in the number of manufacturing steps. suggest.

上記目的を達成するために、本発明の一態様の半導体装置は、半導体基板上に形成されたＭＩＭ型キャパシタを具備する半導体装置において、半導体基板と、 前記半導体基板上に形成された第１の層間絶縁膜と、前記第１の層間絶縁膜中に形成された溝に金属膜が埋め込まれ、線間に前記第１の層間絶縁膜が表出するように形成された第１の配線層と、前記第１の配線層の一部の上面に形成された誘電体膜と、前記誘電体膜上に形成された導電膜からなる上部電極膜と、前記上部電極膜の側面と接触するように前記第１の層間絶縁膜上に形成された第２の層間絶縁膜と、線間に前記第２の層間絶縁膜が表出するように形成された第２の配線、下部電極用配線及び上部電極用配線と、前記誘電体膜が上面に形成されていない第１の配線層と前記第２の配線とを接続させる配線用プラグと、前記誘電体膜が上面に形成された第１の配線層と前記下部電極用配線とを接続させる下部電極用プラグとを具備し、前記誘電体膜が上面に形成された第１の配線層の一部領域を下部電極膜とし、かつ、前記誘電体膜をキャパシタ絶縁膜とするＭＩＭ型キャパシタを有することを特徴とする。 In order to achieve the above object, a semiconductor device of one embodiment of the present invention includes a semiconductor substrate including an MIM capacitor formed over a semiconductor substrate, and a first substrate formed over the semiconductor substrate. An interlayer insulating film, and a first wiring layer formed so that a metal film is embedded in a groove formed in the first interlayer insulating film, and the first interlayer insulating film is exposed between lines A dielectric film formed on a part of the upper surface of the first wiring layer, an upper electrode film made of a conductive film formed on the dielectric film, and a side surface of the upper electrode film A second interlayer insulating film formed on the first interlayer insulating film; a second wiring formed such that the second interlayer insulating film is exposed between lines; a lower electrode wiring; and an upper portion An electrode wiring, a first wiring layer on which the dielectric film is not formed, and a front wiring layer; A wiring plug for connecting the second wiring; and a lower electrode plug for connecting the first wiring layer having the dielectric film formed on the upper surface and the lower electrode wiring; A MIM type capacitor having a partial region of the first wiring layer with the film formed on the upper surface as a lower electrode film and the dielectric film as a capacitor insulating film is provided.

上記目的を達成するために、本発明の別の態様の半導体装置の製造方法は、半導体基板上に第１の層間絶縁膜を形成し、前記第１の層間絶縁膜に第１の配線溝を形成し、前記第１の配線溝に金属膜及び前記金属膜上面にバリアメタル膜を埋め込み、前記金属膜と前記バリアメタル膜とからなる第１の配線層を形成する第１の配線層構造の製造工程と、前記第１の配線層の一部の上面に誘電体膜を形成し、前記誘電体膜上に導電膜を形成し、前記第１の配線層の一部を下部電極膜、前記誘電体膜をキャパシタ絶縁膜、前記導電膜を上部電極膜とするＭＩＭ型キャパシタを形成するＭＩＭ型キャパシタの製造工程と、前記第１の層間絶縁膜上に第２の層間絶縁膜を形成し、前記第２の層間絶縁膜に配線用接続孔及び下部電極用接続孔を同時に形成し、第２の配線溝、下部電極用配線溝及び上部電極用配線溝を同時に形成し、前記配線用接続孔及び下部電極用接続孔並びに第２の配線溝、下部電極用配線溝及び上部電極用配線溝に金属膜を埋め込み、第２の配線層、下部電極用配線層及び上部電極用配線層を形成する第２の配線層構造の製造工程とを有することを特徴とする。 In order to achieve the above object, a method of manufacturing a semiconductor device according to another aspect of the present invention includes forming a first interlayer insulating film on a semiconductor substrate, and forming a first wiring groove in the first interlayer insulating film. And forming a first wiring layer comprising the metal film and the barrier metal film by embedding a metal film in the first wiring groove and a barrier metal film on the upper surface of the metal film. A dielectric film is formed on a top surface of a part of the first wiring layer, a conductive film is formed on the dielectric film, a lower electrode film is formed on a part of the first wiring layer, A MIM capacitor manufacturing process for forming an MIM capacitor having a dielectric film as a capacitor insulating film and the conductive film as an upper electrode film; and forming a second interlayer insulating film on the first interlayer insulating film; Simultaneously forming wiring connection holes and lower electrode connection holes in the second interlayer insulating film The second wiring groove, the lower electrode wiring groove, and the upper electrode wiring groove are simultaneously formed, and the wiring connection hole, the lower electrode connection hole, the second wiring groove, the lower electrode wiring groove, and the upper electrode are formed. And a manufacturing process of a second wiring layer structure in which a metal film is embedded in the wiring groove to form a second wiring layer, a lower electrode wiring layer, and an upper electrode wiring layer.

本発明によれば、ＭＩＭ型キャパシタの形成に際し、製造工程数の増大を抑えながら、キャパシタの電極膜の毀損も防ぎデバイス特性を良好に保たせることができる。 According to the present invention, when forming an MIM type capacitor, it is possible to prevent damage to the electrode film of the capacitor and maintain good device characteristics while suppressing an increase in the number of manufacturing steps.

以下、本発明の実施形態に係る半導体装置およびその製造方法について説明する。 Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described.

本発明の第１の実施例による半導体装置の製造工程について図１〜図２を参照しながら説明する。 A manufacturing process of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.

図１（ａ）に示すように、半導体基板１上に絶縁分離層となる絶縁膜２、さらに、前記絶縁膜２上に第１の層間絶縁膜３を形成する。ここで、前記第１の層間絶縁膜３は、デバイスの高速化を図る目的で配線間容量を低減させるため、比誘電率の低いメチルポリシロキサンを用いる。続いて、第１の配線層６（第１のＣｕ配線５とバリアメタル膜４とからなる。）を形成するために、前記第１の層間絶縁膜３に配線溝を形成し、その後、Ｃｕの拡散及び酸化防止のために前記配線溝の表面にＴａＮ膜をスパッタ法にて約２０ｎｍ堆積し、バリアメタル膜４を形成する。さらに、前記バリアメタル膜４上に約１００ｎｍのＣｕ膜をスパッタ法にて堆積後、電解メッキ法によって前記配線溝内を含む第１の層間絶縁膜３上全面に約８００ｎｍのＣｕを堆積させる。さらに、ＣＭＰ法によって不要なＣｕ及びＴａＮを研磨・除去し、Ｃｕ層５が平坦化して、第１の層間絶縁膜３を露出させる。   As shown in FIG. 1A, an insulating film 2 serving as an insulating separation layer is formed on a semiconductor substrate 1, and a first interlayer insulating film 3 is formed on the insulating film 2. Here, the first interlayer insulating film 3 uses methylpolysiloxane having a low relative dielectric constant in order to reduce inter-wiring capacitance for the purpose of speeding up the device. Subsequently, in order to form the first wiring layer 6 (consisting of the first Cu wiring 5 and the barrier metal film 4), a wiring groove is formed in the first interlayer insulating film 3, and then Cu In order to prevent diffusion and oxidation, a TaN film is deposited on the surface of the wiring trench by a sputtering method to a thickness of about 20 nm to form a barrier metal film 4. Further, after depositing a Cu film of about 100 nm on the barrier metal film 4 by sputtering, Cu of about 800 nm is deposited on the entire surface of the first interlayer insulating film 3 including the inside of the wiring trench by electrolytic plating. Further, unnecessary Cu and TaN are polished and removed by the CMP method, the Cu layer 5 is planarized, and the first interlayer insulating film 3 is exposed.

次に図１（ｂ）に示すように、前記第１の層間絶縁膜３上にＣｕの拡散及び酸化防止のためのバリア膜としてＳｉＮ膜７をＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法を用いて堆積後する。続けて、前記バリア膜７上にスパッタ法にて第１のＴｉＮ膜８を約４０ｎｍ、さらに前記第１のＴｉＮ膜８上にＳｉＮ膜９をＣＶＤ法によって約５０ｎｍ、前記ＳｉＮ膜９上に第２のＴｉＮ膜１０をスパッタ法によって約３００ｎｍを順次堆積する。   Next, as shown in FIG. 1B, a SiN film 7 is deposited on the first interlayer insulating film 3 as a barrier film for preventing Cu diffusion and oxidation using a CVD (Chemical Vapor Deposition) method. To do. Subsequently, the first TiN film 8 is formed on the barrier film 7 by a sputtering method to about 40 nm, the SiN film 9 is formed on the first TiN film 8 by a CVD method to about 50 nm, and the first TiN film 8 is formed on the SiN film 9. Two TiN films 10 are sequentially deposited to a thickness of about 300 nm by sputtering.

次に図１（ｃ）に示すように、前記第１のＴｉＮ膜８、前記ＳｉＮ膜９及び前記第２のＴｉＮ膜１０をリソグラフィー及びＲＩＥ技術を用いて加工し、ＭＩＭ型キャパシタの下部電極膜８ａ、キャパシタ絶縁膜９ａ及び上部電極膜１０ａを形成する。以上の製造工程によって、ＭＩＭ型キャパシタ１１が形成される。   Next, as shown in FIG. 1C, the first TiN film 8, the SiN film 9, and the second TiN film 10 are processed using lithography and RIE techniques to form a lower electrode film of the MIM capacitor. 8a, capacitor insulating film 9a and upper electrode film 10a are formed. Through the above manufacturing process, the MIM type capacitor 11 is formed.

次に図２（ｄ）に示すように、前記第１の層間絶縁膜３上に第２の層間絶縁膜１２を約７００ｎｍ堆積し、ＣＭＰ法によって前記第２の層間絶縁膜１２を平坦化する。さらに、リソグラフィー及びＲＩＥ技術を用いて加工し、前記第２の層間絶縁膜１２に第１の配線層６に達する配線用接続孔１２ａと、前記下部電極膜８ａに達する下部電極用接続孔１２ｂを同時に形成する。前記第２の層間絶縁膜１２の絶縁材料は、前記第１の層間絶縁膜と同様にメチルポリシロキサンを用いている。前記下部電極膜８ａと前記第２の層間絶縁膜１２に用いている材料はそれぞれＴｉＮとメチルポリシロキサンなので両者はエッチングレートが異なっている。さらに、前記第１の配線用接続孔１２ａと前記下部電極用接続孔１２ｂの深さの差は前記下部電極膜８ａの厚さすなわち約４０ｎｍと薄いので、２つの接続孔を同時に形成しても前記下部電極膜８ａが大きくオーバーエッチングされることがない。   Next, as shown in FIG. 2D, a second interlayer insulating film 12 is deposited on the first interlayer insulating film 3 by about 700 nm, and the second interlayer insulating film 12 is planarized by CMP. . Further, a wiring connection hole 12a reaching the first wiring layer 6 and a lower electrode connection hole 12b reaching the lower electrode film 8a are formed in the second interlayer insulating film 12 by processing using lithography and RIE technology. Form at the same time. As the insulating material of the second interlayer insulating film 12, methylpolysiloxane is used similarly to the first interlayer insulating film. Since the materials used for the lower electrode film 8a and the second interlayer insulating film 12 are TiN and methylpolysiloxane, respectively, their etching rates are different. Further, since the difference in depth between the first wiring connection hole 12a and the lower electrode connection hole 12b is as thin as the lower electrode film 8a, ie, about 40 nm, two connection holes can be formed simultaneously. The lower electrode film 8a is not greatly over-etched.

次に図２（ｅ）に示すように、前記第２の層間絶縁膜１２に第２の配線溝１２ｃと、下部電極用配線溝１２ｄと、上部電極用配線溝１２ｅとをそれぞれ約３００ｎｍの深さにリソグラフィー及びＲＩＥ技術によって同時に形成する。前記上部電極膜１０ａは前記第２の層間絶縁膜１２上面から約３００ｎｍの深さにあるので、前記上部電極用配線溝１２ｅは前記上部電極１０ａに達する。   Next, as shown in FIG. 2E, the second interlayer insulating film 12 is provided with a second wiring groove 12c, a lower electrode wiring groove 12d, and an upper electrode wiring groove 12e at a depth of about 300 nm. Further, it is simultaneously formed by lithography and RIE technology. Since the upper electrode film 10a is at a depth of about 300 nm from the upper surface of the second interlayer insulating film 12, the upper electrode wiring groove 12e reaches the upper electrode 10a.

次に図２（ｆ）に示すように、全ての前記接続孔及び配線溝を含む第２の層間絶縁膜の表面部分にＴａＮ膜をスパッタ法にて約２０ｎｍ堆積し、バリアメタル膜１３を形成する。さらに、前記バリアメタル膜１３上に約１００ｎｍのＣｕ膜をスパッタ法にて堆積後、電解メッキ法によって全ての前記接続孔及び配線溝内を含む第２の層間絶縁膜１２上全面に約８００ｎｍのＣｕ層を堆積させる。さらに、ＣＭＰ法により第２の層間絶縁膜１２が露出するまで不要なＣｕ層及びＴａＮを研磨・除去することによって、Ｃｕ層１４が平坦化され、第２の配線層（第２の配線１４ｃと配線用プラグ１４ａからなる。）及び下部電極用配線層（下部電極用配線１４ｄと下部電極用プラグ１４ｂからなる。）並びに上部電極用配線層１４ｃ（上部電極用配線１４ｅのみからなる。）が形成される。   Next, as shown in FIG. 2F, a barrier metal film 13 is formed by depositing a TaN film with a thickness of about 20 nm on the surface of the second interlayer insulating film including all the connection holes and wiring trenches by sputtering. To do. Further, a Cu film having a thickness of about 100 nm is deposited on the barrier metal film 13 by a sputtering method, and then an entire thickness of about 800 nm is formed on the second interlayer insulating film 12 including all the connection holes and wiring trenches by an electrolytic plating method. A Cu layer is deposited. Further, the unnecessary Cu layer and TaN are polished and removed by CMP until the second interlayer insulating film 12 is exposed, whereby the Cu layer 14 is planarized and the second wiring layer (second wiring 14c and And a lower electrode wiring layer (consisting of a lower electrode wiring 14d and a lower electrode plug 14b) and an upper electrode wiring layer 14c (comprising only the upper electrode wiring 14e). Is done.

以上のように、前記上部電極膜１０ａの膜厚を調整し、前記上部電極用配線溝１２ｅの深さに合せ込むことによって、上部電極用接続孔の形成が不要となり、上部電極膜１０ａのオーバーエッチングは回避される。したがって、良好なＭＩＭ型キャパシタの特性を保つことができる。また、複数の接続孔及び配線溝の同時形成が可能なので、特別な製造工程を必要としない。   As described above, by adjusting the film thickness of the upper electrode film 10a and adjusting it to the depth of the upper electrode wiring groove 12e, it is not necessary to form an upper electrode connection hole, and the upper electrode film 10a is not overcoated. Etching is avoided. Therefore, good characteristics of the MIM type capacitor can be maintained. In addition, since a plurality of connection holes and wiring grooves can be formed simultaneously, no special manufacturing process is required.

次に本発明の第２の実施例による半導体装置の製造工程について図３〜図４を参照しながら説明する。 Next, a manufacturing process of the semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS.

図３（ａ）に示すように、第１の実施例と同様に半導体基板１上に絶縁分離層となる絶縁膜２、さらに、前記絶縁膜２上に第１の層間絶縁膜３を形成する。続いて、前記第１の層間絶縁膜３に配線溝を形成し、その後、前記配線溝の表面にバリアメタル膜としてＴａＮ膜４を堆積し、さらにＣｕ層５を堆積して前記配線溝を埋め込む。次に不要な前記Ｃｕ層５及びＴａＮ膜４をＣＭＰ法により研磨・除去し平坦化した後に、前記Ｃｕ層５部分のみを約５０ｎｍ程度一旦リセスし、前記リセス部にＴａＮ膜１５をスパッタ法にて堆積する。さらに前記Ｃｕ層５上面のみに前記ＴａＮ膜１５を形成するため、前記第１の層間絶縁膜３上に堆積された余分なＴａＮ膜を再度ＣＭＰ法によって研磨・除去する。したがって、前記ＴａＮ膜１５は、以降の製造工程において、キャパシタ絶縁膜が上面に形成される第１のＣｕ配線層６上面に堆積されたバリアメタル膜１５ｂと、キャパシタ絶縁膜が形成されない第１のＣｕ配線層６上面に堆積されたバリアメタル膜１５ａとに分離される。   As shown in FIG. 3A, as in the first embodiment, an insulating film 2 serving as an insulating separation layer is formed on the semiconductor substrate 1, and a first interlayer insulating film 3 is formed on the insulating film 2. . Subsequently, a wiring groove is formed in the first interlayer insulating film 3, and then a TaN film 4 is deposited as a barrier metal film on the surface of the wiring groove, and a Cu layer 5 is further deposited to embed the wiring groove. . Next, the unnecessary Cu layer 5 and TaN film 4 are polished and removed by CMP and planarized, and then only the Cu layer 5 portion is temporarily recessed by about 50 nm, and the TaN film 15 is sputtered on the recess. And accumulate. Further, in order to form the TaN film 15 only on the upper surface of the Cu layer 5, the excess TaN film deposited on the first interlayer insulating film 3 is again polished and removed by CMP. Therefore, the TaN film 15 includes a barrier metal film 15b deposited on the upper surface of the first Cu wiring layer 6 on which the capacitor insulating film is formed and a first capacitor insulating film on which the capacitor insulating film is not formed. Separated from the barrier metal film 15 a deposited on the upper surface of the Cu wiring layer 6.

次に図３（ｂ）に示すように、前記第１の層間絶縁膜３上にＳｉＮ膜９を約５０ｎｍ、続けて前記ＳｉＮ膜９上にＴａＮ膜１０を約３００ｎｍ堆積する。さらに、前記ＳｉＮ膜９及び前記ＴａＮ膜１０をリソグラフィー及びＲＩＥ技術を用いて加工し、ＭＩＭ型キャパシタのキャパシタ絶縁膜９ａ及び上部電極膜１０ａを形成する。   Next, as shown in FIG. 3B, a SiN film 9 is deposited on the first interlayer insulating film 3 by about 50 nm, and then a TaN film 10 is deposited on the SiN film 9 by about 300 nm. Further, the SiN film 9 and the TaN film 10 are processed using lithography and RIE techniques to form a capacitor insulating film 9a and an upper electrode film 10a of the MIM type capacitor.

以上の製造工程によって、前記バリアメタル膜１５ｂを下部電極膜とするＭＩＭ型キャパシタ１６が形成される。したがって、第１のＣｕ配線５の拡散及び酸化を防止するバリアメタル膜１５ｂは、同時にＭＩＭ型キャパシタの下部電極膜としての役割も果たすことになる。   Through the above manufacturing process, the MIM type capacitor 16 having the barrier metal film 15b as the lower electrode film is formed. Therefore, the barrier metal film 15b for preventing the diffusion and oxidation of the first Cu wiring 5 also serves as a lower electrode film of the MIM type capacitor.

次に図３（ｃ）に示すように、前記第１の層間絶縁膜３上に第２の層間絶縁膜１２を約７００ｎｍ堆積し、ＣＭＰ法によって前記第２の層間絶縁膜１２を平坦化する。さらに、リソグラフィー及びＲＩＥ技術を用いて加工し、前記第２の層間絶縁膜１２に第１の配線層６に達する第１の配線用接続孔１２ａと、前記下部電極膜１５ｂに達する下部電極用接続孔１２ｂとを同時に形成する。前記第１の配線用接続孔１２ａと前記下部電極用接続孔１２ｂの深さは等しいので、下部電極膜１５ｂはオーバーエッチングされることはない。   Next, as shown in FIG. 3C, a second interlayer insulating film 12 is deposited on the first interlayer insulating film 3 by about 700 nm, and the second interlayer insulating film 12 is planarized by CMP. . Further, the first wiring connection hole 12a reaching the first wiring layer 6 and the lower electrode connection reaching the lower electrode film 15b are processed in the second interlayer insulating film 12 by using lithography and RIE technology. The holes 12b are formed at the same time. Since the first wiring connection hole 12a and the lower electrode connection hole 12b have the same depth, the lower electrode film 15b is not over-etched.

次に図４（ｄ）に示すように、前記第２の層間絶縁膜１２に第２の配線溝１２ｃと、下部電極用配線溝１２ｄと、上部電極用配線溝１２ｅとをそれぞれ約３００ｎｍの深さにリソグラフィー及びＲＩＥ技術によって同時に形成する。前記上部電極膜１０ａは前記第２の層間絶縁膜１２上面から約３００ｎｍの深さにあるので、前記上部電極用配線溝１２ｅは前記上部電極膜１０ａに達する。   Next, as shown in FIG. 4D, a second wiring groove 12c, a lower electrode wiring groove 12d, and an upper electrode wiring groove 12e are formed in the second interlayer insulating film 12 at a depth of about 300 nm. Further, it is simultaneously formed by lithography and RIE technology. Since the upper electrode film 10a is at a depth of about 300 nm from the upper surface of the second interlayer insulating film 12, the upper electrode wiring groove 12e reaches the upper electrode film 10a.

次に図４（ｅ）に示すように、全ての前記接続孔及び配線溝の表面にバリアメタル膜１３を堆積し、さらにＣｕ層１４を埋め込み、第１の実施例と同様の第２の配線層（第２の配線１４ｃと配線用プラグ１４ａからなる。）と下部電極用配線層（下部電極用配線１４ｄと下部電極用プラグ１４ｂとからなる。）並びに上部電極用配線層（上部電極用配線１４ｅのみからなる。）が形成される。   Next, as shown in FIG. 4 (e), a barrier metal film 13 is deposited on the surfaces of all the connection holes and wiring grooves, and a Cu layer 14 is further embedded, so that a second wiring similar to the first embodiment is formed. A layer (consisting of a second wiring 14c and a wiring plug 14a), a lower electrode wiring layer (consisting of a lower electrode wiring 14d and a lower electrode plug 14b), and an upper electrode wiring layer (upper electrode wiring). 14e only).

以上のように、第１の実施例同様ＭＩＭ型キャパシタ１６の下部電極膜１５ｂ及び上部電極膜１０ａはオーバーエッチングを回避され、さらに、複数の接続孔及び配線溝の同時形成が可能なので、特別な製造工程を必要としない。   As described above, similar to the first embodiment, the lower electrode film 15b and the upper electrode film 10a of the MIM capacitor 16 are avoided from being over-etched, and a plurality of connection holes and wiring grooves can be formed simultaneously. No manufacturing process is required.

次に本発明の第３の実施例による半導体装置の製造工程について図５〜図６を参照しながら説明する。 Next, a semiconductor device manufacturing process according to the third embodiment of the present invention will be described with reference to FIGS.

本実施例は、第２の実施例の第１の配線層６を形成するまでの製造工程（図３（ａ））は同じなので説明を省略する。   In the present embodiment, the manufacturing process (FIG. 3A) until the formation of the first wiring layer 6 of the second embodiment is the same, and the description thereof is omitted.

次に図５（ａ）に示すように、前記第１の層間絶縁膜３上にＳｉＮ膜９を約５０ｎｍ、続けて前記ＳｉＮ膜９上にＴａＮ膜１７を約６０ｎｍ堆積する。さらに、前記ＳｉＮ膜９及び前記ＴａＮ膜１７をリソグラフィー及びＲＩＥ技術を用いて加工し、ＭＩＭ型キャパシタのキャパシタ絶縁膜９ａ及び上部電極膜１７ａを形成する。以上の製造工程によって、前記バリアメタル膜１５ｂを下部電極膜とするＭＩＭ型キャパシタ１８が形成される。 Next, as shown in FIG. 5A, a SiN film 9 is deposited on the first interlayer insulating film 3 by about 50 nm, and then a TaN film 17 is deposited on the SiN film 9 by about 60 nm. Further, the SiN film 9 and the TaN film 17 are processed using lithography and RIE technology to form a capacitor insulating film 9a and an upper electrode film 17a of the MIM type capacitor. Through the above manufacturing process, the MIM type capacitor 18 having the barrier metal film 15b as the lower electrode film is formed.

次に図５（ｂ）に示すように、前記第１の層間絶縁膜３上に第２の層間絶縁膜１２を約７００ｎｍ堆積し、ＣＭＰ法によって前記第２の層間絶縁膜１２を平坦化する。さらに、リソグラフィー及びＲＩＥ技術を用いて加工し、前記第２の層間絶縁膜１２に第１の配線層６に達する第１の配線用接続孔１２ａと、前記下部電極膜１５ｂに達する下部電極用接続孔１２ｂと、前記上部電極膜１７ａに達する上部電極用接続孔１２ｆを同時に形成する。前記上部電極用接続孔１２ｆは他の２つの接続孔の深さよりも浅いので、オーバーエッチングが懸念されるが、これら３つの接続孔の底に用いられている材料が全てＴａＮ膜と同じものでできている。したがって、第２の層間絶縁膜１２と上部電極膜１７ａはエッチングレートが異なるので、前記上部電極膜１７ａがエッチングストッパ膜的な役割を果たし、また、前記キャパシタ絶縁膜９ａと上部電極膜１７ａの厚みは薄いので、前記上部電極膜１７ａが大きくオーバーエッチングされることはない。   Next, as shown in FIG. 5B, a second interlayer insulating film 12 is deposited on the first interlayer insulating film 3 to a thickness of about 700 nm, and the second interlayer insulating film 12 is planarized by CMP. . Further, the first wiring connection hole 12a reaching the first wiring layer 6 and the lower electrode connection reaching the lower electrode film 15b are processed in the second interlayer insulating film 12 by using lithography and RIE technology. The hole 12b and the upper electrode connection hole 12f reaching the upper electrode film 17a are formed simultaneously. Since the upper electrode connection hole 12f is shallower than the other two connection holes, over-etching is a concern. However, the materials used for the bottom of these three connection holes are all the same as those of the TaN film. is made of. Therefore, since the second interlayer insulating film 12 and the upper electrode film 17a have different etching rates, the upper electrode film 17a serves as an etching stopper film, and the thickness of the capacitor insulating film 9a and the upper electrode film 17a. Therefore, the upper electrode film 17a is not greatly over-etched.

次に図６（ｃ）に示すように、前記第２の層間絶縁膜１２に第２の配線溝１２ｃと、下部電極用配線溝１２ｄと、上部電極用配線溝１２ｇとをそれぞれ約３００ｎｍの深さにリソグラフィー及びＲＩＥ技術を用いて同時に形成する。   Next, as shown in FIG. 6C, a second wiring groove 12c, a lower electrode wiring groove 12d, and an upper electrode wiring groove 12g are formed in the second interlayer insulating film 12 at a depth of about 300 nm. Further, it is formed simultaneously using lithography and RIE technology.

次に図６（ｄ）に示すように、全ての前記接続孔及び配線溝の表面にバリアメタル膜１３を堆積し、さらにＣｕ層１４を埋め込み、第１の実施例と同様の第２の配線層（第２の配線１４ａと配線用プラグ１４ｃとからなる。）及び下部電極用配線層（下部電極用配線１４ｄと下部電極用プラグ１４ｂとからなる。）並びに上部電極用配線層（上部電極用配線１４ｇと上部電極用プラグ１４ｆとからなる。）が形成される。   Next, as shown in FIG. 6 (d), a barrier metal film 13 is deposited on the surfaces of all the connection holes and wiring grooves, and a Cu layer 14 is further embedded to form the second wiring similar to the first embodiment. Layer (consisting of second wiring 14a and wiring plug 14c), lower electrode wiring layer (consisting of lower electrode wiring 14d and lower electrode plug 14b), and upper electrode wiring layer (for upper electrode) The wiring 14g and the upper electrode plug 14f are formed.

以上のように、前記第１の配線層６の上面のバリアメタル膜１５ａ、前記下部電極膜１５ｂ及び前記上部電極膜１７ａには同一材料、かつ、第２の層間絶縁膜１２とのエッチングレートの異なるものを使用し、また、形成されたＭＩＭ型キャパシタ１８が薄いので、前記上部電極膜１７ａの大幅なオーバーエッチングは回避される。また、複数の接続孔及び配線溝の同時形成が可能なので、特別な製造工程を必要としない。   As described above, the barrier metal film 15a, the lower electrode film 15b, and the upper electrode film 17a on the upper surface of the first wiring layer 6 are made of the same material and have an etching rate with the second interlayer insulating film 12. Since different ones are used and the formed MIM capacitor 18 is thin, significant over-etching of the upper electrode film 17a is avoided. In addition, since a plurality of connection holes and wiring grooves can be formed simultaneously, no special manufacturing process is required.

次に本発明の第４の実施例による半導体装置の製造工程について図７〜図８を参照しながら説明する。 Next, a semiconductor device manufacturing process according to the fourth embodiment of the present invention will be described with reference to FIGS.

図７（ａ）に示すように、半導体基板１上に絶縁分離層となる絶縁膜２、さらに、前記絶縁膜２上に第１の層間絶縁膜３を形成する。続いて、第１の配線層６（第１のＣｕ配線５とバリアメタル膜４とからなる。）を形成するために、前記第１の層間絶縁膜３に配線溝を形成し、その後、前記配線溝の表面にバリアメタル膜としてＴａＮ膜４を堆積し、さらにＣｕ層５を堆積して前記配線溝を埋め込む。次に不要な前記Ｃｕ層５及びＴａＮ膜４をＣＭＰ法により研磨・除去し平坦化した後に、前記第１の層間絶縁膜３上にＣｕの拡散及び酸化防止のバリア膜としてＳｉＮ膜７を堆積する。   As shown in FIG. 7A, an insulating film 2 serving as an insulating separation layer is formed on the semiconductor substrate 1, and a first interlayer insulating film 3 is formed on the insulating film 2. Subsequently, in order to form the first wiring layer 6 (consisting of the first Cu wiring 5 and the barrier metal film 4), a wiring groove is formed in the first interlayer insulating film 3, and thereafter A TaN film 4 is deposited as a barrier metal film on the surface of the wiring groove, and a Cu layer 5 is further deposited to fill the wiring groove. Next, the unnecessary Cu layer 5 and TaN film 4 are polished and removed by CMP and planarized, and then a SiN film 7 is deposited on the first interlayer insulating film 3 as a barrier film for diffusion and prevention of Cu. To do.

次に図７（ｂ）に示すように、前記第１の層間絶縁膜３上に第２の層間絶縁膜１２を約７００ｎｍ堆積する。さらにリソグラフィー及びＲＩＥ技術を用いて加工し、前記第２の層間絶縁膜１２に第１の配線層６に達する配線用接続孔１２ａ及び電極用接続孔１２ｈを形成する。続けて、第２の配線溝１２ｃ及び電極用配線溝１２ｉ形成のため、リソグラフィー及びＲＩＥ技術を用いて処理する。さらに、前記接続孔１２ａ及び１２ｈ底面の前記バリア膜７をＲＩＥにより除去し、溝７ａ、７ｂを形成する。次に、全ての前記配線溝及び接続孔の表面部分にＴａＮ膜１９を約４０ｎｍスパッタ法にて堆積する。   Next, as shown in FIG. 7B, a second interlayer insulating film 12 is deposited on the first interlayer insulating film 3 to a thickness of about 700 nm. Further, by using lithography and RIE technology, wiring connection holes 12 a and electrode connection holes 12 h reaching the first wiring layer 6 are formed in the second interlayer insulating film 12. Subsequently, in order to form the second wiring groove 12c and the electrode wiring groove 12i, processing is performed using lithography and RIE technology. Further, the barrier film 7 on the bottom surfaces of the connection holes 12a and 12h is removed by RIE to form grooves 7a and 7b. Next, a TaN film 19 is deposited on the surface portions of all the wiring grooves and connection holes by an approximately 40 nm sputtering method.

次に図７（ｃ）に示すように、前記ＴａＮ膜１９をリソグラフィー及びＲＩＥ技術を用いて加工し、ＴａＮ膜１９ａを形成する。このＴａＮ膜１９ａはＭＩＭ型キャパシタの下部電極膜となる。さらに、前記ＴａＮ膜１９ａ及び前記第２の層間絶縁膜１２の接続孔及び配線溝の表面にＳｉＮ膜２０をプラズマＣＶＤ法により約５０ｎｍ堆積する。   Next, as shown in FIG. 7C, the TaN film 19 is processed by lithography and RIE technology to form a TaN film 19a. This TaN film 19a becomes the lower electrode film of the MIM type capacitor. Further, a SiN film 20 is deposited by about 50 nm on the surface of the connection hole and the wiring groove of the TaN film 19a and the second interlayer insulating film 12 by plasma CVD.

次に図８（ｄ）に示すように、前記ＳｉＮ膜２０をリソグラフィー及びＲＩＥ技術を用いて加工し、ＳｉＮ膜２０ａを形成する。このＳｉＮ膜２０ａはＭＩＭ型キャパシタのキャパシタ絶縁膜となる。さらに、全ての前記接続孔及び配線溝を含む前記ＳｉＮ膜ａ及び前記第２の層間絶縁膜１２の表面にＴａＮ膜２１をスパッタ法を用いて堆積する。   Next, as shown in FIG. 8D, the SiN film 20 is processed by lithography and RIE technology to form a SiN film 20a. This SiN film 20a becomes a capacitor insulating film of an MIM type capacitor. Further, a TaN film 21 is deposited on the surfaces of the SiN film a and the second interlayer insulating film 12 including all the connection holes and wiring trenches by sputtering.

次に図８（ｅ）に示すように、前記ＴａＮ膜２１上に約１００ｎｍのＣｕ膜をスパッタ法にて堆積後、電解メッキ法によって前記配線溝内を含む第２の層間絶縁膜１２上全面に約８００ｎｍのＣｕ層２３を堆積させる。さらに、不要なＣｕ及びＴａＮをＣＭＰ法によって研磨・除去することによって、Ｃｕ層２３が平坦化され、第２の層間絶縁膜１２を露出させ、第２の配線層（第２の配線２３ｃと配線用プラグ２３ａとからなる。）と電極用配線層（電極用配線２３ｉと電極用プラグ２３ｈとからなる。）が形成される。その結果、前記ＴａＮ膜２１は、第１及び第２のＣｕ配線層の拡散及び酸化防止のためのバリアメタル膜２１ａと、電極用配線のバリアメタル膜及びＭＩＭ型キャパシタ２２の上部電極膜を構成する２１ｂを形成する。   Next, as shown in FIG. 8E, a Cu film having a thickness of about 100 nm is deposited on the TaN film 21 by a sputtering method, and then the entire surface of the second interlayer insulating film 12 including the inside of the wiring trench is formed by an electrolytic plating method. Then, a Cu layer 23 of about 800 nm is deposited. Further, unnecessary Cu and TaN are polished and removed by the CMP method, whereby the Cu layer 23 is planarized, the second interlayer insulating film 12 is exposed, and the second wiring layer (the second wiring 23c and the wiring is formed). And the electrode wiring layer (consisting of the electrode wiring 23i and the electrode plug 23h) are formed. As a result, the TaN film 21 constitutes a barrier metal film 21a for diffusion and oxidation prevention of the first and second Cu wiring layers, a barrier metal film for electrode wiring, and an upper electrode film of the MIM type capacitor 22. 21b is formed.

ここでは、下部電極用プラグ形成についての説明を省略しているが、配線用プラグ２３ａ及び電極用プラグ２３ｈと同時に形成することができる。すなわち、配線用接続孔１２ａ及び電極用接続孔１２ｈ形成時に、下部電極膜１９ａと接触している第１の配線層６に対して、下部電極接続孔を形成する。さらに、図８（ｅ）に示す製造工程時に、前記下部電極接続孔に対してバリアメタル膜となるＴａＮ膜２１及びＣｕ層２３を堆積し、ＣＭＰ法により研磨・除去して下部電極用プラグが形成される。なお、上部電極用プラグは前記電極用プラグ２３ｈ、上部電極用配線は前記電極用配線２３ｉが該当する。   Here, the description of the formation of the lower electrode plug is omitted, but it can be formed simultaneously with the wiring plug 23a and the electrode plug 23h. That is, when the wiring connection hole 12a and the electrode connection hole 12h are formed, the lower electrode connection hole is formed in the first wiring layer 6 in contact with the lower electrode film 19a. Further, during the manufacturing process shown in FIG. 8E, a TaN film 21 and a Cu layer 23, which serve as a barrier metal film, are deposited on the lower electrode connection hole, and are polished and removed by a CMP method to form a lower electrode plug. It is formed. The upper electrode plug corresponds to the electrode plug 23h, and the upper electrode wiring corresponds to the electrode wiring 23i.

本実施例では接続孔の深さは全て同じであるため、深さの違いによるオーバーエッチングはない。また、配線層のバリアメタル膜とＭＩＭ型キャパシタの上部電極膜を同時に作成可能な点で特別な製造工程を設ける必要がない。さらに、本発明で作成されたＭＩＭ型キャパシタ２２は立体的構造を構成しているため、平行平板によるキャパシタと比較して大容量のキャパシタを作成することが可能である。   In this embodiment, all the connection holes have the same depth, so there is no over-etching due to the difference in depth. Further, it is not necessary to provide a special manufacturing process in that the barrier metal film of the wiring layer and the upper electrode film of the MIM capacitor can be formed at the same time. Furthermore, since the MIM type capacitor 22 produced in the present invention has a three-dimensional structure, it is possible to produce a capacitor with a larger capacity than a capacitor using a parallel plate.

なお、ＭＩＭ型キャパシタの電極面積を大きくするためには電極用接続孔１２ｈの個数を多くすればよい。（本実施例では電極用接続孔は３個である。）また、前記電極用接続孔１２ｈの形状によってもＭＩＭ型キャパシタの電極面積を大きくすることができる。例えば、図９（ｂ）に示すように円筒状の電極用接続孔１２ｈを連続的に配置する形状が考えられる。図９（ｂ）は、図９（ａ）の面ＡＢにおける上面断面図を表している。ここで、図９（ａ）は第４の実施例における第２の層間絶縁膜１２に対し、デュアルダマシン法によって全ての配線溝及び接続孔を形成した後における半導体装置の側面断面図である。また、前記電極用接続孔１２ｈを図９（ｃ）に示すように水平断面が矩形の溝形状にすることによってもＭＩＭ型キャパシタの電極面積を大きくすることは可能である。図９（ｃ）も図９（ｂ）と同様に、本発明の第４の実施例における半導体装置の側面断面図である図９（ａ）の面ＡＢにおける上面断面図を表している。   In order to increase the electrode area of the MIM capacitor, the number of electrode connection holes 12h may be increased. (In the present embodiment, the number of electrode connection holes is three). Also, the electrode area of the MIM capacitor can be increased by the shape of the electrode connection hole 12h. For example, as shown in FIG. 9B, a shape in which cylindrical electrode connection holes 12h are continuously arranged is conceivable. FIG. 9B shows a top cross-sectional view along the plane AB in FIG. Here, FIG. 9A is a side sectional view of the semiconductor device after all wiring trenches and connection holes are formed by the dual damascene method in the second interlayer insulating film 12 in the fourth embodiment. It is also possible to increase the electrode area of the MIM capacitor by making the electrode connection hole 12h into a groove shape having a rectangular horizontal cross section as shown in FIG. 9C. FIG. 9C, like FIG. 9B, also shows a top cross-sectional view along the plane AB in FIG. 9A, which is a side cross-sectional view of the semiconductor device in the fourth embodiment of the present invention.

また、本実施例では、平坦なバリア膜７上に第２の層間絶縁膜１２を堆積するので、ＣＭＰ法によって第２の層間絶縁膜を研磨・除去する必要がない。ここで層間絶縁膜の材料として用いているメチルポリシロキサン等の低誘電率の絶縁材料はＣＭＰ法による研磨によって損傷を受けやすい性質を有している。したがって、層間絶縁膜を研磨する工程が不要になるので良好なデバイス特性を保つことができる。   Further, in this embodiment, since the second interlayer insulating film 12 is deposited on the flat barrier film 7, it is not necessary to polish and remove the second interlayer insulating film by the CMP method. Here, an insulating material having a low dielectric constant such as methylpolysiloxane used as a material for the interlayer insulating film has a property of being easily damaged by polishing by the CMP method. Accordingly, the step of polishing the interlayer insulating film is not necessary, and good device characteristics can be maintained.

次に本発明の第５の実施例による半導体装置の製造工程について図１０〜図１１を参照しながら説明する。 Next, a semiconductor device manufacturing process according to the fifth embodiment of the present invention will be described with reference to FIGS.

本実施例は、第４の実施例のバリア膜７を形成するまでの製造工程（図７（ａ））は同じなので説明を省略する。   In this embodiment, the manufacturing process (FIG. 7A) up to the formation of the barrier film 7 of the fourth embodiment is the same, and the description thereof is omitted.

次に図１０（ａ）に示すように、前記バリア膜７上に第２の層間絶縁膜１２を約７００ｎｍ堆積する。さらにリソグラフィー及びＲＩＥ技術を用いて加工し、前記第２の層間絶縁膜１２に第１の配線層６に達する配線用接続孔１２ａ及び電極用接続孔１２ｈを形成する。続けて、第２の配線溝１２ｃ及び電極用配線溝１２ｉ形成のため、リソグラフィー及びＲＩＥ技術を用いて加工する。さらに、前記電極用接続孔１２ｈのみの底面の前記バリア膜７をＲＩＥにより除去し、溝７ｂを形成する。   Next, as shown in FIG. 10A, a second interlayer insulating film 12 is deposited on the barrier film 7 by about 700 nm. Further, by using lithography and RIE technology, wiring connection holes 12 a and electrode connection holes 12 h reaching the first wiring layer 6 are formed in the second interlayer insulating film 12. Subsequently, in order to form the second wiring trench 12c and the electrode wiring trench 12i, processing is performed using lithography and RIE technology. Further, the barrier film 7 on the bottom surface of only the electrode connection hole 12h is removed by RIE to form a groove 7b.

ここで、第４の実施例においては、バリア膜７の溝７ｂの形成と同時に溝７ａ形成をしていたが、本実施例では溝７ａの形成は後の工程において行われる。これはＭＩＭ型キャパシタ形成の過程で繰返し行われるリソグラフィー、ＲＩＥ及びレジスト剥離等によって生じる第１の配線層６のダメージを防止するためである。   Here, in the fourth embodiment, the groove 7a is formed simultaneously with the formation of the groove 7b of the barrier film 7. However, in this embodiment, the formation of the groove 7a is performed in a later step. This is to prevent damage to the first wiring layer 6 caused by lithography, RIE, resist stripping, and the like repeatedly performed in the process of forming the MIM type capacitor.

次に、全ての前記配線溝及び接続孔の表面部分にＴａＮ膜１９を約４０ｎｍスパッタ法にて堆積する。   Next, a TaN film 19 is deposited on the surface portions of all the wiring grooves and connection holes by an approximately 40 nm sputtering method.

次に図１０（ｂ）に示すように、前記ＴａＮ膜１９をリソグラフィー及びＲＩＥ技術を用いて加工し、ＴａＮ膜１９ａを形成する。このＴａＮ膜１９ａはＭＩＭ型キャパシタの下部電極膜となる。さらに、全ての前記接続孔及び配線溝を含むＴａＮ膜１９ａ及び第２の層間絶縁膜１２の表面部分にＳｉＮ膜２０を約５０ｎｍ堆積する。   Next, as shown in FIG. 10B, the TaN film 19 is processed by lithography and RIE technology to form a TaN film 19a. This TaN film 19a becomes the lower electrode film of the MIM type capacitor. Further, a SiN film 20 is deposited on the surface portions of the TaN film 19a and the second interlayer insulating film 12 including all the connection holes and wiring trenches by about 50 nm.

次に図１０（ｃ）に示すように、前記ＳｉＮ膜２０をリソグラフィー及びＲＩＥ技術を用いて加工し、ＳｉＮ膜２０ａを形成する。このＳｉＮ膜２０ａはＭＩＭ型キャパシタのキャパシタ絶縁膜となる。   Next, as shown in FIG. 10C, the SiN film 20 is processed using lithography and RIE techniques to form a SiN film 20a. This SiN film 20a becomes a capacitor insulating film of an MIM type capacitor.

次に図１１（ｄ）に示すように、前記第１の配線用接続孔１２ａのみの底面の前記バリア膜７をＲＩＥにより除去し、溝７ａを形成する。   Next, as shown in FIG. 11D, the barrier film 7 on the bottom surface of only the first wiring connection hole 12a is removed by RIE to form a groove 7a.

次に図１１（ｅ）に示すように、全ての前記接続孔及び配線溝を含む前記ＳｉＮ膜２０ａ及び前記第２の層間絶縁膜１２の表面部分にＴａＮ膜２１を約６０ｎｍ堆積する。続けて、前記ＴａＮ膜２１上に約１００ｎｍのＣｕ膜をスパッタ法にて堆積後、電解メッキ法によって前記配線溝内を含む第２の層間絶縁膜１２上全面に約８００ｎｍのＣｕ層２３を堆積させる。さらに、不要なＣｕ層及びＴａＮ膜を研磨・除去することによって、Ｃｕ層２３が平坦化され、第２の層間絶縁膜１２を露出させる。   Next, as shown in FIG. 11E, a TaN film 21 is deposited on the surface portions of the SiN film 20a and the second interlayer insulating film 12 including all the connection holes and wiring trenches by about 60 nm. Subsequently, after depositing a Cu film of about 100 nm on the TaN film 21 by sputtering, a Cu layer 23 of about 800 nm is deposited on the entire surface of the second interlayer insulating film 12 including the inside of the wiring trench by electrolytic plating. Let Further, unnecessary Cu layer and TaN film are polished and removed, so that the Cu layer 23 is planarized and the second interlayer insulating film 12 is exposed.

以上により、第４の実施例と同じ構造を有した前記ＴａＮ膜２１ｂを上部電極膜としたＭＩＭ型キャパシタ２２を形成する。本実施例では、ＭＩＭ型キャパシタ２２形成領域以外の配線層はＭＩＭ型キャパシタの上部電極膜２１ｂ及び第１の配線層のバリアメタル膜２１ａを堆積する直前に露出されるので、Ｃｕ表面の酸化若しくは腐食の防止が図られる。   Thus, the MIM type capacitor 22 having the same structure as that of the fourth embodiment and using the TaN film 21b as the upper electrode film is formed. In this embodiment, the wiring layer other than the region where the MIM capacitor 22 is formed is exposed immediately before the upper electrode film 21b of the MIM capacitor and the barrier metal film 21a of the first wiring layer are deposited. Corrosion can be prevented.

以上の実施例では、ＭＩＭ型キャパシタの上部及び下部電極膜の材料にＴｉＮ膜若しくはＴａＮ膜を用いたが、その他にＣｕの拡散及び酸化防止の役割を果たし、かつ、仕事関数の高い金属導電性材料である、ＷＮ、Ｗ−Ｓｉ−Ｎ若しくはＴｉ−Ｓｉ−Ｎ等を用いることにより、本発明の実施が可能である。   In the above embodiments, TiN film or TaN film is used as the material of the upper and lower electrode films of the MIM type capacitor. In addition, it plays a role of Cu diffusion and oxidation prevention and has a high work function metal conductivity. By using WN, W—Si—N, Ti—Si—N, or the like, which is a material, the present invention can be implemented.

また、キャパシタ絶縁膜としてＳｉＮ膜を用いているが、ＳｉＯＮ膜やＴａ２Ｏ５膜等の誘電体膜を用いても本発明の実施が可能である。   Further, although the SiN film is used as the capacitor insulating film, the present invention can also be implemented using a dielectric film such as a SiON film or a Ta2O5 film.

また、層間絶縁膜はメチルポリシロキサンに限定されないが、デバイスの高速動作に対応させるため低誘電率の絶縁膜であることが望ましく、かつ、ＴａＮ等の前記キャパシタ電極膜の材料とエッチングレートの異なるもの、例えば、ポリアリーレンエーテルやＨＳＱ（商品名：ＦＯｘ）等を用いても本発明の実施が可能である。   The interlayer insulating film is not limited to methylpolysiloxane, but is preferably a low dielectric constant insulating film to cope with high-speed operation of the device, and the etching rate is different from that of the capacitor electrode film such as TaN. For example, polyarylene ether or HSQ (trade name: FOx) can be used to implement the present invention.

また、配線材料としてＣｕを使用したが、前記Ｃｕの代わりにＡｌ、Ａｕ、Ａｇ、Ｗ等の他の金属でも使用することも可能である。   Further, although Cu is used as the wiring material, other metals such as Al, Au, Ag, and W can be used instead of the Cu.

なお、第１と第２の層間絶縁膜との層間中に形成されたＭＩＭ型キャパシタについての実施例であったが、第２と第３の層間絶縁膜との層間中、若しくはそれ以外の層間中のＭＩＭ型キャパシタの形成にも当然有効である。   In this example, the MIM type capacitor is formed in the interlayer between the first and second interlayer insulating films, but in the interlayer between the second and third interlayer insulating films or in other layers. Of course, it is also effective for forming the MIM type capacitor.

したがって、本発明は、かかる特定の実施例に限定されるものではなく、特許請求の範囲に記載した要旨内において様々な変形・変更が可能である。   Therefore, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope described in the claims.

本発明の第１の実施例による半導体装置の製造工程を示す図である（その１）。It is a figure which shows the manufacturing process of the semiconductor device by the 1st Example of this invention (the 1). 本発明の第１の実施例による半導体装置の製造工程を示す図である（その２）。FIG. 8 is a diagram for showing a manufacturing process of the semiconductor device according to the first example (No. 2). 本発明の第２の実施例による半導体装置の製造工程を示す図である（その１）。It is a figure which shows the manufacturing process of the semiconductor device by the 2nd Example of this invention (the 1). 本発明の第２の実施例による半導体装置の製造工程を示す図である（その２）。It is a figure which shows the manufacturing process of the semiconductor device by the 2nd Example of this invention (the 2). 本発明の第３の実施例による半導体装置の製造工程を示す図である（その１）。It is a figure which shows the manufacturing process of the semiconductor device by the 3rd Example of this invention (the 1). 本発明の第３の実施例による半導体装置の製造工程を示す図である（その２）。It is a figure which shows the manufacturing process of the semiconductor device by the 3rd Example of this invention (the 2). 本発明の第４の実施例による半導体装置の製造工程を示す図である（その１）。It is a figure which shows the manufacturing process of the semiconductor device by the 4th Example of this invention (the 1). 本発明の第４の実施例による半導体装置の製造工程を示す図である（その２）。It is a figure which shows the manufacturing process of the semiconductor device by the 4th Example of this invention (the 2). 本発明の第４の実施例による半導体装置の側面断面図及び上面断面図である。FIG. 7 is a side sectional view and a top sectional view of a semiconductor device according to a fourth embodiment of the present invention. 本発明の第５の実施例による半導体装置の製造工程を示す図である（その１）。It is a figure which shows the manufacturing process of the semiconductor device by the 5th Example of this invention (the 1). 本発明の第５の実施例による半導体装置の製造工程を示す図である（その２）。It is a figure which shows the manufacturing process of the semiconductor device by the 5th Example of this invention (the 2). 従来のＭＩＭ型キャパシタの製造工程を示す図である（その１）。It is a figure which shows the manufacturing process of the conventional MIM type | mold capacitor (the 1). 従来のＭＩＭ型キャパシタの製造工程を示す図である（その２）。It is a figure which shows the manufacturing process of the conventional MIM type | mold capacitor (the 2). 従来のＭＩＭ型キャパシタの製造工程を示す図である（その３）。It is a figure which shows the manufacturing process of the conventional MIM type | mold capacitor (the 3).

符号の説明Explanation of symbols

１…半導体基板
２…絶縁膜
３…第１の層間絶縁膜
４…バリアメタル膜
５…第１の配線（Ｃｕ配線）
６…第１の配線層、
７…バリア膜（ＳｉＮ膜）
８ａ…下部電極膜
９ａ…キャパシタ絶縁膜
１０ａ…上部電極膜
１１…ＭＩＭ型キャパシタ
１２…第２の層間絶縁膜
１２ａ…配線用接続孔
１２ｂ…下部電極用接続孔
１２ｃ…第２の配線溝
１２ｄ…下部電極用配線溝
１２ｅ…上部電極用配線溝
１２ｆ…上部電極用接続孔
１２ｇ…上部電極用配線溝
１２ｈ…電極用接続孔
１２ｉ…電極用配線溝
１３…バリアメタル膜
１４ａ…配線用プラグ
１４ｂ…下部電極用プラグ
１４ｃ…第２の配線
１４ｄ…下部電極用配線
１４ｅ…上部電極用配線
１４ｆ…上部電極用プラグ
１４ｇ…上部電極用配線
１５ａ…バリアメタル膜
１５ｂ…下部電極膜
１６…ＭＩＭ型キャパシタ
１７ａ…上部電極膜
１８…ＭＩＭ型キャパシタ
１９…ＴａＮ膜
１９ａ…下部電極膜
２０…誘電体膜
２０ａ…キャパシタ絶縁膜
２１…ＴａＮ膜
２１ａ…バリアメタル膜
２１ｂ…上部電極膜
２２…ＭＩＭ型キャパシタ
２３…Ｃｕ層 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Insulating film 3 ... 1st interlayer insulating film 4 ... Barrier metal film 5 ... 1st wiring (Cu wiring)
6 ... 1st wiring layer,
7: Barrier film (SiN film)
8a ... lower electrode film 9a ... capacitor insulating film 10a ... upper electrode film 11 ... MIM type capacitor 12 ... second interlayer insulating film 12a ... wiring connection hole 12b ... lower electrode connection hole 12c ... second wiring groove 12d ... Lower electrode wiring groove 12e ... Upper electrode wiring groove 12f ... Upper electrode connection hole 12g ... Upper electrode wiring groove 12h ... Electrode connection hole 12i ... Electrode wiring groove 13 ... Barrier metal film 14a ... Wiring plug 14b ... Lower electrode plug 14c ... second wiring 14d ... lower electrode wiring 14e ... upper electrode wiring 14f ... upper electrode plug 14g ... upper electrode wiring 15a ... barrier metal film 15b ... lower electrode film 16 ... MIM capacitor 17a ... Upper electrode film 18 ... MIM type capacitor 19 ... TaN film 19a ... Lower electrode film 20 ... Dielectric film 20a ... Capacitor insulating film 21 ... TaN film 2 a ... barrier metal film 21b ... upper electrode film 22 ... MIM type capacitor 23 ... Cu layer

Claims (5)

半導体基板上に形成されたＭＩＭ型キャパシタを具備する半導体装置において、
半導体基板と、
前記半導体基板上に形成された第１の層間絶縁膜と、
前記第１の層間絶縁膜中に形成された溝に金属膜が埋め込まれ、線間に前記第１の層間絶縁膜が表出するように形成された第１の配線層と、
前記第１の配線層の一部の上面に形成された誘電体膜と、
前記誘電体膜上に形成された導電膜からなる上部電極膜と、
前記上部電極膜の側面と接触するように前記第１の層間絶縁膜上に形成された第２の層間絶縁膜と、
線間に前記第２の層間絶縁膜が表出するように形成された第２の配線、下部電極用配線及び上部電極用配線と、
前記誘電体膜が上面に形成されていない第１の配線層と前記第２の配線とを接続させる配線用プラグと、
前記誘電体膜が上面に形成された第１の配線層と前記下部電極用配線とを接続させる下部電極用プラグと、
を具備し、
前記誘電体膜が上面に形成された第１の配線層の一部領域を下部電極膜とし、かつ、前記誘電体膜をキャパシタ絶縁膜とするＭＩＭ型キャパシタを有することを特徴とする半導体装置。 In a semiconductor device including an MIM type capacitor formed on a semiconductor substrate,
A semiconductor substrate;
A first interlayer insulating film formed on the semiconductor substrate;
A first wiring layer formed so that a metal film is embedded in a groove formed in the first interlayer insulating film, and the first interlayer insulating film is exposed between lines;
A dielectric film formed on an upper surface of a part of the first wiring layer;
An upper electrode film made of a conductive film formed on the dielectric film;
A second interlayer insulating film formed on the first interlayer insulating film so as to be in contact with a side surface of the upper electrode film;
A second wiring, a lower electrode wiring, and an upper electrode wiring formed so as to expose the second interlayer insulating film between the lines;
A wiring plug for connecting the first wiring layer, on which the dielectric film is not formed on the upper surface, and the second wiring;
A lower electrode plug for connecting the first wiring layer having the dielectric film formed on the upper surface and the lower electrode wiring;
Comprising
A semiconductor device comprising an MIM type capacitor having a partial region of the first wiring layer on which the dielectric film is formed as a lower electrode film and the dielectric film as a capacitor insulating film. 前記第１の配線層が、金属配線と、前記金属配線の上面に形成されたバリアメタル膜とからなることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the first wiring layer includes a metal wiring and a barrier metal film formed on an upper surface of the metal wiring. 前記上部電極膜と前記上部電極用配線とが接触していることを特徴とする請求項１記載の半導体装置 2. The semiconductor device according to claim 1, wherein the upper electrode film and the upper electrode wiring are in contact with each other. 前記下部電極膜及び前記上部電極膜は、ＴａＮ、ＴｉＮ、ＷＮ、Ｗ−Ｓｉ−Ｎ、Ｔｉ−Ｓｉ−Ｎ、Ｔａ−Ｓｉ−Ｎの群から選択される少なくとも１つの材料から成ることを特徴とする請求項１乃至３のいずれか一項記載の半導体装置。 The lower electrode film and the upper electrode film are made of at least one material selected from the group consisting of TaN, TiN, WN, W—Si—N, Ti—Si—N, and Ta—Si—N. The semiconductor device according to any one of claims 1 to 3. 半導体基板上に第１の層間絶縁膜を形成し、前記第１の層間絶縁膜に第１の配線溝を形成し、前記第１の配線溝に金属膜及び前記金属膜上面にバリアメタル膜を埋め込み、前記金属膜と前記バリアメタル膜とからなる第１の配線層を形成する第１の配線層構造の製造工程と、
前記第１の配線層の一部の上面に誘電体膜を形成し、前記誘電体膜上に導電膜を形成し、前記第１の配線層の一部を下部電極膜、前記誘電体膜をキャパシタ絶縁膜、前記導電膜を上部電極膜とするＭＩＭ型キャパシタを形成するＭＩＭ型キャパシタの製造工程と、
前記第１の層間絶縁膜上に第２の層間絶縁膜を形成し、前記第２の層間絶縁膜に配線用接続孔及び下部電極用接続孔を同時に形成し、第２の配線溝、下部電極用配線溝及び上部電極用配線溝を同時に形成し、前記配線用接続孔及び下部電極用接続孔並びに第２の配線溝、下部電極用配線溝及び上部電極用配線溝に金属膜を埋め込み、第２の配線層、下部電極用配線層及び上部電極用配線層を形成する第２の配線層構造の製造工程と、
を有することを特徴とする半導体装置の製造方法。 A first interlayer insulating film is formed on a semiconductor substrate, a first wiring groove is formed in the first interlayer insulating film, a metal film is formed in the first wiring groove, and a barrier metal film is formed on the upper surface of the metal film. A manufacturing process of a first wiring layer structure for forming a first wiring layer that is buried and formed of the metal film and the barrier metal film;
A dielectric film is formed on a part of the upper surface of the first wiring layer, a conductive film is formed on the dielectric film, a lower electrode film is formed on a part of the first wiring layer, and the dielectric film is formed on the dielectric film. MIM type capacitor manufacturing process for forming a capacitor insulating film and an MIM type capacitor using the conductive film as an upper electrode film;
A second interlayer insulating film is formed on the first interlayer insulating film, a wiring connection hole and a lower electrode connection hole are simultaneously formed in the second interlayer insulating film, and a second wiring groove and a lower electrode are formed. A wiring groove for the upper electrode and a wiring groove for the upper electrode are formed at the same time, and a metal film is embedded in the wiring connection hole, the lower electrode connection hole, the second wiring groove, the lower electrode wiring groove, and the upper electrode wiring groove; A manufacturing process of a second wiring layer structure for forming two wiring layers, a lower electrode wiring layer and an upper electrode wiring layer;
A method for manufacturing a semiconductor device, comprising:
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