JP2006286878A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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JP2006286878A
JP2006286878A JP2005103921A JP2005103921A JP2006286878A JP 2006286878 A JP2006286878 A JP 2006286878A JP 2005103921 A JP2005103921 A JP 2005103921A JP 2005103921 A JP2005103921 A JP 2005103921A JP 2006286878 A JP2006286878 A JP 2006286878A
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film
wiring
insulating film
forming step
semiconductor device
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Yoshiaki Funatsu
圭亮 船津
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CONSORTIUM ADVANCED SEMICONDUCTOR MATERIALS & RELATED TECHNOLOGIES
CONSORTIUM FOR ADVANCED SEMICONDUCTOR MATERIALS &RELATED TECHNOLOGIES
Consortium for Advanced Semiconductor Materials and Related Technologies
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CONSORTIUM ADVANCED SEMICONDUCTOR MATERIALS & RELATED TECHNOLOGIES
CONSORTIUM FOR ADVANCED SEMICONDUCTOR MATERIALS &RELATED TECHNOLOGIES
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a high quality high performance semiconductor device in which a wiring capacity and a leakage current can be reduced while preventing the drift and diffusion of a wiring material effectively. <P>SOLUTION: The method for manufacturing a semiconductor device comprises a step for forming a first insulating film 2 on a substrate, step for forming a cap film on the insulating film 2 formed in the first insulating film forming step, a step for forming a wiring trench 3 on the insulating film 2 following to the cap film forming step, a step for forming a metal barrier film 4 in the wiring trench 3 following to the wiring trench forming step, a step for filling the wiring trench 3 with a wiring material 5 to form a wiring film following to the metal barrier film forming step, a step for removing the cap film following to the wiring film forming step, a step for providing an organic barrier film 6 by applying organic paint following to the cap film removing step, and a step for forming a second insulating film 7 following to the organic barrier film forming step. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は半導体装置の製造方法に関する。特に、配線間リーク電流が低減し、更にはＴＤＤＢ特性が向上した半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device. In particular, the present invention relates to a method for manufacturing a semiconductor device in which leakage current between wirings is reduced and TDDB characteristics are improved.

今日、ＣｕはＡｌ，Ｗに比べて低抵抗であることから、半導体装置における配線材料はＡｌ，ＷからＣｕに移って来ている。しかしながら、ＡｌやＷと比べて、Ｃｕは、絶縁膜であるシリコン酸化膜（ＳｉＯ膜）中に拡散し易い特徴が有る。従って、Ｃｕ配線間の電界により、絶縁膜−Ｃｕ拡散バリア膜（絶縁膜）界面においては、Ｃｕの拡散を如何に抑制するかが重要である。   Today, since Cu has a lower resistance than Al and W, the wiring material in a semiconductor device has moved from Al and W to Cu. However, compared to Al and W, Cu has a feature that it is easy to diffuse into a silicon oxide film (SiO film) which is an insulating film. Accordingly, it is important how to suppress the diffusion of Cu at the interface between the insulating film and the Cu diffusion barrier film (insulating film) due to the electric field between the Cu wirings.

又、今日のダマシン法によるＣｕ配線形成技術においては、
（１） ＣＭＰ（化学機械研磨）時にマイクロスクラッチが出来るだけ起きないようにすること、
（２） ＣＭＰ後の洗浄不足に起因するＣｕ配線膜上面とＣｕ拡散防止バリア膜（絶縁膜）との界面にＣｕ残渣が出来るだけ残留しないようにすること
が重要である。 Moreover, in today's damascene Cu wiring formation technology,
(1) To prevent micro-scratching as much as possible during CMP (Chemical Mechanical Polishing),
(2) It is important to prevent Cu residue from remaining at the interface between the upper surface of the Cu wiring film and the Cu diffusion prevention barrier film (insulating film) due to insufficient cleaning after CMP.

そして、従来から、絶縁膜−Ｃｕ拡散バリア膜（絶縁膜）界面におけるＣｕの拡散を抑制する為、各種の技術が提案されている。   Conventionally, various techniques have been proposed in order to suppress Cu diffusion at the insulating film-Cu diffusion barrier film (insulating film) interface.

例えば、絶縁膜とＣｕ拡散バリア膜（絶縁膜）との密着性を向上させることによって、Ｃｕの拡散を抑制することが提案されている。すなわち、ＣＭＰ後に、Ｃｕ配線膜上面やＣｕ拡散バリア膜（絶縁膜）上面にＮＨ3ガスのプラズマ処理を施すことにより、密着性を向上させると共に、Ｃｕをイオン化させない構造のものとし、Ｃｕが拡散し難くすることが提案（特開２００１−５３０７６）されている。 For example, it has been proposed to suppress Cu diffusion by improving the adhesion between an insulating film and a Cu diffusion barrier film (insulating film). That is, after the CMP, plasma treatment with NH 3 gas is performed on the upper surface of the Cu wiring film and the upper surface of the Cu diffusion barrier film (insulating film), thereby improving adhesion and preventing Cu from being ionized. It has been proposed (Japanese Patent Laid-Open No. 2001-53076) to make this difficult.

又、絶縁膜−Ｃｕ拡散バリア膜（絶縁膜）界面におけるＣｕのドリフト・拡散を防止する為、又、Ｃｕ配線内の電流（電子の衝突）によるＣｕ原子の移動（エレクトロマイグレーション：ＥＭ）を防止する為、Ｗ−ＣＶＤを用いることによってＣｕ配線膜の上面にＷキャップを設けたり、無電解メッキを用いることによってＣｕ配線膜の上面にＣｏＷＢ，ＣｏＷＰキャップを設ける技術も提案（T,SAITO et al）されている。   In addition, to prevent Cu drift / diffusion at the interface between the insulating film and Cu diffusion barrier film (insulating film), it also prevents movement of Cu atoms (electromigration: EM) due to current (electron collision) in the Cu wiring. Therefore, a technique of providing a W cap on the upper surface of the Cu wiring film by using W-CVD or providing a CoWB or CoWP cap on the upper surface of the Cu wiring film by using electroless plating is also proposed (T, SAITO et al. )

又、ＣＭＰによって出来たマイクロスクラッチによる配線ショートについては次の手法が提案されている。すなわち、ＣＭＰ後に、ハロゲンガスを用いたプラズマ処理によって、マイクロスクラッチが発生した絶縁膜上面を軽く削り取る技術が提案（特開平１０−５６０１４）されている。
特開２００１−５３０７６ 特開平１０−５６０１４ T,Saito et al,IEEE TRANSACTIONS ONELECTRONDEVICES ,vol.51,pp2129-2135,2004 Further, the following method has been proposed for wiring short-circuiting by micro scratch generated by CMP. That is, a technique for lightly scraping the upper surface of the insulating film in which micro scratches are generated by plasma processing using halogen gas after CMP has been proposed (Japanese Patent Laid-Open No. 10-56014).
JP 2001-53076 A JP-A-10-56014 T, Saito et al, IEEE TRANSACTIONS ONELECTRON DEVICES, vol.51, pp2129-2135, 2004

ところで、上記第１の提案（特許文献１）の技術では、絶縁膜−Ｃｕ拡散バリア膜（絶縁膜）界面におけるＣｕの残渣が除去できない。従って、界面に残されたＣｕのドリフト・拡散の問題が残されたままである。   By the way, the technique of the first proposal (Patent Document 1) cannot remove Cu residues at the interface between the insulating film and the Cu diffusion barrier film (insulating film). Therefore, the problem of Cu drift / diffusion left at the interface remains.

上記第２の提案（非特許文献１）の技術は、絶縁膜−Ｃｕ拡散バリア膜（絶縁膜）界面におけるＣｕの残渣が除去できない。従って、界面に残されたＣｕのドリフト・拡散の問題が残されたままである。更には、Ｃｕ配線膜の絶縁膜部分にＣｕの残渣が残留していた場合、絶縁膜部分にもキャップ膜が形成されてしまい、配線ショートが発生する。この為、所望の選択性を得る為には、絶縁膜表面の十分な清浄化と管理とが必要であり、実用化の上では問題が有る。   The technique of the second proposal (Non-Patent Document 1) cannot remove Cu residue at the interface between the insulating film and the Cu diffusion barrier film (insulating film). Therefore, the problem of Cu drift / diffusion left at the interface remains. Furthermore, if Cu residues remain in the insulating film portion of the Cu wiring film, a cap film is also formed in the insulating film portion, causing a wiring short circuit. For this reason, in order to obtain a desired selectivity, it is necessary to sufficiently clean and manage the surface of the insulating film, which is problematic in practical use.

上記第３の提案（特許文献２）の技術では、機械的にスクラッチ溝内に押し込まれたＣｕが除去出来ない。更には、Ｃｕとハロゲンとの反応性は弱い。従って、それ程の効果が期待できない。かつ、仮に、Ｃｕとハロゲンとが反応したとしても、蒸気圧は低く、気化し難いので、表面に残ってしまう。   In the technique of the third proposal (Patent Document 2), Cu that is mechanically pushed into the scratch groove cannot be removed. Furthermore, the reactivity between Cu and halogen is weak. Therefore, such an effect cannot be expected. And even if Cu reacts with halogen, the vapor pressure is low and hardly vaporized, so it remains on the surface.

すなわち、従来の技術では、Ｃｕ配線膜形成に際して、ＣＭＰ後のＣｕ残渣の問題、ＣＭＰ時のスクラッチによる配線耐圧低下の問題が有る。   That is, in the conventional technique, there are a problem of Cu residue after CMP and a problem of a decrease in wiring breakdown voltage due to scratches during CMP when forming a Cu wiring film.

又、Ｃｕ拡散防止の為に、ＳｉＣＮ等のＣｕ拡散バリア膜（絶縁膜）が用いられているが、この場合には誘電率が高くなり、配線容量の増大をもたらす。   In order to prevent Cu diffusion, a Cu diffusion barrier film (insulating film) such as SiCN is used. However, in this case, the dielectric constant increases and the wiring capacity increases.

又、配線膜とＣｕ拡散バリア膜（絶縁膜）との界面におけるリーク電流が多い。又、低誘電率膜とキャップ膜との間の界面も有り、これ等の界面におけるリーク電流も多い。すなわち、無機膜と無機膜との界面が多く、リーク電流が多い。   In addition, there are many leak currents at the interface between the wiring film and the Cu diffusion barrier film (insulating film). There is also an interface between the low dielectric constant film and the cap film, and there is a large amount of leakage current at these interfaces. That is, there are many interfaces between the inorganic film and the inorganic film, and the leakage current is large.

従って、本発明が解決しようとする課題は、上記の問題点を解決することである。特に、配線容量の減少、リーク電流の減少、配線材料のドリフト・拡散を効果的に防止でき、高品質・高性能な半導体装置を提供することである。   Therefore, the problem to be solved by the present invention is to solve the above problems. In particular, it is to provide a high-quality and high-performance semiconductor device that can effectively prevent a reduction in wiring capacitance, a leakage current, and drift / diffusion of wiring material.

前記の課題は、基板上に絶縁膜を設ける第１絶縁膜成膜工程と、
前記第１絶縁膜成膜工程で成膜された絶縁膜上にキャップ膜を設けるキャップ膜成膜工程と、
前記キャップ膜成膜工程の後、前記絶縁膜に配線用溝を形成する配線用溝形成工程と、
前記配線用溝形成工程の後、前記配線用溝にメタルバリア膜を設けるメタルバリア膜形成工程と、
前記メタルバリア膜形成工程の後、配線用溝に配線材料を充填する配線膜形成工程と、
前記配線膜形成工程の後、前記キャップ膜を除去するキャップ膜除去工程と、
前記キャップ膜除去工程の後、有機系塗料を塗布してバリア膜を設ける有機バリア膜成膜工程と、
前記有機バリア膜成膜工程の後、絶縁膜を設ける第２絶縁膜成膜工程
とを具備することを特徴とする半導体装置の製造方法によって解決される。 The above-described problems include a first insulating film forming step of providing an insulating film on a substrate,
A cap film forming step of providing a cap film on the insulating film formed in the first insulating film forming step;
A wiring groove forming step of forming a wiring groove in the insulating film after the cap film forming step;
A metal barrier film forming step of providing a metal barrier film in the wiring groove after the wiring groove forming step;
After the metal barrier film forming step, a wiring film forming step of filling the wiring groove with a wiring material;
After the wiring film forming step, a cap film removing step for removing the cap film;
After the cap film removing step, an organic barrier film forming step of applying an organic paint and providing a barrier film;
After the organic barrier film forming step, the semiconductor device manufacturing method includes a second insulating film forming step of providing an insulating film.

上記本発明において、配線材料は、特に、Ｃｕである。有機バリア膜を構成する材料は、比誘電率が３．５以下のＣｕ拡散防止機能を有する樹脂である。特に、Ｎ含有樹脂である。更には、Ｎ含有量が５〜２５原子％の樹脂である。例えば、ポリベンゾオキサゾール、ポリシラザン、及びポリイミドの群の中から選ばれる少なくとも一つである。   In the present invention, the wiring material is particularly Cu. The material constituting the organic barrier film is a resin having a Cu diffusion preventing function with a relative dielectric constant of 3.5 or less. In particular, it is an N-containing resin. Furthermore, it is a resin having an N content of 5 to 25 atomic%. For example, at least one selected from the group of polybenzoxazole, polysilazane, and polyimide.

上記本発明において、キャップ膜除去工程は、ウェットエッチング、ドライエツチング、アッシング、又は溶媒による除去の技術によって行われる。すなわち、従来から良く用いられて来た熟練技術によって簡単に行なえる。   In the present invention, the cap film removal step is performed by a technique of wet etching, dry etching, ashing, or removal using a solvent. That is, it can be easily performed by skilled techniques that have been used frequently.

本発明は、例えばＣＭＰ後にＣＭＰキャップ膜を除去し、即ち、ＣＭＰ後でもＣｕが残っていたり、ＣＭＰによって出来たスクラッチの付いたＣＭＰキャップ膜を除去し、そしてＣｕ配線膜の上面に、新たに、塗布系有機バリア膜を設けるようにした。尚、ＣＭＰキャップ膜は、選択ＣＶＤや選択メッキ等の制御性に乏しい技術と異なり、従来から用いられて来たウェットエッチング、ドライエツチング、アッシング、又は溶媒による除去の技術によって簡単に除去できる。従って、簡単な製造技術を用いて製造できるから、信頼性の高い半導体装置を簡単に得ることが出来る。又、Ｃｕによる汚染部は除去されることから、残留Ｃｕの拡散に起因するリーク電流は大幅に低減する。かつ、Ｃｕ配線膜の上面は、比誘電率が３．５以下のＣｕ拡散防止機能を有する樹脂、特に、Ｎ含有量が５〜２５原子％の樹脂、例えばポリベンゾオキサゾール、ポリシラザン、又はポリイミドの塗膜で覆われているから、Ｃｕの拡散も効果的に防止される。   The present invention, for example, removes a CMP cap film after CMP, that is, removes a CMP cap film with Cu remaining after CMP or a scratch formed by CMP, and newly forms a top surface of the Cu wiring film. A coating type organic barrier film was provided. The CMP cap film can be easily removed by conventional techniques such as wet etching, dry etching, ashing, or solvent removal, unlike techniques with poor controllability such as selective CVD and selective plating. Therefore, since it can be manufactured using a simple manufacturing technique, a highly reliable semiconductor device can be easily obtained. Further, since the contaminated portion due to Cu is removed, the leakage current due to the diffusion of residual Cu is greatly reduced. Further, the upper surface of the Cu wiring film is made of a resin having a Cu diffusion preventing function with a relative dielectric constant of 3.5 or less, particularly a resin having an N content of 5 to 25 atomic%, such as polybenzoxazole, polysilazane, or polyimide. Since it is covered with the coating film, Cu diffusion is also effectively prevented.

そして、本発明では、ＳｉＣＮ等のＣｕ拡散バリア膜（絶縁膜）が不要である。従って、誘電率の増大を防止できる。   In the present invention, a Cu diffusion barrier film (insulating film) such as SiCN is unnecessary. Therefore, an increase in dielectric constant can be prevented.

更には、絶縁膜−Ｃｕ拡散バリア膜（絶縁膜）の界面が無く、従ってリーク電流も少なくなる。又、ＴＤＤＢ特性の向上も期待できる。   Further, there is no interface between the insulating film and the Cu diffusion barrier film (insulating film), and therefore the leakage current is reduced. In addition, improvement in TDDB characteristics can be expected.

又、本発明では、配線膜層の上に有機塗料を塗布して塗膜を設けるので、平坦性が高いものとなる。その結果、上層において、リソグラフィ技術を用いる場合、平坦化されていることから、リソグラフィマージンが確保される。   Moreover, in this invention, since an organic coating material is apply | coated and a coating film is provided on a wiring film layer, it becomes a thing with high flatness. As a result, in the case of using a lithography technique in the upper layer, the lithography margin is ensured because it is flattened.

図１〜図３は、本発明になる半導体装置の製造方法の工程図である。   1 to 3 are process diagrams of a method of manufacturing a semiconductor device according to the present invention.

尚、本発明の理解を一層容易なものとする為、従来の半導体装置の概略を図４に示す。図４中、１１はＳｉ基板上に設けられたエッチング停止膜、１２はエッチング停止膜１１上に設けられたポーラス状の低誘電率絶縁膜、１３は低誘電率絶縁膜１２上に設けられたＣＭＰキャップ膜、１４は低誘電率絶縁膜１２及びＣＭＰキャップ膜１３に形成された凹条溝の壁面に薄く形成されたメタルバリア膜、１５はメタルバリア膜１４上の凹条溝内に充填されたＣｕ配線膜、１６はＣＭＰキャップ膜１３及びＣｕ配線膜１５上に設けられたＣｕ拡散バリア膜（絶縁膜）、１７はＣｕ拡散バリア膜（絶縁膜）上に設けられた層間絶縁膜である。   In order to facilitate the understanding of the present invention, an outline of a conventional semiconductor device is shown in FIG. In FIG. 4, 11 is an etching stop film provided on the Si substrate, 12 is a porous low dielectric constant insulating film provided on the etching stop film 11, and 13 is provided on the low dielectric constant insulating film 12. The CMP cap film 14 is a thin metal barrier film formed on the wall surface of the groove formed in the low dielectric constant insulating film 12 and the CMP cap film 13, and 15 is filled in the groove on the metal barrier film 14. Cu wiring film, 16 is a Cu diffusion barrier film (insulating film) provided on the CMP cap film 13 and Cu wiring film 15, and 17 is an interlayer insulating film provided on the Cu diffusion barrier film (insulating film). .

本実施形態の半導体装置は、図３と図４との対比から判る通り、ＣＭＰキャップ膜１３及びＣｕ拡散バリア膜（絶縁膜）１６が設けられていない点に特徴が有る。   The semiconductor device of this embodiment is characterized in that the CMP cap film 13 and the Cu diffusion barrier film (insulating film) 16 are not provided, as can be seen from the comparison between FIG. 3 and FIG.

このような特徴の半導体装置は、次のようにして得られる。
すなわち、先ず、図１に示される如く、Ｓｉ基板上にエッチング停止膜１が設けられる。そして、エッチング停止膜１上に、ポーラス状の低誘電率絶縁膜２が設けられる。更に、低誘電率絶縁膜２上にＣＭＰキャップ膜（図示せず）が設けられる。この後、フォトリソグラフィー技術を用いて、所定パターンの配線用凹溝３を、ＣＭＰキャップ膜および低誘電率絶縁膜２に対して形成する。次いで、配線用凹溝３の溝内表面に所定厚さのメタルバリア膜４を形成する。この後、配線用凹溝３のメタルバリア膜４上にＣｕを充填し、Ｃｕ配線膜５を形成する。尚、この工程までは、従来と同様に行うことが出来る。 The semiconductor device having such characteristics is obtained as follows.
That is, first, as shown in FIG. 1, the etching stop film 1 is provided on the Si substrate. A porous low dielectric constant insulating film 2 is provided on the etching stopper film 1. Further, a CMP cap film (not shown) is provided on the low dielectric constant insulating film 2. Thereafter, a wiring concave groove 3 having a predetermined pattern is formed on the CMP cap film and the low dielectric constant insulating film 2 by using a photolithography technique. Next, a metal barrier film 4 having a predetermined thickness is formed on the groove inner surface of the wiring groove 3. Thereafter, Cu is filled on the metal barrier film 4 of the wiring groove 3 to form a Cu wiring film 5. In addition, it can carry out similarly to the past until this process.

そして、Ｃｕ配線膜５を形成した後、ウェットエッチング、ドライエッチング、アッシング、或いは有機溶剤による除去と言った材料に適した手法を用いて、ＣＭＰキャップ膜を除去する（図１参照）。   Then, after the Cu wiring film 5 is formed, the CMP cap film is removed using a technique suitable for the material such as wet etching, dry etching, ashing, or removal with an organic solvent (see FIG. 1).

ＣＭＰキャップ膜を除去した後、図２に示される通り、比誘電率が３のポリベンゾオキサゾールを含む塗料をスピンコーティングで塗布し、そして硬化処理し、Ｃｕ拡散防止機能を有する有機バリア塗膜６を設ける。従って、図２からも判る通り、Ｃｕ配線膜５は、その周囲がメタルバリア膜４と有機バリア塗膜６とによって完全に覆われている。よって、Ｃｕのドリフト・拡散が効果的に防止される。そして、ＥＭ耐性の改善が得られる。又、従来用いられていたＣｕ拡散バリア膜（絶縁膜）が不要になる。   After removing the CMP cap film, as shown in FIG. 2, a coating material containing polybenzoxazole having a relative dielectric constant of 3 is applied by spin coating and cured to form an organic barrier coating film 6 having a Cu diffusion preventing function. Is provided. Therefore, as can be seen from FIG. 2, the periphery of the Cu wiring film 5 is completely covered with the metal barrier film 4 and the organic barrier coating film 6. Therefore, Cu drift / diffusion is effectively prevented. And the improvement of EM tolerance is obtained. Further, a conventionally used Cu diffusion barrier film (insulating film) is not required.

この後、図３に示される通り、ポーラス状の低誘電率絶縁膜２と同材質のポーラス状の低誘電率絶縁膜７を設ける。   Thereafter, as shown in FIG. 3, a porous low dielectric constant insulating film 7 made of the same material as the porous low dielectric constant insulating film 2 is provided.

上記のように構成させた半導体装置は、図３からも判る通り、Ｃｕ配線膜５は、その周囲がＣｕ拡散防止機能を有する有機バリア塗膜６とメタルバリア膜４とによって完全に覆われている。よって、Ｃｕのドリフト・拡散が効果的に防止される。そして、ＥＭ耐性の改善が得られる。又、従来用いられていたＣｕ拡散バリア膜（絶縁膜）が不要になる。   In the semiconductor device configured as described above, as can be seen from FIG. 3, the Cu wiring film 5 is completely covered with the organic barrier coating 6 and the metal barrier film 4 that have a Cu diffusion preventing function. Yes. Therefore, Cu drift / diffusion is effectively prevented. And the improvement of EM tolerance is obtained. Further, a conventionally used Cu diffusion barrier film (insulating film) is not required.

そして、上記のようにして得られた半導体装置は、Ｃｕ配線膜５の周囲が有機バリア塗膜６とメタルバリア膜４によって完全に覆われているから、配線間リーク電流の減少、ＴＤＤＢ特性が向上する。因みに、図５に示される通り、リーク電流は低減している。   In the semiconductor device obtained as described above, since the periphery of the Cu wiring film 5 is completely covered with the organic barrier coating film 6 and the metal barrier film 4, the reduction in inter-wiring leakage current and the TDDB characteristics are achieved. improves. Incidentally, as shown in FIG. 5, the leakage current is reduced.

そして、ＣＭＰ後のＣｕ残渣（残留物）が無い。かつ、ＣＭＰによってＣＭＰキャップ膜にスクラッチが出来たとしても、ＣＭＰキャップ膜は除去されることから、スクラッチに起因した問題は完全に解決される。   And there is no Cu residue (residue) after CMP. Even if the CMP cap film is scratched by CMP, the CMP cap film is removed, so that the problem caused by the scratch is completely solved.

更には、一般的には誘電率が高いＣＭＰキャップ膜やＣｕ拡散バリア膜（絶縁膜）が無いことから、誘電率の増大を防止でき、実効誘電率は低下し、配線間容量が低下し、配線遅延の問題も改善される。   Furthermore, in general, since there is no CMP cap film or Cu diffusion barrier film (insulating film) having a high dielectric constant, an increase in the dielectric constant can be prevented, the effective dielectric constant is lowered, and the capacitance between wirings is reduced. The problem of wiring delay is also improved.

又、本発明では、有機バリア塗膜６が塗布手段で設けられたので、層の平坦性が高いものとなる。その結果、上層において、リソグラフィ技術を用いる場合、平坦化されていることから、リソグラフィ解像マージン及び露光裕度（ＤＯＦ）のマージンが確保される。   Moreover, in this invention, since the organic barrier coating film 6 was provided by the application means, the flatness of the layer becomes high. As a result, when the lithography technique is used in the upper layer, since it is flattened, a lithography resolution margin and a margin of exposure tolerance (DOF) are ensured.

本発明になる半導体装置の製造工程における断面図Sectional drawing in the manufacturing process of the semiconductor device which becomes this invention 本発明になる半導体装置の製造工程における断面図Sectional drawing in the manufacturing process of the semiconductor device which becomes this invention 本発明になる半導体装置の特徴を示す断面図Sectional drawing which shows the characteristics of the semiconductor device which becomes this invention 従来の半導体装置の断面図Sectional view of a conventional semiconductor device 本発明の特長を示すグラフGraph showing the features of the present invention

符号の説明Explanation of symbols

１ エッチング停止膜
２，７ ポーラス状低誘電率絶縁膜
３ 配線用凹溝
４ メタルバリア膜
５ Ｃｕ配線膜
６ 有機バリア塗膜

代 理 人 宇 高 克 己 DESCRIPTION OF SYMBOLS 1 Etching stop film 2, 7 Porous low dielectric constant insulating film 3 Groove for wiring 4 Metal barrier film 5 Cu wiring film 6 Organic barrier coating film

Representative Katsumi Udaka

Claims (7)

基板上に絶縁膜を設ける第１絶縁膜成膜工程と、
前記第１絶縁膜成膜工程で成膜された絶縁膜上にキャップ膜を設けるキャップ膜成膜工程と、
前記キャップ膜成膜工程の後、前記絶縁膜に配線用溝を形成する配線用溝形成工程と、
前記配線用溝形成工程の後、前記配線用溝にメタルバリア膜を設けるメタルバリア膜形成工程と、
前記メタルバリア膜形成工程の後、配線用溝に配線材料を充填する配線膜形成工程と、
前記配線膜形成工程の後、前記キャップ膜を除去するキャップ膜除去工程と、
前記キャップ膜除去工程の後、有機系塗料を塗布してバリア膜を設ける有機バリア膜成膜工程と、
前記有機バリア膜成膜工程の後、絶縁膜を設ける第２絶縁膜成膜工程
とを具備することを特徴とする半導体装置の製造方法。 A first insulating film forming step of providing an insulating film on the substrate;
A cap film forming step of providing a cap film on the insulating film formed in the first insulating film forming step;
A wiring groove forming step of forming a wiring groove in the insulating film after the cap film forming step;
A metal barrier film forming step of providing a metal barrier film in the wiring groove after the wiring groove forming step;
After the metal barrier film forming step, a wiring film forming step of filling the wiring groove with a wiring material;
After the wiring film forming step, a cap film removing step for removing the cap film;
After the cap film removing step, an organic barrier film forming step of applying an organic paint and providing a barrier film;
A method of manufacturing a semiconductor device, comprising: a second insulating film forming step of providing an insulating film after the organic barrier film forming step. 配線材料がＣｕであることを特徴とする請求項１の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the wiring material is Cu. キャップ膜除去工程は、ウェットエッチング、ドライエツチング、アッシング、又は溶媒による除去の技術によって行われることを特徴とする請求項１又は請求項２の半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein the cap film removing step is performed by a technique of wet etching, dry etching, ashing, or removal using a solvent. 有機バリア膜は、比誘電率が３．５以下のＣｕ拡散防止機能を有する樹脂からなることを特徴とする請求項１〜請求項３いずれかの半導体装置の製造方法。   4. The method of manufacturing a semiconductor device according to claim 1, wherein the organic barrier film is made of a resin having a relative dielectric constant of 3.5 or less and having a Cu diffusion preventing function. 有機バリア膜は、比誘電率が３．５以下のＮ含有樹脂からなることを特徴とする請求項１〜請求項４いずれかの半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 1, wherein the organic barrier film is made of an N-containing resin having a relative dielectric constant of 3.5 or less. 有機バリア膜は、比誘電率が３．５以下で、Ｎ含有量が５〜２５原子％の樹脂からなることを特徴とする請求項１〜請求項５いずれかの半導体装置の製造方法。   6. The method of manufacturing a semiconductor device according to claim 1, wherein the organic barrier film is made of a resin having a relative dielectric constant of 3.5 or less and an N content of 5 to 25 atomic%. 有機バリア膜は、ポリベンゾオキサゾール、ポリシラザン、及びポリイミドの群の中から選ばれる少なくとも一つからなることを特徴とする請求項１〜請求項６いずれかの半導体装置の製造方法。
7. The method of manufacturing a semiconductor device according to claim 1, wherein the organic barrier film is made of at least one selected from the group consisting of polybenzoxazole, polysilazane, and polyimide.
JP2005103921A 2005-03-31 2005-03-31 Method for manufacturing semiconductor device Pending JP2006286878A (en)

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JP2003007705A (en) * 2001-06-26 2003-01-10 Mitsubishi Electric Corp Formation method of copper wiring
JP2004068005A (en) * 2002-06-27 2004-03-04 Infineon Technologies Ag Dielectric material having barrier effect on diffusion of copper
JP2004296835A (en) * 2003-03-27 2004-10-21 Applied Materials Inc Method for constructing damascene structure
JP2004296515A (en) * 2003-03-25 2004-10-21 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2005033164A (en) * 2003-07-09 2005-02-03 Hynix Semiconductor Inc Method of forming copper wiring for semiconductor element
JP2005072384A (en) * 2003-08-26 2005-03-17 Matsushita Electric Ind Co Ltd Method for manufacturing electronic device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000077519A (en) * 1998-09-01 2000-03-14 Fujitsu Ltd Semiconductor device and its manufacture
JP2003007705A (en) * 2001-06-26 2003-01-10 Mitsubishi Electric Corp Formation method of copper wiring
JP2004068005A (en) * 2002-06-27 2004-03-04 Infineon Technologies Ag Dielectric material having barrier effect on diffusion of copper
JP2004296515A (en) * 2003-03-25 2004-10-21 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2004296835A (en) * 2003-03-27 2004-10-21 Applied Materials Inc Method for constructing damascene structure
JP2005033164A (en) * 2003-07-09 2005-02-03 Hynix Semiconductor Inc Method of forming copper wiring for semiconductor element
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