JP2006278771A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP2006278771A
JP2006278771A JP2005096227A JP2005096227A JP2006278771A JP 2006278771 A JP2006278771 A JP 2006278771A JP 2005096227 A JP2005096227 A JP 2005096227A JP 2005096227 A JP2005096227 A JP 2005096227A JP 2006278771 A JP2006278771 A JP 2006278771A
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semiconductor device
resin
wiring board
heat sink
gap
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Yuichi Miyazaki
裕一 宮崎
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof capable of preventing occurrence of a bent by increasing the rigidity of a structure in one way or another. <P>SOLUTION: The semiconductor device 10 includes a wiring substrate 51, an LSI chip 52 provided on the wiring substrate 51, a heat sink 11 provided on the LSI chip 52, a reinforcing plate 12 inserted to a circumferential edge of air gap between the heat sink 11 and the wiring substrate 51, a capacitor 71 provided on the wiring substrate 51 in the air gap between the heat sink 11 and the wiring substrate 51, and a resin 13 filled in the air gap between the heat sink 11 and the wiring substrate 51. The resin 13 is filled in the air gap surrounded by the LSI chip 52, wiring substrate 51, the reinforcing plate 12 and the head sink 11. The resin 13 suppresses the occurrence of a bent caused by the entire heat of the semiconductor 10 produced by the existence of the air gap. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、例えばＦＣＢＧＡ（flip-chip ball grid array）などの半導体装置、及びその製造方法に関する。   The present invention relates to a semiconductor device such as a FCBGA (flip-chip ball grid array) and a method for manufacturing the same.

ＦＣＢＧＡは、高密度実装に適した構造であるため、コンピュータ装置などに広く用いられている（例えば特許文献１）。図４は、この種の半導体装置（第一従来例）を示す断面図である。以下、この図面に基づき説明する。   Since FCBGA has a structure suitable for high-density mounting, it is widely used in computer devices and the like (for example, Patent Document 1). FIG. 4 is a sectional view showing this type of semiconductor device (first conventional example). Hereinafter, description will be given based on this drawing.

半導体装置５０は、配線基板５１と、配線基板５１上に設けられたＬＳＩチップ５２と、ＬＳＩチップ５２上に設けられた放熱板５３と、放熱板５３と配線基板５１との間の空隙に介挿された補強板５４と、を備えたＦＣＢＧＡである。ＬＳＩチップ５２は、はんだバンプ５５の溶着によって配線基板５１に接続されている。ＬＳＩチップ５２と配線基板５１との間のギャップには、アンダーフィル樹脂５６が注入されている。アンダーフィル樹脂５６は、ＬＳＩチップ５２と配線基板５１との熱膨張係数差による熱応力を緩和する働きをする。配線基板５１には、半導体装置５０（パッケージ）全体の剛性を高めるための補強板５４が具備されている。つまり、補強板５４は、接着剤５７を介して配線基板５１に接着され、接着剤５８を介して放熱板５３に接着されることにより、半導体装置５０全体の剛性を高めている。また、ＬＳＩチップ５２には、効率よく排熱するための放熱板５３が熱伝導性樹脂５９によって接続されている。更に、配線基板５１の裏面には、他の配線基板（以下「マザーボード」という。）に実装させるためのはんだボール６０が設けられている。   The semiconductor device 50 includes a wiring board 51, an LSI chip 52 provided on the wiring board 51, a heat sink 53 provided on the LSI chip 52, and a gap between the heat sink 53 and the wiring board 51. It is FCBGA provided with the inserted reinforcement board 54. FIG. The LSI chip 52 is connected to the wiring substrate 51 by welding of solder bumps 55. An underfill resin 56 is injected into the gap between the LSI chip 52 and the wiring substrate 51. The underfill resin 56 functions to alleviate thermal stress due to a difference in thermal expansion coefficient between the LSI chip 52 and the wiring substrate 51. The wiring board 51 is provided with a reinforcing plate 54 for increasing the rigidity of the entire semiconductor device 50 (package). That is, the reinforcing plate 54 is bonded to the wiring substrate 51 through the adhesive 57 and is bonded to the heat dissipation plate 53 through the adhesive 58, thereby increasing the rigidity of the entire semiconductor device 50. Further, a heat radiating plate 53 for efficiently exhausting heat is connected to the LSI chip 52 by a heat conductive resin 59. Furthermore, solder balls 60 for mounting on another wiring board (hereinafter referred to as “mother board”) are provided on the back surface of the wiring board 51.

ここで、アンダーフィル樹脂５６の作用について詳しく説明する。半導体装置５０のＯＮ／ＯＦＦによって、ＬＳＩチップ５２と配線基板５１とは膨張及び収縮を繰り返す。このとき、ＬＳＩチップ５２の熱膨張係数は３．５ｐｐｍである。これに対し、配線基板５１の熱膨張係数は、プリント基板の場合が１６ｐｐｍであり、アルミナ基板の場合が８ｐｐｍである。そのため、これらの熱膨張差によりはんだバンプ５５が圧縮及び引っ張りの応力を交互に受けることになる。この熱疲労によってはんだバンプ５５が早期に破壊されることにより、電気的な接続が無くなるので、ＬＳＩチップ５２への信号伝達や電源供給が断絶してしまう。よって、このような構造では信頼性の低い半導体装置５０となってしまう。そこで、ＬＳＩチップ５２と配線基板５１との間隙にアンダーフィル樹脂５６を充填することにより、ＬＳＩチップ５２と配線基板５１との間に発生する熱応力を緩和させる。アンダーフィル樹脂５６は、主にエポキシ系の樹脂が使用される。   Here, the action of the underfill resin 56 will be described in detail. The LSI chip 52 and the wiring board 51 are repeatedly expanded and contracted by turning on and off the semiconductor device 50. At this time, the thermal expansion coefficient of the LSI chip 52 is 3.5 ppm. On the other hand, the thermal expansion coefficient of the wiring board 51 is 16 ppm for the printed circuit board and 8 ppm for the alumina board. Therefore, the solder bumps 55 are alternately subjected to compressive and tensile stresses due to these thermal expansion differences. Since the solder bumps 55 are destroyed early due to this thermal fatigue, the electrical connection is lost, so that signal transmission and power supply to the LSI chip 52 are interrupted. Therefore, such a structure results in a semiconductor device 50 with low reliability. Therefore, by filling the gap between the LSI chip 52 and the wiring substrate 51 with an underfill resin 56, thermal stress generated between the LSI chip 52 and the wiring substrate 51 is relieved. As the underfill resin 56, an epoxy resin is mainly used.

特開２００２−１９０５６０号公報JP 2002-190560 A

最近、半導体装置を高周波動作させるため、ＬＳＩチップの周辺にコンデンサを配置することが多くなってきている。図５は、この種の半導体装置（第二従来例）を示す断面図である。以下、この図面に基づき説明する。ただし、図４と同じ部分は同じ符号を付すことにより説明を省略する。   Recently, in order to operate a semiconductor device at a high frequency, a capacitor is often arranged around an LSI chip. FIG. 5 is a sectional view showing this type of semiconductor device (second conventional example). Hereinafter, description will be given based on this drawing. However, the same parts as those in FIG.

半導体装置７０では、ＬＳＩチップ５２の周辺の配線基板５１上にコンデンサ７１が配置されている。そして、コンデンサ７１の占有面積を得るために、補強板７２の大きさを小さくしている。しかしながら、補強板７２を第一従来例よりも小さくしたことにより、補強板７２本来の目的である剛性確保が損なわれ、半導体装置７０の反りなどが生じやすくなる。また、近年のはんだの鉛フリー化により、はんだバンプ５５が硬くなったことから、半導体装置７０がますます反りやすくなってきている。このような問題は、アンダーフィル樹脂５６では解決できない。   In the semiconductor device 70, a capacitor 71 is disposed on the wiring substrate 51 around the LSI chip 52. And in order to obtain the occupation area of the capacitor | condenser 71, the magnitude | size of the reinforcement board 72 is made small. However, by making the reinforcing plate 72 smaller than that of the first conventional example, securing the rigidity, which is the original purpose of the reinforcing plate 72, is impaired, and the semiconductor device 70 is likely to be warped. In addition, since the solder bump 55 has become hard due to the recent lead-free soldering, the semiconductor device 70 is more likely to warp. Such a problem cannot be solved by the underfill resin 56.

そこで、本発明の目的は、何らかの形で構造体の剛性を上げることにより、反りの発生を防ぐことができる、半導体装置及びその製造方法を提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can prevent the occurrence of warping by increasing the rigidity of the structure in some form.

本発明に係る半導体装置は、配線基板と、配線基板上に設けられた半導体チップと、半導体チップ上に設けられた放熱板と、放熱板と配線基板との間の空隙に充填された樹脂と、を備えている。放熱板と配線基板との間の空隙に樹脂が充填されていることにより、半導体チップと配線基板との熱膨張係数差によって生じる応力が樹脂によって吸収されるので、半導体装置の反りが抑制される。   A semiconductor device according to the present invention includes a wiring board, a semiconductor chip provided on the wiring board, a heat sink provided on the semiconductor chip, and a resin filled in a gap between the heat sink and the wiring board. It is equipped with. By filling the gap between the heat sink and the wiring board with the resin, the stress caused by the difference in thermal expansion coefficient between the semiconductor chip and the wiring board is absorbed by the resin, so that the warpage of the semiconductor device is suppressed. .

また、半導体チップと配線基板とは突起電極を介して電気的に接続された、としてもよい。このとき、突起電極ははんだバンプでもよく、はんだバンプは鉛フリーはんだから成るものでもよい。鉛フリーはんだは、鉛を含むはんだに比べて硬い。したがって、鉛フリーはんだから成るはんだバンプを用いた半導体装置は、より一層反りやすいので、本発明の効果が顕著になる。   Further, the semiconductor chip and the wiring board may be electrically connected via protruding electrodes. At this time, the bump electrode may be a solder bump, and the solder bump may be made of lead-free solder. Lead-free solder is harder than solder containing lead. Therefore, since the semiconductor device using the solder bump made of lead-free solder is more likely to warp, the effect of the present invention becomes remarkable.

また、放熱板と配線基板との間の空隙の一部の配線基板上にチップ部品が設けられた、としてもよい。チップ部品は、コンデンサ、抵抗器、インダクタなどの受動素子でもよいし、ダイオード、トランジスタ、ＩＣなどの能動素子でもよい。   Further, a chip component may be provided on a part of the wiring board in the gap between the heat sink and the wiring board. The chip component may be a passive element such as a capacitor, a resistor, or an inductor, or may be an active element such as a diode, a transistor, or an IC.

また、放熱板と配線基板との間の空隙に補強板が介挿された、としてもよい。このとき、空隙にチップ部品を設けると、補強板を設けるスペースが少なくなることにより、補強板を小さくしなければならない。そうなると、半導体装置の剛性が低下するので、本発明の効果がより顕著になる。   Moreover, it is good also as the reinforcement board inserted in the space | gap between a heat sink and a wiring board. At this time, if the chip component is provided in the gap, the space for providing the reinforcing plate is reduced, so that the reinforcing plate must be made small. As a result, the rigidity of the semiconductor device is lowered, so that the effect of the present invention becomes more remarkable.

また、放熱板と補強板との互いの対向面の少なくとも一方に、樹脂を注入する樹脂注入溝が形成された、としてもよい。この場合は、樹脂注入溝を使って、放熱板と配線基板との間の空隙に樹脂を効率よく充填するこができる。   Moreover, it is good also as the resin injection | pouring groove | channel which inject | pours resin was formed in at least one of the mutually opposing surface of a heat sink and a reinforcement board. In this case, the resin can be efficiently filled into the gap between the heat sink and the wiring board using the resin injection groove.

本発明に係る半導体装置の製造方法は、本発明に係る半導体装置を製造する方法であって、次の（１）〜（３）の工程を有する。（１）配線基板上に、半導体チップを設ける。（２）半導体チップ上に、放熱板を設ける。（３）放熱板と配線基板との間の形成された空隙に、樹脂を充填する。   A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device according to the present invention, and includes the following steps (1) to (3). (1) A semiconductor chip is provided on a wiring board. (2) A heat sink is provided on the semiconductor chip. (3) Fill the gap formed between the heat sink and the wiring board with resin.

配線基板上に半導体チップを設け、樹脂を充填した後に、半導体チップ上に放熱板を設けると、半導体チップと放熱板との間に樹脂が入り込み、熱放散を妨げることがある。これに対し、本発明では、半導体チップ上に放熱板を設けた後に樹脂を充填するので、そのようなことが起こらない。   If a semiconductor chip is provided on the wiring board and a heat sink is provided on the semiconductor chip after the resin is filled, the resin may enter between the semiconductor chip and the heat sink to prevent heat dissipation. On the other hand, in this invention, since resin is filled after providing a heat sink on a semiconductor chip, such a thing does not occur.

また、本発明に係る半導体装置の製造方法は、次の構成の本発明に係る半導体装置を製造する方法である。その半導体装置は、配線基板と、配線基板上に設けられた半導体チップと、半導体チップ上に設けられた放熱板と、放熱板と配線基板との間の空隙に充填された樹脂と、前記空隙に介挿された補強板と、補強板と放熱板との対向面の少なくとも一方に形成された樹脂注入溝と、を備えたものである。って、次の（１）〜（３）の工程を有する。そして、その製造方法は、次の（１）〜（３）の工程を有する。（１）配線基板上に半導体チップ及び補強板を設ける。（２）半導体チップ上に、放熱板を設ける。（３）樹脂注入溝から樹脂を注入することにより、空隙に樹脂を充填する。この場合は、樹脂注入溝を使って、放熱板と配線基板との間の空隙に樹脂を効率よく充填することができる。   The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device according to the present invention having the following configuration. The semiconductor device includes a wiring board, a semiconductor chip provided on the wiring board, a heat sink provided on the semiconductor chip, a resin filled in a gap between the heat sink and the wiring board, and the gap. And a resin injection groove formed on at least one of the opposing surfaces of the reinforcing plate and the heat radiating plate. Thus, the following steps (1) to (3) are included. The manufacturing method includes the following steps (1) to (3). (1) A semiconductor chip and a reinforcing plate are provided on the wiring board. (2) A heat sink is provided on the semiconductor chip. (3) Filling the gap with resin by injecting resin from the resin injection groove. In this case, the resin can be efficiently filled into the gap between the heat sink and the wiring board using the resin injection groove.

本発明に係る半導体装置は、放熱板と配線基板との間の空隙に樹脂を充填したことにより、熱による反りを抑制できるため、マザーボードにはんだ付によって搭載した際に、はんだ付の品質やはんだ接続の信頼性を向上できる。   Since the semiconductor device according to the present invention can suppress warping due to heat by filling the gap between the heat sink and the wiring board with resin, the soldering quality and soldering can be reduced when mounted on the mother board by soldering. Connection reliability can be improved.

本発明によれば、放熱板と配線基板との間の空隙に樹脂を充填したことにより、半導体チップと配線基板との熱膨張差による反りの発生を抑制できるので、半導体装置の信頼性を向上できる。また、半導体装置の反りを抑制できることにより、半導体装置とマザーボードとを接続するはんだボールに対して、半導体装置のオン／オフによって発生するストレスを軽減できる。これによっても、半導体装置の信頼性を向上できる。更に、半導体装置の反りを軽減できることから、マザーボードに対して半導体装置を面接続できるので、マザーボードへ半導体装置をリフローはんだ付する際の歩留まりを向上できる。   According to the present invention, since the resin is filled in the gap between the heat sink and the wiring board, it is possible to suppress the occurrence of warpage due to the difference in thermal expansion between the semiconductor chip and the wiring board, thereby improving the reliability of the semiconductor device. it can. In addition, since the warpage of the semiconductor device can be suppressed, the stress generated by turning on / off the semiconductor device can be reduced with respect to the solder balls connecting the semiconductor device and the mother board. This also improves the reliability of the semiconductor device. Further, since the warpage of the semiconductor device can be reduced, the semiconductor device can be surface-connected to the motherboard, so that the yield when the semiconductor device is reflow soldered to the motherboard can be improved.

図１は、本発明に係る半導体装置の一実施形態を示す断面図である。以下、この図面に基づき説明する。ただし、図５と同じ部分は同じ符号を付すことにより説明を省略する。   FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device according to the present invention. Hereinafter, description will be given based on this drawing. However, the same parts as those in FIG.

半導体装置１０は、配線基板５１と、配線基板５１上に設けられたＬＳＩチップ５２と、ＬＳＩチップ５２上に設けられた放熱板１１と、放熱板１１と配線基板５１との間の空隙の周縁部に介挿された補強板１２と、放熱板１１と配線基板５１との間の空隙の配線基板５１上に設けられたコンデンサ７１と、放熱板１１と配線基板５１との間の空隙に充填された樹脂１３と、を備えている。   The semiconductor device 10 includes a wiring board 51, an LSI chip 52 provided on the wiring board 51, a heat radiation plate 11 provided on the LSI chip 52, and a peripheral edge of a gap between the heat radiation plate 11 and the wiring board 51. The reinforcing plate 12 inserted in the part, the capacitor 71 provided on the wiring board 51 in the gap between the heat sink 11 and the wiring board 51, and the gap between the heat sink 11 and the wiring board 51 are filled. Resin 13.

ＬＳＩチップ５２には、その回路面に信号の入出力や電源の供給を行うはんだバンプ５５が設けられている。はんだバンプ５５の組成は、Ｓｎ／Ｐｂ合金、Ｓｎ／Ｂｉ／Ａｇ合金、Ｓｎ／Ａｇ合金等が使用される。一方、Ｃｕなどの導電体で形成された内部配線１４を有する配線基板５１の表面には、補強板１２及び複数のパッド（符号省略）が具備されている。複数のパッドは、それぞれ内部配線１４によって、配線基板５１の電源層への接続又は他の部品への相互接続が行われる。   The LSI chip 52 is provided with solder bumps 55 for inputting / outputting signals and supplying power on the circuit surface. As the composition of the solder bump 55, Sn / Pb alloy, Sn / Bi / Ag alloy, Sn / Ag alloy, or the like is used. On the other hand, a reinforcing plate 12 and a plurality of pads (reference numerals omitted) are provided on the surface of the wiring substrate 51 having the internal wiring 14 formed of a conductor such as Cu. The plurality of pads are respectively connected to the power supply layer of the wiring board 51 or to other components by the internal wiring 14.

配線基板５１に設けられたパッド上にはんだバンプ５５を介してＬＳＩチップ５２が搭載されることにより、配線基板５１とＬＳＩチップ５２とが電気的かつ機械的に接続される。その上で、ＬＳＩチップ５２と配線基板５１との間隙には、アンダーフィル樹脂５６が充填されている。アンダーフィル樹脂５６は、機械的強度を確保するだけではなく、ＬＳＩチップ５２と配線基板５１との熱膨張係数差によって発生するはんだボール６０の熱応力を緩和する。   By mounting the LSI chip 52 on the pads provided on the wiring board 51 via the solder bumps 55, the wiring board 51 and the LSI chip 52 are electrically and mechanically connected. In addition, the gap between the LSI chip 52 and the wiring board 51 is filled with an underfill resin 56. The underfill resin 56 not only ensures mechanical strength, but also relieves the thermal stress of the solder ball 60 generated by the difference in thermal expansion coefficient between the LSI chip 52 and the wiring substrate 51.

ＬＳＩチップ５２の近傍にはコンデンサ７１が実装されており、ＬＳＩチップ５２による高速のデータ転送を可能としている。また、ＬＳＩチップ５２のはんだバンプ５５の反対面には、放熱板１１が熱伝導性樹脂５９によって取り付けられている。そのため、ＬＳＩチップ５２から発生する熱を、放熱板１１で効率よく排出することが可能となっている。放熱板１１には、排熱性を確保するため、熱伝導性に優れたＣｕなどが用いられる。   A capacitor 71 is mounted in the vicinity of the LSI chip 52 so that high-speed data transfer by the LSI chip 52 is possible. Further, the heat radiating plate 11 is attached to the opposite surface of the LSI chip 52 from the solder bump 55 by a heat conductive resin 59. Therefore, the heat generated from the LSI chip 52 can be efficiently discharged by the heat radiating plate 11. For the heat radiating plate 11, Cu or the like having excellent thermal conductivity is used in order to ensure exhaust heat.

ＬＳＩチップ５２、配線基板５１、補強板１２及び放熱板１１によって囲まれた空隙には、樹脂１３が充填されている。樹脂１３は、空隙部分の存在によって発生する半導体装置１０全体の熱による反りを抑制する。このとき、樹脂１３は、熱膨張係数が配線基板５１や放熱板１１に近く、かつヤング率の大きなものを選択することにより、より一層効果が顕著になる。例えば、配線基板５１が有機材料で構成される場合、樹脂１３は、熱膨張係数が３０ｐｐｍ程度、かつヤング率が５００００ＭＰａ程度のものが好ましい。これによって、半導体装置１０をはんだボール６０を介してマザーボードに実装したとき、半導体装置１０の電源オンオフに起因するはんだボール６０への熱ストレスの発生を抑制できるので、はんだボール６０の寿命を延ばすことができ、その結果信頼性の高い半導体装置１０を提供することが可能となる。   A space surrounded by the LSI chip 52, the wiring substrate 51, the reinforcing plate 12 and the heat radiating plate 11 is filled with the resin 13. The resin 13 suppresses the warp due to the heat of the entire semiconductor device 10 that occurs due to the presence of the void portion. At this time, the resin 13 is more effective by selecting a resin whose thermal expansion coefficient is close to that of the wiring board 51 or the heat sink 11 and has a large Young's modulus. For example, when the wiring board 51 is made of an organic material, the resin 13 preferably has a thermal expansion coefficient of about 30 ppm and a Young's modulus of about 50000 MPa. As a result, when the semiconductor device 10 is mounted on the mother board via the solder balls 60, it is possible to suppress the occurrence of thermal stress on the solder balls 60 due to power on / off of the semiconductor device 10, thereby extending the life of the solder balls 60. As a result, the highly reliable semiconductor device 10 can be provided.

次に、半導体装置１０の製造方法について、図１乃至図３に基づき説明する。   Next, a method for manufacturing the semiconductor device 10 will be described with reference to FIGS.

図２［１］は放熱板１１の平面図及び正面図であり、図２［２］は、補強板１２の平面図及び正面図である。以下、この図面に基づき説明する。   FIG. 2 [1] is a plan view and a front view of the heat radiating plate 11, and FIG. 2 [2] is a plan view and a front view of the reinforcing plate 12. Hereinafter, description will be given based on this drawing.

放熱板１１の表面１１ｂは平面である。一方、放熱板１１の裏面１１ａには、放熱板１１各辺の中央に全部で四本の樹脂注入溝１１１〜１１４が形成されている。同じように、補強板１２の裏面１１ｂは平面である。一方、補強板１２の表面１１ａには、補強板１２各辺の中央に全部で四本の樹脂注入溝１２１〜１２４が形成されている。樹脂注入溝１１１〜１１４と樹脂注入溝１２１〜１２４とは、それぞれ対向する位置に形成されているので、対向することによってより大きな樹脂注入溝となる。なお、樹脂注入溝１１１〜１１４，１２１〜１２４は、図示したものに限らず、本数、幅、長さ及び深さを自由に選択してよい。   The surface 11b of the heat sink 11 is a plane. On the other hand, a total of four resin injection grooves 111 to 114 are formed on the back surface 11a of the heat radiating plate 11 at the center of each side of the heat radiating plate 11. Similarly, the back surface 11b of the reinforcing plate 12 is a flat surface. On the other hand, a total of four resin injection grooves 121 to 124 are formed in the center of each side of the reinforcing plate 12 on the surface 11 a of the reinforcing plate 12. Since the resin injection grooves 111 to 114 and the resin injection grooves 121 to 124 are formed at positions facing each other, the resin injection grooves 111 to 114 become larger resin injection grooves by facing each other. The resin injection grooves 111 to 114 and 121 to 124 are not limited to those shown in the figure, and the number, width, length, and depth may be freely selected.

図３は半導体装置１０の製造方法を示す断面図であり、図３［１］は第一工程、図３［２］は第二工程である。以下、図１及び図３に基づき説明する。   FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device 10, in which FIG. 3 [1] is a first step and FIG. 3 [2] is a second step. Hereinafter, a description will be given based on FIGS. 1 and 3.

まず、配線基板５１上に、はんだバンプ５５を介してＬＳＩチップ５２を設けるとともに、接着剤５７を介して補強板１２を設ける。このとき、補強板１２は、樹脂注入溝１２２，１２４が上になるように、配線基板５１上に設ける。続いて、ＬＳＩチップ５２上に、熱伝導性樹脂５９を介して、放熱板１１を設ける。このとき、放熱板１１は、樹脂注入溝１１２，１１４が下になるように、ＬＳＩチップ５２上に設ける（図３［１］）。   First, the LSI chip 52 is provided on the wiring board 51 via the solder bumps 55, and the reinforcing plate 12 is provided via the adhesive 57. At this time, the reinforcing plate 12 is provided on the wiring board 51 so that the resin injection grooves 122 and 124 are on the top. Subsequently, the heat radiating plate 11 is provided on the LSI chip 52 through the heat conductive resin 59. At this time, the heat radiating plate 11 is provided on the LSI chip 52 so that the resin injection grooves 112 and 114 are located downward (FIG. 3 [1]).

続いて、ディスペンサ２０などを用いて、樹脂注入溝１１４，１２４から樹脂１３を注入する（図３［２］）。これにより、配線基板５１、放熱板１１、補強板１２及びＬＳＩチップ５２によって囲まれた空隙に、樹脂１３が充填される（図１）。   Subsequently, the resin 13 is injected from the resin injection grooves 114 and 124 using the dispenser 20 or the like (FIG. 3 [2]). Thereby, the resin 13 is filled in the space surrounded by the wiring board 51, the heat radiating plate 11, the reinforcing plate 12, and the LSI chip 52 (FIG. 1).

本実施形態によれば、樹脂注入溝１１４，１２４を使って、放熱板１１と配線基板５１との間の空隙に、樹脂１３を効率よく充填するこができる。また、配線基板５１上にＬＳＩチップ５２を設け、樹脂１３を先に充填した後に、ＬＳＩチップ５２上に放熱板１１を設けると、ＬＳＩチップ５２と放熱板１１との間に樹脂１３が入り込み、熱放散を妨げることがある。これに対し、本実施形態では、ＬＳＩチップ５２上に放熱板１１を設けた後に樹脂１３を充填するので、そのようなことが起こらない。   According to the present embodiment, the resin 13 can be efficiently filled into the gap between the heat sink 11 and the wiring board 51 using the resin injection grooves 114 and 124. Further, when the LSI chip 52 is provided on the wiring substrate 51 and the heat sink 11 is provided on the LSI chip 52 after the resin 13 is first filled, the resin 13 enters between the LSI chip 52 and the heat sink 11. May interfere with heat dissipation. On the other hand, in this embodiment, since the resin 13 is filled after the heat radiation plate 11 is provided on the LSI chip 52, such a situation does not occur.

なお、本発明は、言うまでもなく、上記実施形態に限定されない。例えば、配線基板５１上にコンデンサ７１が搭載されていない場合にも、本発明を適用できる。   Needless to say, the present invention is not limited to the above embodiment. For example, the present invention can be applied even when the capacitor 71 is not mounted on the wiring board 51.

本発明に係る半導体装置の一実施形態を示す断面図である。It is sectional drawing which shows one Embodiment of the semiconductor device which concerns on this invention. 図１の半導体装置における放熱板及び補強板を示し、図２［１］は放熱板の平面図及び正面図であり、図２［２］は補強板の平面図及び正面図である。2 shows a heat sink and a reinforcing plate in the semiconductor device of FIG. 1, FIG. 2 [1] is a plan view and a front view of the heat sink, and FIG. 2 [2] is a plan view and a front view of the reinforcing plate. 図１の半導体装置の製造方法を示す断面図であり、図３［１］は第一工程、図３［２］は第二工程である。FIGS. 3A and 3B are cross-sectional views illustrating a method of manufacturing the semiconductor device of FIG. 1, in which FIG. 従来の半導体装置の第一例を示す断面図である。It is sectional drawing which shows the 1st example of the conventional semiconductor device. 従来の半導体装置の第二例を示す断面図である。It is sectional drawing which shows the 2nd example of the conventional semiconductor device.

符号の説明Explanation of symbols

１０ 半導体装置
１１ 放熱板
１１１〜１１４ 放熱板の樹脂注入溝
１２ 補強板
１２１〜１２４ 補強板の樹脂注入溝
１３ 樹脂
５１ 配線基板
５２ ＬＳＩチップ（半導体チップ）
５５ はんだバンプ
７１ コンデンサ（チップ部品） DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Heat sink 111-114 Resin injection groove of heat sink 12 Reinforcement plate 121-124 Resin injection groove of reinforcement plate 13 Resin 51 Wiring board 52 LSI chip (semiconductor chip)
55 Solder bump 71 Capacitor (chip component)

Claims (9)

配線基板と、この配線基板上に設けられた半導体チップと、この半導体チップ上に設けられた放熱板と、この放熱板と前記配線基板との間の空隙に充填された樹脂と、を備えたことを特徴とする半導体装置。   A wiring board; a semiconductor chip provided on the wiring board; a heat sink provided on the semiconductor chip; and a resin filled in a gap between the heat sink and the wiring board. A semiconductor device. 前記半導体チップと前記配線基板とは突起電極を介して電気的に接続された、
請求項１記載の半導体装置。 The semiconductor chip and the wiring board are electrically connected via protruding electrodes,
The semiconductor device according to claim 1. 前記突起電極ははんだバンプである、
請求項２記載の半導体装置。 The protruding electrode is a solder bump.
The semiconductor device according to claim 2. 前記はんだバンプは鉛フリーはんだから成る、
請求項３記載の半導体装置。 The solder bump is made of lead-free solder.
The semiconductor device according to claim 3. 前記空隙の一部の前記配線基板上にチップ部品が設けられた、
請求項１乃至４のいずれかに記載の半導体装置。 A chip component is provided on the wiring board in a part of the gap,
The semiconductor device according to claim 1. 前記空隙に補強板が介挿された、
請求項１乃至５のいずれかに記載の半導体装置。 A reinforcing plate is inserted in the gap,
The semiconductor device according to claim 1. 前記放熱板と前記補強板との互いの対向面の少なくとも一方に、前記樹脂を注入する樹脂注入溝が形成された、
請求項６記載の半導体装置。
A resin injection groove for injecting the resin is formed on at least one of the opposing surfaces of the heat radiating plate and the reinforcing plate,
The semiconductor device according to claim 6.
配線基板上に半導体チップを設け、この半導体チップ上に放熱板を設け、この放熱板と前記配線基板との間の空隙に樹脂を充填する、
ことを特徴とする半導体装置の製造方法。 A semiconductor chip is provided on the wiring board, a heat sink is provided on the semiconductor chip, and a resin is filled in a gap between the heat sink and the wiring board.
A method for manufacturing a semiconductor device. 配線基板と、この配線基板上に設けられた半導体チップと、この半導体チップ上に設けられた放熱板と、この放熱板と前記配線基板との間の空隙に充填された樹脂と、前記空隙に介挿された補強板と、この補強板と前記放熱板との対向面の少なくとも一方に形成された樹脂注入溝と、を備えた半導体装置を製造する方法であって、
前記配線基板上に前記半導体チップ及び前記補強板を設け、前記半導体チップ上に放熱板を設け、前記樹脂注入溝から前記樹脂を注入することにより前記空隙に樹脂を充填する、
ことを特徴とする半導体装置の製造方法。 A wiring board; a semiconductor chip provided on the wiring board; a heat sink provided on the semiconductor chip; a resin filled in a gap between the heat sink and the wiring board; and A method of manufacturing a semiconductor device comprising an inserted reinforcing plate and a resin injection groove formed on at least one of the opposing surfaces of the reinforcing plate and the heat radiating plate,
Providing the semiconductor chip and the reinforcing plate on the wiring substrate, providing a heat sink on the semiconductor chip, and filling the gap with resin by injecting the resin from the resin injection groove;
A method for manufacturing a semiconductor device.
JP2005096227A 2005-03-29 2005-03-29 Semiconductor device and manufacturing method thereof Pending JP2006278771A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011211243A (en) * 2011-07-27 2011-10-20 Renesas Electronics Corp Method of manufacturing semiconductor device
KR20120010616A (en) * 2010-07-21 2012-02-06 삼성전자주식회사 Stack package, semiconductor package and method of manufacturing the stack package
JP2012216878A (en) * 2012-08-13 2012-11-08 Shinko Electric Ind Co Ltd Resin-sealed package
JP2014179612A (en) * 2013-03-14 2014-09-25 General Electric Co <Ge> Power overlay structure and method for manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0917827A (en) * 1995-06-29 1997-01-17 Fujitsu Ltd Semiconductor device
JPH09186264A (en) * 1995-12-27 1997-07-15 Ibiden Co Ltd Electronic component mounting board
JP2000349203A (en) * 1999-06-07 2000-12-15 Nec Corp Circuit device and manufacture thereof
JP2004119882A (en) * 2002-09-27 2004-04-15 Sony Corp Semiconductor device
JP2004260138A (en) * 2003-02-03 2004-09-16 Nec Electronics Corp Semiconductor device and manufacturing method therefor
JP2004327556A (en) * 2003-04-22 2004-11-18 Matsushita Electric Works Ltd Semiconductor device and its manufacturing process

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0917827A (en) * 1995-06-29 1997-01-17 Fujitsu Ltd Semiconductor device
JPH09186264A (en) * 1995-12-27 1997-07-15 Ibiden Co Ltd Electronic component mounting board
JP2000349203A (en) * 1999-06-07 2000-12-15 Nec Corp Circuit device and manufacture thereof
JP2004119882A (en) * 2002-09-27 2004-04-15 Sony Corp Semiconductor device
JP2004260138A (en) * 2003-02-03 2004-09-16 Nec Electronics Corp Semiconductor device and manufacturing method therefor
JP2004327556A (en) * 2003-04-22 2004-11-18 Matsushita Electric Works Ltd Semiconductor device and its manufacturing process

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120010616A (en) * 2010-07-21 2012-02-06 삼성전자주식회사 Stack package, semiconductor package and method of manufacturing the stack package
KR101678539B1 (en) * 2010-07-21 2016-11-23 삼성전자 주식회사 Stack package, semiconductor package and method of manufacturing the stack package
JP2011211243A (en) * 2011-07-27 2011-10-20 Renesas Electronics Corp Method of manufacturing semiconductor device
JP2012216878A (en) * 2012-08-13 2012-11-08 Shinko Electric Ind Co Ltd Resin-sealed package
JP2014179612A (en) * 2013-03-14 2014-09-25 General Electric Co <Ge> Power overlay structure and method for manufacturing the same
US10269688B2 (en) 2013-03-14 2019-04-23 General Electric Company Power overlay structure and method of making same

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