JP2006270069A - Magnetoresistance effect element and high-speed magnetic recording device based on domain wall displacement by pulse current - Google Patents

Magnetoresistance effect element and high-speed magnetic recording device based on domain wall displacement by pulse current Download PDF

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JP2006270069A
JP2006270069A JP2006043457A JP2006043457A JP2006270069A JP 2006270069 A JP2006270069 A JP 2006270069A JP 2006043457 A JP2006043457 A JP 2006043457A JP 2006043457 A JP2006043457 A JP 2006043457A JP 2006270069 A JP2006270069 A JP 2006270069A
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magnetization
layer
magnetization fixed
fixed layer
free layer
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JP4932275B2 (en
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Masahiko Ichimura
雅彦 市村
宏昌 ▲高▼橋
Hiromasa Takahashi
Hajime Tatara
源 多々良
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Hitachi Ltd
Osaka University NUC
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Abstract

<P>PROBLEM TO BE SOLVED: To realize a magnetoresistance element capable of high-speed magnetization reversal and having low critical current density, and provide a solid memory. <P>SOLUTION: A magnetoresistance effect element comprises a first magnetization fixed layer, a magnetization free layer, and a second magnetization fixed layer. The first magnetization fixed layer is roughly anti-parallel to the second magnetization fixed layer. Both of transition regions between the first magnetization fixed layer and the magnetization free layer and between the second magnetization fixed layer and the magnetization free layer can trap magnetic domain walls, and there is provided a structure in which the magnetic domain wall exists in either one of them. Between the first and second magnetization fixed layers, pulse current having the DC current density with a pulse width of 1 ns that is a value not exceeding 10<SP>6</SP>A/cm<SP>2</SP>is supplied. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、パルス電流の印加に伴う低電流密度かつ高速な磁壁移動による磁化反転過程を利用した記憶、磁気抵抗効果を利用して読み出しをする固体メモリ素子およびこれらを利用した装置に関する。   The present invention relates to a memory using a magnetization reversal process due to low-current density and high-speed domain wall movement accompanying application of a pulse current, a solid-state memory element that reads using a magnetoresistive effect, and a device using these.

磁気抵抗効果は、磁性体に磁場を印加したとき、あるいは磁性体の磁化状態が変化したとき電気抵抗が変化する現象である。この効果を利用した磁気抵抗効果素子として、従来から磁気ヘッドや磁気センサが知られ、最近では不揮発性固体磁気メモリ素子（ＭＲＡＭ）なども試作されるようになってきている。   The magnetoresistance effect is a phenomenon in which the electrical resistance changes when a magnetic field is applied to the magnetic material or when the magnetization state of the magnetic material changes. As a magnetoresistive effect element using this effect, a magnetic head and a magnetic sensor are conventionally known, and recently, a nonvolatile solid-state magnetic memory element (MRAM) or the like has been prototyped.

現在試作されているＭＲＡＭの主要な形態は、ビット線とワード線の交点にトンネル磁気抵抗（ＴＭＲ）素子が配置されたマトリックス状の構造を持つ。各配線に流した電流の作る合成磁場により、ＴＭＲ素子の磁化の向きを反転させ記録の書き込みを行う。つまりＴＭＲ素子がメモリセルの役割を担う。メモリセルの情報を読み出すためには、メモリセルからのリーク電流が存在するため、ＭＯＳトランジスタによるセルの選択が必須となる。これらの構造を有するＭＲＡＭは、その構造ゆえ、プロセス技術の複合化という欠点、ならびに、高密度大容量化に適さない以下の３つの欠点が指摘されている。一つは、メモリセルの縮小化による有効な反転磁場条件が狭くなること。もう一つは、磁性体の薄膜化による反転磁場の増大、それにともなう配線電流、消費電力の増大。最後の一つは、セル選択のためのＭＯＳトランジスタを有するためＤＲＡＭと同程度しか集積できないことである。   The main form of the MRAM currently being prototyped has a matrix structure in which tunnel magnetoresistive (TMR) elements are arranged at the intersections of bit lines and word lines. Recording is performed by reversing the direction of magnetization of the TMR element by a synthetic magnetic field generated by a current flowing through each wiring. That is, the TMR element plays the role of a memory cell. In order to read the information of the memory cell, since there is a leak current from the memory cell, it is essential to select the cell by the MOS transistor. MRAMs having these structures have been pointed out because of their structures, the following disadvantages are the combination of process technologies and the following three defects that are not suitable for high density and large capacity. One is that the effective reversal magnetic field conditions are reduced by downsizing the memory cells. The other is the increase of the reversal magnetic field due to the thin film of the magnetic material, and the accompanying increase in wiring current and power consumption. The last is that it can be integrated only to the same extent as DRAM because it has MOS transistors for cell selection.

一方、最近、反転磁場を利用しない磁化反転過程であるスピントルクが提案され（非特許文献１、２）、実際にスピントルクによる磁化反転が確認された（非特許文献３，４）。このスピントルクによって、メモリセルへの書き込みが提案されている。しかしながら、スピントルクによる磁化反転は、現在、以下の２つの技術的課題を抱えている。一つは、スピントルクによる磁化反転過程の動作速度は、緩和時間により決定されてしまうことである。これは、この磁化反転過程は、磁化の緩和（ダンピング）により引き起こされる準定常状態における磁化回転を利用するためであり、したがって高速磁化反転が要求される固体メモリには対応できない。もう一つは、磁化反転を引き起こすスピントルクの生成には、１０８Ａ／ｃｍ２の程度の高い臨界電流密度が必要とされることである。 On the other hand, recently, spin torque, which is a magnetization reversal process that does not use a reversal magnetic field, has been proposed (Non-Patent Documents 1 and 2), and magnetization reversal by spin torque was actually confirmed (Non-Patent Documents 3 and 4). Writing to a memory cell has been proposed by this spin torque. However, magnetization reversal by spin torque currently has the following two technical problems. One is that the operating speed of the magnetization reversal process by spin torque is determined by the relaxation time. This is because the magnetization reversal process uses magnetization rotation in a quasi-steady state caused by magnetization relaxation (damping), and therefore cannot be applied to a solid-state memory that requires high-speed magnetization reversal. The other is that a critical current density as high as 10 8 A / cm 2 is required to generate spin torque that causes magnetization reversal.

フィジカルレビューＢ３９巻、６９９５−７００２頁（1989)(Phys. Rev. B 39, 6995-7002 (1989)）Physical Review B39, 6995-7002 (1989) (Phys. Rev. B 39, 6995-7002 (1989)) フィジカルレビューＢ５４巻、９３５３−９３５８頁（１９９６）（Phys. Rev. B 54, 9353-9358 (1996)）Physical Review B 54, 9353-9358 (1996) (Phys. Rev. B 54, 9353-9358 (1996)) フィジカルレビューレターズ８４巻、３１４９−３１５２頁（２０００）（Phys. Rev. Lett. 84, 3149-3152 (2000)）Physical Review Letters 84, 3149-3152 (2000) (Phys. Rev. Lett. 84, 3149-3152 (2000)) アプライドフィジックスレターズ７８巻、３６６３−３６６５頁（２００１）（Appl. Phys. Lett. 78, 3663-3665 (2001)）Applied Physics Letters 78, 3663-3665 (2001) (Appl. Phys. Lett. 78, 3663-3665 (2001))

本発明の目的は、スピントルク磁化反転と同様、反転磁場を利用しない磁化反転過程によるメモリセルへの書き込みにおいて、低い臨界電流密度、ならびに高速磁化反転過程を有する磁気抵抗効果素子および磁気記録装置を提供することにある。   An object of the present invention is to provide a magnetoresistive element and a magnetic recording device having a low critical current density and a high-speed magnetization reversal process in writing to a memory cell by a magnetization reversal process that does not use a reversal magnetic field, as in spin torque magnetization reversal. It is to provide.

上記目的を達成するため、本発明の高速磁気記録装置は、第１の磁化固定層、磁化自由層、第２の磁化固定層からなり、前記第１の磁化固定層と前記第２の磁化固定層とを略反平行とし、前記第１磁化固定層と前記磁化自由層間、あるいは前記第２磁化固定層と前記磁化自由層間の両方の遷移領域が磁壁をトラップでき、かつ、どちらか一方に磁壁が存在する構造を備え、前記第１、第２磁化固定層の間に、０．６〜２．０ｎｓの範囲の、十分短いパルス幅のパルス電流を供給する。   In order to achieve the above object, a high-speed magnetic recording apparatus according to the present invention includes a first magnetization fixed layer, a magnetization free layer, and a second magnetization fixed layer, and the first magnetization fixed layer and the second magnetization fixed layer. And the transition region of both the first magnetization fixed layer and the magnetization free layer or the second magnetization fixed layer and the magnetization free layer can trap the domain wall, and one of them is the domain wall. And a pulse current having a sufficiently short pulse width in the range of 0.6 to 2.0 ns is supplied between the first and second magnetization fixed layers.

上記構成において、パルス電流の直流電流密度が１０６Ａ／ｃｍ２を超えない値で磁壁が２つの遷移領域の間で移動することにより磁化自由層の磁化を反転させることが可能となる。磁化自由層の磁化反転により、上記第１あるいは第２磁化固定層間の遷移領域の相対磁化の向きの変化による磁気抵抗を検出する。 In the above configuration, the magnetization of the magnetization free layer can be reversed by moving the domain wall between the two transition regions with a DC current density of the pulse current not exceeding 10 6 A / cm 2 . The magnetic resistance due to the change in the relative magnetization direction of the transition region between the first and second magnetization fixed layers is detected by the magnetization reversal of the magnetization free layer.

本発明の磁気抵抗効果素子によれば、磁化反転に必要な臨界電流密度が低く、かつ高速に書き込みのできる磁気記憶装置が実現できる。   According to the magnetoresistive element of the present invention, it is possible to realize a magnetic storage device that has a low critical current density required for magnetization reversal and can be written at high speed.

以下、図面を参照しつつ本発明の実施の形態について説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

（実施例１）
（固体メモリ素子への応用）
図１は本発明の磁気抵抗効果素子１０を説明するための概念図であり、図２は図１に示す磁気抵抗効果素子１０の特性を説明する図である。 Example 1
(Application to solid-state memory devices)
FIG. 1 is a conceptual diagram for explaining the magnetoresistive effect element 10 of the present invention, and FIG. 2 is a diagram for explaining the characteristics of the magnetoresistive effect element 10 shown in FIG.

幅および厚さが１００ｎｍのＣｏからなる強磁性細線を通常の電子線リソグラフィー技術により作成する。次に、強磁性細線の端部から長さ２００ｎｍの領域を第１の強磁性細線部１１とし、これに隣接して、幅、厚さ、および、長さ２０ｎｍの第１の狭窄部１２、これに隣接して、幅および厚さが１００ｎｍ、長さが１０ｎｍの強磁性微小領域部１３、これに隣接して、幅、厚さ、および、長さ２０ｎｍの第２の狭窄部１４、これに隣接して、幅、厚さ、および、長さ１００ｎｍの第２の強磁性細線部１５となるように、通常の電子線リソグラフィー技術により加工する。   A ferromagnetic fine wire made of Co having a width and thickness of 100 nm is formed by a normal electron beam lithography technique. Next, a region having a length of 200 nm from the end of the ferromagnetic fine wire is defined as a first ferromagnetic fine wire portion 11, and a first constriction portion 12 having a width, a thickness, and a length of 20 nm is adjacent to the first ferromagnetic fine wire portion 11. Adjacent to this, a ferromagnetic microregion part 13 having a width and thickness of 100 nm and a length of 10 nm, and adjoining this, a second constriction part 14 having a width, thickness and length of 20 nm, Is processed by a normal electron beam lithography technique so as to form a second ferromagnetic fine wire portion 15 having a width, a thickness, and a length of 100 nm.

ここで、第１、第２の強磁性細線部１１、１５のそれぞれの磁化の向きが逆（反平行）になるように、外部磁場により、一方の磁化を反転させて、磁化固定層とする。強磁性微小領域部１３が磁化自由層である。以下、それぞれの層の機能に着目して、第１、第２の強磁性細線部１１、１５を第１、第２の磁化固定層１１、１５、また強磁性微小領域部１３を磁化自由層１３と呼ぶ。   Here, the magnetization of one of the first and second ferromagnetic thin wire portions 11 and 15 is reversed (antiparallel) so that one of the magnetizations is reversed by the external magnetic field to form a magnetization fixed layer. . The ferromagnetic minute region 13 is a magnetization free layer. Hereinafter, paying attention to the function of each layer, the first and second ferromagnetic thin wire portions 11 and 15 are changed to the first and second magnetization fixed layers 11 and 15 and the ferromagnetic minute region portion 13 is changed to the magnetization free layer. 13 is called.

また、第１、第２の狭窄部１２，１４は、前記第１、第２の磁化固定層１１、１５、および磁化自由層１３に比べ、幅、厚さ、および、長さ共に小さく作成される部分であり、第１、第２の狭窄部１２，１４を第１、第２の遷移領域と呼ぶ。第１、第２の遷移領域は、上述したＣｏのみならず、他の例としては、複数の膜厚を有する連続した磁性体の膜厚変化部分（ステップ）、磁性体／絶縁体積層構造の絶縁体部分、あるいは前記絶縁体部分に形成されるピンホールなどで形成しても良い。これらは通常の電子線リソグラフィー技術により加工できる。   Further, the first and second constriction portions 12 and 14 are made smaller in width, thickness, and length than the first and second magnetization fixed layers 11 and 15 and the magnetization free layer 13. The first and second constricted portions 12 and 14 are referred to as first and second transition regions. The first and second transition regions include not only the above-described Co, but also other examples of the thickness change portion (step) of a continuous magnetic material having a plurality of thicknesses, and the magnetic / insulator laminated structure. You may form by the insulator part or the pinhole etc. which are formed in the said insulator part. These can be processed by ordinary electron beam lithography techniques.

磁気抵抗効果素子１０における第１、２の磁化固定層１１、１５と接触する電極を外部に設け、さらに磁化自由層１３の外部にも電極を設ける。まず、第１の磁化固定層１１と磁化自由層１３の外部電極間に、測定用の直流電源１６と計測用のメータ１７を接続して測定用の直流電流（大きさは、０．３×１０−４Ａ（＝０．０３ｍＡ））を流す。次に、磁化固定層１１側と１５側との外部電極間にパルス電流源１８から１×１０−４Ａの電流で１ｎｓのパルス幅の直流電流を供給し、３０ｓ間隔で電流の極性を反転させることを繰り返す。素子入力部で測定したときの電流密度は１０６Ａ／ｃｍ２である。すると、第１の磁化固定層１１側と磁化自由層１３側の外部電極間には図２に見られる電圧信号が観測される。 Electrodes that are in contact with the first and second magnetization fixed layers 11 and 15 in the magnetoresistive effect element 10 are provided outside, and electrodes are also provided outside the magnetization free layer 13. First, a DC power source for measurement 16 and a meter 17 for measurement are connected between the external electrodes of the first magnetization fixed layer 11 and the magnetization free layer 13 to measure a DC current for measurement (the magnitude is 0.3 × 10 −4 A (= 0.03 mA)). Next, a direct current with a pulse width of 1 ns is supplied from the pulse current source 18 at a current of 1 × 10 −4 A between the external electrodes on the magnetization fixed layer 11 side and the 15 side, and the polarity of the current is inverted at intervals of 30 s. Repeat. The current density when measured at the element input section is 10 6 A / cm 2 . 2 is observed between the external electrodes on the first magnetization fixed layer 11 side and the magnetization free layer 13 side.

これは、第１、第２の磁化固定層１１、１５のいずれか一方の磁化の向きを反転させた際、第１、第２の遷移領域１２、１４のいずれか一方に磁壁が導入され、その磁壁が第１、第２の磁化固定層１１、１５間に加えられるパルス電流により移動することで、磁化自由層１３の磁化の方向が変化したと考えられる。別の言い方をすれば、パルス電流幅１ｎｓの時間内に、磁壁が磁化自由層１３を走り切ってしまう。走りきった磁壁が勝手に戻ったりしないよう、３０秒待ってから、測定電流もパルス電流も極性を反転したら、ほぼ同様に、磁壁の走る向きだけは反対に走り切る動作をしていると言うことができる。   This is because, when the magnetization direction of one of the first and second magnetization fixed layers 11 and 15 is reversed, a domain wall is introduced into one of the first and second transition regions 12 and 14. It is considered that the magnetization direction of the magnetization free layer 13 has changed due to the domain wall moving by the pulse current applied between the first and second magnetization fixed layers 11 and 15. In other words, the domain wall runs through the magnetization free layer 13 within the time of the pulse current width of 1 ns. If the polarity of both the measurement current and the pulse current is reversed after waiting 30 seconds so that the domain wall that has ran completely does not return, it is said that the domain wall runs almost in the opposite direction. be able to.

図２における出力信号を、前述のように磁化固定層１１と磁化自由層１３間の磁気抵抗と考え、磁気抵抗率に換算すると約２５０％になる。これは、図２の結果から以下のようにして得られる。図２において得られた電圧の大体の値を見積もると、電圧の大きい部分は約５５０ｍＶ、小さい部分は約１５０ｍＶなので、
（５５０−１５０）／１５０＝４００／１５０＝８／３＝２．６６６６６６
となる。すなわち、約２５０％と言うことになる。なお、図２に示す特性は、第２の磁化固定層１５と磁化自由層１３の外部電極間に、測定用の直流電源１６と計測用のメータ１７を接続して直流電流を流して計測した場合でも同じように得られる。ただし、出力信号の波形は反転する。 The output signal in FIG. 2 is considered to be the magnetic resistance between the magnetization fixed layer 11 and the magnetization free layer 13 as described above, and is approximately 250% when converted to the magnetic resistivity. This is obtained as follows from the results of FIG. When the approximate value of the voltage obtained in FIG. 2 is estimated, the large voltage portion is about 550 mV, and the small portion is about 150 mV.
(550-150) /150=400/150=8/3=2.666666
It becomes. That is, about 250%. The characteristics shown in FIG. 2 were measured by connecting a DC power source 16 for measurement and a meter 17 for measurement between the external electrodes of the second magnetization fixed layer 15 and the magnetization free layer 13 to pass a DC current. Even if you get it the same way. However, the waveform of the output signal is inverted.

同様の測定を、磁化固定層１１と１５の外部電極間に供給する電流を単なる直流電流とした場合は、図２と等価な結果が観測されるには１０９Ａ／ｃｍ２以上の大きさの電流密度の電流を供給する必要がある。 In the same measurement, when the current supplied between the external electrodes of the magnetization fixed layers 11 and 15 is simply a direct current, the magnitude equal to or larger than 10 9 A / cm 2 is observed in order to observe a result equivalent to FIG. It is necessary to supply a current having a current density of.

すなわち、本発明によれば、単なる直流電流による駆動と比べて、３桁小さい電流で動作する固体メモリ素子が得られることになる。   That is, according to the present invention, it is possible to obtain a solid-state memory element that operates with a current that is three orders of magnitude smaller than that of driving with a simple direct current.

表１は、図１に示す磁気抵抗効果素子１０の各部のサイズ、すなわち、磁化固定層１１と１５、狭窄部１２,１４及び磁化自由層１３を種々変更したときの磁気抵抗率を示す表である。   Table 1 is a table showing the size of each part of the magnetoresistive effect element 10 shown in FIG. 1, that is, the magnetoresistance ratio when the magnetization fixed layers 11 and 15, the constriction parts 12 and 14 and the magnetization free layer 13 are variously changed. is there.

Figure 2006270069
表１に示すケースは、第１の磁化固定層１１側と磁化自由層１３側の外部電極間に、測定用の直流電流０．０３ｍＡを流し、磁化固定層１１，１５間に１０−４Ａレベルの電流でｎｓレベルのパルス幅の直流電流を供給し、３０ｓ間隔で電流の極性を反転させることを繰り返して上述のようにして得た磁気抵抗率を示すものである。表１のＮｏ．１のケースは、上述の例である。
Figure 2006270069
 In the case shown in Table 1, a measurement DC current of 0.03 mA is passed between the external electrodes on the first magnetization fixed layer 11 side and the magnetization free layer 13 side, and 10 −4 A is applied between the magnetization fixed layers 11 and 15. The magnetic resistance obtained as described above is shown by repeatedly supplying a direct current with a pulse width of ns level at a level current and reversing the polarity of the current at intervals of 30 seconds. No. in Table 1 Case 1 is the example described above.

表１のＮｏ．１〜Ｎｏ．４の結果から分かるように、パルス電流を１×１０−４Ａ、第１、第２の狭窄部１２，１４の大きさを２０ｎｍ×２０ｎｍ×２０ｎｍとしたとき、パルス電流のパルス幅と磁化自由層１３の長さとの関係は、図３に示すように、比例関係が見られる。そして、図３に示す範囲で得られる磁気抵抗率が２００−２５０％となっていることが分かる。 No. in Table 1 1-No. As can be seen from the result of FIG. 4, when the pulse current is 1 × 10 −4 A and the first and second constriction portions 12 and 14 are 20 nm × 20 nm × 20 nm, the pulse width of the pulse current and the magnetization free The relationship with the length of the layer 13 shows a proportional relationship as shown in FIG. And it turns out that the magnetic resistivity obtained in the range shown in FIG. 3 is 200-250%.

表１のＮｏ．５は、第１、第２の狭窄部１２，１４の大きさを４０ｎｍ×４０ｎｍ×４０ｎｍとし、他の条件をパルスＮｏ．１と同じものとした場合の結果を示す。これから分かるように、第１、第２の狭窄部１２，１４を大きくすると磁気抵抗率が大きく低下する。逆に言えば、大きな磁気抵抗率を得るためには、第１、第２の狭窄部１２，１４の大きさを２０ｎｍ×２０ｎｍ×２０ｎｍ以下とすることが必要であることがわかる。これは、小さければ小さい程、大きな磁気抵抗率を得ることができると言えるが、製造プロセスから限界がある。   No. in Table 1 5 shows that the size of the first and second constrictions 12 and 14 is 40 nm × 40 nm × 40 nm, and other conditions are set to pulse No. 5. The result when it is the same as 1 is shown. As can be seen from this, when the first and second constrictions 12 and 14 are made larger, the magnetic resistivity is greatly lowered. In other words, it can be understood that the size of the first and second constrictions 12 and 14 needs to be 20 nm × 20 nm × 20 nm or less in order to obtain a large magnetic resistivity. It can be said that the smaller this is, the larger the magnetic resistivity can be obtained, but there is a limit from the manufacturing process.

（実施例２）
（固体メモリへの応用）
次に、図１に示した磁気抵抗効果素子１０を用いた固体メモリの例を説明する。図４は、図１に示した磁気抵抗効果素子１０をメモリ素子とし、Ｘ−Ｙマトリクス状に配列した例として縦２列、横２列の場合の固体メモリを構成した例を示す接続図である。図４では、ビットライン３１１１，３１１２と、読み出し用ワードライン３１２１，３１２２、書き込み用ワードライン３１３１，３１３２との交点に図１記載のメモリ素子３００１１，３００１２，３００２１および３００２２が配置されている。ビットライン３１１１，３１１２はそれぞれメモリ素子の第２の磁化固定層１５に接続されている。メモリ素子のそれぞれに対し、読み出し用ワードライン３１２１，３１２２のそれぞれと、書き込み用ワードライン３１３１，３１３２のそれぞれが設けられ、それぞれ磁化自由層１３および第１の磁化固定層１１に接続されている。３１８はビットラインのデコーダ、３１９１は、読み出し用ワードライン３１２１，３１２２のデコーダである。３１９２は書き込み用ワードライン３１３１，３１３２のデコーダである。デコーダ３１８は書き込みあるいは読み出しのアドレス指定に対応して、ビットライン３１１１，３１１２の一つを選択する。デコーダ３１９１は読み出しのアドレス指定に対応して、ワードライン３１２１，３１２２の一つを選択する。デコーダ３１９２は書き込みのアドレス指定に対応して、ワードライン３１３１，３１３２の一つを選択する。また、デコーダ３１９２には書き込みのアドレス指定に対応する書き込みデータも入力される。 (Example 2)
(Application to solid-state memory)
Next, an example of a solid state memory using the magnetoresistive effect element 10 shown in FIG. 1 will be described. FIG. 4 is a connection diagram showing an example in which the magnetoresistive effect element 10 shown in FIG. 1 is a memory element and a solid-state memory in the case of two columns and two columns is arranged as an example of an XY matrix arrangement. is there. In FIG. 4, the memory elements 300 11 , 300 12 , and 300 21 shown in FIG. 1 are crossed at bit lines 311 1 , 311 2 , read word lines 312 1 , 312 2 , and write word lines 313 1 , 313 2 . and 300 22 are disposed. The bit lines 311 1 and 311 2 are each connected to the second magnetization fixed layer 15 of the memory element. A read word line 312 1 , 312 2 and a write word line 313 1 , 313 2 are provided for each of the memory elements, and are connected to the magnetization free layer 13 and the first magnetization fixed layer 11, respectively. Has been. Reference numeral 318 denotes a bit line decoder, and 319 1 denotes a decoder for the read word lines 312 1 and 312 2 . Reference numeral 319 2 denotes a decoder for the write word lines 313 1 and 313 2 . The decoder 318 selects one of the bit lines 311 1 and 311 2 in accordance with the write or read addressing. The decoder 319 1 selects one of the word lines 312 1 and 312 2 corresponding to the read addressing. Decoder 319 2 corresponding to the address of the write, selects one of the word lines 313 1, 313 2. Further, write data to the decoder 319 2 corresponding to the address of the write is also input.

ワードライン３１２１、ワードライン３１２２はゲートであるＭＯＳ−ＦＥＴ３１６１、ＭＯＳ−ＦＥＴ３１６２の開閉により、データライン３１４に選択的に接続される。ワードライン３１３１、ワードライン３１３２はゲートであるＭＯＳ−ＦＥＴ３１７１１およびＭＯＳ−ＦＥＴ３１７１２、ＭＯＳ−ＦＥＴ３１７２１およびＭＯＳ−ＦＥＴ３１７２２のいずれかの開閉により、電源線３１５１および３１５２に選択的に接続される。電源線３１５１、３１５２は、それぞれ、図２の入力パルスを供給する正負の電源線である。デコーダ３１９２は書き込みのアドレス指定に対応する書き込みデータも入力されるので、磁気抵抗効果素子３００１１，３００１２，３００２１および３００２２に書き込むべきデータに応じて、電源線３１５１および３１５２のいずれかがゲートであるＭＯＳ−ＦＥＴ３１７１１およびＭＯＳ−ＦＥＴ３１７１２、ＭＯＳ−ＦＥＴ３１７２１およびＭＯＳ−ＦＥＴ３１７２２のいずれかの開閉により、正あるいは負の電源に接続され、所定の電流が供給される。 The word line 312 1 and the word line 312 2 are selectively connected to the data line 314 by opening / closing the gates of the MOS-FET 316 1 and the MOS-FET 316 2 . The word line 313 1 and the word line 313 2 are selectively connected to the power supply lines 315 1 and 315 2 by opening / closing one of the gates of the MOS-FET 317 11 and the MOS-FET 317 12 , the MOS-FET 317 21, and the MOS-FET 317 22. Connected. The power supply lines 315 1 and 315 2 are positive and negative power supply lines for supplying the input pulse of FIG. Since the decoder 319 2 also receives write data corresponding to the write addressing, depending on the data to be written to the magnetoresistive elements 300 11 , 300 12 , 300 21 and 300 22 , the power supply lines 315 1 and 315 2 Any one of the gates of the MOS-FET 317 11 , the MOS-FET 317 12 , the MOS-FET 317 21, and the MOS-FET 317 22 is connected to a positive or negative power source, and a predetermined current is supplied.

例えば、メモリ素子３００１１にデータを書き込むときは、ビットライン３１１１と、電源線３１５１および３１５２のいずれかに接続されたワードライン３１３１との間に１０６Ａ／ｃｍ２で１ｎｓのパルス幅の電流を供給することにより、メモリ素子３００１１における第１の遷移領域１２あるいは第１の遷移領域１４にある磁壁が供給電流の極性により移動、あるいは保持される。すなわち、磁壁の移動に伴って図１における磁化自由層１３の磁化の方向を変化させることにより書き込みが行われる。このとき、ワードライン３１３１を電源線３１５１および３１５２のいずれに接続するかは、書き込むべきデータにより選択される。一方、読み出しは、例えば、ビットライン３１１１と、データライン３１４と選択的に接続されたワードライン３１２１との間に電圧を印加することにより、図１における磁化固定層１１、磁化自由層１３の磁化の相対向きに依存した抵抗を読み出すことにより行われる。本発明の図１における磁気抵抗効果素子は、磁気抵抗率が２５０％に達するので、読み出しの際ＭＯＳ−ＦＥＴでセル選択を行う必要がない。 For example, when writing data into the memory device 300 11, the bit line 311 1, of 1ns at 10 6 A / cm 2 between the word line 313 1 is connected to one of the power lines 315 1 and 315 2 by supplying a current pulse width, moving the domain wall of the first transition region 12 or the first transition area 14 in the memory device 300 11 have the polarity of the supply current, or is held. That is, writing is performed by changing the magnetization direction of the magnetization free layer 13 in FIG. 1 as the domain wall moves. At this time, connect the word line 313 1 to one of the power lines 315 1 and 315 2 are selected by the data to be written. Meanwhile, reading, for example, the bit line 311 1, by applying a voltage between the data lines 314 and selectively connected to the word line 312 1, the magnetization fixed layer 11 in FIG. 1, the magnetization free layer 13 This is done by reading out the resistance depending on the relative direction of the magnetization of. The magnetoresistive effect element in FIG. 1 of the present invention has a magnetic resistivity of 250%, so that it is not necessary to perform cell selection with a MOS-FET during reading.

図５は、上述の図４に示した固体メモリをシリコン基板上に実装した例を一つのメモリ素子１１０について模式的に示す断面図である。シリコン基板１２０の上に、第１のワードライン１１１（図４のワードライン３１３に対応する）、第１の磁化固定層１１、第１の遷移領域１２、磁化自由層１３、第２のワードライン１１７（図４のワードライン３１２に対応する）、第２の遷移領域１４、第２の磁化固定層１５、ビットライン１１６（図３のビットライン３１１に対応する）を、半導体分野で常用されるリソグラフィー技術により形成する。ビットライン１１６は紙面と平行に形成され、第１のワードライン１１１および第２のワードライン１１７は紙面に垂直方向に形成される。その他の層あるいは領域は層間絶縁膜１１８で埋められる。   FIG. 5 is a cross-sectional view schematically showing one memory element 110 in which the solid-state memory shown in FIG. 4 is mounted on a silicon substrate. On the silicon substrate 120, the first word line 111 (corresponding to the word line 313 in FIG. 4), the first magnetization fixed layer 11, the first transition region 12, the magnetization free layer 13, and the second word line. 117 (corresponding to the word line 312 in FIG. 4), the second transition region 14, the second magnetization fixed layer 15, and the bit line 116 (corresponding to the bit line 311 in FIG. 3) are commonly used in the semiconductor field. It is formed by lithography technology. The bit line 116 is formed parallel to the paper surface, and the first word line 111 and the second word line 117 are formed in a direction perpendicular to the paper surface. Other layers or regions are filled with an interlayer insulating film 118.

図５は１メモリ素子のみを示すが、これがＸ−Ｙマトリクス状にシリコン基板１２０上に形成される。図の例では、ビットライン、ワードラインの配線材料にＣｕを、強磁性材料にはＣｏを用いた。ビットライン１１６、第１のワードライン１１１は、それぞれ、第１、第２の磁化固定層１１，１５に接続されているので、磁化固定層をそのまま用いてもよい。すなわち、第１、第２の磁化固定層１１，１５は、メモリ素子単位で独立している必要は無い。また、第１、第２の磁化固定層１１，１５をＣｏとするときは、これの固有抵抗はそれほど大きくないから、電気回路的にも問題はない。こうすることにより、リソグラフィー、磁化固着のプロセスがより簡便になる。   FIG. 5 shows only one memory element, which is formed on the silicon substrate 120 in an XY matrix. In the example shown in the figure, Cu is used for the wiring material of the bit line and the word line, and Co is used for the ferromagnetic material. Since the bit line 116 and the first word line 111 are connected to the first and second magnetization fixed layers 11 and 15, respectively, the magnetization fixed layer may be used as it is. That is, the first and second magnetization fixed layers 11 and 15 do not need to be independent for each memory element. Further, when the first and second magnetization fixed layers 11 and 15 are made of Co, the specific resistance is not so large, so there is no problem in terms of electric circuit. By doing so, the lithography and magnetization fixation processes become easier.

（実施例３）
（他のタイプの固体メモリ素子への応用）
図６は本発明の磁気抵抗効果素子２０の断面構造を示す図である。磁化固定層となる太さ１００ｎｍφ、長さ１００ｎｍのＣｏ細線２１上に、厚さ１０ｎｍの絶縁体層２６を形成して第１の遷移領域を設ける。続いて厚さ１０ｎｍ磁化自由層２３を形成する。次いで、厚さ１０ｎｍの絶縁体層２７を形成して第２の遷移領域を設ける。さらに太さ１００ｎｍφ、長さ１００ｎｍのＣｏ細線２５による磁化固定層を形成する。各部位の機能は図１と同様である。第１、第２の遷移領域となる絶縁体２６，２７を設ける時点で、Ｃｏ細線２１，２３上にＡｕのナノメーターサイズの微粒子を乗せておく。厚さ１０ｎｍの絶縁体層２６，２７を形成する際には、この微粒子が絶縁体層中にピンホール２８，２９を形成して遷移領域として機能する。ここで、絶縁体層２６，２７は、例えば、Ａｌ２Ｏ３で形成するのがよい。 (Example 3)
(Application to other types of solid-state memory devices)
FIG. 6 is a diagram showing a cross-sectional structure of the magnetoresistive element 20 of the present invention. A first transition region is provided by forming an insulator layer 26 having a thickness of 10 nm on a Co thin wire 21 having a thickness of 100 nmφ and a length of 100 nm serving as a magnetization fixed layer. Subsequently, a 10 nm thick magnetization free layer 23 is formed. Next, an insulator layer 27 having a thickness of 10 nm is formed to provide a second transition region. Further, a magnetization fixed layer is formed by Co thin wires 25 having a thickness of 100 nmφ and a length of 100 nm. The function of each part is the same as in FIG. At the time when the insulators 26 and 27 serving as the first and second transition regions are provided, Au nanometer-sized fine particles are placed on the Co thin wires 21 and 23. When forming the insulator layers 26 and 27 having a thickness of 10 nm, the fine particles form pinholes 28 and 29 in the insulator layer and function as transition regions. Here, the insulator layers 26 and 27 are preferably formed of, for example, Al 2 O 3 .

ピンホールを形成するために、Ｃｏ細線２１，２３上にＡｕのナノメーターサイズの微粒子を乗せる際、一つずつ乗せるということはできないから、例えば、適当な数のＡｕのナノメーターサイズの微粒子を振り撒くということが実際的であり、その結果、Ｃｏ細線２１，２３上に乗るＡｕのナノメーターサイズの微粒子は、統計的に分布した数となる。図６では、これを断面位置で３個、２個とした。もちろん平面として見ればもっと多いかもしれないし、場合によっては、一つだけ、と言うこともありうる。図７は、図６における第１の遷移領域としての絶縁体層２６にピンホール２８が５個形成されている様子を模視的に斜視図の形で示す図である。断面位置の３個のピンホール２８の他に２個のピンホール２８が形成されている状態を示すものとしている。   In order to form pinholes, it is not possible to place Au nanometer-size fine particles on Co thin wires 21 and 23 one by one. For example, an appropriate number of Au nanometer-size fine particles can be loaded. It is practical to sprinkle, and as a result, the number of Au nanometer-sized fine particles on the Co thin wires 21 and 23 is a statistically distributed number. In FIG. 6, the number of cross sections is three and two. Of course, it may be more when viewed as a plane, and in some cases, there may be only one. FIG. 7 is a perspective view schematically showing a state where five pinholes 28 are formed in the insulator layer 26 as the first transition region in FIG. 6. A state in which two pinholes 28 are formed in addition to the three pinholes 28 in the cross-sectional position is shown.

磁気抵抗効果素子２０においても、外部電極を設置し、１０６Ａ／ｃｍ２の電流密度で１ｎｓのパルス幅の直流電流を供給し一定時間間隔で電流の極性を反転させることを繰り返すと、図２と同様の信号出力が得られる。本発明の磁気抵抗効果素子２０は、図２で説明したのと同様の計算によると、磁気抵抗率が３００％に達する。 Also in the magnetoresistive effect element 20, when an external electrode is installed, a direct current having a pulse width of 1 ns is supplied at a current density of 10 6 A / cm 2 and the polarity of the current is reversed at regular time intervals, 2 is obtained. The magnetoresistive effect element 20 of the present invention has a magnetoresistance of 300% according to the same calculation as described in FIG.

（実施例４）
（さらに異なるタイプの固体メモリ素子への応用）
図８、図９は本発明の磁気抵抗効果素子４０の平面構造および対応する模式的な斜視図を示す図である。この実施例では、厚さ１０ｎｍのＣｏの薄層の両端に第１、第２の磁化固定層４１、４５が、中央部に磁化自由層４３が形成され、これらの間に切り込みを設けて、第１、第２の遷移領域４２、４４としている。さらには磁化自由層４３の磁化情報を読み出すためのトンネル磁気接合４６が磁化自由層４３の中央部に配置されている。また、図８から分かるように、トンネル磁気接合４６は、絶縁体トンネルバリア層４７、および磁化固定層４８から構成されている。各部位の機能は図１と同様であるが、トンネル磁気接合４６が機能するためには、磁化固定層４８の磁化の向きは磁化固定層４１、４５のどちらか一方の磁化の向きと同じにする必要がある。 Example 4
(Further application to different types of solid-state memory devices)
8 and 9 are diagrams showing a planar structure of the magnetoresistive effect element 40 of the present invention and a corresponding schematic perspective view. In this embodiment, first and second magnetization fixed layers 41 and 45 are formed at both ends of a Co thin layer having a thickness of 10 nm, a magnetization free layer 43 is formed at the center, and a notch is provided between them. First and second transition regions 42 and 44 are provided. Furthermore, a tunnel magnetic junction 46 for reading the magnetization information of the magnetization free layer 43 is disposed at the center of the magnetization free layer 43. As can be seen from FIG. 8, the tunnel magnetic junction 46 includes an insulator tunnel barrier layer 47 and a magnetization fixed layer 48. The function of each part is the same as in FIG. 1, but in order for the tunnel magnetic junction 46 to function, the magnetization direction of the magnetization fixed layer 48 is the same as the magnetization direction of one of the magnetization fixed layers 41 and 45. There is a need to.

図８の磁化自由層４３の長さを１０ｎｍとした場合、１０６Ａ／ｃｍ２の電流密度で１ｎｓのパルス幅の直流電流を供給し一定時間間隔で電流の極性を反転させることを繰り返すと、図２と同様の信号出力が得られる。 When the length of the magnetization free layer 43 in FIG. 8 is 10 nm, when a DC current having a pulse width of 1 ns is supplied at a current density of 10 6 A / cm 2 and the polarity of the current is reversed at regular time intervals, A signal output similar to that shown in FIG. 2 is obtained.

磁気抵抗効果素子４０はプレーナー構造を有しており、隣接するメモリ素子の磁化固定層を共有することが可能なので、固体メモリへの応用に際し高密度化に有利な構造である。   Since the magnetoresistive effect element 40 has a planar structure and can share the magnetization fixed layer of adjacent memory elements, the magnetoresistive effect element 40 is advantageous in increasing the density in application to a solid-state memory.

（実施例５）
（さらに異なるタイプの固体メモリ素子への応用）
図１０は本発明の磁気抵抗効果素子５０の断面構造を示す図である。まず、シリコン基板１２０上に、数原子層分の高さ、長さ１０ｎｍのステップを形成する。その上にＣｏを蒸着し表面を平坦化することで、結果的にＣｏの厚さが相対的に薄い磁化自由層５３が形成できる。シリコン基板１２０上のステップが磁化自由層５３に対応し、前記シリコン基板上のステップエッジが第１、第２の遷移領域５２、５４となる。磁化固定層５１、５５の一方の磁化は、外部磁場により他方の磁化と反対向きにしておく。さらには磁化自由層５３の磁化情報を読み出すためのトンネル磁気接合４６（絶縁体トンネルバリア層４７、および磁化固定層４８）を配置する。この構成は、図７，８で説明した磁気抵抗効果素子４０の切り込みにより形成した第１、第２の遷移領域４２、４４をステップエッジにより５２、５４により形成したものである。 (Example 5)
(Further application to different types of solid-state memory devices)
FIG. 10 is a diagram showing a cross-sectional structure of the magnetoresistive element 50 of the present invention. First, steps having a height of several atomic layers and a length of 10 nm are formed on the silicon substrate 120. By depositing Co thereon and planarizing the surface, the magnetization free layer 53 having a relatively thin Co thickness can be formed as a result. Steps on the silicon substrate 120 correspond to the magnetization free layer 53, and step edges on the silicon substrate become first and second transition regions 52 and 54. One magnetization of the magnetization fixed layers 51 and 55 is kept opposite to the other magnetization by an external magnetic field. Furthermore, a tunnel magnetic junction 46 (insulator tunnel barrier layer 47 and magnetization fixed layer 48) for reading the magnetization information of the magnetization free layer 53 is disposed. In this configuration, first and second transition regions 42 and 44 formed by cutting the magnetoresistive effect element 40 described with reference to FIGS. 7 and 8 are formed by step edges 52 and 54.

磁気抵抗効果素子５０においても、外部電極を設置し、１０６Ａ／ｃｍ２の電流密度で１ｎｓのパルス幅の直流電流を供給し一定時間間隔で電流の極性を反転させることを繰り返すと、図２と同様の信号出力が得られる。磁気抵抗効果素子５０も、磁気抵抗効果素子４０同様プレーナー構造を有しており、隣接するメモリ素子の磁化固定層を共有することが可能なので、固体メモリへの応用に際し高密度化に有利な構造である。 Also in the magnetoresistive effect element 50, when an external electrode is installed, a direct current with a pulse width of 1 ns is supplied at a current density of 10 6 A / cm 2 and the polarity of the current is reversed at regular time intervals, 2 is obtained. The magnetoresistive effect element 50 also has a planar structure similar to the magnetoresistive effect element 40, and can share the magnetization fixed layer of the adjacent memory element, so that it is advantageous for increasing the density when applied to a solid-state memory. It is.

（実施例６）
（さらに異なるタイプの固体メモリ素子への応用）
図１１は本発明の磁気抵抗効果素子６０の断面構造を示す図である。太さ５０ｎｍ、厚さ１００ｎｍのＣｏ細線６１上に厚さ１０ｎｍのＣｕ６２を蒸着して遷移領域とする。Ｃｏ細線６１は磁化固定層である。続いて厚さ５０ｎｍ磁化自由層６３を形成する。外部磁場により、磁化自由層６３の磁化の向きを磁化固定層６１の磁化と反対方向にしておく。 (Example 6)
(Further application to different types of solid-state memory devices)
FIG. 11 is a diagram showing a cross-sectional structure of the magnetoresistive element 60 of the present invention. A Cu 62 film having a thickness of 10 nm is deposited on a Co wire 61 having a thickness of 50 nm and a thickness of 100 nm to form a transition region. The Co thin wire 61 is a magnetization fixed layer. Subsequently, a 50 nm-thick magnetization free layer 63 is formed. The magnetization direction of the magnetization free layer 63 is set opposite to the magnetization direction of the magnetization fixed layer 61 by an external magnetic field.

磁気抵抗効果素子６０における磁化固定層６１と、磁化自由層６３の外部に電極を設ける。まず、磁化固定層６１から磁化自由層６３への方向に、外部電極間に測定用の電流を流しておく。測定用電流は、１０２Ａ／ｃｍ２の大きさの電流密度で直流である。次に、外部電極間に１０６Ａ／ｃｍ２の大きさの電流密度で１ｎｓのパルス幅の直流電流を供給し、１０ｓ間隔で電流の極性を反転させることを繰り返す。すると、図２と同様の出力信号が観測される。この例でも、同様の測定を外部電極間に供給する電流を単なる直流電流とした場合には、図２と等価な結果が観測されるには１０９Ａ／ｃｍ２以上の大きさの電流密度を供給する必要がある。 Electrodes are provided outside the magnetization fixed layer 61 and the magnetization free layer 63 in the magnetoresistive element 60. First, a measurement current is passed between the external electrodes in the direction from the magnetization fixed layer 61 to the magnetization free layer 63. The measurement current is a direct current with a current density of 10 2 A / cm 2 . Next, a direct current having a pulse width of 1 ns is supplied between the external electrodes at a current density of 10 6 A / cm 2 , and the polarity of the current is inverted at intervals of 10 s. Then, an output signal similar to that in FIG. 2 is observed. Also in this example, when the current supplied between the external electrodes in the same measurement is simply a direct current, a current density of 10 9 A / cm 2 or more is required to observe the result equivalent to FIG. Need to supply.

磁気抵抗効果素子６０は２端子素子であるので、固体メモリへの応用に際し高集積度、高密度化に有利である。   Since the magnetoresistive effect element 60 is a two-terminal element, it is advantageous for high integration and high density when applied to a solid-state memory.

（実施例７）
（他のタイプの固体メモリへの応用）
次に、図１１に示した磁気抵抗効果素子６０を用いた固体メモリの例を説明する。図１２は、図１１に示した磁気抵抗効果素子６０をＸ−Ｙマトリクス状に配列した例として縦２列、横２列の場合の固体メモリを示す図である。図１２では、ビットライン７１１１、ビットライン７１１２と、ワードライン７１２１、ワードライン７１２２との交点に図１１記載の磁気抵抗効果素子７００が配置されている。７１５はビットラインのデコーダ、７１６はワードラインのデコーダである。デコーダ７１５および７１６が書き込みあるいは読み出しのアドレス指定に対応して、ビットラインおよびワードラインの一つが選択され磁気抵抗効果素子７００に電流が供給される。なお、ワードラインはＭＯＳ−ＦＥＴ７１４のゲートの開閉により、データライン７１３に選択的に接続される。 (Example 7)
(Application to other types of solid-state memory)
Next, an example of a solid-state memory using the magnetoresistive effect element 60 shown in FIG. 11 will be described. FIG. 12 is a diagram showing a solid-state memory in the case of two vertical rows and two horizontal rows as an example in which the magnetoresistive effect elements 60 shown in FIG. 11 are arranged in an XY matrix. In FIG. 12, the magnetoresistive effect element 700 shown in FIG. 11 is arranged at the intersection of the bit line 711 1, the bit line 711 2 , the word line 712 1 , and the word line 712 2 . Reference numeral 715 denotes a bit line decoder, and reference numeral 716 denotes a word line decoder. Decoders 715 and 716 select one of a bit line and a word line in response to addressing for writing or reading, and a current is supplied to magnetoresistive element 700. Note that the word line is selectively connected to the data line 713 by opening and closing the gate of the MOS-FET 714.

例えば、ビットライン７１１１と、データライン７１３と選択的に接続されたワードライン７１２１との間に１０６Ａ／ｃｍ２で１ｎｓのパルス幅の電流を供給することにより、図１１における磁化自由層の磁化の向きが反転、あるいは保持される。すなわち、図１０における磁化自由層の磁化の方向を変化させることにより書き込みが行われる。一方、読み出しは、例えば、ビットライン７１１１と、データライン７１３と選択的に接続されたワードライン７１２１との間に電圧を印加することにより、図１１における磁化固定層６１、磁化自由層６３の磁化の相対向きに依存した抵抗を読み出すことにより行われる。 For example, by supplying a current with a pulse width of 1 ns at 10 6 A / cm 2 between the bit line 711 1 and the word line 712 1 selectively connected to the data line 713, the magnetization free in FIG. The magnetization direction of the layer is reversed or maintained. That is, writing is performed by changing the magnetization direction of the magnetization free layer in FIG. On the other hand, for reading, for example, a voltage is applied between the bit line 711 1 and the word line 712 1 selectively connected to the data line 713, whereby the magnetization fixed layer 61 and the magnetization free layer 63 in FIG. This is done by reading out the resistance depending on the relative direction of the magnetization of.

なお、上述の実施例では、図１１の磁気抵抗効果素子６０の磁化自由層の長さを５０ｎｍとした他は全て磁化自由層の長さを１０ｎｍとし、書き込みのパルス電流の幅を１ｎｓ、大きさを１０６Ａ／ｃｍ２とする例としたが、これらの磁化自由層の長さを１μｍとし、書き込みのパルス電流の幅を１００ｎｓとしても、書き込みのパルス電流の大きさを１０６Ａ／ｃｍ２とできる。 In the above-described embodiments, the length of the magnetization free layer of the magnetoresistive effect element 60 of FIG. 11 is 50 nm, except that the length of the magnetization free layer is 10 nm, and the width of the write pulse current is 1 ns. Although an example to 10 6 a / cm 2 and is, as a 1μm length of the magnetization free layer, even 100ns width of the write pulse current, the magnitude of the write pulse current 10 6 a / possible to the cm 2.

（産業上の利用可能性）
本発明によれば、単なる直流電流による駆動と比べて、３桁小さい電流で動作する固体メモリ素子が得られるとともに、固体メモリとしても、リソグラフィー、磁化固着のプロセスがより簡便にできるものとなる。 (Industrial applicability)
According to the present invention, it is possible to obtain a solid-state memory element that operates with a current that is three orders of magnitude smaller than that of a simple direct current drive, and also to simplify the lithography and magnetization fixing processes as a solid-state memory.

本発明の磁気抵抗効果素子１０を説明するための概念図である。It is a conceptual diagram for demonstrating the magnetoresistive effect element 10 of this invention. 図１に示す磁気抵抗効果素子１０の特性を説明する図である。It is a figure explaining the characteristic of the magnetoresistive effect element 10 shown in FIG. 図１に示す磁気抵抗効果素子１０のパルス電流のパルス幅と磁化自由層１３の長さとの関係を示す図である。FIG. 2 is a diagram showing the relationship between the pulse width of the pulse current of the magnetoresistive effect element 10 shown in FIG. 1 and the length of the magnetization free layer 13. 図１に示した磁気抵抗効果素子１０をメモリ素子とし、Ｘ−Ｙマトリクス状に配列した例として縦２列、横２列の場合の固体メモリを構成した例を示す接続図である。FIG. 2 is a connection diagram illustrating an example in which a solid-state memory in the case of two vertical columns and two horizontal columns is configured as an example in which the magnetoresistive effect element 10 illustrated in FIG. 1 is a memory element and arranged in an XY matrix. 図４に示した固体メモリをシリコン基板上に実装した例を一つのメモリ素子１１０について模式的に示す断面図である。FIG. 5 is a cross-sectional view schematically showing an example in which the solid-state memory shown in FIG. 4 is mounted on a silicon substrate for one memory element 110. 本発明の磁気抵抗効果素子２０の断面構造を示す図である。It is a figure which shows the cross-section of the magnetoresistive effect element 20 of this invention. 図６における第１の遷移領域としての絶縁体層２６にピンホール２８が５個形成されている様子を模視的に斜視図の形で示す図である。It is a figure which shows typically a mode that five pinholes 28 are formed in the insulator layer 26 as a 1st transition area | region in FIG. 6 in the form of a perspective view. 本発明の磁気抵抗効果素子４０の模式的な平面構造を示す図である。It is a figure which shows the typical planar structure of the magnetoresistive effect element 40 of this invention. 本発明の磁気抵抗効果素子４０の模式的な斜視図である。It is a typical perspective view of the magnetoresistive effect element 40 of this invention. 本発明の磁気抵抗効果素子５０の断面構造を示す図である。It is a figure which shows the cross-section of the magnetoresistive effect element 50 of this invention. 本発明の磁気抵抗効果素子６０の断面構造を示す図である。It is a figure which shows the cross-section of the magnetoresistive effect element 60 of this invention. 図１１に示した磁気抵抗効果素子６０をＸ−Ｙマトリクス状に配列した例として縦２列、横２列の場合の固体メモリを示す図である。It is a figure which shows the solid-state memory in the case of 2 vertical rows and 2 horizontal rows as an example which arranged the magnetoresistive effect element 60 shown in FIG. 11 in XY matrix form.

符号の説明Explanation of symbols

１０，２０，４０，５０，６０…磁気抵抗効果素子、１１，２１，４１，５１，６１…第１の磁化固定層、１２，２６，４２，５２，６２…第１の遷移領域、１３，２３，４３，５３，６３…磁化自由層、１４，２７，４４，５４…第２の遷移領域、１５，２５，４５，５５…第２の磁化固定層、１６…測定用の直流電源、１７…計測用のメータ、１８…パルス電流源、２８，２９…ピンホール、４６…トンネル磁気接合、４７…絶縁体トンネルバリア層、４８…磁化固定層、１１０，３００，７００…メモリ素子、１１６，３１１１，３１１２，７１１１、，７１１２…ビットライン、１１７，３１２１，３１２２…読み出し用ワードライン、１１１，３１３１，３１３２…書き込み用ワードライン、３１４…データライン、３１５１，３１５２…電源線、３１６１，３１６２，３１７１１，３１７１２，３１７２１１，３１７２２…ＭＯＳ−ＦＥＴ、３１８…ビットラインのデコーダ、３１９１…読み出し用ワードラインのデコーダ、３１９２…書き込み用ワードラインのデコーダ、１１８…層間絶縁膜、７１２１，７１２２…ワードライン、７１３…データライン、７１４…ＭＯＳ−ＦＥＴ、７１５…ビットラインのデコーダ、７１６…ワードラインのデコーダ。 10, 20, 40, 50, 60 ... magnetoresistive effect element, 11, 21, 41, 51, 61 ... first magnetization fixed layer, 12, 26, 42, 52, 62 ... first transition region, 13, 23, 43, 53, 63 ... magnetization free layer, 14, 27, 44, 54 ... second transition region, 15, 25, 45, 55 ... second magnetization fixed layer, 16 ... DC power source for measurement, 17 ... Meter for measurement, 18 ... Pulse current source, 28, 29 ... Pinhole, 46 ... Tunnel magnetic junction, 47 ... Insulator tunnel barrier layer, 48 ... Magnetization fixed layer, 110, 300, 700 ... Memory element, 116, 311 1 , 311 2 , 711 1, 711 2, ..., Bit line, 117, 312 1 , 312 2, read word line, 111, 313 1 , 313 2, write word line, 314, data line, 3 15 1 , 315 2 ... power supply line, 316 1 , 316 2 , 317 11 , 317 12 , 317 211 , 317 22 ... MOS-FET, 318 ... bit line decoder, 319 1 ... read word line decoder, 319 2 ... Decoder for write word line, 118... Interlayer insulating film, 712 1 , 712 2 ... Word line, 713... Data line, 714.

Claims (12)

第１の磁化固定層／磁化自由層／第２の磁化固定層を有する磁気抵抗効果素子にあって、該磁化固定層／磁化自由層あるいは磁化自由層／第２の磁化固定層の少なくとも一方の境界となる磁化固定層と磁化自由層間の遷移領域に磁壁発生を誘導するための機構を備え、これら磁化固定層の磁化の向きを略反平行に設定し、磁化固定層／磁化自由層の遷移領域のいずれか一方に磁壁が存在する構造において、所定のパルス幅の電流を印加することにより、直流電流密度１０６Ａ／ｃｍ２を超えない電流で磁壁が２つの遷移領域の間で移動することにより磁化自由層の磁化を反転させ、相対磁化の向きの変化に伴う磁気抵抗を検出することを特徴とする磁気抵抗効果素子。 A magnetoresistive effect element having a first magnetization fixed layer / magnetization free layer / second magnetization fixed layer, wherein at least one of the magnetization fixed layer / magnetization free layer or the magnetization free layer / second magnetization fixed layer It has a mechanism for inducing domain wall generation in the transition region between the magnetization fixed layer and the magnetization free layer that becomes the boundary, and the magnetization direction of these magnetization fixed layers is set to be approximately antiparallel, and the transition between the magnetization fixed layer and the magnetization free layer In a structure in which a domain wall exists in one of the regions, by applying a current having a predetermined pulse width, the domain wall moves between the two transition regions with a current not exceeding the DC current density of 10 6 A / cm 2. Thus, the magnetoresistive effect element is characterized in that the magnetization of the magnetization free layer is reversed and the magnetoresistance associated with the change in the direction of relative magnetization is detected. 磁化固定層／磁化自由層または磁化自由層／磁化固定層の遷移領域に磁壁発生を誘導するための機構として遷移領域が他の領域より断面積が小さいものとされている請求項１記載の磁気抵抗素子。   2. The magnetism according to claim 1, wherein the transition region has a smaller sectional area than other regions as a mechanism for inducing domain wall generation in the transition region of the magnetization fixed layer / magnetization free layer or the magnetization free layer / magnetization fixed layer. Resistance element. 磁化固定層／磁化自由層が１００×１００×１００ｎｍのオーダの大きさであるとき、遷移領域が２０×２０×２０ｎｍのオーダの大きさである請求項２記載の磁気抵抗素子。   3. The magnetoresistive element according to claim 2, wherein when the magnetization fixed layer / magnetization free layer is of the order of 100 × 100 × 100 nm, the transition region is of the order of 20 × 20 × 20 nm. 磁化固定層／磁化自由層／磁化固定層の構造として構成されるとともに、磁化固定層／磁化自由層または磁化自由層／磁化固定層の遷移領域に磁壁発生を誘導するための機構として前記遷移領域が絶縁材料で構成されるとともに、該絶縁材料内に磁化固定層−磁化自由層または磁化自由層−磁化固定層に連なるピンホールを形成したものである請求項１記載の磁気抵抗効果素子。   The transition region is configured as a structure of a magnetization fixed layer / magnetization free layer / magnetization fixed layer, and a mechanism for inducing domain wall generation in the transition region of the magnetization fixed layer / magnetization free layer or the magnetization free layer / magnetization fixed layer 2. The magnetoresistive effect element according to claim 1, wherein the magnetoresistive effect element is formed of an insulating material, and a pinhole connected to the magnetization fixed layer-magnetization free layer or the magnetization free layer-magnetization fixed layer is formed in the insulation material. 磁化固定層／磁化自由層／磁化固定層の構造が単一の平板状の強磁性体材料で構成され、かつ、磁化自由層上に絶縁体トンネルバリア層と磁化固定層から構成されるトンネル磁気接合を備えるとともに、磁化固定層／磁化自由層の遷移領域に磁壁発生を誘導するための機構として前記単一の平板状の強磁性体材料に切り込みを形成したものである請求項１記載の磁気抵抗効果素子。   Tunnel magnetism in which the structure of the magnetization fixed layer / magnetization free layer / magnetization fixed layer is composed of a single flat ferromagnetic material, and an insulating tunnel barrier layer and a magnetization fixed layer are formed on the magnetization free layer. 2. The magnetism according to claim 1, wherein the magnet is provided with a junction and a notch is formed in the single flat ferromagnetic material as a mechanism for inducing domain wall generation in the transition region of the magnetization fixed layer / magnetization free layer. Resistive effect element. 磁化固定層／磁化自由層／磁化固定層の構造として構成されるとともに、磁化固定層／磁化自由層または磁化自由層／磁化固定層の遷移領域に磁壁発生を誘導するための機構として前記磁化自由層の膜厚が磁化固定層の膜厚より薄いものとされ、かつ、磁化自由層上に絶縁体トンネルバリア層と磁化固定層から構成されるトンネル磁気接合を備える請求項１記載の磁気抵抗効果素子。   As a mechanism for inducing domain wall generation in the transition region of the magnetization fixed layer / magnetization free layer or the magnetization free layer / magnetization fixed layer, the magnetization free layer is configured as a magnetization fixed layer / magnetization free layer / magnetization fixed layer structure. The magnetoresistive effect according to claim 1, wherein the thickness of the layer is smaller than the thickness of the magnetization fixed layer, and a tunnel magnetic junction comprising an insulator tunnel barrier layer and a magnetization fixed layer is provided on the magnetization free layer. element. 前記所定のパルス幅の電流が０．３ｎｓ以上１．６ｎｓ以下の範囲のパルス幅の電流である請求項１記載の磁気抵抗効果素子。   The magnetoresistive element according to claim 1, wherein the current having the predetermined pulse width is a current having a pulse width in a range of 0.3 ns to 1.6 ns. 第１の磁化固定層／磁化自由層／第２の磁化固定層を有し、これら磁化固定層の磁化の向きを略反平行に設定した磁気抵抗効果素子をメモリ素子としてマトリックス状に配置するとともに、前記各メモリ素子の第１の磁化固定層または第２の磁化固定層にビットラインを、前記各メモリ素子の第２の磁化固定層または第１の磁化固定層にワードラインを接続し、前記各メモリ素子の磁化自由層にデータラインを、それぞれ、書き込みアドレスあるいは読み出しアドレスに応じて選択的に接続して、前記第１の磁化固定層−前記第２の磁化固定層間に所定のパルス幅の電流を記憶すべきデータに応じた極性で印加することにより、直流電流密度１０６Ａ／ｃｍ２を超えない電流で前記磁化自由層の磁化を反転させて、前記第１の磁化固定層／磁化自由層または前記磁化自由層／第２の磁化固定層の間の２つの遷移領域の間で磁壁が移動することにより前記各メモリ素子にデータを磁気記憶させ、前記各メモリ素子のデータラインと前記各メモリ素子の第１の磁化固定層または第２の磁化固定層のビットラインとの間で磁気記憶されたデータを読み出すことを特徴とする磁気記録装置。 A magnetoresistive effect element having a first magnetization fixed layer / magnetization free layer / second magnetization fixed layer, in which the magnetization directions of these magnetization fixed layers are set substantially antiparallel, is arranged in a matrix as a memory element. A bit line is connected to the first magnetization fixed layer or the second magnetization fixed layer of each memory element, a word line is connected to the second magnetization fixed layer or the first magnetization fixed layer of each memory element, and A data line is selectively connected to the magnetization free layer of each memory element according to a write address or a read address, respectively, and a predetermined pulse width is set between the first magnetization fixed layer and the second magnetization fixed layer. by applying with polarity corresponding to the data to be stored the current, said by reversing the magnetization of the magnetization free layer in a current not exceeding the DC current density 10 6 a / cm 2, the first magnetization pinned layer / Data is stored in each memory element by moving a domain wall between two transition regions between the magnetization free layer or the magnetization free layer / second magnetization fixed layer, and a data line of each memory element A magnetic recording apparatus for reading data magnetically stored between the first magnetization fixed layer and the second magnetization fixed layer of each memory element. 前記所定のパルス幅の電流が０．３ｎｓ以上１．６ｎｓ以下の範囲のパルス幅の電流である請求項８記載の磁気記録装置。   9. The magnetic recording apparatus according to claim 8, wherein the current having the predetermined pulse width is a current having a pulse width in a range of 0.3 ns to 1.6 ns. 前記第１の磁化固定層−前記第２の磁化固定層間にきわめて短いパルス幅の電流を記憶すべきデータに応じた極性で印加するため、前記各メモリ素子の第２の磁化固定層または第１の磁化固定層に接続されるワードラインは記憶すべきデータに応じて正負の異なった電源線に選択的に接続される請求項８記載の磁気記録装置。   In order to apply a current with a very short pulse width between the first magnetization fixed layer and the second magnetization fixed layer with a polarity corresponding to data to be stored, the second magnetization fixed layer or the first magnetization of each memory element 9. The magnetic recording apparatus according to claim 8, wherein the word line connected to the magnetization fixed layer is selectively connected to different power supply lines depending on data to be stored. 磁化固定層／絶縁体層／磁化自由層を有する磁気抵抗効果素子をメモリ素子としてマトリックス状に配置するとともに、前記各メモリ素子の磁化自由層にビットラインを、前記各メモリ素子の磁化固定層にワードラインを接続し、前記各ワードラインにデータラインを、それぞれ、書き込みアドレスあるいは読み出しアドレスに応じて選択的に接続して、前記磁化固定層−前記磁化自由層間に所定のパルス幅の電流を記憶すべきデータに応じた極性で印加することにより、直流電流密度１０６Ａ／ｃｍ２を超えない電流で前記磁化自由層の磁化を反転させて、前記磁化固定層／磁化自由層間の遷移領域の間で磁壁が移動することにより前記各メモリ素子にデータを磁気記憶させ、前記各メモリ素子のデータラインに接続されたワードラインと前記各メモリ素子の磁化自由層のビットラインとの間で磁気記憶されたデータを読み出すことを特徴とする磁気記録装置。 A magnetoresistive effect element having a magnetization fixed layer / insulator layer / magnetization free layer is arranged in a matrix as a memory element, and a bit line is provided in the magnetization free layer of each memory element, and a magnetization fixed layer of each memory element is provided. A word line is connected, and a data line is selectively connected to each word line according to a write address or a read address, and a current having a predetermined pulse width is stored between the magnetization fixed layer and the magnetization free layer. By applying the polarity in accordance with the data to be obtained, the magnetization of the magnetization free layer is reversed with a current not exceeding a DC current density of 10 6 A / cm 2 , so that the transition region of the magnetization fixed layer / magnetization free layer A word line connected to a data line of each memory element by magnetically storing data in each memory element by moving a domain wall between them The magnetic recording apparatus, characterized in that for reading magnetic data stored between the bit lines of the magnetization free layer of each memory device. 前記所定のパルス幅の電流が０．３ｎｓ以上１．６ｎｓ以下の範囲のパルス幅の電流である請求項１１記載の磁気記録装置。   12. The magnetic recording apparatus according to claim 11, wherein the current having the predetermined pulse width is a current having a pulse width in a range of 0.3 ns to 1.6 ns.
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