JP2006222164A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

Info

Publication number
JP2006222164A
JP2006222164A JP2005032334A JP2005032334A JP2006222164A JP 2006222164 A JP2006222164 A JP 2006222164A JP 2005032334 A JP2005032334 A JP 2005032334A JP 2005032334 A JP2005032334 A JP 2005032334A JP 2006222164 A JP2006222164 A JP 2006222164A
Authority
JP
Japan
Prior art keywords
insulating layer
semiconductor device
semiconductor element
support
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005032334A
Other languages
Japanese (ja)
Inventor
Hajime Iizuka
肇 飯塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2005032334A priority Critical patent/JP2006222164A/en
Publication of JP2006222164A publication Critical patent/JP2006222164A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method which can perform further miniaturization and can do in thinning while a semiconductor element is aimed at a protection, which prevents failure generation in a manufacturing process, and can improve productivity. <P>SOLUTION: The semiconductor device includes a semiconductor element 30, and an insulating layer 23 having one surface 23a in which wiring 24 is formed, and a surface 23b of another side used as its reverse side. The semiconductor element 30 is covered at the activity side and the side face by the insulating layer 23, embedded in the insulating layer 23 so that the activity side is directed toward the one surface of the insulating layer 23, the back surface of the semiconductor element 30 is covered with a protective film 22, and the semiconductor element 30 and the wiring 24 are connected electrically. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

近年、電子機器の小型化により、それに搭載される半導体装置の小型化・薄型化が進んでいる。
このため、図１に示すような、支持体１６１上に搭載された半導体素子１７０が、支持体１６１上に形成された絶縁層１６３内部に埋め込まれ、且つ、絶縁層１６３の表面に、半導体素子１７０と電気的に接続する配線１６４と外部接続端子１６６が形成された半導体装置１５０が提案されている（例えば、特許文献１の図４，５参照）。
図1の半導体装置１５０では、配線１６４を表面に形成する絶縁層１６３に半導体素子１７０を内蔵するため、半導体装置１５０の小型化・薄型化を図れる。 In recent years, the downsizing and thinning of semiconductor devices mounted on electronic devices have been progressing due to downsizing of electronic devices.
Therefore, as shown in FIG. 1, the semiconductor element 170 mounted on the support 161 is embedded inside the insulating layer 163 formed on the support 161, and the semiconductor element 170 is formed on the surface of the insulating layer 163. There has been proposed a semiconductor device 150 in which a wiring 164 and an external connection terminal 166 electrically connected to 170 are formed (see, for example, FIGS. 4 and 5 of Patent Document 1).
In the semiconductor device 150 in FIG. 1, the semiconductor element 170 is incorporated in the insulating layer 163 on which the wiring 164 is formed, so that the semiconductor device 150 can be reduced in size and thickness.

図２は、図1の半導体装置の製造方法を説明する図である。
この製造方法では、最初に、図２（ａ）に示すように、支持体１６１上に接着剤１６２により複数の半導体素子１７０を搭載する。支持体１６１は板状のものであり、厚さ２００〜４００μｍのガラスエポキシ基板等の樹脂板や、銅やアルミニウム等の金属板を用いる。また、半導体素子１７０としては、厚さ２０〜５０μｍのものを用いる。
なお、支持体１６１は、半導体装置の製造工程において、製造中の半導体装置の形状維持や、一つの支持体１６１上に一度に多数の半導体装置を造り上げることによる生産性向上のため、必須のものである。また、製造工程中に反り等が発生しないよう、強度維持のため、ある程度の厚さが必要である。更に、半導体装置１５０において、半導体素子１７０の背面を外部から保護するためにも、支持体１７０は必要とされている。 FIG. 2 is a diagram for explaining a method of manufacturing the semiconductor device of FIG.
In this manufacturing method, first, as shown in FIG. 2A, a plurality of semiconductor elements 170 are mounted on a support 161 with an adhesive 162. The support 161 is plate-shaped, and a resin plate such as a glass epoxy substrate having a thickness of 200 to 400 μm or a metal plate such as copper or aluminum is used. Further, as the semiconductor element 170, one having a thickness of 20 to 50 μm is used.
Note that the support 161 is indispensable in the manufacturing process of a semiconductor device in order to maintain the shape of the semiconductor device being manufactured and to improve productivity by building a large number of semiconductor devices on one support 161 at a time. It is. In addition, a certain amount of thickness is required to maintain strength so that no warpage or the like occurs during the manufacturing process. Further, in the semiconductor device 150, the support 170 is required to protect the back surface of the semiconductor element 170 from the outside.

次いで、図２（ｂ）に示すように、支持体１６１上に厚さ４０〜１００μｍの絶縁層１６３を形成する。この絶縁層１６３は、支持体１６１上の半導体素子１７０を埋め込むように形成し、これにより、絶縁層１６３に半導体素子１７０を内蔵し封止する。絶縁層１６３としては、エポキシ樹脂やポリイミド樹脂等の樹脂を用いる。絶縁層１６３は、これら樹脂を塗布したり、または、これら樹脂のフィルムを貼着して形成する。 Next, as illustrated in FIG. 2B, an insulating layer 163 having a thickness of 40 to 100 μm is formed on the support 161. The insulating layer 163 is formed so as to embed the semiconductor element 170 on the support 161, and thereby the semiconductor element 170 is embedded in the insulating layer 163 and sealed. As the insulating layer 163, a resin such as an epoxy resin or a polyimide resin is used. The insulating layer 163 is formed by applying these resins or attaching films of these resins.

次いで、図２（ｃ）に示すように、絶縁層１６３に開口ＶＨを形成する。具体的には、レーザ加工により、絶縁層１６３に半導体素子１７０の電極１７１を露出する開口ＶＨを形成する。
ついで、図２（ｄ）に示すように、絶縁層１６３上に配線１６４を形成する。セミアディティブ法やサブトラクティブ法等の適宜の方法により、銅からなる配線１６４を形成する。
次いで、図２（ｅ）に示すように、配線１６４を保護するためのソルダレジスト１６５を形成する。ソルダレジスト１６５は、一例として感光性のエポキシアクリル系の樹脂からなり、厚さ ２０〜４０μｍに形成する。 また、露光・現像により、配線１６４のパッド１６７部分が露出する開口を形成する。
次いで、図２（ｆ）に示すように、配線１６４のパッド１６７に、はんだボールを搭載・溶融させ、外部接続端子１６６を形成する。この後、互いに隣接する半導体素子１７０間をダイシングにより切断・分離し、図１のような、個々の半導体装置１５０を得る。
特開２００１−２１７３３７号公報 Next, as illustrated in FIG. 2C, an opening VH is formed in the insulating layer 163. Specifically, an opening VH that exposes the electrode 171 of the semiconductor element 170 is formed in the insulating layer 163 by laser processing.
Next, as shown in FIG. 2D, a wiring 164 is formed on the insulating layer 163. The wiring 164 made of copper is formed by an appropriate method such as a semi-additive method or a subtractive method.
Next, as shown in FIG. 2E, a solder resist 165 for protecting the wiring 164 is formed. The solder resist 165 is made of, for example, a photosensitive epoxy acrylic resin and has a thickness of 20 to 40 μm. Further, an opening exposing the pad 167 portion of the wiring 164 is formed by exposure and development.
Next, as shown in FIG. 2 (f), solder balls are mounted and melted on the pads 167 of the wiring 164 to form external connection terminals 166. Thereafter, the adjacent semiconductor elements 170 are cut and separated by dicing to obtain individual semiconductor devices 150 as shown in FIG.
JP 2001-217337 A

近年の半導体装置は、更なる小型化、特に薄型化が求められており、図1、２の従来の半導体装置においても、更なる薄型化の検討がなされている。しかしながら、従来の半導体装置においては、支持体が存在するため、半導体装置の薄型化に限界があった。
また、支持体の片面側に絶縁層を形成し半導体装置を製造するため、支持体と絶縁層との熱膨張率の差により、製造工程中に反り等の変形が発生し、製品の歩留りが悪化する場合があった。
そこで本発明は、上述の問題点に鑑みなされたものであり、半導体素子の保護を図りつつ、更なる小型化・薄型化を為し得ると共に、製造工程中の不良発生を防止し、生産性の向上を可能とする、半導体装置及びその製造方法を提供することにある。 In recent years, there has been a demand for further miniaturization, in particular, thinning of the semiconductor device, and in the conventional semiconductor device of FIGS. However, in the conventional semiconductor device, since there is a support, there is a limit to the reduction in thickness of the semiconductor device.
In addition, since a semiconductor device is manufactured by forming an insulating layer on one side of the support, deformation such as warpage occurs during the manufacturing process due to the difference in thermal expansion coefficient between the support and the insulating layer, resulting in a product yield. There were cases where it worsened.
Therefore, the present invention has been made in view of the above-mentioned problems, and while further protecting the semiconductor element, it is possible to further reduce the size and thickness, prevent the occurrence of defects during the manufacturing process, and improve productivity. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the semiconductor device that can improve the performance.

本発明は、上記課題を解決するため、次に述べる構成を備える。
請求項１の発明では、配線が形成された一方の面と、その反対面となる他方の面とを有する絶縁層とを備え、前記半導体素子が、能働面と側面とが前記絶縁層に被覆され、且つ該能働面が前記絶縁層の一方の面を向くよう、前記絶縁層に埋め込まれ、前記半導体素子の背面が、保護膜により被覆され、前記半導体素子と前記配線とが電気的に接続されていることを特徴とする半導体装置により、解決できる。
上記発明によれば、絶縁層内に半導体素子を埋め込んだ半導体装置において、半導体装置から支持体を排除し、半導体装置の薄型化を図れる。また、支持体が無くとも、半導体素子背面を保護膜で被覆するため、半導体素子を半導体装置の外部環境から保護できる。 In order to solve the above problems, the present invention has the following configuration.
According to a first aspect of the present invention, the semiconductor device includes an insulating layer having one surface on which wiring is formed and the other surface opposite to the surface, and the semiconductor element has an active surface and side surfaces in the insulating layer. The semiconductor element is embedded in the insulating layer so that the active surface faces one surface of the insulating layer, the back surface of the semiconductor element is covered with a protective film, and the semiconductor element and the wiring are electrically connected This can be solved by a semiconductor device characterized by being connected to the semiconductor device.
According to the above invention, in the semiconductor device in which the semiconductor element is embedded in the insulating layer, the support can be eliminated from the semiconductor device, and the semiconductor device can be thinned. Even without a support, the back surface of the semiconductor element is covered with a protective film, so that the semiconductor element can be protected from the external environment of the semiconductor device.

請求項２の発明では、前記半導体素子の背面と前記絶縁層の他方の面とが同一平面に位置し、前記半導体素子の背面と前記絶縁層の他方の面とが、前記保護膜により一体に被覆されていることを特徴とする請求項１記載の半導体装置により、解決できる。
上記発明によれば、半導体素子側面と絶縁層との界面も保護膜により一体に被覆されるため、半導体素子を半導体装置の外部環境から保護できる。
請求項３の発明では、前記保護膜の露出面と前記絶縁層の他方の面とが同一平面に位置することを特徴とする請求項１記載の半導体装置により、解決できる。
上記発明によれば、絶縁層により、より半導体素子を保護できる。 According to a second aspect of the present invention, the back surface of the semiconductor element and the other surface of the insulating layer are located on the same plane, and the back surface of the semiconductor element and the other surface of the insulating layer are integrated by the protective film. The semiconductor device according to claim 1 can be solved by being covered.
According to the above invention, since the interface between the side surface of the semiconductor element and the insulating layer is also integrally covered with the protective film, the semiconductor element can be protected from the external environment of the semiconductor device.
The invention according to claim 3 can be solved by the semiconductor device according to claim 1, wherein the exposed surface of the protective film and the other surface of the insulating layer are located on the same plane.
According to the above invention, the semiconductor element can be further protected by the insulating layer.

請求項４の発明によれば、前記配線がソルダレジストにより被覆され、該ソルダレジストの開口部分に、前記配線と接続された外部接続端子が形成されていることを特徴とする請求項１乃至３のいずれか１項に記載の半導体装置により、解決できる。。
請求項５の発明によれば、前記半導体素子の能働面に突起電極が設けられており、該突起電極の端面が前記配線と接続されていることを特徴とする請求項１乃至４のいずれか１項に記載の半導体装置により、解決できる。 According to a fourth aspect of the present invention, the wiring is covered with a solder resist, and an external connection terminal connected to the wiring is formed in an opening portion of the solder resist. This can be solved by the semiconductor device described in any one of the above. .
According to a fifth aspect of the present invention, a protruding electrode is provided on the active surface of the semiconductor element, and an end surface of the protruding electrode is connected to the wiring. This can be solved by the semiconductor device described in item 1.

請求項６の発明によれば、前記絶縁層部分に貫通ビアが形成され、該貫通ビアの一端が前記配線に接続され、他端が前記絶縁層の他方の面もしくは前記保護膜に形成された外部接続端子に接続されていることを特徴とする、請求項1乃至５のいずれか１項に記載の半導体装置により、解決できる。
請求項７の発明によれば、請求項１乃至５記載の半導体装置の、前記配線が形成されている側とは反対側となる露出面が第二の保護膜により被覆されていることを特徴とする半導体装置により、解決できる。 According to the invention of claim 6, a through via is formed in the insulating layer portion, one end of the through via is connected to the wiring, and the other end is formed on the other surface of the insulating layer or the protective film. The problem can be solved by the semiconductor device according to claim 1, wherein the semiconductor device is connected to an external connection terminal.
According to a seventh aspect of the present invention, the exposed surface of the semiconductor device according to the first to fifth aspects, which is opposite to the side on which the wiring is formed, is covered with a second protective film. This can be solved by the semiconductor device.

請求項８の発明によれば、支持体上に分離層を形成する工程と、前記分離層上に接着剤層を介して半導体素子を搭載する工程と、 前記半導体素子の能動面と側面とを被覆するように絶縁層を形成する工程と、 前記絶縁層上に、前記半導体素子と電気的に接続する配線を形成する工程と、前記支持体と前記分離層との界面から分離を行い、前記支持体を除去する工程とを有することを特徴とする半導体装置の製造方法により、解決できる。
上記発明によれば、半導体装置から簡単に支持体を除去でき、半導体装置を薄型化できる。 According to the invention of claim 8, a step of forming a separation layer on a support, a step of mounting a semiconductor element on the separation layer via an adhesive layer, and an active surface and a side surface of the semiconductor element Forming an insulating layer so as to cover; forming a wiring electrically connected to the semiconductor element on the insulating layer; separating from an interface between the support and the separation layer; This can be solved by a method for manufacturing a semiconductor device, comprising the step of removing the support.
According to the said invention, a support body can be easily removed from a semiconductor device and a semiconductor device can be reduced in thickness.

請求項９の発明によれば、前記支持体の一方の面とその反対面となる他方の面との両面に分離層を形成する工程と、前記分離層上に接着剤層を介して半導体素子を搭載する工程と、前記半導体素子の能動面と側面とを被覆するように絶縁層を形成する工程と、前記絶縁層上に、前記半導体素子と電気的に接続する配線を形成する工程と、前記支持体の両面と前記分離層との界面から分離を行い、前記支持体を除去する工程とを有することを特徴とする半導体装置の製造方法により、解決できる。 According to invention of Claim 9, the process which forms a separation layer on both surfaces of the one surface of the said support body and the other surface which is the other surface, and a semiconductor element via an adhesive layer on the said separation layer A step of forming an insulating layer so as to cover an active surface and a side surface of the semiconductor element, a step of forming a wiring electrically connected to the semiconductor element on the insulating layer, This can be solved by a method for manufacturing a semiconductor device, comprising the steps of separating from the interface between both surfaces of the support and the separation layer and removing the support.

請求項１０の発明によれば、分離層が形成された一方の面と、その反対面となる他方の面とを有する２つの支持体を用意し、該支持体の他方の面同士を接着し、複合支持体を形成する工程と、前記複合支持体の分離層上に接着剤層を介して半導体素子を搭載する工程と、前記半導体素子の能動面と側面とを被覆するように絶縁層を形成する工程と、前記絶縁層上に、前記半導体素子と電気的に接続する配線を形成する工程と、前記複合支持体を形成する２つの支持体を分離し、各支持体の一方の面と前記分離層との界面から分離を行い、前記支持体を除去する工程とを有することを特徴とする半導体装置の製造方法により、解決できる。 According to the invention of claim 10, two supports having one surface on which the separation layer is formed and the other surface being the opposite surface are prepared, and the other surfaces of the support are bonded to each other. A step of forming a composite support, a step of mounting a semiconductor element via an adhesive layer on a separation layer of the composite support, and an insulating layer so as to cover an active surface and a side surface of the semiconductor element A step of forming, a step of forming a wiring electrically connected to the semiconductor element on the insulating layer, and separating two supports forming the composite support, and one surface of each support This can be solved by a method for manufacturing a semiconductor device, comprising: a step of separating from the interface with the separation layer and removing the support.

請求項１１の発明によれば、前記分離層上に複数の半導体素子が搭載され、前記支持体の除去後に、少なくとも一つの半導体素子が前記絶縁層に内蔵されるよう、前記絶縁層および分離層の分割を行うことを特徴とする請求項８乃至１０いずれか１項に記載の半導体装置の製造方法により、解決できる。
請求項１２の発明によれば、前記支持体の除去後に、前記分離層の除去工程を有することを特徴とする請求項８乃至１１いずれか１項に記載の半導体装置の製造方法により、解決できる。 According to the invention of claim 11, a plurality of semiconductor elements are mounted on the isolation layer, and the insulating layer and the isolation layer are arranged such that at least one semiconductor element is incorporated in the insulating layer after the support is removed. The method can be solved by the method for manufacturing a semiconductor device according to any one of claims 8 to 10.
According to a twelfth aspect of the present invention, it is possible to solve the problem by the method for manufacturing a semiconductor device according to any one of the eighth to eleventh aspects, further comprising a step of removing the separation layer after the support is removed. .

請求項１３の発明によれば、前記分離層上全面に，前記接着剤層を形成することを特徴とする請求項８乃至１２のいずれか１項に記載の半導体装置の製造方法により、解決できる。
請求項１４の発明によれば、前記分離層上の半導体素子を搭載するエリアに前記接着剤層を形成し、もしくは半導体素子に接着剤層を形成して、該接着剤層を介して半導体素子を搭載することを特徴とする請求項８乃至１２のいずれか１項に記載の半導体装置の製造方法により、解決できる。 According to the invention of claim 13, the adhesive layer is formed on the entire surface of the separation layer, which can be solved by the method for manufacturing a semiconductor device according to any one of claims 8 to 12. .
According to the invention of claim 14, the adhesive layer is formed in an area where the semiconductor element is mounted on the separation layer, or the adhesive layer is formed on the semiconductor element, and the semiconductor element is interposed through the adhesive layer. This can be solved by the method for manufacturing a semiconductor device according to any one of claims 8 to 12.

請求項１５の発明によれば、前記半導体素子の能動面に突起電極が設けられており、前記絶縁層の表面を研磨して、前記突起電極の端面を前記絶縁層の一方の面に露出する工程と、前記絶縁層の一方の表面に、前記突起電極と接続する配線を形成する工程とを有することを特徴とする請求項８乃至１４のいずれか１項に記載の半導体装置の製造方法により、解決できる。
請求項１６の発明によれば、前記接着剤層もしくは前記絶縁層の露出している部位に外部接続端子を形成する工程と、前記絶縁層に、一端が前記配線に接続され、他端が前記外部接続端子に接続される貫通ビアを形成する工程を有すること特徴とする請求項８乃至１５いずれか１項に記載の半導体装置の製造方法により、解決できる。 According to the invention of claim 15, a protruding electrode is provided on the active surface of the semiconductor element, and the surface of the insulating layer is polished to expose the end surface of the protruding electrode on one surface of the insulating layer. 15. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of forming a wiring connected to the protruding electrode on one surface of the insulating layer. ,can be solved.
According to the invention of claim 16, a step of forming an external connection terminal in the exposed portion of the adhesive layer or the insulating layer, one end of the insulating layer is connected to the wiring, and the other end is the The problem can be solved by the method for manufacturing a semiconductor device according to claim 8, further comprising a step of forming a through via connected to an external connection terminal.

請求項１７の発明によれば、前記支持体が、シリコン基板またはガラス基板からなることを特徴とする請求項８乃至１６のいずれか１項に半導体装置の製造方法により、解決できる。
請求項１８の発明によれば、前記分離層が、金属層からなることを特徴とする請求項８乃至１７のいずれか１項に半導体装置の製造方法により、解決できる。
請求項１９の発明によれば、前記金属層が、クロムまたは銅からなることを特徴とする請求項１８記載の半導体装置の製造方法により、解決できる。 According to the invention of claim 17, the support is made of a silicon substrate or a glass substrate, which can be solved by the method for manufacturing a semiconductor device according to any one of claims 8 to 16.
According to the invention of claim 18, the separation layer is made of a metal layer, which can be solved by the method for manufacturing a semiconductor device according to any one of claims 8 to 17.
According to a nineteenth aspect of the present invention, the metal layer is made of chromium or copper, which can be solved by the semiconductor device manufacturing method according to the eighteenth aspect.

本発明によれば、薄型化できると共に、生産性を向上した半導体装置及びその製造方法を提供できる。 According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing the same that can be thinned and have improved productivity.

次に、本発明の実施の形態に関し、添付の図面を参照して以下に説明する。
（第1の実施形態）
図３は、本発明に関する第1の実施形態の半導体装置を示す断面図であり、図４は、その部分拡大図である。
この半導体装置１０では、半導体素子３０が絶縁層２３に埋め込まれ、且つ、絶縁層２３の一方の面２３ａに、半導体素子３０の電極３１と電気的に接続する配線２４が形成されている。 なお、この例では半導体素子３０を埋め込んでいるが、本発明は、チップキャパシタ、抵抗、インダクタ、ディスクリート半導体等、各種電子部品の埋め込みに適用できる。 Next, embodiments of the present invention will be described below with reference to the accompanying drawings.
(First embodiment)
FIG. 3 is a cross-sectional view showing the semiconductor device according to the first embodiment of the present invention, and FIG. 4 is a partially enlarged view thereof.
In the semiconductor device 10, the semiconductor element 30 is embedded in the insulating layer 23, and a wiring 24 that is electrically connected to the electrode 31 of the semiconductor element 30 is formed on one surface 23 a of the insulating layer 23. In this example, the semiconductor element 30 is embedded, but the present invention can be applied to embedding various electronic components such as a chip capacitor, a resistor, an inductor, and a discrete semiconductor.

絶縁層２３は、エポキシ樹脂やポリイミド樹脂等の電気的絶縁性を有する樹脂材からなり、厚さ４０〜１００μｍに形成される。一例として、厚さ８０μｍに形成する。 この絶縁層２３は、半導体装置１０の基材として機能し、また、半導体素子３０を封止する封止層として機能する。絶縁層２３は、配線２４が形成される一方の面２３ａと、その反対面となる他方の面２３ｂを有する。
半導体素子３０は、電子回路や電極３１が形成された能動面３０ａが絶縁層２３の一方の面２３ａ方向を向くよう、能働面３０ａと側面３０ｃの全周囲が絶縁層２３に被覆され、背面３０ｂが絶縁層２３の他方の面２３ｂ表面と略同一平面となるよう絶縁層２３に埋め込まれている。 The insulating layer 23 is made of an electrically insulating resin material such as an epoxy resin or a polyimide resin, and is formed to a thickness of 40 to 100 μm. As an example, it is formed to a thickness of 80 μm. The insulating layer 23 functions as a base material of the semiconductor device 10 and also functions as a sealing layer that seals the semiconductor element 30. The insulating layer 23 has one surface 23a where the wiring 24 is formed and the other surface 23b which is the opposite surface.
The semiconductor element 30 is covered with the insulating layer 23 around the active surface 30a and the side surface 30c so that the active surface 30a on which the electronic circuit or the electrode 31 is formed faces the one surface 23a of the insulating layer 23. 30 b is embedded in the insulating layer 23 so as to be substantially flush with the surface of the other surface 23 b of the insulating layer 23.

この半導体素子３０としては、厚さ１０〜５０μｍのものを使用し、一例として、厚さ５０μｍのものを使用する。電極３１は、銅等のめっきにより、直径５０〜３００μｍ、高さ１０〜３０μｍの柱状に突出させて形成する。 一例として、直径２００μｍ、高さ２０μｍに形成する。この電極３１の頂部である端面３１ａは、絶縁層２３の一方の面２３ａ表面と略同一平面となるよう位置し、配線２４と電気的に接続されている。具体的には、絶縁層２３表面を研磨して電極３１の端面３１ａと絶縁層２３の一方の面２３ａが略同一平面となるよう形成する。 As this semiconductor element 30, one having a thickness of 10 to 50 μm is used, and as an example, one having a thickness of 50 μm is used. The electrode 31 is formed by projecting into a columnar shape having a diameter of 50 to 300 μm and a height of 10 to 30 μm by plating with copper or the like. As an example, it is formed with a diameter of 200 μm and a height of 20 μm. The end surface 31 a that is the top of the electrode 31 is positioned so as to be substantially flush with the surface of one surface 23 a of the insulating layer 23, and is electrically connected to the wiring 24. Specifically, the surface of the insulating layer 23 is polished so that the end surface 31a of the electrode 31 and one surface 23a of the insulating layer 23 are substantially in the same plane.

更に詳細に説明すると、この半導体素子３０としては、図４（ａ）に示す部分拡大図のように、能動面３０ａに形成されたアルミニウム等からなる接続パッド３２に、電極３１が形成されたものを使用する。または、図４（ｂ）に示すように、能動面３０ａを被覆するパッシベーション膜３３上にエポキシ樹脂やポリイミド樹脂からなる絶縁層３４が形成され、絶縁層３４上に接続パッド３２と電気的に接続する再配線３５が形成され、この再配線３５上に電極３１が形成されたものを使用する。あるいは、図４（ｃ）に示すように、能動面３０ａを被覆するパッシベーション膜３３上に接続パッド３２と電気的に接続する再配線３５が形成され、この再配線３５上に電極３１が形成されたものを使用する。 More specifically, as the semiconductor element 30, as shown in the partial enlarged view of FIG. 4A, an electrode 31 is formed on a connection pad 32 made of aluminum or the like formed on the active surface 30a. Is used. Alternatively, as shown in FIG. 4B, an insulating layer 34 made of epoxy resin or polyimide resin is formed on the passivation film 33 covering the active surface 30a, and is electrically connected to the connection pad 32 on the insulating layer 34. A rewiring 35 is formed, and an electrode 31 is formed on the rewiring 35. Alternatively, as shown in FIG. 4C, a rewiring 35 electrically connected to the connection pad 32 is formed on the passivation film 33 covering the active surface 30a, and the electrode 31 is formed on the rewiring 35. Use the same thing.

絶縁層２３の一方の面２３ａに形成された配線２４は、半導体素子３０の側面３０ｃ周囲に位置する絶縁層２３の一方の面２３ａ上に延出して形成されている。 この配線２４は銅等からなり、アディティブ法やセミアディティブ法により、配線幅２０μｍ〜３０μｍに形成されている。一例として、Ｌ／Ｓ＝２０／２０μｍに形成する。配線２４の外部接続部としてのパッド２４ａには、はんだバンプ２６との濡れ性向上のため、ニッケルめっきと金めっきがこの順に施される（図示せず）。 The wiring 24 formed on the one surface 23 a of the insulating layer 23 is formed to extend on the one surface 23 a of the insulating layer 23 located around the side surface 30 c of the semiconductor element 30. The wiring 24 is made of copper or the like, and is formed with a wiring width of 20 μm to 30 μm by an additive method or a semi-additive method. As an example, L / S = 20/20 μm. The pads 24a as external connection portions of the wiring 24 are subjected to nickel plating and gold plating in this order for improving wettability with the solder bumps 26 (not shown).

なお、この配線２４は、半導体素子３０直上に位置する絶縁層２３の一方の面２３ａ上に設けても良い。 つまり、配線２４は半導体素子３０上方に位置する絶縁層２３の一方の面２３の全ての位置に形成可能である。 半導体素子３０周囲や直上の絶縁層２３の一方の面２３ａ上に配線２４を引き回すと、パッド２４ａを格子状に設けることができ、外部接続端子としてのはんだバンプ２６を高密度に多数設けることができる。 よって、半導体装置１０の多端子化と小型化及び外部接続端子位置の標準化に好適に対応できる。 The wiring 24 may be provided on one surface 23 a of the insulating layer 23 located immediately above the semiconductor element 30. That is, the wiring 24 can be formed at all positions on the one surface 23 of the insulating layer 23 located above the semiconductor element 30. When the wiring 24 is routed around the semiconductor element 30 or on one surface 23a of the insulating layer 23 directly above, the pads 24a can be provided in a lattice shape, and a large number of solder bumps 26 as external connection terminals can be provided at high density. it can. Therefore, it is possible to suitably cope with the multi-terminal and miniaturization of the semiconductor device 10 and the standardization of the external connection terminal position.

絶縁層２３の一方の面２３ａと配線２４は、ソルダレジスト２５により被覆されている。ソルダレジスト２５は感光性のエポキシアクリル系の樹脂からなり、厚さ２０〜４０μｍに形成する。 一例として、厚さ３０μｍに形成する。 また、直径２５０μｍの開口部２５ａが形成されており、配線２４のパッド２４ａを露出している。 パッド２４ａには、外部接続端子としてのはんだバンプ２６が接合されている。 One surface 23 a of the insulating layer 23 and the wiring 24 are covered with a solder resist 25. The solder resist 25 is made of a photosensitive epoxy acrylic resin and has a thickness of 20 to 40 μm. As an example, it is formed to a thickness of 30 μm. An opening 25a having a diameter of 250 μm is formed, and the pad 24a of the wiring 24 is exposed. Solder bumps 26 as external connection terminals are joined to the pads 24a.

絶縁層２３の他方の面２３ｂには半導体素子３０の背面３０ｂが露出しており、背面３０ｂは絶縁層２３の他方の面２３ｂ表面と略同一平面となるよう位置している。 絶縁層２３の他方の面２３ｂと半導体素子３０の背面３０ｂは、保護膜（第一の保護膜）としての接着剤２２により一体に被覆されている。接着剤２２は、例えば、エポキシ系樹脂やポリイミド系樹脂からなり、厚さ４０〜１００μｍに形成される。一例として、厚さ７０μｍに形成される。 接着剤２２（保護膜）が、絶縁層２３の他方の面２３ｂと半導体素子３０の背面３０ｂとを一体に被覆すると、半導体素子３０の側面３０ｃと絶縁層２３との界面を外部から保護でき、界面からの水分等の半導体装置１０内部への浸入を防げ、半導体装置１０の不具合発生を防止できる。 The back surface 30b of the semiconductor element 30 is exposed on the other surface 23b of the insulating layer 23, and the back surface 30b is positioned so as to be substantially flush with the surface of the other surface 23b of the insulating layer 23. The other surface 23b of the insulating layer 23 and the back surface 30b of the semiconductor element 30 are integrally covered with an adhesive 22 as a protective film (first protective film). The adhesive 22 is made of, for example, an epoxy resin or a polyimide resin, and is formed to a thickness of 40 to 100 μm. As an example, it is formed to a thickness of 70 μm. When the adhesive 22 (protective film) integrally covers the other surface 23b of the insulating layer 23 and the back surface 30b of the semiconductor element 30, the interface between the side surface 30c of the semiconductor element 30 and the insulating layer 23 can be protected from the outside. Intrusion of moisture or the like from the interface into the semiconductor device 10 can be prevented, and occurrence of defects in the semiconductor device 10 can be prevented.

以上説明したように、従来の半導体装置では、厚さ２００〜４００μｍの支持体を用いていたが、本発明の半導体装置１０は、支持体を排除することができる。よって、従来の半導体装置にと比較し、大幅な薄型化を達成できる。 更に、絶縁層２３の一方の面２３ａ側に研磨を施すため、より半導体装置１０の薄型化を達成できる。
また、半導体装置１０から支持体を排除すると、絶縁層２３の他方の面２３ｂから半導体素子３０の背面３０ｂが露出することになるが、本実施形態の半導体装置では、半導体素子３０の背面３０ｂが保護膜（接着剤２２）により被覆されている。 よって、半導体素子３０の半導体装置１０外部への露出を防止でき、支持板を排除しても半導体装置１０の信頼性を維持できる。 As described above, the conventional semiconductor device uses the support having a thickness of 200 to 400 μm, but the semiconductor device 10 of the present invention can exclude the support. Therefore, a significant reduction in thickness can be achieved as compared with a conventional semiconductor device. Furthermore, since the one surface 23a side of the insulating layer 23 is polished, the semiconductor device 10 can be made thinner.
When the support is removed from the semiconductor device 10, the back surface 30b of the semiconductor element 30 is exposed from the other surface 23b of the insulating layer 23. However, in the semiconductor device of this embodiment, the back surface 30b of the semiconductor element 30 is It is covered with a protective film (adhesive 22). Therefore, exposure of the semiconductor element 30 to the outside of the semiconductor device 10 can be prevented, and the reliability of the semiconductor device 10 can be maintained even if the support plate is eliminated.

（第1の実施形態の製造方法）
次に、図５〜図８を参照し、図３の第1の実施形態における半導体装置１０の製造方法を説明する。図５〜図８は、第1の実施形態に関する半導体装置１０の製造工程を示した断面図である。
始めに、図５（ａ）に示すように支持体４０を用意する。支持体４０はシリコン基板（シリコンウェハ）からなり、厚さ７００〜８００μｍ程度である。一例として、厚さ７００μｍのものを使用する。支持体４０の一方の面４０ａは、後述する金属層２１との剥離を容易にするため、鏡面研磨を施しておくと好適である。 (Manufacturing method of the first embodiment)
Next, a method for manufacturing the semiconductor device 10 according to the first embodiment of FIG. 3 will be described with reference to FIGS. 5 to 8 are cross-sectional views illustrating manufacturing steps of the semiconductor device 10 according to the first embodiment.
First, a support body 40 is prepared as shown in FIG. The support 40 is made of a silicon substrate (silicon wafer) and has a thickness of about 700 to 800 μm. As an example, one having a thickness of 700 μm is used. One surface 40a of the support 40 is preferably mirror-polished in order to facilitate separation from the metal layer 21 described later.

この支持体４０の一方の面４０ａに、分離層としての金属層２１を形成する。 金属層２１には、シリコンとの密着性の低いクロムや銅を用い、スパッタや蒸着により、３００〜５０００Åの厚さに形成する。 一例として、スパッタにより５００Åの厚さに形成する。 なお、金属層２１の強度確保のため、スパッタによる膜を形成後、さらにクロムや銅のめっきを施し、金属層２１の厚さを１〜２μｍとしても良い。めっきを施す場合、一例として金属層２１全体の厚さを、 １μｍとする。 A metal layer 21 as a separation layer is formed on one surface 40 a of the support 40. The metal layer 21 is formed with a thickness of 300 to 5000 mm by sputtering or vapor deposition using chromium or copper having low adhesion to silicon. As an example, it is formed to a thickness of 500 mm by sputtering. In addition, in order to ensure the strength of the metal layer 21, after forming a film by sputtering, chromium or copper may be further plated to make the metal layer 21 have a thickness of 1 to 2 μm. When plating is performed, the thickness of the entire metal layer 21 is set to 1 μm as an example.

なお、支持体４０としては、シリコン基板の替わりに、ガラス基板（ガラスウェハ）を使用しても良い。ガラス基板を使用する場合も、金属層２１としては、シリコン基板の場合と同様に、クロムや銅を用いる。金属層２１の形成方法もシリコン基板の場合と同様である。
次いで、図５（ｂ）に示すように、金属層２１上に接着剤２２を層状に形成する。接着剤２２としてはエポキシ系樹脂やポリイミド系樹脂を用い、これら樹脂を塗布したり、これら樹脂のフィルムを貼着して形成する。 Note that a glass substrate (glass wafer) may be used as the support 40 instead of the silicon substrate. Even when a glass substrate is used, chromium or copper is used as the metal layer 21 as in the case of the silicon substrate. The method for forming the metal layer 21 is the same as that for the silicon substrate.
Next, as shown in FIG. 5B, an adhesive 22 is formed on the metal layer 21 in layers. As the adhesive 22, an epoxy resin or a polyimide resin is used, and these resins are applied or a film of these resins is attached.

なお、接着剤２２としては、絶縁層２３に使用する樹脂と同じものを使用しても良い。接着剤２２と絶縁層２３とに同じ樹脂を用いる場合、相互の密着性が向上し好適である。例えば、絶縁層２３に熱硬化性のエポキシ樹脂やポリイミド樹脂を使用する場合、半硬化状態（Ｂステージ）のこれら樹脂を接着剤２２として使用できる。半硬化状態の樹脂は接着性を有するため、接着剤２２として使用可能である。 As the adhesive 22, the same resin as that used for the insulating layer 23 may be used. When the same resin is used for the adhesive 22 and the insulating layer 23, the mutual adhesiveness is improved, which is preferable. For example, when a thermosetting epoxy resin or polyimide resin is used for the insulating layer 23, these resins in a semi-cured state (B stage) can be used as the adhesive 22. Since the semi-cured resin has adhesiveness, it can be used as the adhesive 22.

次いで、図５（ｃ）に示すように、接着剤２２上に半導体素子３０を搭載し、加熱により接着剤２２を硬化して固定する。この半導体素子３０としては、図４に示した電極３１を有する構造のものを用いる。
次いで、図５（ｄ）に示すように、接着剤２２上面及び半導体素子３０を被覆するよう、絶縁層２３を形成する。絶縁層２３としては、エポキシ樹脂やポリイミド樹脂を用い、これら樹脂を塗布したり、これら樹脂のフィルムを貼着して形成する。絶縁層２３は、少なくとも半導体素子２３の能働面３０ａが被覆される厚さに形成すれば良いが、好適には、電極３１を含め、半導体素子３０全体が絶縁層２３内に埋設されるように形成する。 Next, as shown in FIG. 5C, the semiconductor element 30 is mounted on the adhesive 22, and the adhesive 22 is cured and fixed by heating. As the semiconductor element 30, a structure having the electrode 31 shown in FIG. 4 is used.
Next, as illustrated in FIG. 5D, the insulating layer 23 is formed so as to cover the upper surface of the adhesive 22 and the semiconductor element 30. As the insulating layer 23, an epoxy resin or a polyimide resin is used, and these resins are applied or a film of these resins is attached. The insulating layer 23 may be formed to a thickness that covers at least the active surface 30 a of the semiconductor element 23, but preferably, the entire semiconductor element 30 including the electrode 31 is embedded in the insulating layer 23. To form.

この際、絶縁層２３に、支持体４０の側面４０ｃ、金属層２１の側面（端面）２１ｃ、接着剤２２の側面（端面）２２ｃを被覆する被覆部２３ｃを設けると好適である。元々、支持体４０と金属層２１には、相互の密着性が低いものを用いる。また、支持体４０と金属層２１との剥離は、相互の積層界面の周縁部分から発生する。 よって、製造工程中に何らかの外力が支持体４０の側面４０ｃ等に加わると、意図せぬ時点で支持体４０と金属層２１との剥離が生じる場合がある。
この為、少なくとも支持体４０の側面４０ｃと金属層２１の側面２１ｃとを絶縁層２３の被覆部２３ｃで被覆・保護すると、不意の剥離を防止でき好適である。また、被覆部２３ｃの存在による、支持体４０と金属層２１との密着性向上によっても不意の剥離を防止できる。 被覆部２３ｃは、支持体４０の側面４０ｃに廻りこむよう樹脂を塗布または樹脂フィルムを貼着することにより、絶縁層２３形成時に同時に形成できる。なお、被覆部２３ｃの形成は必須ではない。被覆部２３ｃを形成しなくとも、本実施形態の製造方法は実施可能である。 At this time, it is preferable to provide the insulating layer 23 with a covering portion 23c that covers the side surface 40c of the support 40, the side surface (end surface) 21c of the metal layer 21, and the side surface (end surface) 22c of the adhesive 22. Originally, the support 40 and the metal layer 21 have low mutual adhesion. Further, the peeling between the support 40 and the metal layer 21 occurs from the peripheral portion of the mutual lamination interface. Therefore, if some external force is applied to the side surface 40c of the support 40 during the manufacturing process, the support 40 and the metal layer 21 may be peeled off at an unintended time.
For this reason, if at least the side surface 40c of the support 40 and the side surface 21c of the metal layer 21 are covered and protected by the covering portion 23c of the insulating layer 23, it is preferable to prevent unexpected peeling. In addition, unexpected peeling can be prevented by improving the adhesion between the support 40 and the metal layer 21 due to the presence of the covering portion 23c. The covering portion 23c can be formed simultaneously with the formation of the insulating layer 23 by applying a resin or attaching a resin film so as to go around the side surface 40c of the support 40. In addition, formation of the coating | coated part 23c is not essential. Even if the covering portion 23c is not formed, the manufacturing method of the present embodiment can be performed.

次いで、図６（ａ）に示すように、絶縁層２３の表面を研磨して、絶縁層２３の一方の面２３ａの表面に、半導体素子３０の電極３１の端面３１ａを露出させる。具体的には、絶縁層２３の一方の面２３ａと電極３１の端面３１ａが略同一平面となるよう形成する。 一例として、研磨により、絶縁層２３の厚さは、７０μｍとなる。このように、本実施形態では絶縁層２３に研磨を施し、絶縁層２３を薄型化するため、より半導体装置１０の小型化を図れる。なお、研磨の際は、電極端子３１の端面３１ａが絶縁層２３と共に削られても良い。 Next, as shown in FIG. 6A, the surface of the insulating layer 23 is polished so that the end surface 31 a of the electrode 31 of the semiconductor element 30 is exposed on the surface of one surface 23 a of the insulating layer 23. Specifically, the one surface 23a of the insulating layer 23 and the end surface 31a of the electrode 31 are formed to be substantially in the same plane. As an example, the thickness of the insulating layer 23 becomes 70 μm by polishing. Thus, in this embodiment, since the insulating layer 23 is polished and the insulating layer 23 is thinned, the semiconductor device 10 can be further reduced in size. When polishing, the end surface 31 a of the electrode terminal 31 may be shaved together with the insulating layer 23.

次いで、図６（ｂ）に示すように、絶縁層２３の一方の面２３ａ表面に、半導体素子３０の電極３１の端面３１ａに接続するよう、配線２４を形成する。 配線２４は、銅からなり、アディティブ法やセミアディティブ法等、各種方法により、配線幅２０〜３０μｍに形成する。一例として、２０μｍに形成する。
なお、この配線２４は、半導体素子３０内蔵部周囲や直上の絶縁層２３の一方の面２３ａ上に、自由に引き回すことができる。 よって、任意の場所にパッド２４ａを位置させることができる。 これにより、例えば、パッド２４ａを格子状に設けることができ、外部接続端子としてのはんだバンプ２６を高密度に多数設けることができる。よって、半導体装置１０の多端子化と小型化及び外部接続端子位置の標準化に好適に対応できる。 Next, as shown in FIG. 6B, a wiring 24 is formed on the surface of one surface 23 a of the insulating layer 23 so as to be connected to the end surface 31 a of the electrode 31 of the semiconductor element 30. The wiring 24 is made of copper and is formed to have a wiring width of 20 to 30 μm by various methods such as an additive method and a semi-additive method. As an example, it is formed to 20 μm.
The wiring 24 can be freely routed around the built-in portion of the semiconductor element 30 or on one surface 23a of the insulating layer 23 immediately above. Therefore, the pad 24a can be positioned at an arbitrary place. Thereby, for example, the pads 24a can be provided in a lattice shape, and a large number of solder bumps 26 as external connection terminals can be provided at high density. Therefore, it is possible to suitably cope with the multi-terminal and miniaturization of the semiconductor device 10 and the standardization of the external connection terminal position.

次いで、図６（ｃ）に示すように、絶縁層２３の一方の面２３ａ上にソルダレジスト２５を形成する。 ソルダレジスト２５は、絶縁層２３の一方の面２３ａと配線２４を被覆するよう形成する。 ソルダレジスト２５は、例えば、感光性のエポキシアクリル系の樹脂からなり、厚さ２０〜４０μｍに形成する。 一例として、厚さ３０μｍに形成する。 また、直径２５０μｍ程度の開口部２５ａを形成し配線２４のパッド２４ａを露出する。 なお、開口部２５ａ形成後、配線２４のパッド２４ａに、はんだバンプ２６との濡れ性向上のため、ニッケルめっきと金めっきをこの順に施し、ニッケル層と金層を形成する（図示せず）。これにより、半導体装置１０の中間体１１が得られる。 Next, as shown in FIG. 6C, a solder resist 25 is formed on one surface 23 a of the insulating layer 23. The solder resist 25 is formed so as to cover the one surface 23 a of the insulating layer 23 and the wiring 24. The solder resist 25 is made of, for example, a photosensitive epoxy acrylic resin and is formed to a thickness of 20 to 40 μm. As an example, it is formed to a thickness of 30 μm. Further, an opening 25a having a diameter of about 250 μm is formed to expose the pad 24a of the wiring 24. After the opening 25a is formed, nickel plating and gold plating are performed in this order on the pad 24a of the wiring 24 in order to improve the wettability with the solder bump 26, thereby forming a nickel layer and a gold layer (not shown). Thereby, the intermediate body 11 of the semiconductor device 10 is obtained.

次いで、図７（ａ）に示すように、絶縁層２３の被覆部２３ｃを除去する。 具体的には、破線で示す分離線Ｃ−Ｃで、中間体１１の周縁部１１ａ（支持体４０、金属層２１、接着剤２２、絶縁層２３、ソルダレジスト２５の周縁部）を切断し、被覆部２３ｃを除去する。 これにより、図７（ｂ）に示すように、支持体４０、金属層２１、接着剤２２、絶縁層２３、ソルダレジスト２５に、外部に露出する新たな側面４０ｃ´、２１ｃ´２２ｃ´、２３ｃ´、２５ｃ´が形成される。 Next, as shown in FIG. 7A, the covering portion 23c of the insulating layer 23 is removed. Specifically, the peripheral portion 11a of the intermediate body 11 (the support portion 40, the metal layer 21, the adhesive 22, the insulating layer 23, and the peripheral portion of the solder resist 25) is cut along the separation line CC indicated by a broken line, The covering portion 23c is removed. As a result, as shown in FIG. 7B, new side surfaces 40c ', 21c'22c', 23c exposed to the outside on the support 40, the metal layer 21, the adhesive 22, the insulating layer 23, and the solder resist 25. ', 25c' are formed.

被覆部２３ｃの除去は、少なくとも被覆部２３ｃのみ何らかの方法で除去すれば良い。 例えば、支持体４０の側面４０ｃ等と被覆部２３ｃの界面で中間体１１の切断を行い被覆部２３ｃのみ除去しても良いし、中間体１１に研磨を施し被覆部２３ｃを削り取り、支持体４０の側面４０ｃ等を露出しても良い。
なお、被覆部２３ｃを形成しない場合、中間体１１の形状は最初から図７（ｂ）となるため、図７（ａ）の除去工程を省略できる。 The covering portion 23c may be removed by some method only at least the covering portion 23c. For example, the intermediate body 11 may be cut at the interface between the side surface 40c and the like of the support 40 and the covering portion 23c to remove only the covering portion 23c, or the intermediate body 11 may be polished to scrape the covering portion 23c. The side surface 40c and the like may be exposed.
When the covering portion 23c is not formed, the shape of the intermediate body 11 is as shown in FIG. 7B from the beginning, so that the removal step of FIG. 7A can be omitted.

次いで、図７（ｃ）に示すように、中間体１１から支持体４０を除去する。具体的には、図中矢印で示す方向に、支持体４０の側面４０ｃ´に物理的な外力を加えることにより、分離層である金属層２１と支持体４０の界面から支持体４０を剥離し、分離・除去する。 支持体４０と金属層２１の材料には密着性の低い組み合わせを用いるため、ごく小さな力により簡単に剥離が行える。この際、カッター等を金属層２１と支持体４０の界面に差し込むと、剥離のきっかけができ、より容易に剥離が行える。支持体４０の除去を容易に行えることにより、本実施形態の半導体装置１０は薄型化が可能となる。 Next, as shown in FIG. 7C, the support body 40 is removed from the intermediate body 11. Specifically, by applying a physical external force to the side surface 40c ′ of the support body 40 in the direction indicated by the arrow in the figure, the support body 40 is peeled off from the interface between the metal layer 21 and the support body 40 as a separation layer. Separate and remove. Since a combination of low adhesion is used for the material of the support 40 and the metal layer 21, peeling can be easily performed with a very small force. At this time, if a cutter or the like is inserted into the interface between the metal layer 21 and the support 40, peeling can be triggered and peeling can be performed more easily. Since the support 40 can be easily removed, the semiconductor device 10 of the present embodiment can be thinned.

次いで、図８（ａ）に示すように、中間体１１から金属層２１を除去する。例えば、金属層２１が銅からなる場合、塩化第二鉄水溶液でエッチングを行う。これにより、接着剤２２が外部に露出する。外部に露出した接着剤２２は保護膜として機能し、半導体素子３０を保護する。
ついで、図８（ｂ）に示すように、配線２４のパッド２４ａに外部接続端子としてのはんだバンプ２６を形成する。 具体的には、直径３００μｍのはんだボールをパッド２４ａに搭載しリフローすることにより形成する。あるいは、はんだペーストをパッド２４ａに塗布し、リフローすることにより形成する。 この例の場合、外部接続端子としてはんだバンプを形成することにより、得られる半導体装置１０は、ＢＧＡ型（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）となる。なお、金属層２１のエッチングによる除去の際に、はんだバンプ２６に溶解等の支障が生じない場合、はんだバンプ２６の形成は、図６（ｃ）または図７（ｂ）の段階で行っても良い。 Next, as shown in FIG. 8A, the metal layer 21 is removed from the intermediate body 11. For example, when the metal layer 21 is made of copper, etching is performed with a ferric chloride aqueous solution. As a result, the adhesive 22 is exposed to the outside. The adhesive 22 exposed to the outside functions as a protective film and protects the semiconductor element 30.
Next, as shown in FIG. 8B, solder bumps 26 as external connection terminals are formed on the pads 24 a of the wiring 24. Specifically, a solder ball having a diameter of 300 μm is mounted on the pad 24a and reflowed. Alternatively, the solder paste is applied to the pad 24a and reflowed. In the case of this example, by forming solder bumps as external connection terminals, the obtained semiconductor device 10 becomes a BGA type (Ball Grid Array). In the case where removal of the metal layer 21 by etching does not cause any trouble such as dissolution in the solder bumps 26, the formation of the solder bumps 26 may be performed at the stage of FIG. 6C or FIG. 7B. good.

この例では、ＢＧＡ型の半導体装置を形成するが、はんだボールの替わりにパッド２４ａにピンを接合して、ＰＧＡ型（Ｐｉｎ Ｇｒｉｄ Ａｒｒａｙ）の半導体装置としても良いし、パッド２４ａ自体を外部接続端子として、ＬＧＡ型（Ｌａｎｄ Ｇｒｉｄ Ａｒｒａｙ）の半導体装置としても良い。
最後に、図８（ｃ）に示すように中間体１１を個々の半導体装置の領域毎に分離し、図３に示す半導体装置１０を得る。 具体的には、ダイサーにより破線で示す分離線Ｃ−Ｃで、接着剤２２、絶縁層２３、ソルダレジスト２５を切断し、個々の半導体装置１０を得る。 In this example, a BGA type semiconductor device is formed, but a PGA type (Pin Grid Array) semiconductor device may be formed by bonding a pin to the pad 24a instead of a solder ball, or the pad 24a itself may be an external connection terminal. As an example, a semiconductor device of an LGA type (Land Grid Array) may be used.
Finally, as shown in FIG. 8C, the intermediate body 11 is separated for each region of the individual semiconductor device to obtain the semiconductor device 10 shown in FIG. Specifically, the adhesive 22, the insulating layer 23, and the solder resist 25 are cut along a separation line CC indicated by a broken line with a dicer to obtain individual semiconductor devices 10.

（第２の実施形態）
図９は、本発明に関する第２の実施形態の半導体装置５０を示す断面図である。図中、先に説明した部分には同一の参照符号を付し、説明を省略する。
この例では、半導体装置５０に、金属層２１を設けた形態を示す。半導体装置５０に金属層２１を設けることにより、半導体装置５０の放熱性が向上する。また、金属層２１は第二の保護膜としての機能も有する。第一の保護膜としての接着剤２２に加え金属層２１を有するので、より好適に半導体素子３０を保護できる。 (Second Embodiment)
FIG. 9 is a cross-sectional view showing a semiconductor device 50 according to the second embodiment of the present invention. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.
In this example, the semiconductor device 50 is provided with a metal layer 21. By providing the metal layer 21 in the semiconductor device 50, the heat dissipation of the semiconductor device 50 is improved. The metal layer 21 also has a function as a second protective film. Since the metal layer 21 is provided in addition to the adhesive 22 as the first protective film, the semiconductor element 30 can be more suitably protected.

（第２の実施形態の製造方法）
次に、図１０を参照し、図９の第２の実施形態における半導体装置５０の製造方法を説明する。図１０は、第２の実施形態に関する半導体装置５０の製造工程を示した断面図である。図中、先に説明した部分には同一の参照符号を付し、説明を省略する。
始めに、図１０（ａ）に示すように、第１の実施形態における製造方法の図５（ａ）から図６（ｃ）と同様の工程を施し、次いで、はんだボールを搭載しリフローを行い、配線２４のパッド２４aにはんだバンプ２６を形成する。この例では、金属層２１を除去しないので、金属層２１のエッチング液により、はんだバンプ２６が溶解する虞が無い。よって、支持体４０の除去前にはんだバンプ２６の形成を行うと好適である。 (Manufacturing method of the second embodiment)
Next, a method for manufacturing the semiconductor device 50 in the second embodiment shown in FIG. 9 will be described with reference to FIG. FIG. 10 is a cross-sectional view illustrating a manufacturing process of the semiconductor device 50 according to the second embodiment. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.
First, as shown in FIG. 10A, the same steps as those in FIGS. 5A to 6C of the manufacturing method in the first embodiment are performed, and then solder balls are mounted and reflow is performed. The solder bumps 26 are formed on the pads 24 a of the wiring 24. In this example, since the metal layer 21 is not removed, there is no possibility that the solder bump 26 is dissolved by the etching solution of the metal layer 21. Therefore, it is preferable to form the solder bumps 26 before the support 40 is removed.

次いで、図１０（ｂ）に示すように、第１の実施形態の製造方法における図７（a）以降と同様の工程を行う（ただし、図８（ａ）の金属層除去工程と、図８（ｂ）のはんだバンプ搭載工程を除く）。 そして、個々の半導体装置の領域毎に分離を行い、図９に示す半導体装置５０を得る。 具体的には、ダイサーにより破線で示す分離線Ｃ−Ｃで、金属層２１、接着剤２２、絶縁層２３、ソルダレジスト２５を切断し、個々の半導体装置５０を得る。
なお、本実施形態の半導体装置５０は、単に第１の実施形態の製造方法における図８（ａ）の金属層２１除去工程を除くだけでも得ることができる。 Next, as shown in FIG. 10B, the same steps as those in FIG. 7A and subsequent steps in the manufacturing method of the first embodiment are performed (however, the metal layer removing step in FIG. 8A and FIG. 8). (Excluding the solder bump mounting step of (b)). And it isolate | separates for every area | region of each semiconductor device, and obtains the semiconductor device 50 shown in FIG. Specifically, the metal layer 21, the adhesive 22, the insulating layer 23, and the solder resist 25 are cut along a separation line CC indicated by a broken line by a dicer to obtain individual semiconductor devices 50.
The semiconductor device 50 of this embodiment can be obtained simply by removing the metal layer 21 removal step of FIG. 8A in the manufacturing method of the first embodiment.

（第３の実施形態）
図１１（ａ）、（ｂ）は、本発明に関する第３の実施形態の半導体装置６０、６０ｂを示す断面図である。図中、先に説明した部分には同一の参照符号を付し、説明を省略する。
図１１（ａ）の例では、半導体装置６０において、絶縁層２３の他方の面２３ｂが外部に露出し、半導体素子３０の背面３０ｂが保護膜としての接着剤２２で被覆されている。 半導体素子３０の封止性を向上するため、半導体素子３０周囲をなるべく絶縁層２３で被覆したい場合、この実施形態をとる。また、半導体素子３０は、背面３０ｂに搭載（ダイボンディング）のための接着剤２２が設けられた状態で供給される場合がある。 この場合も半導体装置６０のような実施形態をとる。
なお、図１１（ａ）の半導体装置６０の更なる封止性の向上や放熱性の向上を図る場合、図１１（ｂ）の半導体装置６０ｂのように、絶縁層２３の他方の面２３ｂと接着剤２２を金属層２１が被覆する形態をとっても良い。 (Third embodiment)
11A and 11B are cross-sectional views showing semiconductor devices 60 and 60b according to a third embodiment of the present invention. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.
In the example of FIG. 11A, in the semiconductor device 60, the other surface 23b of the insulating layer 23 is exposed to the outside, and the back surface 30b of the semiconductor element 30 is covered with an adhesive 22 as a protective film. In order to improve the sealing performance of the semiconductor element 30, this embodiment is used when it is desired to cover the periphery of the semiconductor element 30 with the insulating layer 23 as much as possible. Further, the semiconductor element 30 may be supplied in a state where an adhesive 22 for mounting (die bonding) is provided on the back surface 30b. Also in this case, an embodiment like the semiconductor device 60 is taken.
Note that when further improving the sealing performance and heat dissipation of the semiconductor device 60 of FIG. 11A, the other surface 23b of the insulating layer 23 and the semiconductor device 60b of FIG. A form in which the metal layer 21 covers the adhesive 22 may be employed.

（第３の実施形態の製造方法）
次に、図１２を参照し、図１１の第３の実施形態における半導体装置６０の製造方法を説明する。図１２は、第３の実施形態に関する半導体装置６０の製造工程を示した断面図である。図中、先に説明した部分には同一の参照符号を付し、説明を省略する。
始めに、図１２（ａ）に示すように、金属層２１のみを設けた支持体４０を用意する。
次いで、図１２（ｂ）に示すように、背面３０ｂに接着剤２２を設けた半導体素子３０を搭載する。または、金属層２１上の半導体素子３０の搭載部にのみ接着剤２２を供給し、半導体素子３０を搭載する。以降の工程は、第１の実施形態の製造方法と同様に行うことにより、図１１（ａ）の半導体装置６０を得る。なお、金属層２１の除去工程を省き、絶縁層２３の他方の面２３ｂと接着剤２２を金属層２１が被覆する形態とした場合、図１１（ｂ）の半導体装置６０ｂとなる。 (Manufacturing method of the third embodiment)
Next, a method for manufacturing the semiconductor device 60 in the third embodiment shown in FIG. 11 will be described with reference to FIG. FIG. 12 is a cross-sectional view illustrating a manufacturing process of the semiconductor device 60 according to the third embodiment. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.
First, as shown in FIG. 12A, a support 40 provided with only the metal layer 21 is prepared.
Next, as shown in FIG. 12B, the semiconductor element 30 provided with the adhesive 22 on the back surface 30b is mounted. Alternatively, the adhesive 22 is supplied only to the mounting portion of the semiconductor element 30 on the metal layer 21 to mount the semiconductor element 30. Subsequent steps are performed in the same manner as in the manufacturing method of the first embodiment, thereby obtaining the semiconductor device 60 of FIG. If the metal layer 21 is removed and the metal layer 21 covers the other surface 23b of the insulating layer 23 and the adhesive 22, the semiconductor device 60b shown in FIG. 11B is obtained.

（第４の実施形態）
図１３は、本発明に関する第４の実施形態の半導体装置７０を示す断面図である。図中、先に説明した部分には同一の参照符号を付し、説明を省略する。
この例では、半導体素子３０の電極３１と配線２４とが、ビア２４ｂを介して接続される半導体装置７０を示す。この場合、絶縁層２３の研磨工程を省けるため、製造方法が簡略化される。 (Fourth embodiment)
FIG. 13 is a sectional view showing a semiconductor device 70 according to the fourth embodiment of the present invention. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.
In this example, a semiconductor device 70 in which the electrode 31 of the semiconductor element 30 and the wiring 24 are connected via the via 24b is shown. In this case, since the polishing process of the insulating layer 23 can be omitted, the manufacturing method is simplified.

（第４の実施形態の製造方法）
次に、図１４を参照し、図１４の第４の実施形態における半導体装置７０の製造方法を説明する。図１４は、第４の実施形態に関する半導体装置７０の製造工程を示した断面図である。図中、先に説明した部分には同一の参照符号を付し、説明を省略する。
始めに、図１４（ａ）に示すように、第１の実施形態の製造方法における図５（ａ）から図５（ｄ）と同様の工程を施し、次いで、絶縁層２３にビア穴２３ｄを形成する。ビア穴２３ｄは、例えば、ＣＯ2レーザ等によるレーザ加工により形成する。または、絶縁層２３に感光性樹脂を用い、フォトリソ工程により、ビア穴２３ｄを形成する。
次いで、図１４（ｂ）に示すように、ビア２４ｂと配線２４を形成する。ビア２４ｂと配線２４は、ビア穴２３ｄ内にめっきが充填されるよう、アディティブ法やセミアディティブ法で形成する。その後は、第１の実施形態の製造方法における図６（ｃ）以降と同様の工程を行い、図１３の半導体装置７０を得る。 (Manufacturing method of the fourth embodiment)
Next, a method for manufacturing the semiconductor device 70 according to the fourth embodiment shown in FIG. 14 will be described with reference to FIG. FIG. 14 is a cross-sectional view illustrating a manufacturing process of the semiconductor device 70 according to the fourth embodiment. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.
First, as shown in FIG. 14A, the same steps as in FIGS. 5A to 5D in the manufacturing method of the first embodiment are performed, and then a via hole 23d is formed in the insulating layer 23. Form. The via hole 23d is formed by, for example, laser processing using a CO 2 laser or the like. Alternatively, a photosensitive resin is used for the insulating layer 23, and the via hole 23d is formed by a photolithography process.
Next, as shown in FIG. 14B, vias 24b and wirings 24 are formed. The via 24b and the wiring 24 are formed by an additive method or a semi-additive method so that plating is filled in the via hole 23d. Thereafter, the same steps as those in FIG. 6C and subsequent steps in the manufacturing method of the first embodiment are performed to obtain the semiconductor device 70 of FIG.

（第５の実施形態）
図１５は、本発明に関する第５の実施形態の半導体装置８０を示す断面図である。図中、先に説明した部分には同一の参照符号を付し、説明を省略する。
この例では、絶縁層２３上に次層の絶縁層８３を積層し、次層の配線８４を形成している。つまり、絶縁層２３，８３と配線２４，８４を多層に形成した半導体装置８０を示す。この場合、多層化により配線の引き回しが容易になる。 (Fifth embodiment)
FIG. 15 is a sectional view showing a semiconductor device 80 according to the fifth embodiment of the present invention. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.
In this example, a next-layer insulating layer 83 is stacked on the insulating layer 23 to form a next-layer wiring 84. That is, the semiconductor device 80 in which the insulating layers 23 and 83 and the wirings 24 and 84 are formed in multiple layers is shown. In this case, the wiring can be easily routed by multilayering.

（第５の実施形態の製造方法）
次に、図１６を参照し、図１５の第５の実施形態における半導体装置８０の製造方法を説明する。図１６は、第５の実施形態に関する半導体装置８０の製造工程を示した断面図である。図中、先に説明した部分には同一の参照符号を付し、説明を省略する。
始めに、図１６（ａ）に示すように、第１の実施形態の製造方法における図５（ａ）から図６（ｂ）と同様の工程を施す。 次いで、絶縁層２３と配線２４上に絶縁層８３を形成し、絶縁層８３にビア穴８３ｄを形成する。ビア穴８３ｄは、例えば、ＣＯ2レーザ等によるレーザ加工により形成する。または、絶縁層８３に感光性樹脂を用い、フォトリソ工程により、ビア穴８３ｄを形成する。この際、ビア穴８３ｄ底部に配線２４のパッド２４ａが露出するよう形成する。 (Manufacturing method of 5th Embodiment)
Next, with reference to FIG. 16, a method for manufacturing the semiconductor device 80 in the fifth embodiment of FIG. 15 will be described. FIG. 16 is a cross-sectional view illustrating a manufacturing process of the semiconductor device 80 according to the fifth embodiment. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.
First, as shown in FIG. 16A, the same steps as those in FIGS. 5A to 6B in the manufacturing method of the first embodiment are performed. Next, an insulating layer 83 is formed on the insulating layer 23 and the wiring 24, and a via hole 83 d is formed in the insulating layer 83. The via hole 83d is formed by laser processing using, for example, a CO 2 laser. Alternatively, a photosensitive resin is used for the insulating layer 83, and the via hole 83d is formed by a photolithography process. At this time, the pad 24a of the wiring 24 is formed so as to be exposed at the bottom of the via hole 83d.

次いで、図１６（ｂ）に示すように、ビア８４ｂと配線８４を形成する。ビア８４ｂと配線８４は、ビア穴８３ｄ内にめっきが充填されるよう、アディティブ法やセミアディティブ法で形成する。その後は、第１の実施形態の製造方法における図６（ｃ）以降と同様の工程を行い、図１５の半導体装置８０を得る。
なお、この例では、第１の実施形態の絶縁層２３と配線２４を形成し、その上に絶縁層８３、配線８４を形成したが、第４の実施形態の絶縁層２３とビア２４ｂを有する配線２４を形成し、その上に絶縁層８３、配線８４を形成することも可能である。 Next, as shown in FIG. 16B, a via 84b and a wiring 84 are formed. The via 84b and the wiring 84 are formed by an additive method or a semi-additive method so that the via hole 83d is filled with plating. Thereafter, the same steps as those in FIG. 6C and subsequent steps in the manufacturing method of the first embodiment are performed to obtain the semiconductor device 80 of FIG.
In this example, the insulating layer 23 and the wiring 24 of the first embodiment are formed, and the insulating layer 83 and the wiring 84 are formed thereon. However, the insulating layer 23 and the via 24b of the fourth embodiment are provided. It is also possible to form the wiring 24 and form the insulating layer 83 and the wiring 84 thereon.

（第６の実施形態）
図１７は、本発明に関する第６の実施形態の半導体装置９０を示す断面図である。図中、先に説明した部分には同一の参照符号を付し、説明を省略する。
この例では、図１１（ａ）に示した半導体装置において、絶縁層２３に貫通ビア２４ｄを設ける。 この貫通ビア２４ｄは、一端が配線２４に接続され、他端が、絶縁層２３の他方の面２３ｂに露出するパッド２４ｃに接続される。この貫通ビア２４ｄの存在により、半導体装置９０は、絶縁層２３の一方の面２３ａと他方の面２３ｂとで電気的な接続が取れる。つまり、半導体装置９０の表裏面間の電気的接続が取れる。
なお、図１３に示す半導体装置においても、接着剤層（保護膜）にパッド２４ｃ（図示せず）を形成して、貫通ビア２４ｄ（図示せず）の一端を配線２４に、他端をパッド２４ｃに接続してもよい。 (Sixth embodiment)
FIG. 17 is a sectional view showing a semiconductor device 90 according to the sixth embodiment of the present invention. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.
In this example, a through via 24d is provided in the insulating layer 23 in the semiconductor device shown in FIG. One end of the through via 24 d is connected to the wiring 24, and the other end is connected to the pad 24 c exposed on the other surface 23 b of the insulating layer 23. Due to the presence of the through via 24d, the semiconductor device 90 can be electrically connected between the one surface 23a of the insulating layer 23 and the other surface 23b. That is, electrical connection between the front and back surfaces of the semiconductor device 90 can be established.
In the semiconductor device shown in FIG. 13 as well, a pad 24c (not shown) is formed in the adhesive layer (protective film), one end of the through via 24d (not shown) is used as the wiring 24, and the other end is used as the pad. You may connect to 24c.

図１８は、図１７の半導体装置９０を積層した実装例を示す。半導体装置９０は、上記の構造により、多数の半導体装置９０ａ，９０ｂ，９０ｃを積層したスタック型の半導体装置１００として使用できる。 この半導体装置１００では、下層の半導体装置９０ａのパッド２４ｃに、上層の半導体装置９０ｂのはんだバンプ２６を接続し電気的接続を行う。また、実装基板９１上のパッド９２に最下層の半導体装置９０ａのはんだバンプ２６を接続し実装を行う。 このように、半導体装置９０によれば、スタック型の半導体装置１００を可能とするため実装密度を向上できる。 FIG. 18 shows a mounting example in which the semiconductor devices 90 of FIG. 17 are stacked. The semiconductor device 90 can be used as a stacked semiconductor device 100 in which a large number of semiconductor devices 90a, 90b, and 90c are stacked due to the above structure. In this semiconductor device 100, the solder bumps 26 of the upper semiconductor device 90b are connected to the pads 24c of the lower semiconductor device 90a for electrical connection. Further, the solder bumps 26 of the lowermost semiconductor device 90a are connected to the pads 92 on the mounting substrate 91 for mounting. As described above, according to the semiconductor device 90, the stack type semiconductor device 100 is made possible, so that the mounting density can be improved.

（第６の実施形態の製造方法）
次に、図１９、図２０を参照し、図１７の第６の実施形態における半導体装置９０の製造方法を説明する。図１９、図２０は、第６の実施形態に関する半導体装置９０の製造工程を示した断面図である。図中、先に説明した部分には同一の参照符号を付し、説明を省略する。
始めに、図１９（ａ）に示すように、第１の実施形態の製造方法における図５（ａ）に示した、金属層２１を形成した支持体４０を用意し、金属層２１上にパッド２４ｃを形成する。パッド２４ｃは、金属層２１のエッチングによる除去の際に、エッチング液により溶解しないものを使用する。例えば、金めっきとニッケルめっきをこの順に施し、金層とニッケル層（図示せず）からなるパッド２４ｃを形成する。 (Manufacturing method of 6th Embodiment)
Next, with reference to FIGS. 19 and 20, a method for manufacturing the semiconductor device 90 in the sixth embodiment of FIG. 17 will be described. 19 and 20 are cross-sectional views illustrating the manufacturing steps of the semiconductor device 90 according to the sixth embodiment. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.
First, as shown in FIG. 19A, the support 40 having the metal layer 21 formed thereon as shown in FIG. 5A in the manufacturing method of the first embodiment is prepared, and a pad is formed on the metal layer 21. 24c is formed. As the pad 24c, a pad that is not dissolved by the etching solution when the metal layer 21 is removed by etching is used. For example, gold plating and nickel plating are performed in this order to form a pad 24c composed of a gold layer and a nickel layer (not shown).

次いで、図２０（ｂ）に示すように、半導体素子３０を搭載する。この例の場合、半導体素子３０の搭載部のみに接着剤２２を設けるか、背面３０ｂに接着剤２２が設けられた半導体素子３０を搭載する。
次いで、図２０（ｃ）に示すように、絶縁層２３を形成し、絶縁層２３に研磨を施し、半導体素子３０の電極３１の端面３１ａを絶縁層２３の一方の面２３ａに露出させる。 Next, as shown in FIG. 20B, the semiconductor element 30 is mounted. In the case of this example, the adhesive 22 is provided only on the mounting portion of the semiconductor element 30, or the semiconductor element 30 provided with the adhesive 22 on the back surface 30b is mounted.
Next, as shown in FIG. 20C, the insulating layer 23 is formed, the insulating layer 23 is polished, and the end surface 31 a of the electrode 31 of the semiconductor element 30 is exposed to one surface 23 a of the insulating layer 23.

次いで、図２０（ａ）に示すように、絶縁層２３に貫通ビア穴２３ｅを形成する。貫通ビア穴２３ｅは、例えば、ＣＯ2レーザ等によるレーザ加工により形成する。または、絶縁層２３に感光性樹脂を用い、フォトリソ工程により、貫通ビア穴２３ｅを形成する。
次いで、図２０（ｂ）に示すように、貫通ビア２４ｄと配線２４を形成する。貫通ビア２４ｄと配線２４は、貫通ビア穴２３ｅ内にめっきが充填されるよう、アディティブ法やセミアディティブ法で形成する。その後は、第１の実施形態の製造方法における図６（ｃ）以降と同様の工程を行い、図１７の半導体装置９０を得る。 Next, as shown in FIG. 20A, a through via hole 23 e is formed in the insulating layer 23. The through via hole 23e is formed by, for example, laser processing using a CO 2 laser or the like. Alternatively, a photosensitive resin is used for the insulating layer 23, and the through via hole 23e is formed by a photolithography process.
Next, as shown in FIG. 20B, through vias 24d and wirings 24 are formed. The through via 24d and the wiring 24 are formed by an additive method or a semi-additive method so that plating is filled in the through via hole 23e. Thereafter, the same steps as those in FIG. 6C and subsequent steps in the manufacturing method of the first embodiment are performed to obtain the semiconductor device 90 of FIG.

（第７の実施形態）
図２１は、本発明に関する第７の実施形態の半導体装置１１０を示す断面図である。図中、先に説明した部分には同一の参照符号を付し、説明を省略する。
この例では、保護膜としての接着剤２２の表面に、第二の保護膜としてのフィルム体１１１が積層されている。フィルム体１１１は、銅箔やアルミ箔等の金属箔や、エポキシ樹脂やポリイミド樹脂等の樹脂フィルムからなる。 フィルム体１１１としては、厚さ１０〜３５μｍのものを使用する。 一例として、１８μｍのものを使用する。フィルム体１１１が金属箔からなる場合、半導体装置の構造としては、第２の実施形態の半導体装置５０と類似したものとなる。
フィルム体１１１が樹脂フィルムからなる場合、半導体素子３０の背面３０ｂをより好適に保護でき、半導体装置１１０の信頼性が向上する。 また、フィルム体１１１が金属箔からなる場合、第２の実施形態における半導体装置５０の金属層２１に比較し、金属箔の厚さが厚いため、より放熱性が向上する。 (Seventh embodiment)
FIG. 21 is a sectional view showing a semiconductor device 110 according to the seventh embodiment of the present invention. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.
In this example, a film body 111 as a second protective film is laminated on the surface of the adhesive 22 as a protective film. The film body 111 is made of a metal foil such as a copper foil or an aluminum foil, or a resin film such as an epoxy resin or a polyimide resin. A film body 111 having a thickness of 10 to 35 μm is used. As an example, a 18-micrometer thing is used. When the film body 111 is made of metal foil, the structure of the semiconductor device is similar to the semiconductor device 50 of the second embodiment.
When the film body 111 is made of a resin film, the back surface 30b of the semiconductor element 30 can be more suitably protected, and the reliability of the semiconductor device 110 is improved. Moreover, when the film body 111 consists of metal foil, since the thickness of metal foil is thick compared with the metal layer 21 of the semiconductor device 50 in 2nd Embodiment, heat dissipation is improved more.

（第７の実施形態の製造方法 その１）
次に、図２２を参照し、図２１の第７の実施形態における半導体装置１１０の製造方法（その１）を説明する。図２２は、第７の実施形態に関する半導体装置１１０の製造工程を示した断面図である。図中、先に説明した部分には同一の参照符号を付し、説明を省略する。
始めに、図２２（ａ）に示すように、分離層としてのフィルム体１１１を、接着剤１１２により支持体４０の一方の面４０ａに接着し積層する。具体的には、フィルム体１１１の周縁部１１１ａのみを、接着剤１１２により支持体４０の一方の面４０ａの周縁部４０ｄに接着する。フィルム体１１１は、銅箔やアルミ箔等の金属箔、または、エポキシ樹脂やポリイミド樹脂等の樹脂フィルムからなる。 この例の場合、製造工程に耐え得る強度を有していれば、支持体４０の材質は特に限定されない。適宜の厚さの各種金属板や樹脂基板を使用できる。 (Manufacturing method 1 of 7th Embodiment)
Next, with reference to FIG. 22, the manufacturing method (the 1) of the semiconductor device 110 in 7th Embodiment of FIG. 21 is demonstrated. FIG. 22 is a cross-sectional view showing a manufacturing process of the semiconductor device 110 according to the seventh embodiment. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.
First, as shown in FIG. 22A, a film body 111 as a separation layer is bonded and laminated to one surface 40 a of the support body 40 with an adhesive 112. Specifically, only the peripheral edge portion 111 a of the film body 111 is bonded to the peripheral edge portion 40 d of the one surface 40 a of the support body 40 with the adhesive 112. The film body 111 is made of a metal foil such as a copper foil or an aluminum foil, or a resin film such as an epoxy resin or a polyimide resin. In the case of this example, the material of the support 40 is not particularly limited as long as it has a strength that can withstand the manufacturing process. Various metal plates and resin substrates having appropriate thicknesses can be used.

次いで、図２２（ｂ）に示すように、第１の実施形態の製造方法における図５（ｂ）から図６（ｃ）と同様の工程を施す。 ただし、この例の場合、金属層２１のエッチングによる除去工程がないため、はんだバンプ２６が後の工程で溶解する恐れがない。 よって、図６（ｃ）の工程後にバンプ２６を形成する。
次いで、図２２（ｃ）に示すように、支持体４０とフィルム体１１１の接着剤１１２による接着部分である、支持体４０とフィルム体１１１の周縁部４０ｄ、１１１ａを除去する。具体的には、破線で示す分離線Ｃ−Ｃで、中間体１１の周縁部１１ａ（支持体４０、フィルム体１１１、接着剤２２、絶縁層２３、ソルダレジスト２５の周縁部）を切断し除去する。これにより、支持体４０とフィルム体１１１の接着部分が除去される。 なお、切断は、少なくともフィルム体１１１、接着剤２２、絶縁層２３、ソルダレジスト２５の周縁部に施せば良い。支持体４０の切断は必須では無い。 Next, as shown in FIG. 22B, the same steps as those in FIGS. 5B to 6C in the manufacturing method of the first embodiment are performed. However, in this example, since there is no removal process by etching of the metal layer 21, there is no possibility that the solder bumps 26 are dissolved in a later process. Therefore, the bumps 26 are formed after the step of FIG.
Next, as shown in FIG. 22C, the peripheral portions 40d and 111a of the support body 40 and the film body 111, which are adhesion portions of the support body 40 and the film body 111 with the adhesive 112, are removed. Specifically, the peripheral portion 11a (the support 40, the film body 111, the adhesive 22, the insulating layer 23, and the peripheral portion of the solder resist 25) of the intermediate body 11 is cut and removed by the separation line CC shown by a broken line. To do. Thereby, the adhesion part of the support body 40 and the film body 111 is removed. Note that the cutting may be performed at least on the peripheral portions of the film body 111, the adhesive 22, the insulating layer 23, and the solder resist 25. Cutting the support 40 is not essential.

これにより、図２２（ｄ）に示すように、中間体１１から支持体４０が分離し除去される。具体的には、支持体４０とフィルム体１１１の界面から、支持体４０が分離する。この後、第１の実施形態の製造方法における図８（ｃ）と同様の工程を行い、中間体１１を個々の半導体装置の領域毎に分離し、図２１に示す半導体装置１１０を得る。
この製造方法では、中間体１１の周縁部１１ａの除去により、自動的に支持体４０を分離できるため、支持体４０の分離が容易になる。なお、この製造方法において、フィルム体１１１が金属箔からなる場合、支持体４０の分離後に、エッチングにより金属箔を除去しても良い。この場合、バンプ２６の接合は、金属箔の除去後に行う。 Thereby, as shown in FIG.22 (d), the support body 40 is isolate | separated from the intermediate body 11, and is removed. Specifically, the support 40 is separated from the interface between the support 40 and the film body 111. Thereafter, the same process as in FIG. 8C in the manufacturing method of the first embodiment is performed, and the intermediate body 11 is separated for each region of the individual semiconductor device to obtain the semiconductor device 110 shown in FIG.
In this manufacturing method, since the support body 40 can be automatically separated by removing the peripheral edge portion 11a of the intermediate body 11, the support body 40 can be easily separated. In this manufacturing method, when the film body 111 is made of a metal foil, the metal foil may be removed by etching after the support 40 is separated. In this case, the bumps 26 are joined after the metal foil is removed.

（第７の実施形態の製造方法 その２）
次に、図２３を参照し、図２１の第７の実施形態における半導体装置１１０の製造方法（その２）を説明する。図２３は、第７の実施形態に関する半導体装置１１０の製造工程を示した断面図である。図中、先に説明した部分には同一の参照符号を付し、説明を省略する。
始めに、図２３（ａ）に示すように、分離層としてのフィルム体１１１を、支持体４０の一方の面４０ａに載置して、層状の接着剤２２で被覆し支持体４０に接着する。 具体的には、支持体４０に、支持体４０の一方の面４０ａの周縁部４０ｄが露出するよう、フィルム体１１１を載置して、次いで、フィルム体１１１上及び支持体４０の周縁部４０ｄ上に接着剤２２を層状に設ける。 接着剤２２としてはエポキシ系樹脂やポリイミド系樹脂を用い、これら樹脂を塗布したり、これら樹脂のフィルムを貼着して形成する。 これにより、層状の接着剤２２と支持体４０との間にフィルム体１１１を配置する。 (Manufacturing method 2 of 7th Embodiment)
Next, with reference to FIG. 23, the manufacturing method (the 2) of the semiconductor device 110 in 7th Embodiment of FIG. 21 is demonstrated. FIG. 23 is a cross-sectional view showing a manufacturing process of the semiconductor device 110 according to the seventh embodiment. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.
First, as shown in FIG. 23A, the film body 111 as a separation layer is placed on one surface 40 a of the support 40, covered with the layered adhesive 22, and adhered to the support 40. . Specifically, the film body 111 is placed on the support body 40 so that the peripheral edge portion 40d of the one surface 40a of the support body 40 is exposed, and then the peripheral edge portion 40d on the film body 111 and the support body 40. The adhesive 22 is provided in a layered manner on the top. As the adhesive 22, an epoxy resin or a polyimide resin is used, and these resins are applied or a film of these resins is attached. Thereby, the film body 111 is disposed between the layered adhesive 22 and the support 40.

なお、フィルム体１１１は、銅箔やアルミ箔等の金属箔、または、エポキシ樹脂やポリイミド樹脂等の樹脂フィルムからなる。また、この例の場合、製造工程に耐え得る強度を有していれば、支持体４０の材質は特に限定されない。適宜の厚さの各種金属板や樹脂基板を使用できる。
次いで、図２３（ｂ）に示すように、第１の実施形態の製造方法における図５（ｂ）から図６（ｃ）と同様の工程を施す。 ただし、この例の場合、金属層２１のエッチングによる除去工程がないため、はんだバンプ２６が後の工程で溶解する恐れがない。 よって、図６（ｃ）の工程後にバンプ２６を形成する。 The film body 111 is made of a metal foil such as a copper foil or an aluminum foil, or a resin film such as an epoxy resin or a polyimide resin. In the case of this example, the material of the support 40 is not particularly limited as long as it has a strength that can withstand the manufacturing process. Various metal plates and resin substrates having appropriate thicknesses can be used.
Next, as shown in FIG. 23B, the same steps as in FIGS. 5B to 6C in the manufacturing method of the first embodiment are performed. However, in this example, since there is no removal process by etching of the metal layer 21, there is no possibility that the solder bumps 26 are dissolved in a later process. Therefore, the bumps 26 are formed after the step of FIG.

次いで、図２３（ｃ）に示すように、支持体４０と接着剤２２の接着部分である、支持体４０と接着剤２２の周縁部４０ｄ、２２ａを除去する。具体的には、破線で示す分離線Ｃ−Ｃで、中間体１１の周縁部１１ａ（支持体４０、フィルム体１１１、接着剤２２、絶縁層２３、ソルダレジスト２５の周縁部）を切断し除去する。これにより、支持体４０と接着剤２２の接着部分が除去される。 なお、切断は、少なくともフィルム体１１１、接着剤２２、絶縁層２３、ソルダレジスト２５の周縁部に施せば良い。支持体４０の切断は必須では無い。 Next, as shown in FIG. 23 (c), the peripheral portions 40 d and 22 a of the support 40 and the adhesive 22, which are adhesion portions between the support 40 and the adhesive 22, are removed. Specifically, the peripheral portion 11a (the support 40, the film body 111, the adhesive 22, the insulating layer 23, and the peripheral portion of the solder resist 25) of the intermediate body 11 is cut and removed by the separation line CC shown by a broken line. To do. Thereby, the adhesion part of the support body 40 and the adhesive agent 22 is removed. Note that the cutting may be performed at least on the peripheral portions of the film body 111, the adhesive 22, the insulating layer 23, and the solder resist 25. Cutting the support 40 is not essential.

これにより、図２３（ｄ）に示すように、中間体１１から支持体４０が分離し除去される。具体的には、支持体４０とフィルム体１１１の界面から、支持体４０が分離する。この後、第１の実施形態の製造方法における図８（ｃ）と同様の工程を行い、中間体１１を個々の半導体装置の領域毎に分離し、図２１に示す半導体装置１１０を得る。
この製造方法では、中間体１１の周縁部１１ａの除去により、自動的に支持体４０を分離できるため、支持体４０の分離が容易になる。なお、この製造方法において、フィルム体１１１が金属箔からなる場合、支持体４０の分離後に、エッチングにより金属箔を除去しても良い。この場合、バンプ２６の接合は、金属箔の除去後に行う。 As a result, as shown in FIG. 23 (d), the support 40 is separated from the intermediate body 11 and removed. Specifically, the support 40 is separated from the interface between the support 40 and the film body 111. Thereafter, the same process as in FIG. 8C in the manufacturing method of the first embodiment is performed, and the intermediate body 11 is separated for each region of the individual semiconductor device to obtain the semiconductor device 110 shown in FIG.
In this manufacturing method, since the support body 40 can be automatically separated by removing the peripheral edge portion 11a of the intermediate body 11, the support body 40 can be easily separated. In this manufacturing method, when the film body 111 is made of a metal foil, the metal foil may be removed by etching after the support 40 is separated. In this case, the bumps 26 are joined after the metal foil is removed.

（第８の実施形態）
図２４、図２５は、本発明に関する第８の実施形態（製造方法）を示す断面図である。この例では、第１の実施形態から第７の実施形態における、製造法方法の変形例を示す。図中、先に説明した部分には同一の参照符号を付し、説明を省略する。
まず図２４により、第１の実施形態から第６の実施形態における、製造方法の変形例を示す。始めに、図２４（ａ）に示すように、支持体４０の両面（一方の面４０ａと他方の面４０ｂ）に、分離層としての金属層２１を設ける。支持体４０と金属層２１には第1の実施形態における製造方法と同様のものを用いる。 ただし、この例の場合、支持体４０と金属層２１との密着性を低下させ金属層２１の剥離を容易にするため、支持体４０の両面を鏡面研磨しておくと好適である。 (Eighth embodiment)
24 and 25 are cross-sectional views showing an eighth embodiment (manufacturing method) according to the present invention. In this example, a modification of the manufacturing method in the first to seventh embodiments is shown. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.
First, FIG. 24 shows a modification of the manufacturing method in the first to sixth embodiments. First, as shown in FIG. 24A, metal layers 21 as separation layers are provided on both surfaces of the support 40 (one surface 40a and the other surface 40b). The support 40 and the metal layer 21 are the same as those in the manufacturing method in the first embodiment. However, in the case of this example, it is preferable that both surfaces of the support 40 are mirror-polished in order to reduce the adhesion between the support 40 and the metal layer 21 and facilitate the peeling of the metal layer 21.

次に、図２４（ｂ）に示すように、第１の実施形態の製造方法における図５（ｂ）から図６（ｃ）と同様の工程を施す。これにより、支持体４０の両面に中間体１１を形成する。次いで、破線で示す分離線Ｃ−Ｃで、中間体１１の周縁部１１ａ（支持体４０、金属層２１、接着剤２２、絶縁層２３、ソルダレジスト２５の周縁部）を切断し、被覆部２３ｃを除去する。なお、被覆部２３ｃを形成しない場合、除去工程は省略できる。
次いで、図２４（ｃ）に示すように、中間体１１から支持体４０を除去する。具体的には、図中矢印で示す方向に、中間体１１の側面に物理的な外力を加えることにより、分離層である金属層２１と支持体４０の界面から中間体１１を剥離し、分離する。 Next, as shown in FIG. 24B, steps similar to those in FIGS. 5B to 6C in the manufacturing method of the first embodiment are performed. Thereby, the intermediate body 11 is formed on both surfaces of the support body 40. Next, the peripheral portion 11a of the intermediate body 11 (the support portion 40, the metal layer 21, the adhesive 22, the insulating layer 23, and the peripheral portion of the solder resist 25) is cut along the separation line CC indicated by a broken line, and the covering portion 23c. Remove. If the covering portion 23c is not formed, the removing step can be omitted.
Next, as shown in FIG. 24C, the support body 40 is removed from the intermediate body 11. Specifically, by applying a physical external force to the side surface of the intermediate body 11 in the direction indicated by the arrow in the figure, the intermediate body 11 is peeled off from the interface between the metal layer 21 and the support body 40 as a separation layer and separated. To do.

その後、第１の実施形態の製造方法における図８（ａ）から図８（ｃ）と同様の工程を施すことにより半導体装置を得る。なお、第１の実施形態から第６の実施形態の各半導体装置を得る場合、それぞれの実施形態特有の工程を適宜施す。
支持体４０と絶縁層２３とに熱膨張率の差異がある場合、製造工程中に中間体１１に反りが発生し、製造に支障をきたす場合がある。しかし、この例の場合、支持体４０の両面に半導体装置を形成していくため、熱膨張率の差異による応力が支持体４０の両面で釣り合い、中間体１１の反りを防止できる。 また、支持体４０の両面に半導体装置を製造するため、半導体装置の生産性が向上する。 Thereafter, the semiconductor device is obtained by performing the same steps as in FIGS. 8A to 8C in the manufacturing method of the first embodiment. In addition, when obtaining each semiconductor device of 1st Embodiment to 6th Embodiment, the process peculiar to each embodiment is performed suitably.
When the support 40 and the insulating layer 23 have a difference in thermal expansion coefficient, the intermediate body 11 may be warped during the manufacturing process, which may hinder manufacturing. However, in this example, since the semiconductor device is formed on both surfaces of the support body 40, the stress due to the difference in thermal expansion coefficient is balanced on both surfaces of the support body 40, and the warpage of the intermediate body 11 can be prevented. Moreover, since the semiconductor device is manufactured on both surfaces of the support 40, the productivity of the semiconductor device is improved.

支持体の両面に半導体装置を形成する製造方法は、第７の実施形態における製造方法にも適用できる。図２５に、第７の実施形態における、製造方法の変形例を示す。
図２５（ａ）は、第８の実施例（製造方法）を、図２２に示した第７の実施形態の製造方法（その１）に適用した場合を示す。
この場合、支持体４０の両面（一方の面４０ａと他方の面４０ｂ）に、分離層としてのフィルム体１１１を接着剤１１２により接着し積層する。具体的には、フィルム体１１１の周縁部１１１ａのみを、接着剤１１２により支持体４０の両面の周縁部４０ｄに接着する。
その後、支持体４０の両面に中間体１１を形成していき、破線で示す分離線Ｃ−Ｃで、中間体１１の周縁部１１ａ（支持体４０、フィルム体１１１、接着剤２２、絶縁層２３、ソルダレジスト２５の周縁部）を切断し除去する。これにより、支持体４０とフィルム体１１１の接着部分が除去される。 よって、支持体４０の両面から、中間体１１を分離できる。この後、中間体１１に各工程を施し、図２１の半導体装置１１０を得る。 The manufacturing method for forming the semiconductor device on both sides of the support can also be applied to the manufacturing method in the seventh embodiment. FIG. 25 shows a modification of the manufacturing method in the seventh embodiment.
FIG. 25A shows a case where the eighth example (manufacturing method) is applied to the manufacturing method (part 1) of the seventh embodiment shown in FIG.
In this case, the film body 111 as a separation layer is adhered and laminated on both surfaces (one surface 40a and the other surface 40b) of the support 40 with an adhesive 112. Specifically, only the peripheral edge 111 a of the film body 111 is bonded to the peripheral edge 40 d on both surfaces of the support body 40 with the adhesive 112.
Then, the intermediate body 11 is formed on both surfaces of the support body 40, and the peripheral part 11a (support body 40, the film body 111, the adhesive agent 22, the insulating layer 23 of the intermediate body 11 is shown by the separation line CC shown with a broken line. The peripheral edge of the solder resist 25) is cut and removed. Thereby, the adhesion part of the support body 40 and the film body 111 is removed. Therefore, the intermediate body 11 can be separated from both surfaces of the support body 40. Thereafter, each step is performed on the intermediate body 11 to obtain the semiconductor device 110 of FIG.

図２５（ｂ）は、第８の実施例（製造方法）を、図２３に示した第７の実施形態の製造方法（その２）に適用した場合を示す。
この場合、分離層としてのフィルム体１１１を、支持体４０の両面（一方の面４０ａと他方の面４０ｂに載置して、接着剤２２で被覆し支持体４０に接着する。 具体的には、支持体４０の両面に、支持体４０両面の周縁部４０ｄが露出するようにフィルム体１１１を載置して、次いで、フィルム体１１１上及び支持体４０の周縁部４０ｄ上に接着剤２２を層状に設ける。 接着剤２２としてはエポキシ系樹脂やポリイミド系樹脂を用い、これら樹脂を塗布したり、これら樹脂のフィルムを貼着して形成する。 これにより、層状の接着剤２２と支持体４０との間にフィルム体１１１を配置する。 FIG. 25B shows a case where the eighth example (manufacturing method) is applied to the manufacturing method (part 2) of the seventh embodiment shown in FIG.
In this case, the film body 111 as a separation layer is placed on both surfaces (one surface 40a and the other surface 40b) of the support 40, covered with the adhesive 22, and bonded to the support 40. The film body 111 is placed on both surfaces of the support body 40 so that the peripheral edge portions 40d on both surfaces of the support body 40 are exposed, and then the adhesive 22 is applied on the film body 111 and the peripheral edge portion 40d of the support body 40. The adhesive 22 is formed by using an epoxy resin or a polyimide resin, and applying the resin or pasting a film of the resin, whereby the layered adhesive 22 and the support 40 are formed. The film body 111 is disposed between the two.

その後、支持体４０の両面に中間体１１を形成していき、破線で示す分離線Ｃ−Ｃで、中間体１１の周縁部１１ａ（支持体４０、フィルム体１１１、接着剤２２、絶縁層２３、ソルダレジスト２５の周縁部）を切断し除去する。これにより、支持体４０と接着剤２２との接着部分が除去される。 よって、支持体４０の両面から、中間体１１を分離できる。この後、中間体１１に各工程を施し、図２１の半導体装置１１０を得る。
図２５の場合においても、半導体装置の製造工程中の反りを防止し、且つ半導体装置の生産性を向上できる。 Then, the intermediate body 11 is formed on both surfaces of the support body 40, and the peripheral part 11a (support body 40, the film body 111, the adhesive agent 22, the insulating layer 23 of the intermediate body 11 is shown by the separation line CC shown with a broken line. The peripheral edge of the solder resist 25) is cut and removed. Thereby, the adhesion part of the support body 40 and the adhesive agent 22 is removed. Therefore, the intermediate body 11 can be separated from both surfaces of the support body 40. Thereafter, each step is performed on the intermediate body 11 to obtain the semiconductor device 110 of FIG.
Also in the case of FIG. 25, it is possible to prevent warpage during the manufacturing process of the semiconductor device and improve the productivity of the semiconductor device.

（第９の実施形態）
図２６は、本発明に関する第９の実施形態（製造方法）を示す断面図である。この例では、第１の実施形態から第６の実施形態における、製造法方法の変形例を示す。図中、先に説明した部分には同一の参照符号を付し、説明を省略する。
始めに、図２６（ａ）に示すように、分離層としての金属層２１を形成した二つの支持体４０を用意し、支持体４０の他方の面４０ｂ同士を接着剤４１により接着し、複合支持体４２を形成する。 具体的には、二つの支持体４０の周縁部４０ｄ同士を接着剤４１により接合する。支持体４０と金属層２１には第1の実施形態における製造方法と同様のものを用いる。 (Ninth embodiment)
FIG. 26 is a sectional view showing a ninth embodiment (manufacturing method) according to the present invention. In this example, a modification of the manufacturing method in the first to sixth embodiments is shown. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.
First, as shown in FIG. 26 (a), two supports 40 on which a metal layer 21 as a separation layer is formed are prepared, and the other surfaces 40b of the supports 40 are bonded to each other with an adhesive 41 to form a composite. A support 42 is formed. Specifically, the peripheral portions 40 d of the two supports 40 are joined together by the adhesive 41. The support 40 and the metal layer 21 are the same as those in the manufacturing method in the first embodiment.

次に、図２６（ｂ）に示すように、第１の実施形態の製造方法における図５（ｂ）から図６（ｃ）と同様の工程を施す。これにより、複合支持体４２の両面に中間体１１を形成する。次いで、破線で示す分離線Ｃ−Ｃで、中間体１１の周縁部１１ａ（支持体４０、金属層２１、接着剤２２、絶縁層２３、ソルダレジスト２５の周縁部）を切断し、２つの支持体４０の接着剤４１による接着部分を除去する。これにより、複合支持体４２が分離し、中間体１１が形成された個々の支持体４０の状態となる。 Next, as shown in FIG. 26B, the same steps as in FIGS. 5B to 6C in the manufacturing method of the first embodiment are performed. Thereby, the intermediate body 11 is formed on both surfaces of the composite support 42. Next, the peripheral portion 11a (the support 40, the metal layer 21, the adhesive 22, the insulating layer 23, and the peripheral portion of the solder resist 25) of the intermediate body 11 is cut along the separation line CC indicated by a broken line, and two supports are provided. The adhesion part by the adhesive 41 of the body 40 is removed. As a result, the composite support 42 is separated, and the individual support 40 in which the intermediate body 11 is formed is obtained.

次いで、図２６（ｃ）に示すように、中間体１１から支持体４０除去する。具体的には、図中矢印で示す方向に、中間体１１の側面に物理的な外力を加えることにより、分離層である金属層２１と支持体４０の界面から中間体１１を剥離し、分離する。
その後、第１の実施形態の製造方法における図８（ａ）から図８（ｃ）と同様の工程を施すことにより、第１の実施形態から第６の実施形態の各半導体装置を得る。なお、第１の実施形態から第６の実施形態の各半導体装置を得る場合、それぞれの実施形態特有の工程を適宜施す。 この例の場合も、半導体装置の製造工程中の反りを防止し、且つ半導体装置の生産性を向上できる。
以上、本発明の好ましい実施形態について述べたが、本発明は特定の実施形態に限定されるものでなく、各実施形態の特徴を組み合わせた形態や製造方法が可能であり、特許請求の範囲内に記載された本発明の要旨の範囲内において、種々の変形・改変が可能である。 Next, as shown in FIG. 26C, the support body 40 is removed from the intermediate body 11. Specifically, by applying a physical external force to the side surface of the intermediate body 11 in the direction indicated by the arrow in the figure, the intermediate body 11 is peeled off from the interface between the metal layer 21 and the support body 40 as a separation layer and separated. To do.
Thereafter, by performing the same steps as those in FIGS. 8A to 8C in the manufacturing method of the first embodiment, the semiconductor devices of the first to sixth embodiments are obtained. In addition, when obtaining each semiconductor device of 1st Embodiment to 6th Embodiment, the process peculiar to each embodiment is performed suitably. Also in this example, it is possible to prevent warpage during the manufacturing process of the semiconductor device and improve the productivity of the semiconductor device.
The preferred embodiments of the present invention have been described above. However, the present invention is not limited to specific embodiments, and forms and manufacturing methods in which the features of the embodiments are combined are possible. Various modifications and alterations are possible within the scope of the gist of the present invention described in the above.

本発明は、薄型化でき生産性の向上した半導体装置とその製造方法に適用できる。 The present invention can be applied to a semiconductor device and a manufacturing method thereof that can be thinned and improved in productivity.

従来の半導体装置の断面図である。It is sectional drawing of the conventional semiconductor device. 従来の半導体装置の製造工程を示した図である。It is the figure which showed the manufacturing process of the conventional semiconductor device. 本発明の第１の実施形態の半導体装置を示した断面図である。It is sectional drawing which showed the semiconductor device of the 1st Embodiment of this invention. 本発明の第１の実施形態の半導体装置における部分拡大図（断面図）である。It is the elements on larger scale (sectional drawing) in the semiconductor device of the 1st Embodiment of this invention. 本発明の第１の実施形態の半導体装置の製造工程を示した断面図である（その１）。It is sectional drawing which showed the manufacturing process of the semiconductor device of the 1st Embodiment of this invention (the 1). 本発明の第１の実施形態の半導体装置の製造工程を示した断面図である（その２）。It is sectional drawing which showed the manufacturing process of the semiconductor device of the 1st Embodiment of this invention (the 2). 本発明の第１の実施形態の半導体装置の製造工程を示した断面図である（その３）。It is sectional drawing which showed the manufacturing process of the semiconductor device of the 1st Embodiment of this invention (the 3). 本発明の第１の実施形態の半導体装置の製造工程を示した断面図である（その４）。It is sectional drawing which showed the manufacturing process of the semiconductor device of the 1st Embodiment of this invention (the 4). 本発明の第２の実施形態の半導体装置を示した断面図である。It is sectional drawing which showed the semiconductor device of the 2nd Embodiment of this invention. 本発明の第２の実施形態の半導体装置の製造工程を示した断面図である。It is sectional drawing which showed the manufacturing process of the semiconductor device of the 2nd Embodiment of this invention. 本発明の第３の実施形態の半導体装置を示した断面図である。It is sectional drawing which showed the semiconductor device of the 3rd Embodiment of this invention. 本発明の第３の実施形態の半導体装置の製造工程を示した断面図である。It is sectional drawing which showed the manufacturing process of the semiconductor device of the 3rd Embodiment of this invention. 本発明の第４の実施形態の半導体装置を示した断面図である。It is sectional drawing which showed the semiconductor device of the 4th Embodiment of this invention. 本発明の第４の実施形態の半導体装置の製造工程を示した断面図である。It is sectional drawing which showed the manufacturing process of the semiconductor device of the 4th Embodiment of this invention. 本発明の第５の実施形態の半導体装置を示した断面図である。It is sectional drawing which showed the semiconductor device of the 5th Embodiment of this invention. 本発明の第５の実施形態の半導体装置の製造工程を示した断面図である。It is sectional drawing which showed the manufacturing process of the semiconductor device of the 5th Embodiment of this invention. 本発明の第６の実施形態の半導体装置を示した断面図である。It is sectional drawing which showed the semiconductor device of the 6th Embodiment of this invention. 本発明の第６の実施形態の半導体装置の実装状態を示した断面図である。It is sectional drawing which showed the mounting state of the semiconductor device of the 6th Embodiment of this invention. 本発明の第６の実施形態の半導体装置の製造工程を示した断面図である（その１）。It is sectional drawing which showed the manufacturing process of the semiconductor device of the 6th Embodiment of this invention (the 1). 本発明の第６の実施形態の半導体装置の製造工程を示した断面図である（その２）。It is sectional drawing which showed the manufacturing process of the semiconductor device of the 6th Embodiment of this invention (the 2). 本発明の第７の実施形態の半導体装置を示した断面図である。It is sectional drawing which showed the semiconductor device of the 7th Embodiment of this invention. 本発明の第７の実施形態の半導体装置の製造工程を示した断面図である（その１）。It is sectional drawing which showed the manufacturing process of the semiconductor device of the 7th Embodiment of this invention (the 1). 本発明の第７の実施形態の半導体装置の製造工程を示した断面図である（その２）。It is sectional drawing which showed the manufacturing process of the semiconductor device of the 7th Embodiment of this invention (the 2). 本発明の第８の実施形態の半導体装置の製造工程を示した断面図である（その１）。It is sectional drawing which showed the manufacturing process of the semiconductor device of the 8th Embodiment of this invention (the 1). 本発明の第８の実施形態の半導体装置の製造工程を示した断面図である（その２）。It is sectional drawing which showed the manufacturing process of the semiconductor device of the 8th Embodiment of this invention (the 2). 本発明の第９の実施形態の半導体装置の製造工程を示した断面図である。It is sectional drawing which showed the manufacturing process of the semiconductor device of the 9th Embodiment of this invention.

符号の説明Explanation of symbols

１０、５０、６０、６０ｂ、７０、８０、９０、９０ａ、９０ｂ、９０ｃ、１００、１１０、１５０ 半導体装置
１１ 中間体
１１ａ 周縁部
２１ 金属層
２１ｃ ２２ｃ、２３ｃ 側面
２２、１６２ 接着剤
２２ａ 周縁部
２３、８３、１６３ 絶縁層
２３ａ 一方の面
２３ｂ 他方の面
２３ｃ 側面
２３ｄ、 ８３ｄ ビア穴
２３ｅ 貫通ビア穴
２４、８４、１６４ 配線
２４ａ、パッド
２４ｂ、８４ｂ ビア
２４ｃ パッド
２４ｄ 貫通ビア
２５ １６５ ソルダレジスト
２５ａ 開口部
２６、１６６ はんだバンプ
３０、１７０ 半導体素子
３０ａ 能動面
３０ｂ 背面
３１ 電極
３２、１７１ パッド
３３ パッシベーション膜
３４ 絶縁層
３５ 再配線
４０、１６１ 支持体
４０ａ 一方の面
４０ｂ 他方の面
４０ｃ 側面
４０ｄ 周縁部
４１ 接着剤
４２ 複合支持体
９１ 実装基板
９２ パッド
１１１ フィルム体
１１２ 接着剤 10, 50, 60, 60b, 70, 80, 90, 90a, 90b, 90c, 100, 110, 150 Semiconductor device 11 Intermediate 11a Peripheral part 21 Metal layer 21c 22c, 23c Side surface 22, 162 Adhesive 22a Peripheral part 23 , 83, 163 Insulating layer 23a One surface 23b The other surface 23c Side surface 23d, 83d Via hole 23e Through via hole 24, 84, 164 Wiring 24a, Pad 24b, 84b Via 24c Pad 24d Through via 25 25 165 Solder resist 25a Opening 26, 166 Solder bump 30, 170 Semiconductor element 30a Active surface 30b Back surface 31 Electrode 32, 171 Pad
33 Passivation film 34 Insulating layer 35 Rewiring 40, 161 Support 40a One side 40b The other side 40c Side 40d Peripheral part 41 Adhesive 42 Composite support 91 Mounting substrate 92 Pad 111 Film body 112 Adhesive

Claims (19)

半導体素子と、
配線が形成された一方の面と、その反対面となる他方の面とを有する絶縁層とを備え、
前記半導体素子が、能働面と側面とが前記絶縁層に被覆され、且つ該能働面が前記絶縁層の一方の面を向くよう、前記絶縁層に埋め込まれ、
前記半導体素子の背面が、保護膜により被覆され、
前記半導体素子と前記配線とが電気的に接続されていることを特徴とする半導体装置。 A semiconductor element;
An insulating layer having one surface on which wiring is formed and the other surface on the opposite side;
The semiconductor element is embedded in the insulating layer such that an active surface and side surfaces are covered with the insulating layer, and the active surface faces one surface of the insulating layer,
The back surface of the semiconductor element is covered with a protective film,
The semiconductor device, wherein the semiconductor element and the wiring are electrically connected. 前記半導体素子の背面と前記絶縁層の他方の面とが同一平面に位置し、
前記半導体素子の背面と前記絶縁層の他方の面とが、前記保護膜により一体に被覆されていることを特徴とする請求項１記載の半導体装置。 The back surface of the semiconductor element and the other surface of the insulating layer are located in the same plane,
2. The semiconductor device according to claim 1, wherein the back surface of the semiconductor element and the other surface of the insulating layer are integrally covered with the protective film. 前記保護膜の露出面と前記絶縁層の他方の面とが同一平面に位置することを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the exposed surface of the protective film and the other surface of the insulating layer are located on the same plane. 前記配線がソルダレジストにより被覆され、該ソルダレジストの開口部分に、前記配線と接続された外部接続端子が形成されていることを特徴とする請求項１乃至３のいずれか１項に記載の半導体装置。     4. The semiconductor according to claim 1, wherein the wiring is covered with a solder resist, and an external connection terminal connected to the wiring is formed in an opening portion of the solder resist. 5. apparatus. 前記半導体素子の能働面に突起電極が設けられており、該突起電極の端面が前記配線と接続されていることを特徴とする請求項１乃至４のいずれか１項に記載の半導体装置。   5. The semiconductor device according to claim 1, wherein a protruding electrode is provided on an active surface of the semiconductor element, and an end surface of the protruding electrode is connected to the wiring. 前記絶縁層部分に貫通ビアが形成され、該貫通ビアの一端が前記配線に接続され、他端が前記絶縁層の他方の面もしくは前記保護膜に形成された外部接続端子に接続されていることを特徴とする、請求項1乃至５のいずれか１項に記載の半導体装置。   A through via is formed in the insulating layer portion, one end of the through via is connected to the wiring, and the other end is connected to the other surface of the insulating layer or an external connection terminal formed on the protective film. The semiconductor device according to claim 1, wherein: 請求項１乃至５記載の半導体装置の、前記配線が形成されている側とは反対側となる露出面が第二の保護膜により被覆されていることを特徴とする半導体装置。 6. The semiconductor device according to claim 1, wherein an exposed surface opposite to the side on which the wiring is formed is covered with a second protective film. 支持体上に分離層を形成する工程と、
前記分離層上に接着剤層を介して半導体素子を搭載する工程と、
前記半導体素子の能動面と側面とを被覆するように絶縁層を形成する工程と、
前記絶縁層上に、前記半導体素子と電気的に接続する配線を形成する工程と、
前記支持体と前記分離層との界面から分離を行い、前記支持体を除去する工程とを有することを特徴とする半導体装置の製造方法。 Forming a separation layer on the support;
Mounting a semiconductor element on the separation layer via an adhesive layer;
Forming an insulating layer so as to cover an active surface and a side surface of the semiconductor element;
Forming a wiring electrically connected to the semiconductor element on the insulating layer;
Separating the support from the interface between the support and the separation layer, and removing the support. 支持体の一方の面とその反対面となる他方の面との両面に分離層を形成する工程と、
前記分離層上に接着剤層を介して半導体素子を搭載する工程と、
前記半導体素子の能動面と側面とを被覆するように絶縁層を形成する工程と、
前記絶縁層上に、前記半導体素子と電気的に接続する配線を形成する工程と、
前記支持体の両面と前記分離層との界面から分離を行い、前記支持体を除去する工程とを有することを特徴とする半導体装置の製造方法。 Forming a separation layer on both sides of one side of the support and the other side opposite thereto;
Mounting a semiconductor element on the separation layer via an adhesive layer;
Forming an insulating layer so as to cover an active surface and a side surface of the semiconductor element;
Forming a wiring electrically connected to the semiconductor element on the insulating layer;
A method for manufacturing a semiconductor device, comprising: separating from the interface between both surfaces of the support and the separation layer and removing the support. 分離層が形成された一方の面と、その反対面となる他方の面とを有する２つの支持体を用意し、該支持体の他方の面同士を接着し、複合支持体を形成する工程と、
前記複合支持体の分離層上に接着剤層を介して半導体素子を搭載する工程と、
前記半導体素子の能動面と側面とを被覆するように絶縁層を形成する工程と、
前記絶縁層上に、前記半導体素子と電気的に接続する配線を形成する工程と、
前記複合支持体を形成する２つの支持体を分離し、
各支持体の一方の面と前記分離層との界面から分離を行い、前記支持体を除去する工程とを有することを特徴とする半導体装置の製造方法。 Preparing two supports having one surface on which a separation layer is formed and the other surface being the opposite surface, and bonding the other surfaces of the supports to form a composite support; and ,
Mounting a semiconductor element on the separation layer of the composite support through an adhesive layer;
Forming an insulating layer so as to cover an active surface and a side surface of the semiconductor element;
Forming a wiring electrically connected to the semiconductor element on the insulating layer;
Separating the two supports forming the composite support;
A method for manufacturing a semiconductor device, comprising: separating from an interface between one surface of each support and the separation layer and removing the support. 前記分離層上に複数の半導体素子が搭載され、
前記支持体の除去後に、少なくとも一つの半導体素子が前記絶縁層に内蔵されるよう、前記絶縁層および分離層の分割を行うことを特徴とする請求項８乃至１０いずれか１項に記載の半導体装置の製造方法。 A plurality of semiconductor elements are mounted on the separation layer,
11. The semiconductor according to claim 8, wherein after the support is removed, the insulating layer and the separation layer are divided so that at least one semiconductor element is embedded in the insulating layer. Device manufacturing method. 前記支持体の除去後に、前記分離層の除去工程を有することを特徴とする請求項８乃至１１いずれか１項に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 8, further comprising a step of removing the separation layer after removing the support. 前記分離層上全面に，前記接着剤層を形成することを特徴とする請求項８乃至１２のいずれか１項に記載の半導体装置の製造方法   13. The method for manufacturing a semiconductor device according to claim 8, wherein the adhesive layer is formed on the entire surface of the separation layer. 前記分離層上の半導体素子を搭載するエリアに前記接着剤層を形成し、もしくは半導体素子に接着剤層を形成して、該接着剤層を介して半導体素子を搭載することを特徴とする請求項８乃至１２のいずれか１項に記載の半導体装置の製造方法。   The adhesive layer is formed in an area on which the semiconductor element is mounted on the separation layer, or the adhesive layer is formed on the semiconductor element, and the semiconductor element is mounted through the adhesive layer. Item 13. A method for manufacturing a semiconductor device according to any one of Items 8 to 12. 前記半導体素子の能動面に突起電極が設けられており、
前記絶縁層の表面を研磨して、前記突起電極の端面を前記絶縁層の一方の面に露出する工程と、
前記絶縁層の一方の表面に、前記突起電極と接続する配線を形成する工程と、を有することを特徴とする、請求項８乃至１４のいずれか１項に記載の半導体装置の製造方法。 Protruding electrodes are provided on the active surface of the semiconductor element,
Polishing the surface of the insulating layer to expose an end surface of the protruding electrode on one surface of the insulating layer;
The method for manufacturing a semiconductor device according to claim 8, further comprising: forming a wiring connected to the protruding electrode on one surface of the insulating layer. 前記接着剤層もしくは前記絶縁層の露出している部位に外部接続端子を形成する工程と、
前記絶縁層に、一端が前記配線に接続され、他端が前記外部接続端子に接続される貫通ビアを形成する工程を有すること特徴とする請求項８乃至１５いずれか１項に記載の半導体装置の製造方法。 Forming an external connection terminal on the exposed portion of the adhesive layer or the insulating layer;
The semiconductor device according to claim 8, further comprising: forming a through via in the insulating layer, one end of which is connected to the wiring and the other end is connected to the external connection terminal. Manufacturing method. 前記支持体が、シリコン基板またはガラス基板からなることを特徴とする請求項８乃至１６のいずれか１項に半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 8, wherein the support is made of a silicon substrate or a glass substrate. 前記分離層が、金属層からなることを特徴とする請求項８乃至１７のいずれか１項に半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 8, wherein the separation layer is made of a metal layer. 前記金属層が、クロムまたは銅からなることを特徴とする請求項１８記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 18, wherein the metal layer is made of chromium or copper.
JP2005032334A 2005-02-08 2005-02-08 Semiconductor device and its manufacturing method Pending JP2006222164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005032334A JP2006222164A (en) 2005-02-08 2005-02-08 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005032334A JP2006222164A (en) 2005-02-08 2005-02-08 Semiconductor device and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2006222164A true JP2006222164A (en) 2006-08-24

Family

ID=36984282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005032334A Pending JP2006222164A (en) 2005-02-08 2005-02-08 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2006222164A (en)

Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008306085A (en) * 2007-06-11 2008-12-18 Sumitomo Metal Mining Package Materials Co Ltd Manufacturing method of semiconductor device and substrate used for manufacturing semiconductor device
JP2009044160A (en) * 2007-08-10 2009-02-26 Samsung Electronics Co Ltd Semiconductor package equipped with embedded conductive post and its manufacturing method
JP2009064879A (en) * 2007-09-05 2009-03-26 Casio Comput Co Ltd Semiconductor device, and manufacturing method thereof
JP2009218561A (en) * 2008-02-12 2009-09-24 Nitto Denko Corp Wiring circuit board manufacturing method
JP2009278070A (en) * 2008-04-18 2009-11-26 Nitto Denko Corp Manufacturing method of wired circuit board
JP2010109181A (en) * 2008-10-30 2010-05-13 Shinko Electric Ind Co Ltd Method of manufacturing substrate with built-in semiconductor device
JP2011061116A (en) * 2009-09-14 2011-03-24 Shinko Electric Ind Co Ltd Semiconductor device and method of manufacturing the same
JP2011100793A (en) * 2009-11-04 2011-05-19 Shinko Electric Ind Co Ltd Method of manufacturing semiconductor package
JP2011119502A (en) * 2009-12-04 2011-06-16 Shinko Electric Ind Co Ltd Semiconductor package and method of manufacturing the same
CN102194716A (en) * 2010-03-05 2011-09-21 株式会社东芝 Method for manufacturing a semiconductor device and a semiconductor device
CN102299078A (en) * 2010-06-23 2011-12-28 株式会社东芝 Method for manufacturing semiconductor device
KR101123805B1 (en) * 2010-07-26 2012-03-12 주식회사 하이닉스반도체 Stack package and method for manufacturing thereof
JP2012084938A (en) * 2012-02-03 2012-04-26 Sumitomo Metal Mining Co Ltd Substrate for manufacturing semiconductor device
JP2012109350A (en) * 2010-11-16 2012-06-07 Shinko Electric Ind Co Ltd Electronic component package and method for manufacturing the same
CN102598257A (en) * 2009-11-06 2012-07-18 英特尔公司 Microelectronic package and method of manufacturing same
US8232639B2 (en) 2009-11-30 2012-07-31 Shinko Electric Industries Co., Ltd. Semiconductor-device mounted board and method of manufacturing the same
US8410614B2 (en) 2010-03-10 2013-04-02 Shinko Electric Industries Co., Ltd. Semiconductor device having a semiconductor element buried in an insulating layer and method of manufacturing the same
JP2013069808A (en) * 2011-09-21 2013-04-18 Shinko Electric Ind Co Ltd Semiconductor package and method for manufacturing the same
JP2014056924A (en) * 2012-09-12 2014-03-27 Hitachi Chemical Co Ltd Semiconductor device manufacturing method and thermosetting resin composition used therefor, and semiconductor device obtained by those
US8745860B2 (en) 2011-03-11 2014-06-10 Ibiden Co., Ltd. Method for manufacturing printed wiring board
JP2016025281A (en) * 2014-07-23 2016-02-08 株式会社ジェイデバイス Semiconductor device and method for manufacturing the same
US9474158B2 (en) 2013-07-12 2016-10-18 Ibiden Co., Ltd. Printed wiring board
JP2016213315A (en) * 2015-05-08 2016-12-15 日立化成株式会社 Method of manufacturing semiconductor device, and semiconductor device
JP2017073441A (en) * 2015-10-06 2017-04-13 日立化成株式会社 Photosensitive sealing resin composition, semiconductor device manufacturing method using the same, and semiconductor device
WO2018043008A1 (en) * 2016-08-31 2018-03-08 リンテック株式会社 Semiconductor device manufacturing method
JP2019033175A (en) * 2017-08-08 2019-02-28 日立化成株式会社 Semiconductor device manufacturing method
JP2019140150A (en) * 2018-02-06 2019-08-22 アオイ電子株式会社 Manufacturing method of semiconductor device
JP2021044447A (en) * 2019-09-12 2021-03-18 株式会社東芝 Carrier and method for manufacturing semiconductor device
KR20210140872A (en) * 2020-05-14 2021-11-23 주식회사 네패스라웨 Semiconductor package and method for manufacturing thereof
WO2022118969A1 (en) * 2020-12-04 2022-06-09 昭和電工マテリアルズ株式会社 Curable resin film, film material for semiconductor device production, curable resin composition for semiconductor device production, and method for producing semiconductor device
WO2022118971A1 (en) * 2020-12-04 2022-06-09 昭和電工マテリアルズ株式会社 Method for manufacturing semiconductor device
JPWO2022118929A1 (en) * 2020-12-04 2022-06-09

Cited By (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008306085A (en) * 2007-06-11 2008-12-18 Sumitomo Metal Mining Package Materials Co Ltd Manufacturing method of semiconductor device and substrate used for manufacturing semiconductor device
JP2009044160A (en) * 2007-08-10 2009-02-26 Samsung Electronics Co Ltd Semiconductor package equipped with embedded conductive post and its manufacturing method
JP2009064879A (en) * 2007-09-05 2009-03-26 Casio Comput Co Ltd Semiconductor device, and manufacturing method thereof
JP2009218561A (en) * 2008-02-12 2009-09-24 Nitto Denko Corp Wiring circuit board manufacturing method
JP2009278070A (en) * 2008-04-18 2009-11-26 Nitto Denko Corp Manufacturing method of wired circuit board
JP2010109181A (en) * 2008-10-30 2010-05-13 Shinko Electric Ind Co Ltd Method of manufacturing substrate with built-in semiconductor device
JP2011061116A (en) * 2009-09-14 2011-03-24 Shinko Electric Ind Co Ltd Semiconductor device and method of manufacturing the same
JP2011100793A (en) * 2009-11-04 2011-05-19 Shinko Electric Ind Co Ltd Method of manufacturing semiconductor package
KR101376990B1 (en) 2009-11-06 2014-03-25 인텔 코포레이션 Microelectronic package and method of manufacturing same
CN102598257A (en) * 2009-11-06 2012-07-18 英特尔公司 Microelectronic package and method of manufacturing same
JP2013507788A (en) * 2009-11-06 2013-03-04 インテル コーポレイション Microelectronic package and manufacturing method thereof
US8232639B2 (en) 2009-11-30 2012-07-31 Shinko Electric Industries Co., Ltd. Semiconductor-device mounted board and method of manufacturing the same
JP2011119502A (en) * 2009-12-04 2011-06-16 Shinko Electric Ind Co Ltd Semiconductor package and method of manufacturing the same
TWI467669B (en) * 2010-03-05 2015-01-01 Toshiba Kk Semiconductor device manufacturing method and semiconductor device
JP2011187551A (en) * 2010-03-05 2011-09-22 Toshiba Corp Method for manufacturing semiconductor device and semiconductor device
US8673690B2 (en) 2010-03-05 2014-03-18 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device and a semiconductor device
CN102194716A (en) * 2010-03-05 2011-09-21 株式会社东芝 Method for manufacturing a semiconductor device and a semiconductor device
US8410614B2 (en) 2010-03-10 2013-04-02 Shinko Electric Industries Co., Ltd. Semiconductor device having a semiconductor element buried in an insulating layer and method of manufacturing the same
CN102299078A (en) * 2010-06-23 2011-12-28 株式会社东芝 Method for manufacturing semiconductor device
KR101123805B1 (en) * 2010-07-26 2012-03-12 주식회사 하이닉스반도체 Stack package and method for manufacturing thereof
US9082634B2 (en) 2010-07-26 2015-07-14 SK Hynix Inc. Stack package and method for manufacturing the same
JP2012109350A (en) * 2010-11-16 2012-06-07 Shinko Electric Ind Co Ltd Electronic component package and method for manufacturing the same
US9226382B2 (en) 2011-03-11 2015-12-29 Ibiden Co., Ltd. Printed wiring board
US8745860B2 (en) 2011-03-11 2014-06-10 Ibiden Co., Ltd. Method for manufacturing printed wiring board
JP2013069808A (en) * 2011-09-21 2013-04-18 Shinko Electric Ind Co Ltd Semiconductor package and method for manufacturing the same
US9041211B2 (en) 2011-09-21 2015-05-26 Shinko Electric Industries Co., Ltd. Semiconductor package and method for manufacturing the semiconductor package embedded with semiconductor chip
JP2012084938A (en) * 2012-02-03 2012-04-26 Sumitomo Metal Mining Co Ltd Substrate for manufacturing semiconductor device
JP2014056924A (en) * 2012-09-12 2014-03-27 Hitachi Chemical Co Ltd Semiconductor device manufacturing method and thermosetting resin composition used therefor, and semiconductor device obtained by those
US9474158B2 (en) 2013-07-12 2016-10-18 Ibiden Co., Ltd. Printed wiring board
JP2016025281A (en) * 2014-07-23 2016-02-08 株式会社ジェイデバイス Semiconductor device and method for manufacturing the same
JP2016213315A (en) * 2015-05-08 2016-12-15 日立化成株式会社 Method of manufacturing semiconductor device, and semiconductor device
JP2017073441A (en) * 2015-10-06 2017-04-13 日立化成株式会社 Photosensitive sealing resin composition, semiconductor device manufacturing method using the same, and semiconductor device
TWI773341B (en) * 2016-08-31 2022-08-01 日商琳得科股份有限公司 Manufacturing method of semiconductor device
JP7317187B2 (en) 2016-08-31 2023-07-28 リンテック株式会社 Semiconductor device manufacturing method
KR20190045091A (en) * 2016-08-31 2019-05-02 린텍 가부시키가이샤 Method for manufacturing semiconductor device
JPWO2018043008A1 (en) * 2016-08-31 2019-06-24 リンテック株式会社 Semiconductor device manufacturing method
WO2018043008A1 (en) * 2016-08-31 2018-03-08 リンテック株式会社 Semiconductor device manufacturing method
JP7096766B2 (en) 2016-08-31 2022-07-06 リンテック株式会社 Manufacturing method of semiconductor device
KR102487681B1 (en) * 2016-08-31 2023-01-11 린텍 가부시키가이샤 Semiconductor device manufacturing method
TWI732921B (en) * 2016-08-31 2021-07-11 日商琳得科股份有限公司 Manufacturing method of semiconductor device
KR20220045255A (en) * 2016-08-31 2022-04-12 린텍 가부시키가이샤 Semiconductor device manufacturing method
KR102385965B1 (en) * 2016-08-31 2022-04-12 린텍 가부시키가이샤 Method of manufacturing a semiconductor device
JP2019033175A (en) * 2017-08-08 2019-02-28 日立化成株式会社 Semiconductor device manufacturing method
JP7172022B2 (en) 2017-08-08 2022-11-16 昭和電工マテリアルズ株式会社 Semiconductor device manufacturing method
TWI802648B (en) * 2018-02-06 2023-05-21 日商青井電子股份有限公司 Manufacturing method of semiconductor device
US11521948B2 (en) 2018-02-06 2022-12-06 Aoi Electronics Co., Ltd. Method of manufacturing semiconductor device
KR102407800B1 (en) * 2018-02-06 2022-06-10 아오이 전자 주식회사 Method of manufacturing a semiconductor device
CN111684585A (en) * 2018-02-06 2020-09-18 青井电子株式会社 Method for manufacturing semiconductor device
KR20200094780A (en) * 2018-02-06 2020-08-07 아오이 전자 주식회사 Method for manufacturing semiconductor device
JP2019140150A (en) * 2018-02-06 2019-08-22 アオイ電子株式会社 Manufacturing method of semiconductor device
JP7362378B2 (en) 2019-09-12 2023-10-17 株式会社東芝 Carrier and semiconductor device manufacturing method
JP2021044447A (en) * 2019-09-12 2021-03-18 株式会社東芝 Carrier and method for manufacturing semiconductor device
KR102438494B1 (en) * 2020-05-14 2022-09-01 주식회사 네패스라웨 Semiconductor package and method for manufacturing thereof
KR20210140872A (en) * 2020-05-14 2021-11-23 주식회사 네패스라웨 Semiconductor package and method for manufacturing thereof
WO2022118929A1 (en) * 2020-12-04 2022-06-09 昭和電工マテリアルズ株式会社 Method for manufacturing semiconductor device
JPWO2022118929A1 (en) * 2020-12-04 2022-06-09
JP7226664B2 (en) 2020-12-04 2023-02-21 株式会社レゾナック Semiconductor device manufacturing method
WO2022118971A1 (en) * 2020-12-04 2022-06-09 昭和電工マテリアルズ株式会社 Method for manufacturing semiconductor device
WO2022118969A1 (en) * 2020-12-04 2022-06-09 昭和電工マテリアルズ株式会社 Curable resin film, film material for semiconductor device production, curable resin composition for semiconductor device production, and method for producing semiconductor device

Similar Documents

Publication Publication Date Title
JP2006222164A (en) Semiconductor device and its manufacturing method
JP4171499B2 (en) Electronic device substrate and manufacturing method thereof, and electronic device and manufacturing method thereof
JP4361826B2 (en) Semiconductor device
US8181342B2 (en) Method for manufacturing a coreless packaging substrate
JP5460388B2 (en) Semiconductor device and manufacturing method thereof
JP4830120B2 (en) Electronic package and manufacturing method thereof
JP5367523B2 (en) Wiring board and method of manufacturing wiring board
US20090001570A1 (en) Electronic device and method of manufacturing the same
JP2006165252A (en) Method of manufacturing substrate with built-in chip
JP5406572B2 (en) Electronic component built-in wiring board and manufacturing method thereof
JP5357239B2 (en) WIRING BOARD, SEMICONDUCTOR DEVICE, AND WIRING BOARD MANUFACTURING METHOD
JP6341714B2 (en) Wiring board and manufacturing method thereof
TWI685935B (en) Semiconductor device and method of manufacturing semiconductor device
WO2017006391A1 (en) Semiconductor device
JP4955259B2 (en) WIRING BOARD, SEMICONDUCTOR DEVICE, AND WIRING BOARD MANUFACTURING METHOD
JP5355363B2 (en) Semiconductor device embedded substrate and manufacturing method thereof
JP4203537B2 (en) Wiring board manufacturing method and wiring board
JP4549695B2 (en) Wiring board manufacturing method
JP4549692B2 (en) Wiring board manufacturing method
JP4549693B2 (en) Wiring board manufacturing method
JP5555400B2 (en) Semiconductor device and manufacturing method thereof
JP4549694B2 (en) Wiring substrate manufacturing method and multi-cavity substrate
JP2007059493A (en) Semiconductor device and its manufacturing method
JP5880036B2 (en) Electronic component built-in substrate, manufacturing method thereof, and multilayer electronic component built-in substrate
JP3933910B2 (en) Manufacturing method of semiconductor device and manufacturing method of laminated structure