JP2006222149A - Semiconductor module - Google Patents

Semiconductor module Download PDF

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JP2006222149A
JP2006222149A JP2005032008A JP2005032008A JP2006222149A JP 2006222149 A JP2006222149 A JP 2006222149A JP 2005032008 A JP2005032008 A JP 2005032008A JP 2005032008 A JP2005032008 A JP 2005032008A JP 2006222149 A JP2006222149 A JP 2006222149A
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metal electrode
semiconductor element
element group
semiconductor
semiconductor module
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JP4532303B2 (en
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Katsuhiko Nishiyama
克彦 西山
Yuji Yagi
雄二 八木
Yuji Nishibe
祐司 西部
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Toyota Motor Corp
Toyota Central R&D Labs Inc
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Toyota Central R&D Labs Inc
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor module wherein upper and lower arms are paired and which has high heat dissipation as well as reduced parasitic inductance. <P>SOLUTION: The semiconductor module 100 has a structure wherein a semiconductor element is pinched by a pair of metallic electrodes. An intermediate connection is provided between the upper and lower arms to electrically connect them. In addition, the upper arm is provided with an external terminal section for a power supply positive terminal on the same side surface as a side surface to be bonded with the intermediate connection. The lower arm is provided with an external terminal section for a power supply negative terminal on the same side surface as a side surface to be bonded with the intermediate connection. Furthermore, the external terminal of the power supply positive terminal is arranged face to face with that of the power supply negative terminal, so that they are overlapped when viewed in the direction of thickness of the semiconductor module. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は，複数個の半導体素子（パワーＭＯＳＦＥＴやＩＧＢＴ等）を組み合わせてなる半導体モジュールに関する。さらに詳細には，電力制御に供するものであって，上アームと下アームとが一組となった半導体モジュールに関するものである。   The present invention relates to a semiconductor module formed by combining a plurality of semiconductor elements (power MOSFET, IGBT, etc.). More specifically, the present invention relates to a semiconductor module that is used for power control and includes a pair of an upper arm and a lower arm.

従来から，電力制御に供する半導体モジュールとして，上アームと下アームとが一組となった半導体モジュールが利用されている。この半導体モジュールは，図１７に示すようにＩＧＢＴ素子１１と，ＩＧＢＴ素子１１と逆並列に接続されたダイオード素子１２とからなる上アーム１０と，ＩＧＢＴ素子２１と，ＩＧＢＴ素子２１と逆並列に接続されたダイオード素子２２とからなる下アーム２０とを備え，上アーム１０と下アーム２０とが直列接続された構成となっている。このような半導体モジュールを複数個組み合わせることにより周知のインバータ回路が構成される。   Conventionally, as a semiconductor module for power control, a semiconductor module in which an upper arm and a lower arm are paired is used. As shown in FIG. 17, this semiconductor module is connected in an antiparallel manner to an upper arm 10 composed of an IGBT element 11 and a diode element 12 connected in antiparallel to the IGBT element 11, an IGBT element 21, and an IGBT element 21. The upper arm 10 and the lower arm 20 are connected in series. A known inverter circuit is configured by combining a plurality of such semiconductor modules.

一般的に，半導体モジュールを高耐圧・大電流用のパワーＩＣに適用すると，使用時の素子からの発熱が大きい。そのため，高放熱性が要求される。この問題を解決する構成の一例として，例えば特許文献１に，素子の両面に高熱伝導性を備えた基板にて複数個の半導体素子を挟み込んだ両面放熱構造の半導体装置が提案されている。
特開平１０−５６１３１号公報 In general, when a semiconductor module is applied to a power IC for high withstand voltage and large current, heat generated from the element during use is large. Therefore, high heat dissipation is required. As an example of a configuration that solves this problem, for example, Patent Document 1 proposes a semiconductor device having a double-sided heat dissipation structure in which a plurality of semiconductor elements are sandwiched between substrates having high thermal conductivity on both sides of the elements.
JP-A-10-56131

しかしながら，前記した従来の半導体モジュールには，次のような問題があった。すなわち，上アームと下アームとが一組となった半導体モジュールでは，配線部分の寄生インダクタンスが大きい。具体的には，図１７中，Ｌ１（Ｐ端子と上アーム１０のコレクタとの間のインダクタンス），Ｌ２（上アーム１０のエミッタと接続点との間のインダクタンス），Ｌ３（接続点と下アーム２０のコレクタとの間のインダクタンス），Ｌ４（下アーム２０のエミッタとＮ端子との間のインダクタンス）の各所に寄生インダクタンスを有する。この寄生インダクタンスＬが大きくなればなるほどサージ電圧が高くなる（サージ電圧＝寄生インダクタンスＬ×電流変化率ｄＩ／ｄｔ）。そのため，高耐圧・大電流用の電力変換装置に適用される半導体モジュールでは，特にこの寄生インダクタンスＬを小さくすることが求められる。   However, the conventional semiconductor module described above has the following problems. That is, in the semiconductor module in which the upper arm and the lower arm are paired, the parasitic inductance of the wiring portion is large. Specifically, in FIG. 17, L1 (inductance between the P terminal and the collector of the upper arm 10), L2 (inductance between the emitter of the upper arm 10 and the connection point), L3 (connection point and lower arm). 20), and L4 (inductance between the emitter of the lower arm 20 and the N terminal) has parasitic inductance. As the parasitic inductance L increases, the surge voltage increases (surge voltage = parasitic inductance L × current change rate dI / dt). Therefore, in the semiconductor module applied to the power converter for high withstand voltage and large current, it is particularly required to reduce the parasitic inductance L.

具体的に寄生インダクタンスＬを小さくするには，配線部分の長さを短くする，あるいは配線の断面積を大きくすることが考えられる。しかしながら，配線の配置などの関係から半導体モジュールの大きさそのものが大型化してしまうため，それら物理的サイズの変更には限界がある。   Specifically, to reduce the parasitic inductance L, it is conceivable to shorten the length of the wiring portion or increase the cross-sectional area of the wiring. However, since the size of the semiconductor module itself increases due to the wiring arrangement and the like, there is a limit to changing the physical size.

そこで，例えば特許文献１に示した半導体装置のように，表裏面の基板の外部配線用端子を半導体モジュールの同一側面から同一方向に延びるように配設することで，寄生インダクタンスの低減を図ることが提案されている（図１８参照）。すなわち，互いに逆向きの電流が流れる外部配線用端子Ｐ，Ｎ間の相互インダクタンスを利用してインダクタンスを低減することが開示されている。   Therefore, for example, as in the semiconductor device disclosed in Patent Document 1, the external wiring terminals of the front and back substrates are arranged so as to extend in the same direction from the same side surface of the semiconductor module, thereby reducing the parasitic inductance. Has been proposed (see FIG. 18). That is, it is disclosed that the inductance is reduced by utilizing the mutual inductance between the external wiring terminals P and N through which currents in opposite directions flow.

しかし，特許文献１の半導体装置では，外部配線用端子Ｐ，Ｎが対向しているもののその間隔が広い。また，外部配線用端子が基板の面方向に並行配置されているため，対向している面積が小さい。そのため，相互インダクタンスによる内部インダクタンスの低減効果が期待できない。また，外部配線用端子Ｐ，Ｎが対向することで外部配線用端子部分の寄生インダクタンスＬ１，Ｌ４を多少なりとも低減できたとしても，その他の部分，例えば内部端子のインダクタンスＬ２，Ｌ３を低減することはできない。そのため，インダクタンスの低減効果は殆ど期待できない。   However, in the semiconductor device of Patent Document 1, although the external wiring terminals P and N are opposed to each other, the distance between them is wide. Further, since the external wiring terminals are arranged in parallel in the surface direction of the substrate, the facing area is small. Therefore, the effect of reducing internal inductance due to mutual inductance cannot be expected. Even if the external wiring terminals P and N face each other and the parasitic inductances L1 and L4 of the external wiring terminal portion can be reduced to some extent, the other portions, for example, the inductances L2 and L3 of the internal terminals are reduced. It is not possible. For this reason, the inductance reduction effect can hardly be expected.

本発明は，前記した従来の半導体装置が有する問題点を解決するためになされたものである。すなわちその課題とするところは，上アームと下アームとが一組となった半導体モジュールであって，高放熱性を備えつつ寄生インダクタンスの低減が図られた半導体モジュールを提供することにある。   The present invention has been made to solve the problems of the conventional semiconductor device described above. That is, an object of the present invention is to provide a semiconductor module in which an upper arm and a lower arm are a set, and has a high heat dissipation property and a reduced parasitic inductance.

この課題の解決を目的としてなされた半導体モジュールは，上アーム部を構成する第１半導体素子群と，下アーム部を構成する第２半導体素子群とを備え，第１半導体素子群と第２半導体素子群とを同一平面内に配置した半導体モジュールであって，第１半導体素子群の一方の面側に位置する第１金属電極と，第１半導体素子群の他方の面側に位置し，第１半導体素子群を挟んで第１金属電極と対向する第２金属電極と，第２半導体素子群の一方の面側に位置し，第２金属電極と電気的に接続された第３金属電極と，第２半導体素子群の他方の面側に位置し，第２半導体素子群を挟んで第３金属電極と対向する第４金属電極と，一方の端部が第２金属電極のうちの下アーム部と対向する部位と接合し，他方の端部が第３金属電極のうちの上アーム部と対向する部位と接合し，第２金属電極と第３金属電極とを電気的に接続する中間接続部と，第１金属電極のうちの下アーム部と対向する部位と接合する平板状の正極側取出し端子と，第４金属電極のうちの上アーム部と対向する部位と接合する平板状の負極側取出し端子とを備えることを特徴とするものである。   A semiconductor module for solving this problem includes a first semiconductor element group constituting an upper arm part and a second semiconductor element group constituting a lower arm part. The first semiconductor element group and the second semiconductor A semiconductor module having an element group arranged in the same plane, the first metal electrode located on one side of the first semiconductor element group, and the other side of the first semiconductor element group, A second metal electrode opposed to the first metal electrode across one semiconductor element group; a third metal electrode located on one side of the second semiconductor element group and electrically connected to the second metal electrode; , A fourth metal electrode which is located on the other surface side of the second semiconductor element group and faces the third metal electrode across the second semiconductor element group, and one end portion of which is the lower arm of the second metal electrode The other end is the upper metal electrode of the third metal electrode. A plate-like shape that is joined to a portion opposed to the first metal portion and electrically connected to the second metal electrode and the third metal electrode, and a portion of the first metal electrode opposite to the lower arm portion. And a flat negative electrode side extraction terminal joined to a portion of the fourth metal electrode facing the upper arm portion.

すなわち，本発明の半導体モジュールは，第１半導体素子群を有する上アームと第２半導体素子群を有する下アームとが一組となったものである。また，本発明の半導体モジュールは，平板状の第１金属電極および第２金属電極によって第１半導体素子群を挟み，平板状の第３金属電極および第４金属電極によって第２半導体素子群を挟んでいる。つまり，放熱板の機能を兼ねた一対の板状金属電極によって半導体素子群を挟み込んでおり，上面および下面の２方向からの放熱を図るものである。   That is, the semiconductor module of the present invention is a set of an upper arm having a first semiconductor element group and a lower arm having a second semiconductor element group. In the semiconductor module of the present invention, the first semiconductor element group is sandwiched between the flat plate-like first metal electrode and the second metal electrode, and the second semiconductor element group is sandwiched between the plate-like third metal electrode and the fourth metal electrode. It is out. That is, the semiconductor element group is sandwiched between a pair of plate-like metal electrodes that also function as a heat radiating plate, and heat is radiated from two directions, the upper surface and the lower surface.

そして，本発明の半導体モジュールは，第１半導体素子群と第２半導体素子群とが同一平面内に配置されている。すなわち，上アーム部と下アーム部とが同一平面内に並列配置されている。さらに，本発明の半導体モジュールは，上アーム部と下アーム部との間に，第２金属電極と第３金属電極とを電気的に接続する中間接続部を備えている。そして，正極側取出し端子が第１金属電極のうちの下アーム部と対向する部位に接合され，負極側取出し端子が第４金属電極のうちの上アーム部と対向する部位に接合されている。中間接続部および各アーム部の電源取出し端子をこのように配置することで，上アーム部では，従来の端子配置に比べ，第１金属電極を流れる主電流と第２金属電極を流れる主電流との対向成分がより増加する。一方，下アーム部でも，第３金属電極を流れる主電流と第４金属電極を流れる主電流との対向成分がより増加する。よって，内部端子部であっても相互インダクタンスによる寄生インダクタンスの低減効果が得られ，半導体モジュール全体としての寄生インダクタンスの低減が図られる。   In the semiconductor module of the present invention, the first semiconductor element group and the second semiconductor element group are arranged in the same plane. That is, the upper arm portion and the lower arm portion are arranged in parallel in the same plane. Furthermore, the semiconductor module of the present invention includes an intermediate connection portion that electrically connects the second metal electrode and the third metal electrode between the upper arm portion and the lower arm portion. And the positive electrode side extraction terminal is joined to the site | part facing the lower arm part among 1st metal electrodes, and the negative electrode side extraction terminal is joined to the site | part facing the upper arm part among 4th metal electrodes. By arranging the intermediate connection portion and the power supply terminal of each arm portion in this way, the upper arm portion has a main current flowing through the first metal electrode and a main current flowing through the second metal electrode as compared with the conventional terminal arrangement. The opposing component of increases more. On the other hand, in the lower arm portion, the opposing component of the main current flowing through the third metal electrode and the main current flowing through the fourth metal electrode is further increased. Therefore, even if it is an internal terminal part, the reduction effect of the parasitic inductance by a mutual inductance is acquired, and the reduction of the parasitic inductance as the whole semiconductor module is achieved.

なお，主電流が対向するあるいは主電流の向きが反対であるとは，それらの向きが厳密に１８０度の差があることを意味するものではない。すなわち，相互インダクタンスによるインダクタンスの低減が期待できる範囲内の差であればよい。具体的には，反対方向の電流成分の半分以上が低減効果として見込まれる１８０度±６０度の範囲内の差であればその効果が期待できる。   Note that the fact that the main currents face each other or the directions of the main currents are opposite does not mean that the directions are strictly different by 180 degrees. That is, the difference may be within a range where reduction of inductance due to mutual inductance can be expected. Specifically, if more than half of the current component in the opposite direction is within a range of 180 ° ± 60 °, which is expected as a reduction effect, the effect can be expected.

また，本発明の半導体モジュールでは，各アーム部の電源取出し端子が他方のアーム部と対向する部位に設けられている。すなわち，各アーム部の電源取出し端子が両アーム部の間に位置する。一方，上アームと下アームとを電気的に接続する中間接続部も両アーム部の間に位置する。このことから，電源取出し端子と中間端子部とが近接配置される。そのため，半導体モジュールの内部に位置する電源取出し端子のインダクタンスおよび中間端子部のインダクタンスの低減も図ることができる。   Further, in the semiconductor module of the present invention, the power supply terminal of each arm portion is provided at a portion facing the other arm portion. That is, the power supply terminal of each arm part is located between both arm parts. On the other hand, an intermediate connection portion that electrically connects the upper arm and the lower arm is also located between the arm portions. For this reason, the power supply output terminal and the intermediate terminal portion are arranged close to each other. Therefore, it is possible to reduce the inductance of the power supply extraction terminal and the inductance of the intermediate terminal portion located inside the semiconductor module.

また，本発明の半導体モジュールは，電極面から見て，第１半導体素子群を構成する半導体素子（トランジスタ素子領域およびダイオード素子領域）と，第２半導体素子群を構成する半導体素子（トランジスタ素子領域およびダイオード素子領域）とが同一直線上に配置されていることとするとよりよい。このような配置とすることにより，半導体素子を挟んで対向する金属電極を流れる電流の向きを確実に対向させることができる。よって，内部端子部の寄生インダクタンスの低減が確実に図られる。   In addition, the semiconductor module of the present invention includes a semiconductor element (transistor element region and diode element region) constituting the first semiconductor element group and a semiconductor element (transistor element area) constituting the second semiconductor element group as viewed from the electrode surface. And the diode element region) are more preferably arranged on the same straight line. With such an arrangement, it is possible to reliably make the directions of currents flowing through the metal electrodes facing each other across the semiconductor element face each other. Therefore, the parasitic inductance of the internal terminal portion can be reliably reduced.

また，本発明の半導体モジュールは，正極側取出し端子と負極側取出し端子とがその平面同士が対向していることとするとよりよい。すなわち，本発明の半導体モジュールでは，平板状の正極側取出し端子と平板状の負極側取出し端子とが厚さ方向に重ね合わせられるように対向している。そのため，両電源取出し端子間の距離は短く，両端子の相互インダクタンスは大きい。そして，両端子を流れる主電流は互いに逆向きであることから，外部端子部の寄生インダクタンスは大幅に低減される。   In the semiconductor module of the present invention, it is better that the positive electrode side extraction terminal and the negative electrode side extraction terminal are opposed to each other. That is, in the semiconductor module of the present invention, the flat positive electrode side extraction terminal and the flat negative electrode side extraction terminal face each other so as to be overlapped in the thickness direction. For this reason, the distance between the power supply terminals is short and the mutual inductance of both terminals is large. Since the main currents flowing through both terminals are opposite to each other, the parasitic inductance of the external terminal portion is greatly reduced.

本発明によれば，半導体素子を金属電極で挟み込み，両面放熱構造とすることにより高放熱性が確保される。また，本発明によれば，半導体モジュールを構成する配線のうち，主電流の向きが対向する部位が広範囲に設けられる。そのため，相互インダクタンスによる寄生インダクタンスの低減が図られる。よって，上アームと下アームとが一組となった半導体モジュールであって，高放熱性を備えつつ寄生インダクタンスの低減が図られた半導体モジュールが実現されている。   According to the present invention, high heat dissipation is ensured by sandwiching the semiconductor element between the metal electrodes to form a double-sided heat dissipation structure. In addition, according to the present invention, a portion of the wiring constituting the semiconductor module, in which the direction of the main current is opposite, is provided in a wide range. Therefore, parasitic inductance can be reduced by mutual inductance. Therefore, a semiconductor module in which the upper arm and the lower arm are combined as one set and having a high heat dissipation property while reducing the parasitic inductance is realized.

以下，本発明を具体化した実施の形態について，添付図面を参照しつつ詳細に説明する。なお，以下の形態では，インバータ装置に利用されるパワーモジュール（半導体モジュール）に本発明を適用する。   DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described below in detail with reference to the accompanying drawings. In the following embodiment, the present invention is applied to a power module (semiconductor module) used in an inverter device.

図１は，本形態の半導体モジュール１００の等価回路を示している。半導体モジュール１００は，図１に示すようにＩＧＢＴ素子１１と，ＩＧＢＴ素子１１と逆並列に接続されたダイオード素子１２とからなる上アーム１０と，ＩＧＢＴ素子２１と，ＩＧＢＴ素子２１と逆並列に接続されたダイオード素子２２とからなる下アーム２０とを備え，上アーム１０と下アーム２０とが直列接続された構成となっている。すなわち，半導体モジュール１００は，上アーム１０と下アーム２０とが一組となった構造を有している。   FIG. 1 shows an equivalent circuit of the semiconductor module 100 of this embodiment. As shown in FIG. 1, the semiconductor module 100 is connected in an antiparallel manner to an upper arm 10 including an IGBT element 11 and a diode element 12 connected in antiparallel to the IGBT element 11, an IGBT element 21, and an IGBT element 21. The upper arm 10 and the lower arm 20 are connected in series. That is, the semiconductor module 100 has a structure in which the upper arm 10 and the lower arm 20 are a set.

この半導体モジュール１００では，制御信号を各ＩＧＢＴ素子のゲート端子に入力することにより各ＩＧＢＴ素子がオンオフする。これにより，制御対象のモータへの供給電力を制御する。   In this semiconductor module 100, each IGBT element is turned on and off by inputting a control signal to the gate terminal of each IGBT element. Thereby, the power supplied to the motor to be controlled is controlled.

次に，半導体モジュール１００の具体的構造について説明する。なお，図２は，半導体モジュール１００の上面および右側面から見た外観を示している。また，図３は図２のＡ−Ａ断面および同図のＤ−Ｄ断面，図４は図３のＢ−Ｂ断面，図５は図３のＣ−Ｃ断面をそれぞれ示している。なお，各図中，各金属電極内の矢印は主電流の流れの向きを意味する。   Next, a specific structure of the semiconductor module 100 will be described. FIG. 2 shows the appearance of the semiconductor module 100 as viewed from the top and right sides. 3 shows an AA section of FIG. 2 and a DD section of FIG. 4, FIG. 4 shows a BB section of FIG. 3, and FIG. 5 shows a CC section of FIG. In each figure, the arrow in each metal electrode means the direction of the main current flow.

半導体モジュール１００は，図２ないし図５に示すように，上アーム１０と下アーム２０とが同一平面内に並置された構造を有している。上アーム１０は，ＩＧＢＴ素子１１とダイオード素子１２とを備え，両半導体素子が平板状の金属電極１３，１４に挟み込まれた構造を有している。また，下アーム２０は，ＩＧＢＴ素子２１とダイオード素子２２とを備え，両半導体素子が平板状の金属電極２３，２４に挟み込まれた構造を有している。すなわち，上アーム１０では，金属電極１３，１４が半導体素子１１，１２を挟んでその平面同士が対向している。一方，下アーム２０では，金属電極２３，２４が半導体素子２１，２２を挟んでその平面同士が対向している。そして両アームともに，半導体素子と金属電極とが半田または導電性の接着剤によって接合されている。そのため，半導体モジュール１００では，図３中の縦方向に電流が流れる。   As shown in FIGS. 2 to 5, the semiconductor module 100 has a structure in which the upper arm 10 and the lower arm 20 are juxtaposed in the same plane. The upper arm 10 includes an IGBT element 11 and a diode element 12, and has a structure in which both semiconductor elements are sandwiched between flat metal electrodes 13 and 14. The lower arm 20 includes an IGBT element 21 and a diode element 22, and has a structure in which both semiconductor elements are sandwiched between flat metal electrodes 23 and 24. That is, in the upper arm 10, the metal electrodes 13 and 14 face each other with the semiconductor elements 11 and 12 therebetween. On the other hand, in the lower arm 20, the metal electrodes 23 and 24 face each other with the semiconductor elements 21 and 22 interposed therebetween. In both arms, the semiconductor element and the metal electrode are joined by solder or a conductive adhesive. Therefore, in the semiconductor module 100, a current flows in the vertical direction in FIG.

また，上アーム１０の金属電極１３と下アーム２０の金属電極２３とが同一平面内に配置されている。また，金属電極１４と金属電極２４とについても同一平面内に配置されている。さらに，上アーム１０のＩＧＢＴ素子１１およびダイオード素子１２と，下アーム２０のＩＧＢＴ素子２１およびダイオード素子２２とについても同一平面内，より具体的には同一直線内に配置されている。   Further, the metal electrode 13 of the upper arm 10 and the metal electrode 23 of the lower arm 20 are arranged in the same plane. The metal electrode 14 and the metal electrode 24 are also arranged in the same plane. Furthermore, the IGBT element 11 and the diode element 12 of the upper arm 10 and the IGBT element 21 and the diode element 22 of the lower arm 20 are also arranged in the same plane, more specifically in the same straight line.

また，半導体モジュール１００は，各金属電極間の隙間が樹脂（例えば，エポキシ樹脂）６で充填されている。すなわち，上アーム１０と下アーム２０とは，樹脂６でモールドされることによって一体となっている。   In the semiconductor module 100, the gaps between the metal electrodes are filled with a resin (for example, epoxy resin) 6. That is, the upper arm 10 and the lower arm 20 are integrated by being molded with the resin 6.

また，半導体モジュール１００は，外部端子部として，正極側取出し端子１と，負極側取出し端子２と，中間取出し端子３とを有している。各端子は，平板状の金属端子であり，半導体モジュール１００の側面から突出している。またこの他の外部端子として，上アーム１０用のゲート電極端子１５と，下アーム２０用のゲート電極端子２５とを備えている。   Moreover, the semiconductor module 100 has a positive electrode side extraction terminal 1, a negative electrode side extraction terminal 2, and an intermediate extraction terminal 3 as external terminal portions. Each terminal is a flat metal terminal and protrudes from the side surface of the semiconductor module 100. As other external terminals, a gate electrode terminal 15 for the upper arm 10 and a gate electrode terminal 25 for the lower arm 20 are provided.

具体的に，正極側取出し端子１の側面は，金属電極１３の側面のうち，下アーム２０と対向する側の側面に接合している。すなわち，正極側取出し端子１は，上アーム１０と下アーム２０との間に位置し，金属電極１３と一体になっている（以下，正極側取出し端子１と内部配線である金属電極１３とが一体となった部分を「電源＋端子」とする）。また，負極側取出し端子２の側面は，金属電極２４の側面のうち，上アーム１０と対向する側の側面に接合している。すなわち，負極側取出し端子２は，正極側取出し端子１と同様に上アーム１０と下アーム２０との間に位置し，金属電極２４と一体になっている（以下，負極側取出し端子２と内部配線である金属電極２４とが一体となった部分を「電源−端子」とする）。さらに，正極側取出し端子１と負極側取出し端子２とは，半導体モジュール１００の同一側面から同一方向に突出しており，その平面同士が対向している。すなわち，半導体モジュール１００の上面から見て，正極側取出し端子１と負極側取出し端子２とが重ね合わせられた配置となっている。   Specifically, the side surface of the positive electrode extraction terminal 1 is joined to the side surface of the metal electrode 13 that faces the lower arm 20. That is, the positive electrode side extraction terminal 1 is located between the upper arm 10 and the lower arm 20 and is integrated with the metal electrode 13 (hereinafter, the positive electrode side extraction terminal 1 and the metal electrode 13 that is an internal wiring are connected to each other). The integrated part is called “power supply + terminal”). Further, the side surface of the negative electrode side extraction terminal 2 is joined to the side surface of the metal electrode 24 facing the upper arm 10. That is, the negative electrode side extraction terminal 2 is located between the upper arm 10 and the lower arm 20 in the same manner as the positive electrode side extraction terminal 1, and is integrated with the metal electrode 24 (hereinafter referred to as the negative electrode side extraction terminal 2 and the internal portion). A portion where the metal electrode 24 that is the wiring is integrated is referred to as a “power supply-terminal”). Furthermore, the positive electrode side extraction terminal 1 and the negative electrode side extraction terminal 2 protrude in the same direction from the same side surface of the semiconductor module 100, and the planes thereof face each other. That is, when viewed from the upper surface of the semiconductor module 100, the positive electrode side extraction terminal 1 and the negative electrode side extraction terminal 2 are arranged to overlap each other.

また，中間取出し端子３の側面は，金属電極１４の側面のうち，下アーム２０と対向する側以外の側面に接合している。すなわち，中間取出し端子３は，上アーム１０側であって正極側取出し端子１から離れた部位に位置し，金属電極１４と一体になっている。なお，中間取出し端子３は，金属電極２３に接合していてもよい。その場合，中間取出し端子３は，金属電極２３の側面のうち，上アーム１０と対向する側以外の側面に接合するものとする。   Further, the side surface of the intermediate extraction terminal 3 is joined to the side surface of the metal electrode 14 other than the side facing the lower arm 20. That is, the intermediate extraction terminal 3 is located on the upper arm 10 side and away from the positive electrode extraction terminal 1 and is integrated with the metal electrode 14. The intermediate extraction terminal 3 may be bonded to the metal electrode 23. In this case, the intermediate extraction terminal 3 is joined to the side surface of the metal electrode 23 other than the side facing the upper arm 10.

また，ゲート電極端子１５は，ボンディングワイヤを介してＩＧＢＴ素子１１のゲート電極部と電気的に接続されている。一方，ゲート電極２５は，ボンディングワイヤを介してＩＧＢＴ素子２５のゲート電極部と電気的に接続されている。   The gate electrode terminal 15 is electrically connected to the gate electrode portion of the IGBT element 11 through a bonding wire. On the other hand, the gate electrode 25 is electrically connected to the gate electrode portion of the IGBT element 25 through a bonding wire.

また，半導体モジュール１００は，上アーム１０と下アーム２０との間の位置に，両アームを電気的に接続する中間接続部４を有している。具体的に，中間接続部４は，上アーム１０の金属電極１４の側面のうち，下アーム２０と対向する側の側面と，下アーム２０の金属電極２３の側面のうち，上アーム１０と対向する側の側面とにそれぞれ接合しており，両金属電極間を電気的に接続している。すなわち，金属電極１４と金属電極２３とは中間接続部４を介して一体になっている（以下，内部配線である金属電極１３，２３および中間接続部４が一体となった部分を「中間端子」とする）。   In addition, the semiconductor module 100 includes an intermediate connection portion 4 that electrically connects both arms at a position between the upper arm 10 and the lower arm 20. Specifically, the intermediate connection portion 4 faces the upper arm 10 among the side surfaces of the metal electrode 14 of the upper arm 10 facing the lower arm 20 and the side surface of the metal electrode 23 of the lower arm 20. The two metal electrodes are electrically connected to each other. That is, the metal electrode 14 and the metal electrode 23 are integrated via the intermediate connection portion 4 (hereinafter, the portion where the metal electrodes 13 and 23 and the intermediate connection portion 4 as internal wiring are integrated is referred to as “intermediate terminal”. ”).

すなわち，正極側取出し端子１および負極側取出し端子２と，中間接続部４とはともに上アーム１０と下アーム２０との間に位置している。そのため，両者は互いに近接しており，半導体モジュール１００の上面側から見ると対向配置となっている。   That is, the positive electrode side extraction terminal 1 and the negative electrode side extraction terminal 2 and the intermediate connection portion 4 are both located between the upper arm 10 and the lower arm 20. Therefore, both are close to each other, and are opposed to each other when viewed from the upper surface side of the semiconductor module 100.

また，各外部端子および各金属電極には，Ｃｕ，Ｃｕ系合金，あるいはＡｌ，Ａｌ系合金が使用される。これらの金属によって各半導体素子を挟み込むことにより，各半導体素子から発生した熱が上面と下面との両面から放熱される。すなわち，各金属電極および各金属端子が放熱板としての機能を兼ねており，上面と下面との２方向の放熱を行う。そのため，半導体モジュール１００は，高放熱性を備える。   Further, Cu, Cu-based alloy, Al, Al-based alloy is used for each external terminal and each metal electrode. By sandwiching each semiconductor element with these metals, heat generated from each semiconductor element is dissipated from both the upper surface and the lower surface. That is, each metal electrode and each metal terminal also function as a heat sink, and perform heat radiation in two directions, the upper surface and the lower surface. Therefore, the semiconductor module 100 has high heat dissipation.

続いて，半導体モジュール１００内の主電流の流れについて図６を基に説明する。なお，図６中の矢印は電流の流れの向きを示しており，ＩＰ１，ＩＱ１，ＩＰ２，ＩＵ，ＩＮ１，ＩＱ２，ＩＮ２はそれぞれ電流を意味しており，図１の回路図中の同記号と同義である。   Next, the flow of the main current in the semiconductor module 100 will be described with reference to FIG. The arrows in FIG. 6 indicate the direction of current flow, and IP1, IQ1, IP2, IU, IN1, IQ2, and IN2 represent currents, respectively, and the same symbols in the circuit diagram of FIG. It is synonymous.

上アーム１０のＩＧＢＴ素子１１がオンで下アーム２０のＩＧＢＴ素子２１がオフでの場合は，電源＋端子の正極側取出し端子１から内部端子部に向けて電流が流れる（ＩＰ１）。そして，ＩＧＢＴ素子１１を経由し（ＩＱ１），中間端子の中間取出し端子３に向けて電流が流れる（ＩＰ２，ＩＵ）。   When the IGBT element 11 of the upper arm 10 is on and the IGBT element 21 of the lower arm 20 is off, a current flows from the positive terminal 1 of the power source + terminal toward the internal terminal (IP1). Then, a current flows through the IGBT element 11 (IQ1) toward the intermediate extraction terminal 3 of the intermediate terminal (IP2, IU).

一方，上アーム１０のＩＧＢＴ素子１１がオフで下アーム２０のＩＧＢＴ素子２１がオンでの場合は，中間端子の中間取出し端子３から内部端子部に向けて電流が流れる（ＩＮ２）。そして，中間接続部を経由し（ＩＮ２），さらにＩＧＢＴ素子２１を経由する（ＩＱ２）。そして，ＩＧＢＴ素子２１から電源−端子の負極側取出し端子２に向けて電流が流れる（ＩＮ１）。   On the other hand, when the IGBT element 11 of the upper arm 10 is off and the IGBT element 21 of the lower arm 20 is on, a current flows from the intermediate extraction terminal 3 of the intermediate terminal toward the internal terminal portion (IN2). Then, it passes through the intermediate connection part (IN2) and further passes through the IGBT element 21 (IQ2). Then, a current flows from the IGBT element 21 toward the negative output terminal 2 of the power source terminal (IN1).

続いて，導体間の相互インダクタンスのシミュレーション結果について説明する。本シミュレーションでは，図７に示すように導体Ａ，導体Ｂを用意し，両導体の平面同士が対向するように厚さ方向に並行配置する。導体Ａ，Ｂは，ともに幅８ｍｍ×長さ５０ｍｍ×厚さ１ｍｍのサイズであり，各導体の自己インダクタンスは３０ｎＨである。このように配置した導体Ａ，Ｂの，相互インダクタンスと導体間距離との関係を図８に示す。図８のグラフに示すように，導体Ａ，Ｂ間の距離が狭いほど相互インダクタンスの値が大きいことがわかる。   Next, a simulation result of mutual inductance between conductors will be described. In this simulation, conductor A and conductor B are prepared as shown in FIG. 7, and are arranged in parallel in the thickness direction so that the planes of both conductors face each other. Each of the conductors A and B has a size of width 8 mm × length 50 mm × thickness 1 mm, and the self-inductance of each conductor is 30 nH. FIG. 8 shows the relationship between the mutual inductance and the distance between the conductors A and B arranged in this way. As shown in the graph of FIG. 8, it can be seen that the smaller the distance between the conductors A and B, the larger the mutual inductance value.

具体的に，導体Ａ，導体Ｂ間の距離を１ｍｍとし，各導体にそれぞれ逆向きの電流を同時に流す。その場合，各導体に負の相互インダクタンス２５ｎＨが生じる。この相互インダクタンスが各導体の自己インダクタンスを低減させ，結果として各導体のインダクタンスは５ｎＨとなる。すなわち，本シミュレーションの構成では，導体Ａ，導体Ｂ間の距離を１ｍｍとし，逆向きの電流を同時に流すことにより，各導体のインダクタンスが１／６に低減することがわかる。   Specifically, the distance between the conductor A and the conductor B is set to 1 mm, and reverse currents are simultaneously supplied to the conductors. In that case, a negative mutual inductance of 25 nH is generated in each conductor. This mutual inductance reduces the self-inductance of each conductor, resulting in an inductance of each conductor of 5 nH. That is, in the configuration of this simulation, it can be seen that the inductance of each conductor is reduced to 1/6 by setting the distance between the conductor A and the conductor B to 1 mm and simultaneously flowing reverse currents.

続いて，本形態の半導体装置１００におけるインダクタンスの低減効果について検討する。相互インダクタンスを利用してインダクタンスの低減を図るには，電流変化量が等しくかつ電流の向きが互いに逆向きの導体同士を近接配置することが条件となる。そこで，スイッチング時における電流の変化を図９ないし図１２に示す。なお，図９は，ＩＵ＞０で，上アームがＯＮからＯＦＦ，下アームがＯＦＦからＯＮになる瞬間の電流変化を示している。図１０は，ＩＵ＜０で，上アームがＯＮからＯＦＦ，下アームがＯＦＦからＯＮになる瞬間の電流変化を示している。図１１は，ＩＵ＞０で，上アームがＯＦＦからＯＮ，下アームがＯＮからＯＦＦになる瞬間の電流変化を示している。図１２は，ＩＵ＜０で，上アームがＯＦＦからＯＮ，下アームがＯＮからＯＦＦになる瞬間の電流変化を示している。   Next, the inductance reduction effect in the semiconductor device 100 of this embodiment will be examined. In order to reduce the inductance by using the mutual inductance, it is necessary to arrange the conductors having the same amount of current change and the opposite directions of the current in proximity to each other. Therefore, changes in current during switching are shown in FIGS. FIG. 9 shows the current change at the moment when IU> 0, the upper arm is turned from ON to OFF, and the lower arm is turned from OFF to ON. FIG. 10 shows the current change at the moment when IU <0, the upper arm is turned from ON to OFF, and the lower arm is turned from OFF to ON. FIG. 11 shows the current change at the moment when IU> 0, the upper arm is turned from OFF to ON, and the lower arm is turned from ON to OFF. FIG. 12 shows the current change at the moment when IU <0, the upper arm is turned from OFF to ON, and the lower arm is turned from ON to OFF.

図９に示したように，ＩＵ＞０で，上アームがＯＮからＯＦＦ，下アームがＯＦＦからＯＮになると，瞬間的に，上アームの電流（ＩＰ１，ＩＱ１，ＩＰ２）が減少するため，電流変化率が負の値となる。一方，上アームのＩＧＢＴ素子がＯＦＦしたとしても電流ＩＵを流し続けようと作用することから，下アームに流れる負の電流（ＩＮ２，ＩＤ２，ＩＮ１）が増加する。そのため，電流変化率がやはり同様に負の値となる。このとき，上アームのダイオード素子および下アームのＩＧＢＴ素子には電流が流れないため，ＩＤ１とＩＱ２は０のままである。この結果，（ＩＰ１，ＩＱ１，ＩＰ２）と（ＩＮ２，ＩＤ２，ＩＮ１）とを対向配置させると良いことがわかる。   As shown in FIG. 9, when IU> 0, the upper arm is turned from ON to OFF, and the lower arm is turned from OFF to ON, the current (IP1, IQ1, IP2) of the upper arm instantaneously decreases. The rate of change is negative. On the other hand, even if the IGBT element of the upper arm is turned off, the current IU continues to flow, so the negative current (IN2, ID2, IN1) flowing through the lower arm increases. For this reason, the current change rate is similarly negative. At this time, since no current flows through the diode element of the upper arm and the IGBT element of the lower arm, ID1 and IQ2 remain 0. As a result, it can be seen that (IP1, IQ1, IP2) and (IN2, ID2, IN1) are preferably arranged to face each other.

同様に，図１０に示した場合では，上アームがＯＮからＯＦＦとなることから，上アームの電流（ＩＰ１，ＩＤ１，ＩＰ２）が減少する。そのため，電流変化率が正の値となる。一方，下アームでは，ＯＦＦからＯＮになることから，正の電流（ＩＮ２，ＩＱ２，ＩＮ１）が増加する。そのため，電流変化率が同じく正の値となる。従って，（ＩＮ２，ＩＱ２，ＩＮ１）と（ＩＰ１，ＩＤ１，ＩＰ２）とを対向配置させると良いことがわかる。   Similarly, in the case shown in FIG. 10, since the upper arm is turned from ON to OFF, the current (IP1, ID1, IP2) of the upper arm decreases. Therefore, the current change rate becomes a positive value. On the other hand, since the lower arm is turned from OFF to ON, the positive current (IN2, IQ2, IN1) increases. Therefore, the current change rate is also a positive value. Therefore, it can be seen that (IN2, IQ2, IN1) and (IP1, ID1, IP2) are preferably arranged to face each other.

また，図１１に示した場合では，下アームがＯＮからＯＦＦになることから，下アームの電流（ＩＮ２，ＩＤ２，ＩＮ１）が減少する。そのため，電流変化率が正の値となる。一方，上アームでは，ＯＦＦからＯＮになることから，正の電流（ＩＰ１，ＩＱ１，ＩＰ２）が増加する。そのため，電流変化率が同じく正の値となる。従って，（ＩＰ１，ＩＱ１，ＩＰ２）と（ＩＮ２，ＩＤ２，ＩＮ１）とを対向配置させると良いことがわかる。   In the case shown in FIG. 11, since the lower arm is turned from ON to OFF, the current (IN2, ID2, IN1) of the lower arm decreases. Therefore, the current change rate becomes a positive value. On the other hand, in the upper arm, the positive current (IP1, IQ1, IP2) increases because it is turned from OFF to ON. Therefore, the current change rate is also a positive value. Therefore, it can be seen that (IP1, IQ1, IP2) and (IN2, ID2, IN1) are preferably arranged to face each other.

また，図１２に示した場合では，下アームがＯＮからＯＦＦになることから，下アームの電流（ＩＮ２，ＩＱ２，ＩＮ１）が減少する。そのため，電流変化率が負の値となる。一方，上アームでは，ＯＦＦからＯＮになることから，負の電流（ＩＰ１，ＩＤ１，ＩＰ２）が増加する。そのため，電流変化率が同じく負の値となる。従って，（ＩＮ２，ＩＱ２，ＩＮ１）と（ＩＰ１，ＩＤ１，ＩＰ２）とを対向配置させると良いことがわかる。   In the case shown in FIG. 12, since the lower arm is turned from ON to OFF, the current (IN2, IQ2, IN1) of the lower arm decreases. Therefore, the current change rate becomes a negative value. On the other hand, since the upper arm is turned from OFF to ON, negative currents (IP1, ID1, IP2) increase. For this reason, the current change rate is also negative. Therefore, it can be seen that (IN2, IQ2, IN1) and (IP1, ID1, IP2) are preferably arranged to face each other.

すなわち，図９ないし図１２に示したすべてのケースで相互インダクタンスを利用するためには，ＩＰ１，ＩＰ２が流れる部位とＩＮ１，ＩＮ２が流れる部位とを対向させると良いことがわかる。   That is, it can be seen that in order to use the mutual inductance in all cases shown in FIGS. 9 to 12, it is preferable that the part where IP1 and IP2 flow is opposite to the part where IN1 and IN2 flow.

そこで，本形態の半導体モジュール１００では，特に次の４箇所で相互インダクタンスによる寄生インダクタンスの低減効果が期待できる。１箇所目は，電源＋端子の正極側取出し端子１と，電源−端子の負極側取出し端子２とが対向する部位である（図６中の（１））。すなわち，正極側取出し端子１と負極側取出し端子２とが対向配置されており，それらを流れるＩＰ１とＩＮ１とが互いに逆向きである。従って，寄生インダクタンス（インダクタンスＬ１，Ｌ４）の低減が図られる。   Therefore, in the semiconductor module 100 of the present embodiment, the effect of reducing the parasitic inductance due to the mutual inductance can be expected particularly at the following four locations. The first part is a portion where the positive electrode side extraction terminal 1 of the power source + terminal and the negative electrode side extraction terminal 2 of the power source terminal are opposed to each other ((1) in FIG. 6). That is, the positive electrode side extraction terminal 1 and the negative electrode side extraction terminal 2 are arranged to face each other, and IP1 and IN1 flowing through them are opposite to each other. Therefore, the parasitic inductance (inductances L1 and L4) can be reduced.

２箇所目は，電源＋端子の金属電極１３の取出し部近傍と，中間端子の中間接続部４とが対向する部位である（図６中の（２））。すなわち，電流ＩＰ１が流れる金属電極１３と，電流ＩＮ２が流れる中間接続部４とが対向配置されていることから，寄生インダクタンス（インダクタンスＬ１，Ｌ３）の低減が図られる。   The second part is a part where the vicinity of the take-out part of the metal electrode 13 of the power source + terminal and the intermediate connection part 4 of the intermediate terminal face each other ((2) in FIG. 6). That is, since the metal electrode 13 through which the current IP1 flows and the intermediate connection portion 4 through which the current IN2 flows are arranged to face each other, parasitic inductance (inductances L1 and L3) can be reduced.

３箇所目は，中間端子の中間接続部４と，電源−端子の金属電極２４の取出し部近傍とが対向する部位である（図６中の（３））。すなわち，電流ＩＮ２が流れる中間接続部４と，電流ＩＮ１が流れる金属電極２４とが対向配置されていることから，寄生インダクタンス（インダクタンスＬ３，Ｌ４）の低減が図られる。   The third place is a portion where the intermediate connection portion 4 of the intermediate terminal and the vicinity of the take-out portion of the metal electrode 24 of the power source-terminal face each other ((3) in FIG. 6). That is, since the intermediate connection portion 4 through which the current IN2 flows and the metal electrode 24 through which the current IN1 flows are disposed to face each other, parasitic inductance (inductances L3 and L4) can be reduced.

４箇所目は，中間端子の金属電極部２３と，電源−端子の金属電極２４とが対向する部位である（図６中の（４））。すなわち，電流ＩＮ２が流れる金属電極２３と，電流ＩＮ１が流れる金属電極２４とが対向配置されていることから，寄生インダクタンス（インダクタンスＬ３，Ｌ４）の低減が図られる。   The fourth part is a part where the metal electrode part 23 of the intermediate terminal and the metal electrode 24 of the power source-terminal face each other ((4) in FIG. 6). That is, since the metal electrode 23 through which the current IN2 flows and the metal electrode 24 through which the current IN1 flows are arranged to face each other, parasitic inductance (inductances L3 and L4) can be reduced.

一方，特許文献１（従来の形態）で示した半導体装置では，図１３に示すように電流が流れる。この半導体装置では，確かに外部端子部同士が対向している（図１３中の（１’））。しかしながら，外部端子部間の距離が大きく，相互インダクタンスが小さい。そのため，相互インダクタンスによる寄生インダクタンスの低減が期待できない。また，内部端子部同士についても，中間端子内を流れる電流の向きとそれ以外の端子内を流れる電流の向きとが直交に近い角度で交わる（図１３中の（２’））。そのため，相互インダクタンスによる寄生インダクタンスの低減が期待できない。   On the other hand, in the semiconductor device shown in Patent Document 1 (conventional form), a current flows as shown in FIG. In this semiconductor device, the external terminal portions are certainly facing each other ((1 ′) in FIG. 13). However, the distance between the external terminals is large and the mutual inductance is small. Therefore, reduction of parasitic inductance due to mutual inductance cannot be expected. As for the internal terminal portions, the direction of the current flowing in the intermediate terminal and the direction of the current flowing in the other terminals intersect at an angle close to orthogonal ((2 ') in FIG. 13). Therefore, reduction of parasitic inductance due to mutual inductance cannot be expected.

以上詳細に説明したように本形態の半導体モジュール１００は，上アーム部１０と下アーム部２０とが一組であり，各アームを構成する半導体素子が一対の金属電極に挟み込まれた構造を有することとしている。すなわち，両面放熱構造を備えており，高放熱性を有している。また，上アーム１０と下アーム２０との間には，両アームを電気的に接続する中間接続部４を設けることとしている。さらに，上アーム１０では，正極側取出し端子１を中間接続部４と接合する側面と同じ側面に設けることとしている。また，下アーム２０では，負極側取出し端子２を中間接続部４と接合する側面と同じ側面に設けることとしている。そのため，各金属電極のうち，電源取出し端子と接合する部位および中間接続部４と接合する部位の近傍領域では，主電流の対向成分が多い。そのため，それらの領域部分での寄生インダクタンスの低減が図られる。従って，上アームと下アームとが一組となった半導体モジュールであって，高放熱性を備えつつ寄生インダクタンスの低減が図られた半導体モジュールが実現されている。   As described in detail above, the semiconductor module 100 of this embodiment has a structure in which the upper arm portion 10 and the lower arm portion 20 are a set, and the semiconductor elements constituting each arm are sandwiched between a pair of metal electrodes. I am going to do that. That is, it has a double-sided heat dissipation structure and has high heat dissipation. Further, between the upper arm 10 and the lower arm 20, an intermediate connection portion 4 that electrically connects both arms is provided. Further, in the upper arm 10, the positive electrode side extraction terminal 1 is provided on the same side surface as the side surface joined to the intermediate connection portion 4. In the lower arm 20, the negative electrode side extraction terminal 2 is provided on the same side surface as the side surface joined to the intermediate connection portion 4. For this reason, among the metal electrodes, there are many opposing components of the main current in the region near the portion where the power supply terminal is joined and the portion where the intermediate connection portion 4 is joined. Therefore, it is possible to reduce the parasitic inductance in those areas. Therefore, a semiconductor module in which the upper arm and the lower arm are combined as one set and having a high heat dissipation property and a reduction in parasitic inductance is realized.

また，半導体モジュール１００では，外部端子部である正極側取出し端子１と負極側取出し端子２とがその平面同士で対向することとしている。すなわち，半導体モジュールの上面からみて正極側取出し端子１と負極側取出し端子２とが重ね合わせられた配置となっている。そのため，両端子間の距離が狭く，相互インダクタンスの値が大きい。よって，インダクタンスの低減の効果が大きい。   Further, in the semiconductor module 100, the positive electrode side extraction terminal 1 and the negative electrode side extraction terminal 2 which are external terminal portions are opposed to each other on their planes. That is, when viewed from the top surface of the semiconductor module, the positive electrode side extraction terminal 1 and the negative electrode side extraction terminal 2 are superposed. Therefore, the distance between both terminals is narrow and the mutual inductance value is large. Therefore, the effect of reducing inductance is great.

なお，本実施の形態は単なる例示にすぎず，本発明を何ら限定するものではない。したがって本発明は当然に，その要旨を逸脱しない範囲内で種々の改良，変形が可能である。例えば，半導体素子の配置は，実施の形態に限定するものではない。すなわち，対向する金属電極内を流れる電流の向きが逆向きとなるような配置であればよい。   Note that this embodiment is merely an example, and does not limit the present invention. Therefore, the present invention can naturally be improved and modified in various ways without departing from the gist thereof. For example, the arrangement of the semiconductor elements is not limited to the embodiment. In other words, the arrangement may be such that the direction of the current flowing in the opposing metal electrode is opposite.

また，各アームを構成するＩＧＢＴ素子，ダイオード素子の個数は１つずつに限るものではない。すなわち，図１４や図１５に示すように１つのアームに複数個のＩＧＢＴ素子，ダイオード素子を配置してもよい。なお，図１６に，図１４および図１５に示した半導体モジュールの等価回路を示す。   Further, the number of IGBT elements and diode elements constituting each arm is not limited to one. That is, as shown in FIGS. 14 and 15, a plurality of IGBT elements and diode elements may be arranged on one arm. FIG. 16 shows an equivalent circuit of the semiconductor module shown in FIGS.

実施の形態にかかる半導体モジュールの等価回路を示す図である。It is a figure which shows the equivalent circuit of the semiconductor module concerning embodiment. 実施の形態にかかる半導体モジュールの上面および側面から見た外観を示す図である。It is a figure which shows the external appearance seen from the upper surface and side surface of the semiconductor module concerning embodiment. 図２に示した半導体モジュールのＡ−Ａ断面を示す図である。It is a figure which shows the AA cross section of the semiconductor module shown in FIG. 図３に示した半導体モジュールのＢ−Ｂ断面を示す図である。It is a figure which shows the BB cross section of the semiconductor module shown in FIG. 図３に示した半導体モジュールのＣ−Ｃ断面を示す図である。It is a figure which shows CC cross section of the semiconductor module shown in FIG. 実施の形態にかかる半導体モジュールの，半導体素子の配置および主電流の流れを示す図である。It is a figure which shows arrangement | positioning of a semiconductor element, and the flow of main current of the semiconductor module concerning embodiment. シミュレーションにかかる導体Ａ，Ｂの配置を示す図である。It is a figure which shows arrangement | positioning of the conductors A and B concerning a simulation. 図７に示した配置における相互インダクタンスと導体間距離との関係を示すグラフである。It is a graph which shows the relationship between the mutual inductance in the arrangement | positioning shown in FIG. 7, and the distance between conductors. スイッチング時（ＩＵ＞０，上アームＯＮからＯＦＦ，下アームＯＦＦからＯＮ）における電流の変化を示す図である。It is a figure which shows the change of the electric current at the time of switching (IU> 0, upper arm ON to OFF, lower arm OFF to ON). スイッチング時（ＩＵ＜０，上アームＯＮからＯＦＦ，下アームＯＦＦからＯＮ）における電流の変化を示す図である。It is a figure which shows the change of the electric current at the time of switching (IU <0, upper arm ON to OFF, lower arm OFF to ON). スイッチング時（ＩＵ＞０，上アームＯＦＦからＯＮ，下アームＯＮからＯＦＦ）における電流の変化を示す図である。It is a figure which shows the change of the electric current at the time of switching (IU> 0, upper arm OFF to ON, lower arm ON to OFF). スイッチング時（ＩＵ＜０，上アームＯＦＦからＯＮ，下アームＯＮからＯＦＦ）における電流の変化を示す図である。It is a figure which shows the change of the electric current at the time of switching (IU <0, upper arm OFF to ON, lower arm ON to OFF). 従来の形態にかかる半導体モジュールの，半導体素子の配置および主電流の流れを示す図である。It is a figure which shows arrangement | positioning of a semiconductor element, and the flow of main current of the semiconductor module concerning the conventional form. 半導体素子の配置の応用例を示す図（その１）である。It is FIG. (1) which shows the application example of arrangement | positioning of a semiconductor element. 半導体素子の配置の応用例を示す図（その２）である。It is FIG. (2) which shows the application example of arrangement | positioning of a semiconductor element. 応用例にかかる半導体モジュールの等価回路を示す図である。It is a figure which shows the equivalent circuit of the semiconductor module concerning an application example. 上アームと下アームとが一組となった半導体モジュールの等価回路を示す図である。It is a figure which shows the equivalent circuit of the semiconductor module with which the upper arm and the lower arm became one set. 従来の形態にかかる半導体モジュールの外観を示す斜視図である。It is a perspective view which shows the external appearance of the semiconductor module concerning the conventional form.

符号の説明Explanation of symbols

１ 正極側取出し端子（正極側取出し端子）
２ 負極側取出し端子（負極側取出し端子）
３ 中間取出し端子
４ 中間接続部（中間接続部）
６ 樹脂
１０ 上アーム（上アーム部）
１１ ＩＧＢＴ素子（第１半導体素子群）
１２ ダイオード素子（第１半導体素子群）
１３ 金属電極（第１金属電極）
１４ 金属電極（第２金属電極）
１５ ゲート電極端子
２０ 下アーム（下アーム部）
２１ ＩＧＢＴ素子（第２半導体素子群）
２２ ダイオード素子（第２半導体素子群）
２３ 金属電極（第３金属電極）
２４ 金属電極（第４金属電極）
２５ ゲート電極端子
１００ 半導体モジュール（半導体モジュール） 1 Positive side extraction terminal (Positive side extraction terminal)
2 Negative side extraction terminal (Negative side extraction terminal)
3 Intermediate extraction terminal 4 Intermediate connection (intermediate connection)
6 Resin 10 Upper arm (upper arm)
11 IGBT element (first semiconductor element group)
12 Diode element (first semiconductor element group)
13 Metal electrode (first metal electrode)
14 Metal electrode (second metal electrode)
15 Gate electrode terminal 20 Lower arm (lower arm)
21 IGBT element (second semiconductor element group)
22 Diode element (second semiconductor element group)
23 Metal electrode (third metal electrode)
24 Metal electrode (4th metal electrode)
25 Gate electrode terminal 100 Semiconductor module (semiconductor module)

Claims (5)

上アーム部を構成する第１半導体素子群と，下アーム部を構成する第２半導体素子群とを備え，前記第１半導体素子群と前記第２半導体素子群とを同一平面内に配置した半導体モジュールにおいて，
前記第１半導体素子群の一方の面側に位置する第１金属電極と，
前記第１半導体素子群の他方の面側に位置し，前記第１半導体素子群を挟んで前記第１金属電極と対向する第２金属電極と，
前記第２半導体素子群の一方の面側に位置し，前記第２金属電極と電気的に接続された第３金属電極と，
前記第２半導体素子群の他方の面側に位置し，前記第２半導体素子群を挟んで前記第３金属電極と対向する第４金属電極と，
一方の端部が前記第２金属電極のうちの前記下アーム部と対向する部位と接合し，他方の端部が前記第３金属電極のうちの前記上アーム部と対向する部位と接合し，前記第２金属電極と前記第３金属電極とを電気的に接続する中間接続部と，
前記第１金属電極のうちの前記下アーム部と対向する部位と接合する平板状の正極側取出し端子と，
前記第４金属電極のうちの前記上アーム部と対向する部位と接合する平板状の負極側取出し端子とを備えることを特徴とする半導体モジュール。 A semiconductor comprising a first semiconductor element group constituting an upper arm part and a second semiconductor element group constituting a lower arm part, wherein the first semiconductor element group and the second semiconductor element group are arranged in the same plane In the module,
A first metal electrode located on one surface side of the first semiconductor element group;
A second metal electrode located on the other surface side of the first semiconductor element group and facing the first metal electrode across the first semiconductor element group;
A third metal electrode located on one surface side of the second semiconductor element group and electrically connected to the second metal electrode;
A fourth metal electrode positioned on the other surface side of the second semiconductor element group and facing the third metal electrode across the second semiconductor element group;
One end is joined to a part of the second metal electrode facing the lower arm part, and the other end is joined to a part of the third metal electrode facing the upper arm part, An intermediate connection portion for electrically connecting the second metal electrode and the third metal electrode;
A plate-like positive electrode side extraction terminal joined to a portion of the first metal electrode facing the lower arm portion;
A semiconductor module comprising: a flat-plate-like negative electrode side extraction terminal joined to a portion of the fourth metal electrode facing the upper arm portion. 請求項１に記載する半導体モジュールにおいて，
前記第１金属電極を流れる主電流の向きが前記第２金属電極を流れる主電流の向きと略反対となるように前記第１半導体素子群を配置し，前記第３金属電極を流れる主電流の向きが前記第４金属電極を流れる主電流の向きと略反対となるように前記第２半導体素子群を配置することを特徴とする半導体モジュール。 The semiconductor module according to claim 1,
The first semiconductor element group is arranged such that the direction of the main current flowing through the first metal electrode is substantially opposite to the direction of the main current flowing through the second metal electrode, and the main current flowing through the third metal electrode is 2. The semiconductor module according to claim 1, wherein the second semiconductor element group is disposed so that a direction is substantially opposite to a direction of a main current flowing through the fourth metal electrode. 請求項１または請求項２に記載する半導体モジュールにおいて，
電極面から見て，前記第１半導体素子群を構成する半導体素子と，前記第２半導体素子群を構成する半導体素子とが同一直線上に配置されていることを特徴とする半導体モジュール。 In the semiconductor module according to claim 1 or 2,
A semiconductor module, wherein a semiconductor element constituting the first semiconductor element group and a semiconductor element constituting the second semiconductor element group are arranged on the same straight line when viewed from the electrode surface. 請求項１から請求項３のいずれか１つに記載する半導体モジュールにおいて，
前記正極側取出し端子と前記負極側取出し端子とは，その平面同士が対向していることを特徴とする半導体モジュール。 In the semiconductor module according to any one of claims 1 to 3,
The semiconductor module according to claim 1, wherein the positive electrode side extraction terminal and the negative electrode side extraction terminal are opposed to each other. 上アーム部を構成する第１半導体素子群と，下アーム部を構成する第２半導体素子群とを備え，前記第１半導体素子群と前記第２半導体素子群とを同一平面内に配置した半導体モジュールにおいて，
前記第１半導体素子群の一方の面側に位置する第１金属電極と，
前記第１半導体素子群の他方の面側に位置し，前記第１半導体素子群を挟んで前記第１金属電極と対向する第２金属電極と，
前記第２半導体素子群の一方の面側に位置し，前記第２金属電極と電気的に接続された第３金属電極と，
前記第２半導体素子群の他方の面側に位置し，前記第２半導体素子群を挟んで前記第３金属電極と対向する第４金属電極と，
前記第１金属電極と電気的に接続された平板状の正極側取出し端子と，
前記第４金属電極と電気的に接続された平板状の負極側取出し端子とを備え，
前記正極側取出し端子と前記負極側取出し端子とは，その平面同士が対向していることを特徴とする半導体モジュール。 A semiconductor comprising a first semiconductor element group constituting an upper arm part and a second semiconductor element group constituting a lower arm part, wherein the first semiconductor element group and the second semiconductor element group are arranged in the same plane In the module,
A first metal electrode located on one surface side of the first semiconductor element group;
A second metal electrode located on the other surface side of the first semiconductor element group and facing the first metal electrode across the first semiconductor element group;
A third metal electrode located on one surface side of the second semiconductor element group and electrically connected to the second metal electrode;
A fourth metal electrode positioned on the other surface side of the second semiconductor element group and facing the third metal electrode across the second semiconductor element group;
A plate-like positive electrode side extraction terminal electrically connected to the first metal electrode;
A flat negative electrode side extraction terminal electrically connected to the fourth metal electrode,
The semiconductor module according to claim 1, wherein the positive electrode side extraction terminal and the negative electrode side extraction terminal are opposed to each other.
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