JP2006222138A - Method for forming through-electrode - Google Patents

Method for forming through-electrode Download PDF

Info

Publication number
JP2006222138A
JP2006222138A JP2005031829A JP2005031829A JP2006222138A JP 2006222138 A JP2006222138 A JP 2006222138A JP 2005031829 A JP2005031829 A JP 2005031829A JP 2005031829 A JP2005031829 A JP 2005031829A JP 2006222138 A JP2006222138 A JP 2006222138A
Authority
JP
Japan
Prior art keywords
electrode
stop layer
semiconductor substrate
forming
etching stop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005031829A
Other languages
Japanese (ja)
Inventor
Masanao Kamakura
將有 鎌倉
Kaoru Tone
薫 戸根
Takashi Saijo
隆司 西條
Akira Tomoida
亮 友井田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP2005031829A priority Critical patent/JP2006222138A/en
Publication of JP2006222138A publication Critical patent/JP2006222138A/en
Pending legal-status Critical Current

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for forming a through-electrode by which an yield can be improved and a formation step is simplified. <P>SOLUTION: The method is used to form a through-electrode penetrating in the direction the thickness of a semiconductor substrate. The method includes: a first step wherein a first insulating film 2a is formed on the front surface of a semiconductor substrate 1, a second insulating film 2b is formed on the rear surface of the semiconductor substrate 1, and a first etching stop layer 3 made of a conductive member such as a metallic layer or the like having an etching rate different from that of the semiconductor substrate 1 is formed on the second insulating film 2b; a second step wherein the formation objective portion of the through-electrode 7 is etched up to the first etching stop layer 3 to form a recessed part 4; and a third step wherein the first etching stop layer 3 is used as a seed layer, and the recessed part 4 is plated by using bottom-up growth so as to form the through-electrode 7. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、例えば、３次元実装等に用いる半導体基板の厚み方向に貫通する貫通電極の形成方法に関するものである。   The present invention relates to a method for forming a through electrode penetrating in the thickness direction of a semiconductor substrate used for, for example, three-dimensional mounting.

従来の貫通電極の形成方法としては、図４に示すような半導体基板１００の厚み方向に貫通する貫通電極の形成方法があり、図４（ａ）に示すように、半導体基板１００にエッチング加工等により凹部１０１を形成し、凹部１０１の内壁や半導体基板１００表裏面に絶縁層１０２を形成した後、図４（ｂ）、（ｃ）、（ｄ）に示すように、絶縁層１０２上に例えばＣＶＤ（Chemical Vapor Deposition）法やスパッタ法で金属薄膜１０３を堆積させ、金属薄膜１０３をシード層として一般的にコンフォーマル成長と呼ばれるメッキ方法で凹部１０１に配線材料１０４を充填し、図４（e）に示すように、最後に、不要箇所の配線材料１０４を除去し、ＣＭＰ（Chemical Mechanical Planarization）等によって半導体基板１００を研磨して貫通電極１０５を露出させる方法を挙げることができる。   As a conventional through electrode forming method, there is a through electrode forming method penetrating in the thickness direction of the semiconductor substrate 100 as shown in FIG. 4, and as shown in FIG. After forming the recess 101 and forming the insulating layer 102 on the inner wall of the recess 101 and the front and back surfaces of the semiconductor substrate 100, as shown in FIGS. 4B, 4C, and 4D, for example, on the insulating layer 102 A metal thin film 103 is deposited by a CVD (Chemical Vapor Deposition) method or a sputtering method. The metal thin film 103 is used as a seed layer to fill the recess 101 with a wiring material 104 by a plating method generally called conformal growth. Finally, the wiring material 104 in unnecessary portions is removed and the semiconductor substrate 100 is polished by CMP (Chemical Mechanical Planarization) or the like to expose the through electrode 105 as shown in FIG. The method can be mentioned.

このような貫通電極の形成方法においては、凹部１０１が高アスペクト比（深さが開口に対して大きい）であったり、凹部１０１の開口部側が底部側よりも狭まっているような場合、凹部１０１の開口部側が先に塞がってしまい、メッキが充填されない空隙が存在する可能性があった。   In such a through electrode forming method, when the recess 101 has a high aspect ratio (depth is larger than the opening) or the opening side of the recess 101 is narrower than the bottom side, the recess 101 There was a possibility that the opening side was closed first, and there was a gap that was not filled with plating.

そこで、このような空隙の生成という問題点を解決した貫通電極の形成方法として、図５（ａ）に示すように、金属等の導電層２０２が表面に形成された基板２０３を、図５（ｂ）に示すように、エッチング加工等により貫通孔２０１を形成した半導体基板２００に接合や貼り合わせ等で一体化し（図５（ｃ））、貫通孔２０１の底部側から半導体基板２００の厚み方向へ、導電層２０２をシード層としてボトムアップ成長と呼ばれるメッキ方法で貫通孔２０１に配線材料２０４を充填し、図５（ｄ）に示すように、不要部分の配線材料２０４を除去し、図５（ｅ）に示すように、何らかの方法で半導体基板２００から導電層２０２、基板２０３剥離して貫通電極２０５を形成する方法を挙げることができる（例えば、非特許文献１参照。）。
N T Nguyen et al,「Through-wafer copper electroplating for three-dimensional interconnects」,Journal of Micromechanics and Microengineering, (UK) ,2002,12,p.395-399 Therefore, as a through electrode forming method that solves such a problem of void formation, as shown in FIG. 5A, a substrate 203 having a conductive layer 202 made of metal or the like formed on its surface is used as shown in FIG. As shown in FIG. 5B, the semiconductor substrate 200 in which the through hole 201 is formed by etching or the like is integrated by bonding or bonding (FIG. 5C), and the thickness direction of the semiconductor substrate 200 is from the bottom side of the through hole 201. The conductive material 202 is used as a seed layer to fill the through hole 201 with the wiring material 204 by a plating method called bottom-up growth, and the unnecessary wiring material 204 is removed as shown in FIG. As shown to (e), the conductive layer 202 and the board | substrate 203 can be peeled from the semiconductor substrate 200 by a certain method, and the method of forming the penetration electrode 205 can be mentioned (for example, refer nonpatent literature 1).
NT Nguyen et al, `` Through-wafer copper electroplating for three-dimensional interconnects '', Journal of Micromechanics and Microengineering, (UK), 2002,12, p.395-399

ところが、上述のようなボトムアップ成長と呼ばれるメッキ方法を用いた貫通電極の形成方法では、メッキ後、何らかの方法で半導体基板２００から導電層２０２、基板２０３を剥離する必要があるため、結果的に工程が煩雑になるという問題点があった。   However, in the through electrode forming method using the plating method called bottom-up growth as described above, it is necessary to peel the conductive layer 202 and the substrate 203 from the semiconductor substrate 200 by some method after plating. There was a problem that the process became complicated.

また、半導体基板２００は、導電層２０２が表面に形成された基板２０３と貼り合わせ等の処理で一体化されるため、半導体基板２００と導電層２０２との界面に空隙が発生してメッキが入り込む可能性があった。   In addition, since the semiconductor substrate 200 is integrated with the substrate 203 on which the conductive layer 202 is formed by a process such as bonding, a gap is generated at the interface between the semiconductor substrate 200 and the conductive layer 202, and plating enters. There was a possibility.

本発明は上記問題点を改善するためになされたものであり、歩留まりをよくするとともに形成工程を簡略化した貫通電極の形成方法を提供することを目的とするものである。   The present invention has been made to improve the above-described problems, and an object of the present invention is to provide a method of forming a through electrode that improves the yield and simplifies the forming process.

上述の目的を達成するために、本発明の請求項１に係る貫通電極の形成方法は、半導体基板の厚み方向に貫通する貫通電極の形成方法において、前記半導体基板の表面に第１絶縁膜を形成し、前記半導体基板の裏面に第２絶縁膜を形成し、前記半導体基板とはエッチングレートの異なる導電性部材からなる第１エッチングストップ層を前記第２絶縁膜に形成する第１工程と、貫通電極の形成対象箇所に対して、前記第１エッチングストップ層までエッチングして凹部を形成する第２工程と、前記第１エッチングストップ層をシード層として用い、前記凹部に対してボトムアップ成長を用いたメッキにより電極を形成する第３工程と、を含んでいる。   In order to achieve the above-described object, a method for forming a through electrode according to claim 1 of the present invention is the method for forming a through electrode penetrating in the thickness direction of a semiconductor substrate, wherein the first insulating film is formed on the surface of the semiconductor substrate. Forming a second insulating film on the back surface of the semiconductor substrate, and forming a first etching stop layer made of a conductive member having an etching rate different from that of the semiconductor substrate on the second insulating film; A second step of forming a recess by etching up to the first etching stop layer with respect to a formation target of the through electrode, and using the first etching stop layer as a seed layer, bottom-up growth is performed on the recess. And a third step of forming electrodes by the plating used.

また、本発明の請求項２に係る貫通電極の形成方法は、半導体基板の厚み方向に貫通する貫通電極の形成方法において、前記半導体基板の表面に第１絶縁膜を形成し、前記半導体基板の裏面に第２絶縁膜を形成し、前記半導体基板とはエッチングレートの異なる導電性部材からなる第１エッチングストップ層を前記第２絶縁膜に形成した後、前記第１エッチングストップ層にレジスト膜からなる第２エッチングストップ層を形成する第１工程と、貫通電極の形成対象箇所に対して、前記第２エッチングストップ層までエッチングして凹部を形成する第２工程と、前記第１エッチングストップ層をシード層として用い、前記凹部に対してボトムアップ成長を用いたメッキにより電極を形成する第３工程と、を含んでいる。   According to a second aspect of the present invention, there is provided a method for forming a through electrode, wherein the first insulating film is formed on the surface of the semiconductor substrate, and the through electrode penetrates in the thickness direction of the semiconductor substrate. A second insulating film is formed on the back surface, a first etching stop layer made of a conductive member having an etching rate different from that of the semiconductor substrate is formed on the second insulating film, and then a resist film is formed on the first etching stop layer. A second step of forming a second etching stop layer, a second step of forming a recess by etching up to the second etching stop layer with respect to a formation target portion of the through electrode, and the first etching stop layer And a third step of forming an electrode by plating using bottom-up growth on the concave portion as a seed layer.

また、本発明の請求項３に係る貫通電極の形成方法は、請求項１又は請求項２に記載の貫通電極の形成方法において、前記第２工程は、ＲＩＥを用いてエッチングする。   According to a third aspect of the present invention, there is provided a through electrode forming method according to the first or second aspect, wherein the second step is performed using RIE.

また、本発明の請求項４に係る貫通電極の形成方法は、請求項１乃至請求項３のいずれかに記載の貫通電極の形成方法において、前記第１工程は、ＣＶＤを用いて前記第１絶縁膜及び前記第２絶縁膜を形成する。   According to a fourth aspect of the present invention, there is provided a through electrode forming method according to any one of the first to third aspects, wherein the first step uses CVD. An insulating film and the second insulating film are formed.

また、本発明の請求項５に係る貫通電極の形成方法は、請求項１乃至請求項３のいずれかに記載の貫通電極の形成方法において、前記第１工程は、熱酸化を用いて前記第１絶縁膜及び前記第２絶縁膜を形成し、前記１エッチングストップ層を高融点金属にて形成する。   A through electrode forming method according to claim 5 of the present invention is the through electrode forming method according to any one of claims 1 to 3, wherein the first step uses thermal oxidation. One insulating film and the second insulating film are formed, and the one etching stop layer is formed of a refractory metal.

このような構成の貫通電極の形成方法は、導電性部材からなる第１エッチングストップ層をそのままメッキ用のシード層として利用することで、貫通電極の形成工程が簡略化できる。   In the method of forming a through electrode having such a configuration, the first etching stop layer made of a conductive member is used as it is as a seed layer for plating, whereby the through electrode forming process can be simplified.

また、このような構成の貫通電極の形成方法は、第１エッチングストップ層又は第２エッチングストップ層をシード層とすることで、不要な箇所にメッキされることがないため、歩留まりをよくすることができる。   In addition, the method of forming the through electrode having such a configuration improves the yield because the first etching stop layer or the second etching stop layer is used as a seed layer so that unnecessary portions are not plated. Can do.

以下、本発明に係る実施形態を図面に基づいて説明する。なお、各図において、同一の符号を付した構成は、同一の構成であることを示し、その説明を省略する。   Embodiments according to the present invention will be described below with reference to the drawings. In addition, in each figure, the structure which attached | subjected the same code | symbol shows that it is the same structure, The description is abbreviate | omitted.

（第１実施形態）
本発明の第１実施形態を図１に基づいて説明する。図１は、本発明の第１実施形態に係る半導体基板に貫通する貫通電極の形成方法を示す概略断面図である。 (First embodiment)
A first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a schematic cross-sectional view illustrating a method for forming a through electrode penetrating a semiconductor substrate according to the first embodiment of the present invention.

例えば、シリコン基板を用いた半導体基板１の厚み方向に貫通する貫通電極の形成方法を図１に基づいて説明する。   For example, a method of forming a through electrode penetrating in the thickness direction of the semiconductor substrate 1 using a silicon substrate will be described with reference to FIG.

まず、図１（ａ）に示すように、例えば熱酸化法やＣＶＤ法によって、半導体基板１の厚み方向に対する表面側に第１絶縁膜２ａを、裏面側に第２絶縁膜２ｂを形成する。次に、図１（ｂ）に示すように、第２絶縁膜２ｂの裏面側全面に、例えばスパッタ法や真空蒸着法によって、半導体基板１とはエッチングレートの異なる金属層を第１エッチングストップ層３として形成する。なお、第１エッチングストップ層３のエッチングレートは、半導体基板１のエッチングレートに比べ非常に遅いものであればよい。   First, as shown in FIG. 1A, the first insulating film 2a is formed on the front surface side with respect to the thickness direction of the semiconductor substrate 1 and the second insulating film 2b is formed on the back surface side by, for example, thermal oxidation or CVD. Next, as shown in FIG. 1B, a metal layer having an etching rate different from that of the semiconductor substrate 1 is formed on the entire back surface of the second insulating film 2b by, for example, sputtering or vacuum deposition. 3 is formed. The etching rate of the first etching stop layer 3 only needs to be very slow as compared with the etching rate of the semiconductor substrate 1.

そして、第１絶縁膜２ａ側から後述の貫通電極７を形成したい所定の領域をパターニング除去して開口させて後、図１（ｃ）に示すように、例えばＲＩＥ（反応性イオンエッチング、Reactive Ion Etching）によって半導体基板１の深さ方向に第１エッチングストップ層３までエッチングして凹部４を形成する。   Then, a predetermined region in which a later-described through electrode 7 to be described later is to be formed is removed by patterning and opened from the first insulating film 2a side, and then, for example, RIE (reactive ion etching, reactive ion etching) is performed as shown in FIG. Etching) etches the first etching stop layer 3 in the depth direction of the semiconductor substrate 1 to form the recess 4.

前述のように、第１エッチングストップ層３である金属層は、半導体基板１とはエッチングレートが異なり、エッチングレートが非常に遅いため、エッチングのストップ層として利用する。   As described above, the metal layer that is the first etching stop layer 3 has an etching rate different from that of the semiconductor substrate 1 and has a very low etching rate, and thus is used as an etching stop layer.

なお、貫通電極７は、電極配線として使用する場合、配線間の絶縁性を確保する必要があるため、図１（ｄ）に示すように、凹部４の内壁にも、例えば熱酸化法やＣＶＤ法を用いて第３絶縁膜５を形成する。   Note that when the through electrode 7 is used as an electrode wiring, it is necessary to ensure insulation between the wirings. Therefore, as shown in FIG. The third insulating film 5 is formed using a method.

凹部４の内壁に熱酸化法を用いて第３絶縁膜５を形成する場合、第１エッチングストップ層３である金属層に、少なくとも熱酸化法を用いて第３絶縁膜５を形成して融解しないような高融点金属を使用すれば、第１エッチングストップ層３が例えば１０００℃を超える高温でも溶解することはない。但し、この高融点金属は、高温の雰囲気中で酸化皮膜を作りにくいものが好ましい。なお、この場合、第１エッチングストップ層３の表層にも酸化被膜等の絶縁層（不図示）が形成される可能性があるが、この場合は、エッチング等によりこの絶縁層を除去して第１エッチングストップ層３である金属層の表面が露出するようにする。   When the third insulating film 5 is formed on the inner wall of the recess 4 using the thermal oxidation method, the third insulating film 5 is formed on the metal layer as the first etching stop layer 3 using at least the thermal oxidation method and melted. If such a high melting point metal is used, the first etching stop layer 3 is not dissolved even at a high temperature exceeding 1000 ° C., for example. However, it is preferable that the refractory metal is difficult to form an oxide film in a high temperature atmosphere. In this case, an insulating layer (not shown) such as an oxide film may be formed on the surface layer of the first etching stop layer 3. In this case, the insulating layer is removed by etching or the like. The surface of the metal layer which is the 1 etching stop layer 3 is exposed.

また、熱酸化法より低温で成膜可能なＣＶＤ法を用いて凹部４の内壁に第３絶縁膜５を形成する場合、第１エッチングストップ層３の表層へ酸化被膜等の形成を避けることができる。なお、熱酸化法を用いて形成した酸化膜は、ＣＶＤ法を用いて形成した酸化膜よりも緻密で絶縁性が優れている。   Further, when the third insulating film 5 is formed on the inner wall of the recess 4 by using the CVD method capable of forming at a lower temperature than the thermal oxidation method, it is possible to avoid the formation of an oxide film or the like on the surface layer of the first etching stop layer 3. it can. Note that an oxide film formed using a thermal oxidation method is denser and has better insulating properties than an oxide film formed using a CVD method.

そして、次に、図１（ｅ）に示すように、第１エッチングストップ層３である金属層の表面をメッキ用のシード層としてボトムアップ成長と呼ばれるメッキ方法で銅等の配線材料６を凹部４に充填する。ここで、銅は、低抵抗でありメッキしやすい材料である。ここで、メッキのボトムアップ成長とは、半導体基板１の底部側から厚み方向にメッキを成長させていくことを意味する。   Then, as shown in FIG. 1E, the wiring material 6 such as copper is recessed by a plating method called bottom-up growth using the surface of the metal layer as the first etching stop layer 3 as a seed layer for plating. 4 is filled. Here, copper is a low resistance and easy to plate material. Here, the bottom-up growth of plating means that the plating is grown in the thickness direction from the bottom side of the semiconductor substrate 1.

そして、最後に、表裏面の不要な部分（第１エッチングストップ層３や配線材料６の不要部分）を除去することで、貫通電極７が形成される。   Finally, unnecessary portions on the front and back surfaces (unnecessary portions of the first etching stop layer 3 and the wiring material 6) are removed, whereby the through electrodes 7 are formed.

なお、貫通電極７の表面７ａは、その平坦性が必要な場合、ＣＭＰ等の工程で研磨処理を施せばよい。   Note that the surface 7a of the through electrode 7 may be polished by a process such as CMP when flatness is required.

第１実施形態に係る貫通電極の形成方法は、第１エッチングストップ層３である金属層をそのままメッキ用のシード層として利用することで、貫通電極７の形成工程が簡略化できる。   The formation method of the penetration electrode 7 can simplify the formation method of the penetration electrode concerning a 1st embodiment by using the metal layer which is the 1st etching stop layer 3 as a seed layer for plating as it is.

また、第１実施形態に係る貫通電極の形成方法は、第１エッチングストップ層３である金属層を貫通電極７の裏面７ｂとしてそのまま利用することができる。なお、第１エッチングストップ層３である金属層を例えばスパッタ法や真空蒸着法にて形成すれば、貫通電極７の裏面７ｂの平坦性を良好に形成することができる。   Further, in the method for forming the through electrode according to the first embodiment, the metal layer that is the first etching stop layer 3 can be used as it is as the back surface 7 b of the through electrode 7. In addition, if the metal layer which is the 1st etching stop layer 3 is formed, for example by a sputtering method or a vacuum evaporation method, the flatness of the back surface 7b of the penetration electrode 7 can be formed favorably.

また、第１エッチングストップ層３は、例えばスパッタ法や真空蒸着法にて第２絶縁膜２ｂに対して形成するため、お互いの界面で空隙が発生することはない。また、貫通電極７が形成される際に、第１エッチングストップ層３をシード層とすることで、背景技術に記載したような空隙が存在しないので、凹部４からはみ出し不要な箇所にメッキされることがなく、歩留まりをよくすることができる。   Further, since the first etching stop layer 3 is formed on the second insulating film 2b by, for example, a sputtering method or a vacuum evaporation method, no void is generated at the interface between them. Further, when the through electrode 7 is formed, the first etching stop layer 3 is used as a seed layer, so that there is no void as described in the background art, so that a portion that does not protrude from the recess 4 is plated. And yield can be improved.

（第２実施形態）
次に、他の実施形態を、本発明の第２実施形態として図２及び図３に基づいて説明する。図２は、本発明の第２実施形態に係る半導体基板に貫通する貫通電極の形成方法を示す概略断面図である。また、図３は、本発明の第２実施形態の変形形態にて形成した半導体基板に貫通する貫通電極を示す概略断面図である。 (Second Embodiment)
Next, another embodiment will be described based on FIGS. 2 and 3 as a second embodiment of the present invention. FIG. 2 is a schematic cross-sectional view illustrating a method for forming a through electrode penetrating a semiconductor substrate according to the second embodiment of the present invention. FIG. 3 is a schematic cross-sectional view showing a through electrode penetrating a semiconductor substrate formed in a modification of the second embodiment of the present invention.

ここで、第２実施形態においては、第１実施形態の図１（ａ）、（ｂ）の説明箇所と同様にして、半導体基板１の表裏面にそれぞれ第１絶縁膜２ａ、第２絶縁膜２ｂ及び第１エッチングストップ層３を形成し、その後、図２（ｂ）に示すように、第１エッチングストップ層３の裏面側全面にレジストを第２エッチングストップ層８として形成する。なお、第２エッチングストップ層８であるレジストのエッチングレートは、第１エッチングストップ層３である金属層のエッチングレートに比べ非常に遅いものであればよい。   Here, in the second embodiment, the first insulating film 2a and the second insulating film are respectively formed on the front and back surfaces of the semiconductor substrate 1 in the same manner as the description of FIGS. 1A and 1B of the first embodiment. 2b and the first etching stop layer 3 are formed, and then a resist is formed as a second etching stop layer 8 on the entire back surface side of the first etching stop layer 3 as shown in FIG. Note that the etching rate of the resist that is the second etching stop layer 8 may be very slow as compared with the etching rate of the metal layer that is the first etching stop layer 3.

次に、図２（ｃ）に示すように、例えばＲＩＥによって半導体基板１の深さ方向に第１エッチングストップ層３までエッチングして凹部４（４ａ）を形成する。   Next, as shown in FIG. 2C, the recess 4 (4a) is formed by etching to the first etching stop layer 3 in the depth direction of the semiconductor substrate 1, for example, by RIE.

第１実施形態と同様に、貫通電極７は、電極配線として使用する場合では、配線間の絶縁を確保する必要があるため、図２（ｄ）に示すように、凹部４（４ａ）の内壁にも第３絶縁膜５を形成する。   As in the first embodiment, when the through electrode 7 is used as an electrode wiring, it is necessary to ensure insulation between the wirings. Therefore, as shown in FIG. 2D, the inner wall of the recess 4 (4a) Also, the third insulating film 5 is formed.

そして、図２（ｅ）に示すように、例えばＲＩＥによって半導体基板１の深さ方向に第２エッチングストップ層８までエッチングして凹部４（４ｂ）を形成する。   Then, as shown in FIG. 2E, the concave portion 4 (4b) is formed by etching to the second etching stop layer 8 in the depth direction of the semiconductor substrate 1 by, for example, RIE.

そして、次に、図２（ｆ）、（ｇ）に示すように、第１エッチングストップ層３である金属層の内壁をメッキ用のシード層として配線材料６を凹部４に充填する。詳細には、図２（ｆ）に示すように配線材料６が形成されて後、図２（ｇ）に示すように配線材料６が途中からボトムアップ成長する。最後に、図２（ｈ）に示すように、最も裏面側に設けた第２エッチングストップ層８であるレジストを削除し、他の表裏面の不要な部分を除去することで、貫通電極７が形成される。なお、貫通電極７の表面７ａの平坦性が必要な場合、表面７ａは、ＣＭＰ等の工程で研磨処理を施せばよい。   Then, as shown in FIGS. 2F and 2G, the wiring material 6 is filled in the recess 4 using the inner wall of the metal layer as the first etching stop layer 3 as a seed layer for plating. Specifically, after the wiring material 6 is formed as shown in FIG. 2 (f), the wiring material 6 bottom-up grows in the middle as shown in FIG. 2 (g). Finally, as shown in FIG. 2 (h), by removing the resist which is the second etching stop layer 8 provided on the most back surface side and removing unnecessary portions on the other front and back surfaces, the through electrode 7 is formed. It is formed. In addition, when the flatness of the surface 7a of the penetration electrode 7 is required, the surface 7a may be polished by a process such as CMP.

第２実施形態に係る貫通電極の形成方法は、第１実施形態と同様に、第１エッチングストップ層３である金属層をそのままメッキ用のシード層として利用することで、貫通電極７の形成工程が簡略化できる。   The through electrode forming method according to the second embodiment uses the metal layer that is the first etching stop layer 3 as it is as a seed layer for plating as in the first embodiment, thereby forming the through electrode 7. Can be simplified.

また、第２実施形態に係る貫通電極の形成方法は、第１エッチングストップ層３である金属層を貫通電極７の裏面７ｂの一部としてそのまま利用することができるので、この金属層を例えばスパッタ法や真空蒸着法にて形成すれば、この裏面７ｂの一部の平坦性を良好に形成する。また、裏面７ｂの中央部７ｂ−１は、第２エッチングストップ層３であるレジストに対してメッキ充填で形成されるため、中央部７ｂ−１が良好な平坦性を備える。従って、第２実施形態に係る貫通電極の形成方法は、貫通電極７の裏面７ｂの平坦性を良好に形成することができる。   Further, in the method for forming the through electrode according to the second embodiment, the metal layer that is the first etching stop layer 3 can be used as it is as a part of the back surface 7b of the through electrode 7, so that the metal layer is sputtered, for example. If formed by a method or a vacuum vapor deposition method, the flatness of a part of the back surface 7b is formed satisfactorily. Moreover, since the center part 7b-1 of the back surface 7b is formed by plating filling the resist that is the second etching stop layer 3, the center part 7b-1 has good flatness. Therefore, the through electrode forming method according to the second embodiment can satisfactorily form the flatness of the back surface 7 b of the through electrode 7.

また、貫通電極７が形成される際に、第２エッチングストップ層８をシード層とすることで、背景技術に記載したような空隙が存在しないので、凹部４からはみ出し不要な箇所にメッキされることがなく、歩留まりをよくすることができる。   Further, when the through electrode 7 is formed, the second etching stop layer 8 is used as a seed layer, so that there is no void as described in the background art, so that a portion that does not protrude from the recess 4 is plated. And yield can be improved.

なお、第２実施形態においては、第１エッチングストップ層３である金属層を半導体基板１の表面側からエッチングしているが、凹部４が深い等の理由により半導体基板１の表面側からエッチングするのが困難である場合、第２実施形態の変形形態として、半導体基板１の裏面側から第２エッチングストップ層８であるレジストのパターニングを行い、半導体基板１の裏面側からエッチングを行ってもよい（図３参照）。この場合、メッキを行うと図３に示すように、レジスト開口部分にもメッキが成長する可能性があるため、裏面７ｂの平坦性が必要な際は、適宜研磨処理を施せばよい。   In the second embodiment, the metal layer that is the first etching stop layer 3 is etched from the surface side of the semiconductor substrate 1. However, the metal layer is etched from the surface side of the semiconductor substrate 1 because the recess 4 is deep. If this is difficult, as a modification of the second embodiment, the resist that is the second etching stop layer 8 may be patterned from the back surface side of the semiconductor substrate 1 and the etching may be performed from the back surface side of the semiconductor substrate 1. (See FIG. 3). In this case, as shown in FIG. 3, when plating is performed, there is a possibility that the plating also grows at the opening portion of the resist. Therefore, when flatness of the back surface 7b is necessary, a polishing process may be appropriately performed.

ここで、第１実施形態及び第２実施形態においては、導電性部材である第１エッチングストップ層３は、金属層を用いているが、例えば不純物を高濃度に含んだ状態にすることによって導電性を備えたドープドポリシリコンであってもよい。   Here, in the first embodiment and the second embodiment, the first etching stop layer 3 which is a conductive member uses a metal layer. However, the first etching stop layer 3 is made conductive by, for example, containing impurities in a high concentration. It may be doped polysilicon having the property.

本発明の第１実施形態に係る貫通電極の形成方法を示す概略断面図である。It is a schematic sectional drawing which shows the formation method of the penetration electrode which concerns on 1st Embodiment of this invention. 本発明の第２実施形態に係る貫通電極の形成方法を示す概略断面図である。It is a schematic sectional drawing which shows the formation method of the penetration electrode which concerns on 2nd Embodiment of this invention. 本発明の第２実施形態の変形形態にて形成した貫通電極を示す概略断面図である。It is a schematic sectional drawing which shows the penetration electrode formed in the modification of 2nd Embodiment of this invention. 従来例の貫通電極の形成方法を示す概略断面図である。It is a schematic sectional drawing which shows the formation method of the penetration electrode of a prior art example. 従来例の他の貫通電極の形成方法を示す概略断面図である。It is a schematic sectional drawing which shows the formation method of the other penetration electrode of a prior art example.

符号の説明Explanation of symbols

１ 半導体基板
２ａ 第１絶縁膜
２ｂ 第２絶縁膜
３ 第１エッチングストップ層
４ 凹部
５ 第３絶縁膜
６ 配線材料
７ 貫通電極
８ 第２エッチングストップ層 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2a 1st insulating film 2b 2nd insulating film 3 1st etching stop layer 4 Recessed part 5 3rd insulating film 6 Wiring material 7 Through electrode 8 2nd etching stop layer

Claims (5)

半導体基板の厚み方向に貫通する貫通電極の形成方法において、
前記半導体基板の表面に第１絶縁膜を形成し、前記半導体基板の裏面に第２絶縁膜を形成し、前記半導体基板とはエッチングレートの異なる導電性部材からなる第１エッチングストップ層を前記第２絶縁膜に形成する第１工程と、
貫通電極の形成対象箇所に対して、前記第１エッチングストップ層までエッチングして凹部を形成する第２工程と、
前記第１エッチングストップ層をシード層として用い、前記凹部に対してボトムアップ成長を用いたメッキにより電極を形成する第３工程と、
を含むことを特徴とする貫通電極の形成方法。 In the formation method of the through electrode penetrating in the thickness direction of the semiconductor substrate,
A first insulating film is formed on the surface of the semiconductor substrate, a second insulating film is formed on the back surface of the semiconductor substrate, and a first etching stop layer made of a conductive member having an etching rate different from that of the semiconductor substrate is formed on the first substrate. A first step of forming two insulating films;
A second step of forming a recess by etching up to the first etching stop layer with respect to the formation target portion of the through electrode;
A third step of forming an electrode by plating using bottom-up growth on the concave portion, using the first etching stop layer as a seed layer;
A method of forming a through electrode comprising the steps of: 半導体基板の厚み方向に貫通する貫通電極の形成方法において、
前記半導体基板の表面に第１絶縁膜を形成し、前記半導体基板の裏面に第２絶縁膜を形成し、前記半導体基板とはエッチングレートの異なる導電性部材からなる第１エッチングストップ層を前記第２絶縁膜に形成した後、前記第１エッチングストップ層にレジスト膜からなる第２エッチングストップ層を形成する第１工程と、
貫通電極の形成対象箇所に対して、前記第２エッチングストップ層までエッチングして凹部を形成する第２工程と、
前記第１エッチングストップ層をシード層として用い、前記凹部に対してボトムアップ成長を用いたメッキにより電極を形成する第３工程と、
を含むことを特徴とする貫通電極の形成方法。 In the formation method of the through electrode penetrating in the thickness direction of the semiconductor substrate,
A first insulating film is formed on the surface of the semiconductor substrate, a second insulating film is formed on the back surface of the semiconductor substrate, and a first etching stop layer made of a conductive member having an etching rate different from that of the semiconductor substrate is formed on the first substrate. A first step of forming a second etching stop layer made of a resist film on the first etching stop layer after being formed into two insulating films;
A second step of forming a recess by etching up to the second etching stop layer with respect to the formation target portion of the through electrode;
A third step of forming an electrode by plating using bottom-up growth on the concave portion, using the first etching stop layer as a seed layer;
A method of forming a through electrode comprising the steps of: 前記第２工程は、ＲＩＥを用いてエッチングする請求項１又は請求項２に記載の貫通電極の形成方法。   The method of forming a through electrode according to claim 1, wherein the second step performs etching using RIE. 前記第１工程は、ＣＶＤを用いて前記第１絶縁膜及び前記第２絶縁膜を形成する請求項１乃至請求項３のいずれかに記載の貫通電極の形成方法。   4. The through electrode forming method according to claim 1, wherein the first step forms the first insulating film and the second insulating film using CVD. 5. 前記第１工程は、熱酸化を用いて前記第１絶縁膜及び前記第２絶縁膜を形成し、前記１エッチングストップ層を高融点金属にて形成する請求項１乃至請求項３のいずれかに記載の貫通電極の形成方法。   4. The method according to claim 1, wherein in the first step, the first insulating film and the second insulating film are formed using thermal oxidation, and the first etching stop layer is formed of a refractory metal. The formation method of the penetration electrode of description.
JP2005031829A 2005-02-08 2005-02-08 Method for forming through-electrode Pending JP2006222138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005031829A JP2006222138A (en) 2005-02-08 2005-02-08 Method for forming through-electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005031829A JP2006222138A (en) 2005-02-08 2005-02-08 Method for forming through-electrode

Publications (1)

Publication Number Publication Date
JP2006222138A true JP2006222138A (en) 2006-08-24

Family

ID=36984264

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005031829A Pending JP2006222138A (en) 2005-02-08 2005-02-08 Method for forming through-electrode

Country Status (1)

Country Link
JP (1) JP2006222138A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100883806B1 (en) 2007-01-02 2009-02-17 삼성전자주식회사 Semiconductor device and method of forming the same
KR100916771B1 (en) 2007-10-08 2009-09-14 성균관대학교산학협력단 Method for forming a through hole electrode
US7973415B2 (en) 2007-06-06 2011-07-05 Renesas Electronics Corporation Manufacturing process and structure of through silicon via
KR101144573B1 (en) * 2010-08-03 2012-05-09 엘지이노텍 주식회사 The printed circuit board and the method for manufacturing the same
JP2013098369A (en) * 2011-11-01 2013-05-20 Seiko Epson Corp Method of manufacturing semiconductor device, semiconductor device, and electronic apparatus
KR20160019960A (en) * 2013-06-17 2016-02-22 어플라이드 머티어리얼스, 인코포레이티드 Method for copper plating through silicon vias using wet wafer back contact
CN107978553A (en) * 2016-10-21 2018-05-01 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and its manufacture method

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100883806B1 (en) 2007-01-02 2009-02-17 삼성전자주식회사 Semiconductor device and method of forming the same
US7973415B2 (en) 2007-06-06 2011-07-05 Renesas Electronics Corporation Manufacturing process and structure of through silicon via
US8324736B2 (en) 2007-06-06 2012-12-04 Renesas Electronics Corporation Manufacturing process and structure of through silicon via
KR100916771B1 (en) 2007-10-08 2009-09-14 성균관대학교산학협력단 Method for forming a through hole electrode
KR101144573B1 (en) * 2010-08-03 2012-05-09 엘지이노텍 주식회사 The printed circuit board and the method for manufacturing the same
JP2013098369A (en) * 2011-11-01 2013-05-20 Seiko Epson Corp Method of manufacturing semiconductor device, semiconductor device, and electronic apparatus
KR20160019960A (en) * 2013-06-17 2016-02-22 어플라이드 머티어리얼스, 인코포레이티드 Method for copper plating through silicon vias using wet wafer back contact
JP2016526784A (en) * 2013-06-17 2016-09-05 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ Method for copper plating through silicon via using wet wafer back contact
KR102245104B1 (en) 2013-06-17 2021-04-26 어플라이드 머티어리얼스, 인코포레이티드 Method for copper plating through silicon vias using wet wafer back contact
CN107978553A (en) * 2016-10-21 2018-05-01 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and its manufacture method

Similar Documents

Publication Publication Date Title
CN101785103B (en) Low resistance through-wafer via
CN102246299B (en) Method for making via interconnection
US8586474B2 (en) Method to form a via
US8455357B2 (en) Method of plating through wafer vias in a wafer for 3D packaging
JP4581864B2 (en) Method for forming through wiring on semiconductor substrate
JP2006222138A (en) Method for forming through-electrode
JP4199206B2 (en) Manufacturing method of semiconductor device
JP2007005402A (en) Method of forming through interconnection line in semiconductor substrate
KR20000012027A (en) Method for manufacturing a semiconductor device
US6610597B2 (en) Method of fabricating a semiconductor device
TW201603153A (en) Semiconductor component with at least a through-contact in the carrier substrate and process to produce such a through-contact
US11776849B2 (en) Through silicon via fabrication
JP5453763B2 (en) Method for manufacturing through electrode substrate
CN115312451A (en) Perforation of superconducting substrates
JP2009016619A (en) Semiconductor device and manufacturing method thereof
US8405190B2 (en) Component having a silicon carbide coated via
JP6187008B2 (en) Method for manufacturing metal-filled structure and metal-filled structure
KR20090020243A (en) Method of manufacturing inductor in a semiconductor device
JP6191322B2 (en) Metal filling method
JP6031746B2 (en) Semiconductor device manufacturing method, semiconductor device, and electronic apparatus
JP2006114568A (en) Method for forming through electrode
JPH04127425A (en) Manufacture of semiconductor integrated circuit
KR20040041879A (en) Method of manufacturing a semiconductor device
CN108140565A (en) The manufacturing method of wiring structure
KR20060054692A (en) Substrate structure having embedded conductive pattern and method of manufacturing the same