JP2006165310A - Manufacturing device of semiconductor device - Google Patents

Manufacturing device of semiconductor device Download PDF

Info

Publication number
JP2006165310A
JP2006165310A JP2004355351A JP2004355351A JP2006165310A JP 2006165310 A JP2006165310 A JP 2006165310A JP 2004355351 A JP2004355351 A JP 2004355351A JP 2004355351 A JP2004355351 A JP 2004355351A JP 2006165310 A JP2006165310 A JP 2006165310A
Authority
JP
Japan
Prior art keywords
bump
bonding
electrode pad
semiconductor device
manufacturing apparatus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004355351A
Other languages
Japanese (ja)
Inventor
Yukiko Haraguchi
友紀子 原口
Noriyuki Nagai
紀行 永井
Kazuhiko Matsushita
和彦 松下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2004355351A priority Critical patent/JP2006165310A/en
Publication of JP2006165310A publication Critical patent/JP2006165310A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • H01L2224/13019Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/14104Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
    • H01L2224/1411Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body the bump connectors being bonded to at least one common bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/742Apparatus for manufacturing bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301Capillary
    • H01L2224/78302Shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To stabilize a junction by enlarging an alloy junction area between a bump and a bonding pad surface when joined. <P>SOLUTION: A bonding capillary 10 has two wire insertion openings 4, and has two parallel wire insertion holes 5 vertically to the bonding capillary 10. Formation of a bump 3' by the bonding capillary 10 is carried out by inserting two metallic wires 6 into each wire insertion hole 5 in the bonding capillary 10, melting the tip of two metallic wires 6 coming out of a wire outlet 7 simultaneously, forming one gold ball 8 to a gourd shape on purpose, and performing alloy junction for a bump covering a needle mark part 9 all over a rectangular electrode pad surface of a chip surface. Consequently, it is possible to perform alloy junction all over the rectangular electrode pad surface, to enlarge a junction area between the electrode pad 2 and the bump 3', to raise junction strength, and to improve connection reliability. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置を製造する組立工程における半導体素子チップに対して、ボンディングを行ってひょうたん形状のバンプを形成する半導体装置の製造装置に関するものである。   The present invention relates to a semiconductor device manufacturing apparatus for bonding a semiconductor element chip in a manufacturing process for manufacturing a semiconductor device to form a gourd-shaped bump.

従来、半導体素子は外部環境から素子への影響を防ぐためにパッケージに収納して構成した半導体装置として使用されている。この半導体素子への電源供給や信号の出力を行うために半導体素子上に設けられたボンディングパッド部とパッケージ側へのインターポーザーなどへ電気的に接続することが必要である。   Conventionally, a semiconductor element is used as a semiconductor device that is housed in a package in order to prevent the element from being affected by an external environment. In order to supply power and output signals to the semiconductor element, it is necessary to electrically connect to a bonding pad portion provided on the semiconductor element and an interposer to the package side.

従来のボンディング技術について、図面を参照しながら説明する。図4は従来のボンディングキャピラリーを使用したボンディング方法によりチップ表面の電極パッド2上に形成された幅約85μm〜110μmのバンプ3の形状を示し、(a)は上方から見た正面図、(b)はA−A’断面図である。また、電極パッド2表面の中心に位置するのはプローブ検査の針跡部9である。   A conventional bonding technique will be described with reference to the drawings. FIG. 4 shows the shape of a bump 3 having a width of about 85 μm to 110 μm formed on the electrode pad 2 on the chip surface by a conventional bonding method using a bonding capillary, (a) is a front view seen from above, (b) ) Is an AA ′ sectional view. In addition, the probe trace 9 is located at the center of the electrode pad 2 surface.

次に、図5は従来の半導体装置の製造装置に用いるセラミックあるいはルビー素材のボンディングキャピラリーの断面図を示す。図5に示すように、ボンディングキャピラリー1は1個のワイヤー挿入口4を持ち、かつ1本のワイヤー挿入孔5を有している。ボンディングキャピラリー1によるバンプの作成方法は図6(a),(b)に示すように、ワイヤー挿入孔5にアルミニウム、金またはそれらの合金等からなる金属ワイヤー6を通し、ボンディングキャピラリー1のワイヤー出口7から出てきた金属ワイヤー6の先端に超音波や熱を加えて溶融させ1つの直径約60μm〜80μmの金ボール8を形成させ、チップ表面の電極パッド2上にボンディングキャピラリー1を押し付け、電極パッド2上のアルミニウムと金ボール8を合金接合し、電極パッド2上にバンプ3を形成する。また、ボンディング時に使用する金属ワイヤー径は約24.5μmである。   Next, FIG. 5 shows a sectional view of a ceramic or ruby material bonding capillary used in a conventional semiconductor device manufacturing apparatus. As shown in FIG. 5, the bonding capillary 1 has one wire insertion port 4 and one wire insertion hole 5. As shown in FIGS. 6 (a) and 6 (b), a method for creating a bump by the bonding capillary 1 is such that a metal wire 6 made of aluminum, gold, or an alloy thereof is passed through the wire insertion hole 5, and the wire outlet of the bonding capillary 1 is used. 7 to form a gold ball 8 having a diameter of about 60 μm to 80 μm, and press the bonding capillary 1 onto the electrode pad 2 on the chip surface. Aluminum on the pad 2 and gold ball 8 are alloyed to form bumps 3 on the electrode pad 2. The metal wire diameter used for bonding is about 24.5 μm.

これら半導体素子の各電極は、微細技術の進展に伴ってバンプボンディング等の接合技術も狭ピッチが必須となり、限られた電極パッド2内でチップを検査した傷の針跡部9を避けた電極パッド2上でのバンプ接合において、強度的に保つことが厳しくなってきた。従来までは電極パッド2の面積が広くかつバンプ3の金ボールも大きく形成することができたため、検査による針跡面積が接合に対して貢献できなくても充分な強度を保つことが可能な接合面積を有していた。   Each electrode of these semiconductor elements requires a narrow pitch in the bonding technique such as bump bonding as the fine technology advances, and the electrode pad avoiding the scratched needle mark portion 9 inspecting the chip within the limited electrode pad 2 It has become stricter to maintain strength in bump bonding on 2. Conventionally, since the area of the electrode pad 2 is large and the gold balls of the bumps 3 can be formed large, the bonding can maintain a sufficient strength even if the needle trace area by inspection cannot contribute to the bonding. Had an area.

しかしながら、拡散プロセスの微細技術によりチップの面積の縮小が顕著になってきており、それに伴い電極パッド2の配列によりチップサイズを制限することがないように、パッドサイズ及びパッドピッチの縮小が必然的に求められる。これは半導体回路形成を担う組立工程、特にバンプボンディング工程で問題となる。   However, the reduction of the area of the chip has become remarkable due to the fine technology of the diffusion process, and accordingly, the pad size and the pad pitch must be reduced so that the chip size is not limited by the arrangement of the electrode pads 2. Is required. This becomes a problem in an assembly process for forming a semiconductor circuit, particularly in a bump bonding process.

また、検査後の針跡部9を除く電極パッド2が同じ面積であるにも関わらず、電極パッド2への小ボール化したバンプボンディングを行った場合においても、接合面積が足らず、機械的強度不足や金ボール不着など信頼性の面で問題となってしまう。   Further, even when the electrode pad 2 except the needle trace portion 9 after the inspection has the same area, even when bump bonding with a small ball is performed on the electrode pad 2, the bonding area is insufficient and the mechanical strength is insufficient. It becomes a problem in terms of reliability such as non-attachment of gold balls.

そこで従来の電極パッド2を長方形に形成し、検査の針跡部9を避けるように、金ボールと電極パッド2を接合をさせる位置を移動して、安定した接合ができるような半導体装置を形成することが行われてる。
特開2002−190493号公報
Therefore, the conventional electrode pad 2 is formed in a rectangular shape, and the position where the gold ball and the electrode pad 2 are bonded is moved so as to avoid the inspection trace 9 to form a semiconductor device capable of stable bonding. Things are going on.
JP 2002-190493 A

しかしながら、このような構成の従来の半導体装置の製造方法において、さらなる拡散プロセスの微細化に伴い、狭パッド技術及び接合を良化させるパッド構造技術が進み、小さい面積にボンディングすることが可能になってきた。それに伴い、さらに微細化が進み小さな面積に対する金ボールとボンディングパッド部の接続性をより安定にすることが課題となっている。また、微細化に伴う狭パッドピッチの長方形電極パッドにおいて、チップ検査の針跡部を避け、金ボールと電極パッドの接合をさせる位置を移動させることも困難になってきた。そのため、電極パッド上のアルミニウムと金ボールとの合金が均一に形成されず、剥離強度の低下やボール不着につながるといった問題があった。   However, in the conventional method for manufacturing a semiconductor device having such a configuration, along with further miniaturization of the diffusion process, a narrow pad technology and a pad structure technology for improving the bonding advance, and it becomes possible to bond to a small area. I came. Along with this, further miniaturization has progressed, and it has become an issue to further stabilize the connectivity between the gold ball and the bonding pad for a small area. In addition, in a rectangular electrode pad with a narrow pad pitch accompanying miniaturization, it has become difficult to avoid a needle mark portion for chip inspection and to move a position for bonding a gold ball and an electrode pad. For this reason, there has been a problem that an alloy of aluminum and gold balls on the electrode pad is not formed uniformly, leading to a decrease in peel strength and a ball non-adherence.

本発明は、前記従来技術の問題を解決することに指向するものであり、半導体素子チップに金属ワイヤーをバンプボンディングする際に、バンプを上方より見た形状が2つの同一円の一部を重ね合わせたひょうたん形状として、バンプとボンディングパッド部表面の合金接合面積を大きくする。このために、バンプ用ボンディングキャピラリーにワイヤー挿入孔を2本設け、この2本の金属ワイヤー先端を同時に溶融させた1つの金ボールを、ひょうたん形状のバンプとし、接合した際の合金接合面積を大きくして、接合の安定化を図る半導体装置の製造装置を提供することを目的とする。   The present invention is directed to solving the problems of the prior art. When bump bonding a metal wire to a semiconductor element chip, the shape of the bump viewed from above overlaps a part of two identical circles. As a combined gourd shape, the alloy bonding area of the bump and bonding pad surface is increased. For this purpose, two wire insertion holes are provided in the bonding capillary for bumps, and one gold ball in which the two metal wire tips are melted at the same time is used as a gourd-shaped bump to increase the alloy bonding area when bonded. Then, it aims at providing the manufacturing apparatus of the semiconductor device which aims at stabilization of joining.

前記の目的を達成するために、本発明に係る半導体装置の製造装置は、半導体素子チップの長方形電極パッド上にバンプを形成する半導体装置の製造装置であって、形成されるバンプには、上方より見た形状が2つの同一円の一部を重ね合わせたひょうたん形状で、かつ側方より見た形状が凸部を2箇所有することを特徴とする。   In order to achieve the above object, a semiconductor device manufacturing apparatus according to the present invention is a semiconductor device manufacturing apparatus that forms a bump on a rectangular electrode pad of a semiconductor element chip. The shape seen from is a gourd shape obtained by overlapping a part of two identical circles, and the shape seen from the side has two convex portions.

また、前記ひょうたん形状のバンプは、長方形電極パッド表面全体で合金接合して検査針跡を覆うこと、さらに、前記バンプは金属ワイヤーを2本用いて、バンプボンディングキャピラリーのワイヤー出口から出てきた2本の金属ワイヤー先端を同時に溶融し1つの金ボールとして、バンプのひょうたん形状を形成すること、さらに、前記バンプボンディングキャピラリーは、2本の平行したワイヤー挿入孔を有することを特徴とする。   Further, the gourd-shaped bump covers the inspection needle mark by alloy bonding over the entire surface of the rectangular electrode pad, and the bump comes out from the wire outlet of the bump bonding capillary using two metal wires. A metal wire tip is melted at the same time to form a gourd shape of a bump as one gold ball, and the bump bonding capillary has two parallel wire insertion holes.

前記構成によれば、バンプとボンディングパッド部表面における合金接合面積を大きくでき、電気的接続の信頼性を高めることができる。   According to the said structure, the alloy junction area in a bump and a bonding pad part surface can be enlarged, and the reliability of an electrical connection can be improved.

本発明によれば、チップ検査の針跡部を避けて従来では接合に貢献していなかった残りの電極パッド面積を、針跡部を覆うことによりバンプとボンディングパッド部表面の合金接合面積を大きくすることができ、これにより大きな合金接合面積を確保でき接続信頼性を高めることができるという効果を奏する。   According to the present invention, the remaining electrode pad area that has not previously contributed to bonding by avoiding the needle trace portion of the chip inspection is increased, and the alloy bonding area between the bump and the bonding pad portion surface is increased by covering the needle trace portion. As a result, there is an effect that a large alloy joint area can be secured and connection reliability can be improved.

以下、図面を参照して本発明の実施の形態に係る半導体装置の製造装置について詳細に説明する。ここで、前記従来例を示す図4〜図6において説明した構成要件に対応し同等機能を有するものには同一の符号を付して示す。   Hereinafter, a semiconductor device manufacturing apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings. Here, components having the same functions corresponding to the components described in FIGS. 4 to 6 showing the conventional example are denoted by the same reference numerals.

まず、図1は本実施の形態によるバンプ用のボンディングキャピラリーを使用したボンディング方法により、チップ表面の電極パッド2上に合金接合されたバンプ3’の形状を示し、(a)は上方から見た正面図、(b)はA−A’断面図である。バンプ3’は上方より見た形状が2つの同一円の一部を重ね合わせたひょうたん形状であって、断面より見た形状が凸部を2ヶ所有するバンプ3’である。   First, FIG. 1 shows the shape of a bump 3 ′ alloy-bonded to the electrode pad 2 on the chip surface by the bonding method using the bump bonding capillary according to the present embodiment, and (a) is viewed from above. A front view and (b) are AA 'sectional views. The bump 3 'is a gourd shape obtained by overlapping a part of two identical circles as viewed from above, and the shape viewed from a cross section is a bump 3' having two convex portions.

電極パッド2には、チップを検査したプローブ検査針による傷跡があり、電極パッド2上のアルミニウムが削れることにより、金属ワイヤーとの合金が均一に形成されず、図4に示すように、この針跡部9を避けて形成することで電極パッド2とバンプ3との合金接合面積が小さくなり、バンプ3の接合強度を保つことが厳しくなってきている。従来は約40μm〜60μmの狭パッドピッチに伴う長方形電極パッド2においては、検査の針跡部9を避けるように金ボールと電極パッド2を接合させる位置を移動させていた。   The electrode pad 2 has a scar due to the probe inspection needle inspecting the chip, and the aluminum on the electrode pad 2 is scraped, so that an alloy with the metal wire is not uniformly formed. As shown in FIG. By avoiding the trace portion 9, the alloy bonding area between the electrode pad 2 and the bump 3 is reduced, and it is becoming strict to maintain the bonding strength of the bump 3. Conventionally, in the rectangular electrode pad 2 with a narrow pad pitch of about 40 μm to 60 μm, the position where the gold ball and the electrode pad 2 are joined is moved so as to avoid the needle trace portion 9 for inspection.

本実施の形態ではひょうたん形状のバンプ3’により、長方形電極パッド2表面全体に合金接合することができる。したがって、プローブ検査の針跡部9の部分を避けることで、従来では接合に貢献していなかった残りの電極パッド部分においても、針跡部9の部分を覆うことによって、より大きな合金接合面積を確保することができる。   In the present embodiment, the entire surface of the rectangular electrode pad 2 can be alloy-bonded by the gourd-shaped bump 3 ′. Therefore, by avoiding the portion of the needle trace portion 9 for probe inspection, a larger alloy bonding area is ensured by covering the portion of the needle trace portion 9 even in the remaining electrode pad portion that has not contributed to the bonding in the past. be able to.

次に、図2は本実施の形態における半導体装置の製造装置に用いるボンディングキャピラリーの断面図である。図2に示すように、セラミックあるいはルビー素材のボンディングキャピラリー10は、2個のワイヤー挿入口4を持ち、ボンディングキャピラリー10に垂直に、2本の平行したワイヤー挿入孔5を有している。ボンディングキャピラリー10によるバンプの作成方法としては、図3(a),(b)に示すように、ボンディングキャピラリー10において、2本の金属ワイヤー6をそれぞれのワイヤー挿入孔5に通し、ボンディングキャピラリー10のワイヤー出口7から出てきたそれぞれの2本の金属ワイヤー6の先端を同時に溶融させて1つの金ボール8を形成し、金ボール8の形状を故意にひょうたん形状として形成し、チップ表面の長方形電極パッド2表面全体にプローブ検査の針跡部9を覆うようにバンプ3’を合金接合する。   Next, FIG. 2 is a cross-sectional view of a bonding capillary used in the semiconductor device manufacturing apparatus in the present embodiment. As shown in FIG. 2, a ceramic or ruby material bonding capillary 10 has two wire insertion ports 4 and has two parallel wire insertion holes 5 perpendicular to the bonding capillary 10. As shown in FIGS. 3A and 3B, a method for creating a bump by the bonding capillary 10 includes passing two metal wires 6 through the respective wire insertion holes 5 in the bonding capillary 10 to form the bonding capillary 10. The tip of each of the two metal wires 6 coming out from the wire outlet 7 is melted simultaneously to form one gold ball 8, and the shape of the gold ball 8 is intentionally formed into a gourd shape, and a rectangular electrode on the chip surface A bump 3 ′ is alloy-bonded over the entire surface of the pad 2 so as to cover the probe trace 9.

これにより、長方形電極パッド表面全体に合金接合することができ、電極パッド2とバンプ3’の接合面積が大きくなって接合強度が上がり、電気的な接続信頼性を向上することができる。   Thereby, alloy bonding can be performed on the entire surface of the rectangular electrode pad, the bonding area between the electrode pad 2 and the bump 3 ′ is increased, the bonding strength is increased, and the electrical connection reliability can be improved.

本発明に係る半導体装置の製造装置は、バンプとボンディングパッド部表面の合金接合面積を大きくして電気的接続の信頼性を高めることができ、組立工程における半導体素子チップにバンプ形成する半導体装置の製造に有用である。   The semiconductor device manufacturing apparatus according to the present invention can increase the reliability of electrical connection by increasing the alloy bonding area between the bump and the bonding pad surface, and the semiconductor device for bump formation on the semiconductor element chip in the assembly process. Useful for manufacturing.

本発明の実施の形態におけるボンディングキャピラリーを使用したバンプ形状を示す(a)は正面図、(b)はA−A’断面図FIG. 4A is a front view showing a bump shape using a bonding capillary in an embodiment of the present invention, and FIG. 本実施の形態における半導体装置の製造装置に用いるボンディングキャピラリーの断面図Sectional drawing of the bonding capillary used for the manufacturing apparatus of the semiconductor device in this Embodiment 本実施の形態におけるボンディングキャピラリーにより形成した(a)は金ボール、(b)はバンプを示す図(A) formed by the bonding capillary in this embodiment is a gold ball, (b) is a diagram showing a bump 従来のバンプ用のボンディングキャピラリーを使用したバンプ形状を示す(a)は正面図、(b)はA−A’断面図A bump shape using a conventional bump bonding capillary is shown in (a) is a front view, and (b) is a cross-sectional view along A-A '. 従来の半導体装置の製造装置に用いるボンディングキャピラリーの断面図Cross-sectional view of a bonding capillary used in a conventional semiconductor device manufacturing apparatus 従来のボンディングキャピラリーにより形成した(a)は金ボール、(b)はバンプを示す図(A) is a gold ball and (b) is a bump formed by a conventional bonding capillary.

符号の説明Explanation of symbols

1,10 ボンディングキャピラリー
2 電極パッド
3,3’ バンプ
4 ワイヤー挿入口
5 ワイヤー挿入孔
6 金属ワイヤー
7 ワイヤー出口
8 金ボール
9 針跡部
DESCRIPTION OF SYMBOLS 1,10 Bonding capillary 2 Electrode pad 3, 3 'Bump 4 Wire insertion slot 5 Wire insertion hole 6 Metal wire 7 Wire exit 8 Gold ball 9 Needle trace part

Claims (4)

半導体素子チップの長方形電極パッド上にバンプを形成する半導体装置の製造装置であって、
形成される前記バンプには、上方より見た形状が2つの同一円の一部を重ね合わせたひょうたん形状で、かつ側方より見た形状が凸部を2箇所有することを特徴とする半導体装置の製造装置。
A semiconductor device manufacturing apparatus for forming a bump on a rectangular electrode pad of a semiconductor element chip,
The bumps to be formed have a gourd shape in which the shape seen from above overlaps two parts of the same circle, and the shape seen from the side has two convex portions. Manufacturing equipment.
前記ひょうたん形状のバンプは、前記長方形電極パッド表面全体で合金接合して、検査針跡を覆うことを特徴とする請求項1記載の半導体装置の製造装置。   2. The semiconductor device manufacturing apparatus according to claim 1, wherein the gourd-shaped bumps are alloy-bonded over the entire surface of the rectangular electrode pad to cover the inspection needle trace. 前記ひょうたん形状のバンプは、2本の金属ワイヤーを用いて、バンプボンディングキャピラリーのワイヤー出口から出てきた前記2本の金属ワイヤー先端を同時に溶融し1つの金ボールとして、前記バンプのひょうたん形状を形成することを特徴とする請求項1または2記載の半導体装置の製造装置。   The gourd-shaped bump uses two metal wires to melt the tip of the two metal wires coming out from the wire outlet of the bump bonding capillary at the same time to form a gourd shape of the bump as one gold ball The semiconductor device manufacturing apparatus according to claim 1, wherein the semiconductor device manufacturing apparatus is a semiconductor device manufacturing apparatus. 前記バンプボンディングキャピラリーは、2本の平行したワイヤー挿入孔を有することを特徴とする請求項3記載の半導体装置の製造装置。   4. The semiconductor device manufacturing apparatus according to claim 3, wherein the bump bonding capillary has two parallel wire insertion holes.
JP2004355351A 2004-12-08 2004-12-08 Manufacturing device of semiconductor device Pending JP2006165310A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004355351A JP2006165310A (en) 2004-12-08 2004-12-08 Manufacturing device of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004355351A JP2006165310A (en) 2004-12-08 2004-12-08 Manufacturing device of semiconductor device

Publications (1)

Publication Number Publication Date
JP2006165310A true JP2006165310A (en) 2006-06-22

Family

ID=36666978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004355351A Pending JP2006165310A (en) 2004-12-08 2004-12-08 Manufacturing device of semiconductor device

Country Status (1)

Country Link
JP (1) JP2006165310A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7679188B2 (en) 2006-02-06 2010-03-16 Fujitsu Microelectronics Limited Semiconductor device having a bump formed over an electrode pad

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7679188B2 (en) 2006-02-06 2010-03-16 Fujitsu Microelectronics Limited Semiconductor device having a bump formed over an electrode pad

Similar Documents

Publication Publication Date Title
US8008785B2 (en) Microelectronic assembly with joined bond elements having lowered inductance
JP2008153494A (en) Substrate for flip chip packaging
JP4819335B2 (en) Semiconductor chip package
KR20130007484A (en) Method of manufacturing semiconductor device
KR20080013865A (en) Semiconductor device, substrate and semiconductor device manufacturing method
JP2010140986A (en) Wiring board having lead pin, and lead pin
JP2008277751A (en) Method of manufacturing semiconductor device, and semiconductor device
JP2008147472A (en) Semiconductor device and manufacturing method therefor
JP2009043793A (en) Semiconductor device and method of manufacturing the same
JPH10189806A (en) Semiconductor device and junction structure of semiconductor device and substrate
TWI420639B (en) Semiconductor device
JP2008066654A (en) Semiconductor device
JP2006165310A (en) Manufacturing device of semiconductor device
US20060091535A1 (en) Fine pitch bonding pad layout and method of manufacturing same
KR100671808B1 (en) Semiconductor device
JP2009043844A (en) Wiring board with lead pin and the lead pin
JP2009130217A (en) Semiconductor device and method of manufacturing the same
JPH10233401A (en) Semiconductor device
JP2001217342A (en) Wiring board with lead pin and lead pin used therefor
JP2009064942A (en) Pad for bonding and electronic equipment
JP4712426B2 (en) Semiconductor device
JP2012124426A (en) Semiconductor device and manufacturing method therefor
JP2010021471A (en) Semiconductor device and method for manufacturing the same
JP2010067913A (en) Semiconductor device, semiconductor element, and method of inspecting the same
JP2007250749A (en) Semiconductor device, method of manufacturing semiconductor device, and electronic apparatus