JP2006147835A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2006147835A
JP2006147835A JP2004335712A JP2004335712A JP2006147835A JP 2006147835 A JP2006147835 A JP 2006147835A JP 2004335712 A JP2004335712 A JP 2004335712A JP 2004335712 A JP2004335712 A JP 2004335712A JP 2006147835 A JP2006147835 A JP 2006147835A
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semiconductor device
semiconductor
insulating layer
hard sheet
semiconductor structure
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JP4990492B2 (en
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Hiroyasu Sadabetto
裕康 定別当
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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    • H—ELECTRICITY
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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    • H01L2924/15192—Resurf arrangement of the internal vias
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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Abstract

<P>PROBLEM TO BE SOLVED: To reduce the warpage of a transparent substrate generated upon manufacturing a semiconductor device, having the transparent substrate and a photoelectric conversion device region, such as CCD or the like. <P>SOLUTION: A semiconductor constituted body 3, having the photoelectric conversion device region 5 on the lower surface of a silicon substrate 4, is arranged at a predetermined plurality of places on the transparent substrate 1 in a size corresponding to a plurality of semiconductor devices. Then lattice-type insulating layer forming sheets 21a, 21b, comprising semi-rigid resin are arranged on the base plate 1 between the semiconductor constituted bodies 3 and a lattice-type hard sheet 22 consisting of a material having a thermal expansion coefficient same as or near to that of the transparent substrate 1, is arranged thereon, and an upper-layer insulating film forming sheet 23a comprising the semi-rigid resin is arranged thereon. Then, heating and pressurizing are conducted from vertical directions to form an insulating layer on the base plate 1 between the semiconductor constituted bodies 3; and a hard sheet 22 is embedded into the upper surface of the semiconductor constituted body 3 to form an upper layer insulating film on the upper surface of the semiconductor constituted body 3, the insulating layer, and the hard sheet 22. In this case, the warpage of the transparent substrate 1 can be reduced by the presence of a hard sheet 15. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は、光電変換デバイス領域等を備えた半導体装置に関する。   The present invention relates to a semiconductor device provided with a photoelectric conversion device region and the like.

従来の光電変換デバイス領域を備えた半導体装置には、シリコン基板の下面中央部にＣＣＤ（電荷結合素子）等の素子を含む光電変換デバイス領域が設けられ、シリコン基板の下面周辺部に複数の接続パッドが設けられ、シリコン基板の上面およびその周囲に絶縁層が設けられ、シリコン基板および絶縁層の下面に下層配線が接続パッドに接続されて設けられ、下層配線を含むシリコン基板および絶縁層の下面に透明接着層を介してベース基板としてのガラス基板が設けられ、絶縁層の上面に上層配線が下層配線の接続パッド部に接続されて設けられ、上層配線の接続パッド部上面に柱状電極が設けられ、柱状電極の周囲に封止膜が設けられ、柱状電極上に半田ボールが設けられたものがある（例えば、特許文献１参照）。   In a conventional semiconductor device having a photoelectric conversion device region, a photoelectric conversion device region including an element such as a CCD (charge coupled device) is provided at the center of the lower surface of the silicon substrate, and a plurality of connections are provided on the periphery of the lower surface of the silicon substrate. Pads are provided, an insulating layer is provided on and around the upper surface of the silicon substrate, and lower layer wiring is provided on the lower surface of the silicon substrate and insulating layer, connected to the connection pad, and the lower surface of the silicon substrate and insulating layer including the lower layer wiring A glass substrate as a base substrate is provided via a transparent adhesive layer, an upper layer wiring is connected to the connection pad portion of the lower layer wiring on the upper surface of the insulating layer, and a columnar electrode is provided on the upper surface of the connection pad portion of the upper layer wiring In some cases, a sealing film is provided around the columnar electrode, and a solder ball is provided on the columnar electrode (see, for example, Patent Document 1).

特開２００４−１１１７９２号公報（図１）JP 2004-111792 A (FIG. 1)

上記従来の半導体装置を製造する場合、生産性を高めるため、完成された半導体装置を複数個形成することが可能な面積を有するガラス基板上に透明接着層を介して複数のシリコン基板が設けられた状態とした後において、絶縁層、上層配線、柱状電極、封止膜および半田ボールをこの順で形成し、シリコン基板間における封止膜、絶縁層、透明接着層およびガラス基板を切断して、上記従来の半導体装置を複数個得ている。   In the case of manufacturing the conventional semiconductor device, a plurality of silicon substrates are provided on a glass substrate having an area capable of forming a plurality of completed semiconductor devices through a transparent adhesive layer in order to increase productivity. After forming the insulating state, the insulating layer, the upper layer wiring, the columnar electrode, the sealing film and the solder ball are formed in this order, and the sealing film, the insulating layer, the transparent adhesive layer and the glass substrate between the silicon substrates are cut. A plurality of the above conventional semiconductor devices are obtained.

しかしながら、上記従来の半導体装置の製造方法では、特に、絶縁層を形成するとき、未硬化樹脂からなる絶縁層形成用層を加熱により硬化収縮させて絶縁層を形成するため、ガラス基板が大きく反ってしまい、それ以後の工程への搬送やそれ以後の工程での加工精度に支障を来すという問題があった。   However, in the conventional method for manufacturing a semiconductor device, particularly when an insulating layer is formed, the insulating layer forming layer made of an uncured resin is cured and shrunk by heating to form the insulating layer. As a result, there is a problem that the transfer to the subsequent process and the processing accuracy in the subsequent process are hindered.

そこで、この発明は、ベース基板の反りを低減することができる半導体装置を提供することを目的とする。   In view of the above, an object of the present invention is to provide a semiconductor device capable of reducing warpage of a base substrate.

この発明は、上記目的を達成するため、上面に下層配線を有するベース基板と、前記ベース基板上に、半導体基板下に設けられた外部接続用電極を前記下層配線に接続されて設けられた半導体構成体と、前記半導体構成体の周囲における前記ベース基板上に設けられた絶縁層と、前記絶縁層上に設けられたハードシートと、前記半導体構成体、前記絶縁層および前記ハードシート上に設けられた上層絶縁膜と、前記上層絶縁膜上に前記下層配線に接続されて設けられた上層配線とを備えていることを特徴とするものである。   In order to achieve the above object, the present invention provides a base substrate having a lower layer wiring on the upper surface, and a semiconductor provided on the base substrate by connecting an external connection electrode provided below the semiconductor substrate to the lower layer wiring A structure, an insulating layer provided on the base substrate around the semiconductor structure, a hard sheet provided on the insulating layer, and provided on the semiconductor structure, the insulating layer, and the hard sheet And an upper-layer wiring provided on the upper-layer insulating film so as to be connected to the lower-layer wiring.

この発明によれば、ベース基板上に設けられた絶縁層上にハードシートを設けているので、この部分における厚さ方向の材料構成がほぼ対称的となり、絶縁層を形成するとき、未硬化樹脂からなる絶縁膜形成用膜を加熱加圧しても、絶縁層形成用層が厚さ方向にほぼ対称的に硬化収縮し、ひいては、ベース基板の反りを低減することができる。   According to the present invention, since the hard sheet is provided on the insulating layer provided on the base substrate, the material composition in the thickness direction in this portion becomes almost symmetrical, and when the insulating layer is formed, an uncured resin is formed. Even when the insulating film forming film is heated and pressed, the insulating layer forming layer is cured and contracted almost symmetrically in the thickness direction, and thus warpage of the base substrate can be reduced.

（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の断面図を示す。この半導体装置は平面方形状のガラス基板等からなる透明基板（ベース基板）１を備えている。透明基板１の上面の所定の箇所には銅箔からなる下層配線２が設けられている。下層配線２を含む透明基板１の上面には、透明基板１のサイズよりもある程度小さいサイズの平面方形状の半導体構成体（光センサ）３が設けられている。 (First embodiment)
FIG. 1 is a sectional view of a semiconductor device as a first embodiment of the present invention. This semiconductor device includes a transparent substrate (base substrate) 1 made of a planar rectangular glass substrate or the like. A lower layer wiring 2 made of copper foil is provided at a predetermined location on the upper surface of the transparent substrate 1. On the upper surface of the transparent substrate 1 including the lower layer wiring 2, a planar rectangular semiconductor structure (photosensor) 3 having a size somewhat smaller than the size of the transparent substrate 1 is provided.

半導体構成体３はシリコン基板（半導体基板）４を備えている。シリコン基板４の下面中央部にはＣＣＤ、フォトダイオード、フォトトランジスタ等の素子を含む光電変換デバイス領域５が設けられ、下面周辺部にはアルミニウム系金属等からなる複数の接続パッド６が光電変換デバイス領域５に接続されて設けられている。   The semiconductor structure 3 includes a silicon substrate (semiconductor substrate) 4. A photoelectric conversion device region 5 including elements such as a CCD, a photodiode, and a phototransistor is provided in the center portion of the lower surface of the silicon substrate 4, and a plurality of connection pads 6 made of aluminum-based metal or the like are provided in the periphery of the lower surface. It is connected to the region 5.

接続パッド６の中央部を除くシリコン基板４の下面には酸化シリコン等からなる絶縁膜７が設けられ、接続パッド６の中央部は絶縁膜７に設けられた開口部８を介して露出されている。絶縁膜７の下面にはエポキシ系樹脂やポリイミド系樹脂等からなる保護膜９が設けられている。この場合、絶縁膜７の開口部８に対応する部分における保護膜９には開口部１０が設けられている。   An insulating film 7 made of silicon oxide or the like is provided on the lower surface of the silicon substrate 4 except for the central portion of the connection pad 6, and the central portion of the connection pad 6 is exposed through an opening 8 provided in the insulating film 7. Yes. A protective film 9 made of epoxy resin, polyimide resin or the like is provided on the lower surface of the insulating film 7. In this case, an opening 10 is provided in the protective film 9 in a portion corresponding to the opening 8 of the insulating film 7.

保護膜９の下面には銅等からなる下地金属層１１が両開口部８、１０を介して接続パッド６に接続されて設けられている。下地金属層１１の下面全体には銅からなる柱状電極（外部接続用電極）１２が設けられている。保護膜９の下面にはエポキシ系樹脂やポリイミド系樹脂等からなる封止膜１３がその下面が柱状電極１２の下面と面一となるように設けられている。   A base metal layer 11 made of copper or the like is provided on the lower surface of the protective film 9 so as to be connected to the connection pad 6 through both openings 8 and 10. A columnar electrode (external connection electrode) 12 made of copper is provided on the entire lower surface of the base metal layer 11. A sealing film 13 made of epoxy resin, polyimide resin or the like is provided on the lower surface of the protective film 9 so that the lower surface thereof is flush with the lower surface of the columnar electrode 12.

そして、半導体構成体３は、柱状電極１２の下面が透明基板１上の下層配線２の内側の接続パッド部上面に半田層１４を介して接続されていることにより、下層配線２を含む透明基板１の上面に設けられている。この場合、透明基板１と半導体構成体３との間およびその周辺部にはエポキシ系樹脂等からなるアンダーフィル材１５が設けられている。   The semiconductor structure 3 includes a transparent substrate including the lower layer wiring 2 by connecting the lower surface of the columnar electrode 12 to the upper surface of the connection pad portion inside the lower layer wiring 2 on the transparent substrate 1 via the solder layer 14. 1 is provided on the top surface. In this case, an underfill material 15 made of an epoxy resin or the like is provided between the transparent substrate 1 and the semiconductor structure 3 and in the periphery thereof.

半導体構成体３の周囲における下層配線２を含む透明基板１の上面には方形枠状の絶縁層２１が設けられている。絶縁層２１は、通常、プリプレグ材と言われるもので、例えば、ガラス布、ガラス繊維、アラミド繊維等からなる基材にエポキシ系樹脂、ポリイミド系樹脂、ＢＴ樹脂等からなる熱硬化性樹脂を含浸させたものからなっている。   A rectangular frame-shaped insulating layer 21 is provided on the upper surface of the transparent substrate 1 including the lower layer wiring 2 around the semiconductor structure 3. The insulating layer 21 is usually called a prepreg material. For example, a base material made of glass cloth, glass fiber, aramid fiber or the like is impregnated with a thermosetting resin made of epoxy resin, polyimide resin, BT resin, or the like. Is made up of

絶縁層２１の上面周辺部には方形枠状のハードシート２２が埋め込まれている。ハードシート２２は、例えばガラスからなる透明基板１の熱膨張係数と同じかそれに近い熱膨張係数を有する材料、例えばセラミックスシートやニッケル合金等の低膨張金属シートからなっている。そして、絶縁層２１およびハードシート２２の上面は半導体構成体３の上面とほぼ面一となっている。   A square frame-shaped hard sheet 22 is embedded in the periphery of the upper surface of the insulating layer 21. The hard sheet 22 is made of a material having a thermal expansion coefficient equal to or close to that of the transparent substrate 1 made of glass, for example, a low expansion metal sheet such as a ceramic sheet or a nickel alloy. The upper surfaces of the insulating layer 21 and the hard sheet 22 are substantially flush with the upper surface of the semiconductor structure 3.

半導体構成体３、絶縁層２１およびハードシート２２の上面には上層絶縁膜２３がその上面を平坦とされて設けられている。上層絶縁膜２３は、ビルドアップ基板に用いられる、通常、ビルドアップ材と言われるもので、例えば、エポキシ系樹脂、ポリイミド系樹脂、ＢＴ樹脂等からなる熱硬化性樹脂中にガラス繊維、アラミド繊維、シリカフィラー、セラミックス系フィラー等からなる補強材を分散させたものからなっている。   An upper insulating film 23 is provided on the upper surface of the semiconductor structure 3, the insulating layer 21, and the hard sheet 22 so that the upper surface is flat. The upper insulating film 23 is generally used as a build-up material used for a build-up substrate. For example, glass fibers and aramid fibers are contained in a thermosetting resin made of epoxy resin, polyimide resin, BT resin, or the like. Further, a reinforcing material made of silica filler, ceramic filler or the like is dispersed.

透明基板１上の下層配線２の外側の接続パッド部に対応する部分における上層絶縁膜２３および絶縁層２１には開口部２４が設けられている。上層絶縁膜２３の上面には銅等からなる上層下地金属層２５が設けられている。上層下地金属層２５の上面全体には銅からなる上層配線２６が設けられている。上層下地金属層２５を含む上層配線２６の一端部は、上層絶縁膜２３および絶縁層２１の開口部２４を介して下層配線２の外側の接続パッド部上面に接続されている。   An opening 24 is provided in the upper insulating film 23 and the insulating layer 21 in a portion corresponding to the connection pad portion outside the lower wiring 2 on the transparent substrate 1. An upper base metal layer 25 made of copper or the like is provided on the upper surface of the upper insulating film 23. An upper wiring 26 made of copper is provided on the entire upper surface of the upper base metal layer 25. One end portion of the upper layer wiring 26 including the upper base metal layer 25 is connected to the upper surface of the connection pad portion outside the lower layer wiring 2 through the upper layer insulating film 23 and the opening 24 of the insulating layer 21.

上層配線２６を含む上層絶縁膜２３の上面にはソルダーレジスト等からなるオーバーコート膜２７が設けられている。上層配線２６の接続パッド部に対応する部分におけるオーバーコート膜２７には開口部２８が設けられている。開口部２８内およびその上方には半田ボール２９が上層配線２６の接続パッド部に接続されて設けられている。複数の半田ボール２９は、絶縁層２１上におけるオーバーコート膜２７上にマトリクス状に配置されている。   An overcoat film 27 made of a solder resist or the like is provided on the upper surface of the upper insulating film 23 including the upper wiring 26. An opening 28 is provided in the overcoat film 27 in a portion corresponding to the connection pad portion of the upper wiring 26. Solder balls 29 are provided in and above the opening 28 so as to be connected to the connection pad portion of the upper layer wiring 26. The plurality of solder balls 29 are arranged in a matrix on the overcoat film 27 on the insulating layer 21.

次に、この半導体装置の製造方法の一例について説明するに、まず、半導体構成体３の製造方法の一例について説明する。この場合、まず、図２に示すように、ウエハ状態のシリコン基板（半導体基板）４上にＣＣＤ等からなる光電変換デバイス領域５、アルミニウム系金属等からなる接続パッド６、酸化シリコン等からなる絶縁膜７およびエポキシ系樹脂やポリイミド系樹脂等からなる保護膜９が設けられ、接続パッド６の中央部が絶縁膜７および保護膜９に形成された開口部８、１０を介して露出されたものを用意する。   Next, an example of a method for manufacturing the semiconductor device 3 will be described. In this case, first, as shown in FIG. 2, on a silicon substrate (semiconductor substrate) 4 in a wafer state, a photoelectric conversion device region 5 made of CCD or the like, a connection pad 6 made of aluminum-based metal, etc., an insulation made of silicon oxide or the like. The film 7 and a protective film 9 made of epoxy resin, polyimide resin, or the like are provided, and the central portion of the connection pad 6 is exposed through the openings 8 and 10 formed in the insulating film 7 and the protective film 9 Prepare.

この場合、ウエハ状態のシリコン基板４の上面の各半導体構成体３が形成される領域の中央部に光電変換デバイス領域５が形成され、当該領域の周辺部に形成された接続パッド６は、それぞれ、対応する領域に形成された光電変換デバイス領域５に電気的に接続されている。   In this case, the photoelectric conversion device region 5 is formed in the central portion of the region where each semiconductor structure 3 is formed on the upper surface of the silicon substrate 4 in the wafer state, and the connection pads 6 formed in the peripheral portion of the region are respectively Are electrically connected to the photoelectric conversion device region 5 formed in the corresponding region.

次に、図３に示すように、両開口部８、１０を介して露出された接続パッド６の上面を含む保護膜９の上面全体に下地金属層１１を形成する。この場合、下地金属層１１は、無電解メッキにより形成された銅層のみであってもよく、またスパッタにより形成された銅層のみであってもよく、さらにスパッタにより形成されたチタン等の薄膜層上にスパッタにより銅層を形成したものであってもよい。   Next, as shown in FIG. 3, a base metal layer 11 is formed on the entire upper surface of the protective film 9 including the upper surface of the connection pad 6 exposed through both openings 8 and 10. In this case, the base metal layer 11 may be only a copper layer formed by electroless plating, may be only a copper layer formed by sputtering, or a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering.

次に、下地金属層１１の上面にメッキレジスト膜３１をパターン形成する。この場合、柱状電極１２形成領域に対応する部分におけるメッキレジスト膜３１には開口部３２が形成されている。次に、下地金属層１１をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜３１の開口部３２内の下地金属層１１の上面に柱状電極１２を形成する。次に、メッキレジスト膜３１を剥離し、次いで、柱状電極１２をマスクとして下地金属層１１の不要な部分をエッチングして除去すると、図４に示すように、柱状電極１２下にのみ下地金属層１１が残存される。   Next, a plating resist film 31 is pattern-formed on the upper surface of the base metal layer 11. In this case, an opening 32 is formed in the plating resist film 31 in a portion corresponding to the columnar electrode 12 formation region. Next, by performing electrolytic plating of copper using the base metal layer 11 as a plating current path, the columnar electrode 12 is formed on the upper surface of the base metal layer 11 in the opening 32 of the plating resist film 31. Next, when the plating resist film 31 is peeled off, and then unnecessary portions of the base metal layer 11 are removed by etching using the columnar electrodes 12 as a mask, as shown in FIG. 11 remains.

次に、図５に示すように、スクリーン印刷法、スピンコート法、ダイコート法等により、柱状電極１２を含む保護膜９の上面全体にエポキシ系樹脂やポリイミド系樹脂等からなる封止膜１３をその厚さが柱状電極１２の高さよりも厚くなるように形成する。したがって、この状態では、柱状電極１２の上面は封止膜１３によって覆われている。   Next, as shown in FIG. 5, a sealing film 13 made of epoxy resin, polyimide resin, or the like is formed on the entire upper surface of the protective film 9 including the columnar electrode 12 by screen printing, spin coating, die coating, or the like. The thickness is formed so as to be thicker than the height of the columnar electrode 12. Therefore, in this state, the upper surface of the columnar electrode 12 is covered with the sealing film 13.

次に、封止膜１３および柱状電極１２の上面側を適宜に研磨し、図６に示すように、柱状電極１２の上面を露出させ、且つ、この露出された柱状電極１２の上面を含む封止膜１３の上面を平坦化する。ここで、柱状電極１２の上面側を適宜に研磨するのは、電解メッキにより形成される柱状電極１２の高さにばらつきがあるため、このばらつきを解消して、柱状電極１２の高さを均一にするためである。   Next, the upper surface side of the sealing film 13 and the columnar electrode 12 is appropriately polished to expose the upper surface of the columnar electrode 12 and to include the exposed upper surface of the columnar electrode 12 as shown in FIG. The upper surface of the stop film 13 is flattened. Here, the reason why the upper surface side of the columnar electrode 12 is appropriately polished is that there is a variation in the height of the columnar electrode 12 formed by electrolytic plating, so this variation is eliminated and the height of the columnar electrode 12 is made uniform. It is to make it.

次に、シリコン基板４の下面をダイシングテープ（図示せず）に貼り付け、図７に示すダイシング工程を経た後に、ダイシングテープから剥がすと、図１に示す半導体構成体３が複数個得られる。なお、図６に示す工程後に、柱状電極１２の上面に半田層１４（図１参照）を設け、この後に、ダイシングを行なうようにしてもよい。   Next, the lower surface of the silicon substrate 4 is attached to a dicing tape (not shown), and after passing through the dicing process shown in FIG. 7, the semiconductor substrate 3 is peeled off from the dicing tape to obtain a plurality of semiconductor structures 3 shown in FIG. 1. Note that, after the step shown in FIG. 6, a solder layer 14 (see FIG. 1) may be provided on the upper surface of the columnar electrode 12, and then dicing may be performed.

次に、このようにして得られた半導体構成体３を用いて、図１に示す半導体装置を製造する場合の一例について説明する。まず、図８に示すように、図１に示す完成された半導体装置を複数個形成することが可能な面積を有するガラス基板等からなる透明基板１を用意する。この場合、透明基板１の上面には、透明基板１の上面にラミネートされた銅箔をフォトリソグラフィ法によりバターニングすることにより、下層配線２が形成されている。   Next, an example of manufacturing the semiconductor device shown in FIG. 1 using the semiconductor structure 3 obtained in this manner will be described. First, as shown in FIG. 8, a transparent substrate 1 made of a glass substrate or the like having an area capable of forming a plurality of completed semiconductor devices shown in FIG. 1 is prepared. In this case, the lower layer wiring 2 is formed on the upper surface of the transparent substrate 1 by patterning the copper foil laminated on the upper surface of the transparent substrate 1 by photolithography.

次に、半導体構成体３の柱状電極１２の下面を透明基板１上の下層配線２の内側の接続パッド部上面に半田層１４を介して接続することにより、半導体構成体３を下層配線２を含む透明基板１の上面に配置する。次に、透明基板１と半導体構成体３との間およびその周辺部にエポキシ系樹脂等からなるアンダーフィル材１５を充填する。   Next, the lower surface of the columnar electrode 12 of the semiconductor structure 3 is connected to the upper surface of the connection pad portion inside the lower layer wiring 2 on the transparent substrate 1 through the solder layer 14 so that the semiconductor structure 3 is connected to the lower layer wiring 2. It arrange | positions on the upper surface of the transparent substrate 1 containing. Next, an underfill material 15 made of an epoxy resin or the like is filled between the transparent substrate 1 and the semiconductor structure 3 and in the periphery thereof.

次に、図９に示すように、半導体構成体３の周囲における下層配線２を含む透明基板１の上面に、格子状の２枚の絶縁層形成用シート２１ａ、２１ｂおよび同じく格子状の１枚のハードシート２２をピン等で位置決めしながら積層して配置する。なお、２枚の絶縁層形成用シート２１ａ、２１ｂおよび１枚のハードシート２２を積層して配置した後に、半導体構成体３を配置するようにしてもよい。   Next, as shown in FIG. 9, on the upper surface of the transparent substrate 1 including the lower layer wiring 2 around the semiconductor structure 3, two grid-like insulating layer forming sheets 21a and 21b and one grid-like sheet are formed. The hard sheets 22 are stacked and positioned with pins or the like. The semiconductor structure 3 may be arranged after the two insulating layer forming sheets 21a and 21b and the one hard sheet 22 are laminated.

格子状の絶縁層形成用シート２１ａ、２１ｂは、ガラス布等からなる基材にエポキシ系樹脂等からなる熱硬化性樹脂を含浸させ、熱硬化性樹脂を半硬化状態（Ｂステージ）にしてシート状となしたプリプレグ材に、パンチング、あるいは、ドリルまたはルーター加工等により、複数の方形状の開口部３３を形成することにより得られる。   The grid-like insulating layer forming sheets 21a and 21b are made by impregnating a base material made of glass cloth or the like with a thermosetting resin made of epoxy resin or the like, and making the thermosetting resin semi-cured (B stage). It is obtained by forming a plurality of rectangular openings 33 in the prepreg material formed into a shape by punching, drilling or router processing.

格子状のハードシート２２は、例えばガラス基板からなる透明基板１の熱膨張係数と同じかそれに近い熱膨張係数を有する材料、例えばセラミックスシートやニッケル合金等の低膨張金属シートに、パンチング、あるいは、ドリルまたはルーター加工等により、複数の方形状の開口部３４を形成することにより得られる。   The lattice-like hard sheet 22 is punched on a material having a thermal expansion coefficient equal to or close to the thermal expansion coefficient of the transparent substrate 1 made of a glass substrate, for example, a low expansion metal sheet such as a ceramic sheet or a nickel alloy, or It is obtained by forming a plurality of rectangular openings 34 by drilling or router processing.

ここで、ハードシート２２の開口部３４のサイズは絶縁層形成用シート２１ａ、２１ｂの開口部３３のサイズよりもある程度大きくなっている。これは、図１に示す開口部２４を形成することができるようにするためである。また、絶縁層形成用シート２１ａ、２１ｂの開口部３３のサイズは半導体構成体３のサイズよりもやや大きくなっている。このため、絶縁層形成用シート２１ａ、２１ｂおよびハードシート２２と半導体構成体３との間には隙間３５が形成されている。   Here, the size of the opening 34 of the hard sheet 22 is somewhat larger than the size of the opening 33 of the insulating layer forming sheets 21a and 21b. This is because the opening 24 shown in FIG. 1 can be formed. In addition, the size of the opening 33 of the insulating layer forming sheets 21 a and 21 b is slightly larger than the size of the semiconductor structure 3. For this reason, a gap 35 is formed between the insulating layer forming sheets 21 a and 21 b and the hard sheet 22 and the semiconductor structure 3.

また、絶縁層形成用シート２１ａ、２１ｂおよびハードシート２２の合計厚さは、半導体構成体３の厚さよりもある程度厚く、後述の如く、加熱加圧されたときに、絶縁層形成用シート２１ａ、２１ｂ中の熱硬化性樹脂によって隙間３５を十分に埋めることができる程度の厚さとなっている。   Further, the total thickness of the insulating layer forming sheets 21a and 21b and the hard sheet 22 is somewhat thicker than the thickness of the semiconductor structure 3, and when heated and pressurized as will be described later, the insulating layer forming sheet 21a, The thickness is such that the gap 35 can be sufficiently filled with the thermosetting resin in 21b.

ところで、絶縁層形成用シート２１ａ、２１ｂとして、厚さが同じものを用いているが、厚さが異なるものを用いてもよい。また、絶縁層形成用シートは、上記の如く、２層であってもよいが、１層または３層以上であってもよい。要は、絶縁層形成用シートの上面にハードシート２２が配置されていればよい。   By the way, although the same thickness is used as the insulating layer forming sheets 21a and 21b, sheets having different thicknesses may be used. Further, the insulating layer forming sheet may have two layers as described above, but may have one layer or three or more layers. In short, it is sufficient that the hard sheet 22 is disposed on the upper surface of the insulating layer forming sheet.

次に、ハードシート２２の上面に上層絶縁膜形成用シート２３ａを配置する。この場合、上層絶縁膜形成用シート２３ａは、限定する意味ではないが、シート状のビルドアップ材が好ましく、このビルドアップ材としては、エポキシ系樹脂等の熱硬化性樹脂中にシリカフィラーを混入させ、熱硬化性樹脂を半硬化状態にしたものがある。   Next, the upper insulating film forming sheet 23 a is disposed on the upper surface of the hard sheet 22. In this case, the upper insulating film forming sheet 23a is not limited, but is preferably a sheet-like buildup material. As this buildup material, a silica filler is mixed in a thermosetting resin such as an epoxy resin. Some thermosetting resins are in a semi-cured state.

次に、図１０に示すように、一対の加熱加圧板３６、３７を用いて上下から絶縁層形成用シート２１ａ、２１ｂ、ハードシート２２および上層絶縁膜形成用シート２３ａを加熱加圧する。すると、絶縁層形成用シート２１ａ、２１ｂ中の溶融された熱硬化性樹脂が図９に示す隙間３５内に押し出されて充填され、その後の冷却により、半導体構成体３の周囲における下層配線２を含む透明基板１の上面に絶縁層２１が形成される。   Next, as shown in FIG. 10, the insulating layer forming sheets 21 a and 21 b, the hard sheet 22, and the upper insulating film forming sheet 23 a are heated and pressed from above and below using a pair of heating and pressing plates 36 and 37. Then, the melted thermosetting resin in the insulating layer forming sheets 21a and 21b is extruded and filled in the gap 35 shown in FIG. 9, and the subsequent lower layer wiring 2 around the semiconductor structure 3 is formed by cooling. An insulating layer 21 is formed on the upper surface of the transparent substrate 1 including the insulating substrate 21.

ハードシート２２は、セラミックスシートやニッケル合金等の低膨張金属シートからなっているため、加熱加圧されても変形せず、絶縁層２１の上面の所定の領域（例えば、図１に示す開口部２４を除く領域）に埋め込まれる。そして、この状態では、絶縁層２１およびハードシート２２の上面は半導体構成体１の上面とほぼ面一となる。なお、ハードシート２２は、必ずしもその上面が絶縁層２１の上面と面一となるように埋め込む必要はなく、また、半導体構成体３の上面とも面一にする必要もない。   Since the hard sheet 22 is made of a low expansion metal sheet such as a ceramic sheet or a nickel alloy, the hard sheet 22 does not deform even when heated and pressed, and a predetermined region (for example, the opening shown in FIG. 1) on the upper surface of the insulating layer 21. Embedded in the area excluding 24). In this state, the upper surfaces of the insulating layer 21 and the hard sheet 22 are substantially flush with the upper surface of the semiconductor structure 1. The hard sheet 22 does not necessarily need to be embedded so that the upper surface thereof is flush with the upper surface of the insulating layer 21, and does not need to be flush with the upper surface of the semiconductor structure 3.

また、半導体構成体３、絶縁層２１およびハードシート２２の上面に上層絶縁膜２３が形成される。この場合、上層絶縁膜２３の上面は、上側の加熱加圧板３８の下面によって押さえ付けられるため、平坦面となる。したがって、上層絶縁膜２３の上面を平坦化するための研磨工程は不要である。   An upper insulating film 23 is formed on the upper surfaces of the semiconductor structure 3, the insulating layer 21, and the hard sheet 22. In this case, since the upper surface of the upper insulating film 23 is pressed by the lower surface of the upper heating / pressing plate 38, it becomes a flat surface. Therefore, a polishing step for flattening the upper surface of the upper insulating film 23 is not necessary.

ところで、図９に示すように、下層配線２を含む透明基板１の上面に配置された絶縁層形成用シート２１ａ、２１ｂの上面に、透明基板１の熱膨張係数と同じかそれに近い熱膨張係数を有する材料からなるハードシート２２を配置しているので、この部分における厚さ方向の材料構成がほぼ対称的となる。また、絶縁層形成用シート２１ａ、２１ｂの合計体積をハードシート２２の体積に相当する分だけ少なくすることができる。   By the way, as shown in FIG. 9, the thermal expansion coefficient is the same as or close to the thermal expansion coefficient of the transparent substrate 1 on the upper surface of the insulating layer forming sheets 21 a and 21 b disposed on the upper surface of the transparent substrate 1 including the lower layer wiring 2. Since the hard sheet 22 made of a material having the above is disposed, the material structure in the thickness direction in this portion is almost symmetrical. Further, the total volume of the insulating layer forming sheets 21 a and 21 b can be reduced by an amount corresponding to the volume of the hard sheet 22.

この結果、加熱加圧により、絶縁層形成用シート２１ａ、２１ｂおよび上層絶縁膜形成用シート２３ａが厚さ方向にほぼ対称的に硬化収縮し、ひいては、透明基板１に発生する反りが低減され、それ以後の工程への搬送やそれ以後の工程での加工精度に支障を来しにくいようにすることができる。   As a result, the insulating layer forming sheets 21a and 21b and the upper insulating film forming sheet 23a are cured and contracted substantially symmetrically in the thickness direction by heating and pressurization, and as a result, the warpage generated in the transparent substrate 1 is reduced. It is possible to make it difficult for the conveyance to the subsequent process and the processing accuracy in the subsequent process to be hindered.

なお、上層絶縁膜形成用シート２３ａとして、ガラス布等からなる基材にエポキシ系樹脂等からなる熱硬化性樹脂を含浸させ、熱硬化性樹脂を半硬化状態にしてシート状となしたプリプレグ材、または、シリカフィラーが混入されない半硬化状態の熱硬化性樹脂のみからなるシート状のものを用いるようにしてもよい。   As the upper insulating film forming sheet 23a, a prepreg material in which a base material made of glass cloth or the like is impregnated with a thermosetting resin made of an epoxy resin or the like and the thermosetting resin is made into a semi-cured state into a sheet shape Or you may make it use the sheet-like thing which consists only of a semi-hardened thermosetting resin in which a silica filler is not mixed.

次に、図１１に示すように、ＣＯ2レーザ等のレーザビームを照射するレーザ加工により、下層配線２の外側の接続パッドに対応する部分における上層絶縁膜２３および絶縁層２１に開口部２４を形成する。次に、必要に応じて、開口部２４内等に発生したエポキシスミア等をデスミア処理により除去する。 Next, as shown in FIG. 11, an opening 24 is formed in the upper insulating film 23 and the insulating layer 21 in a portion corresponding to the connection pad outside the lower wiring 2 by laser processing that irradiates a laser beam such as a CO 2 laser. Form. Next, the epoxy smear etc. which generate | occur | produced in the opening part 24 etc. are removed by a desmear process as needed.

次に、図１２に示すように、開口部２４を介して露出された下層配線２の外側の接続パッド上面を含む上層絶縁膜２３の上面全体に、銅の無電解メッキ等により、上層下地金属層２５を形成する。次に、上層下地金属層２５の上面にメッキレジスト膜３８をパターン形成する。この場合、上層配線２６形成領域に対応する部分におけるメッキレジスト膜３８には開口部３９が形成されている。   Next, as shown in FIG. 12, the upper layer base metal is formed on the entire upper surface of the upper insulating film 23 including the upper surface of the connection pad outside the lower layer wiring 2 exposed through the opening 24 by electroless plating of copper or the like. Layer 25 is formed. Next, a plating resist film 38 is patterned on the upper surface of the upper base metal layer 25. In this case, an opening 39 is formed in the plating resist film 38 in a portion corresponding to the upper layer wiring 26 formation region.

次に、上層下地金属層２５をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜３８の開口部３９内の上層下地金属層２５の上面に上層配線２６を形成する。次に、メッキレジスト膜３８を剥離し、次いで、上層配線２６をマスクとして上層下地金属層２５の不要な部分をエッチングして除去すると、図１３に示すように、上層配線２６下にのみ上層下地金属層２５が残存される。この状態では、上層下地金属層２５を含む上層配線２６の一端部は、上層絶縁膜２３および絶縁層２１の開口部２４を介して下層配線２の外側の接続パッド部上面に接続されている。   Next, by performing copper electroplating using the upper base metal layer 25 as a plating current path, the upper layer wiring 26 is formed on the upper surface of the upper base metal layer 25 in the opening 39 of the plating resist film 38. Next, the plating resist film 38 is peeled off, and then an unnecessary portion of the upper base metal layer 25 is removed by etching using the upper layer wiring 26 as a mask. As shown in FIG. The metal layer 25 remains. In this state, one end portion of the upper layer wiring 26 including the upper base metal layer 25 is connected to the upper surface of the connection pad portion outside the lower layer wiring 2 through the upper layer insulating film 23 and the opening 24 of the insulating layer 21.

次に、図１４に示すように、スクリーン印刷法、スピンコート法、ダイコート法等により、上層配線２６を含む第２の上層絶縁膜２３の上面にソルダーレジスト等からなるオーバーコート膜２７を形成する。この場合、上層配線２６の接続パッド部に対応する部分におけるオーバーコート膜２７には開口部２８が形成されている。   Next, as shown in FIG. 14, an overcoat film 27 made of a solder resist or the like is formed on the upper surface of the second upper layer insulating film 23 including the upper layer wiring 26 by screen printing, spin coating, die coating, or the like. . In this case, an opening 28 is formed in the overcoat film 27 in a portion corresponding to the connection pad portion of the upper layer wiring 26.

次に、開口部２８内およびその上方に半田ボール２９を上層配線２６の接続パッド部に接続させて形成する。次に、互いに隣接する半導体構成体３間において、オーバーコート膜２７、上層絶縁膜２３、ハードシート２２、絶縁層２１および透明基板１を切断すると、図１に示す半導体装置が複数個得られる。   Next, a solder ball 29 is formed in and above the opening 28 by being connected to the connection pad portion of the upper wiring 26. Next, when the overcoat film 27, the upper insulating film 23, the hard sheet 22, the insulating layer 21, and the transparent substrate 1 are cut between the adjacent semiconductor structures 3, a plurality of semiconductor devices shown in FIG. 1 are obtained.

このようにして得られた半導体装置では、透明基板１の上面に設けられた絶縁層２１の上面に、透明基板１の熱膨張係数と同じかそれに近い熱膨張係数を有するハードシート２２が設けられているので、この部分における厚さ方向の材料構成がほぼ対称的となり、したがって、全体として反りにくい構造とすることができる。   In the semiconductor device thus obtained, a hard sheet 22 having a thermal expansion coefficient equal to or close to that of the transparent substrate 1 is provided on the upper surface of the insulating layer 21 provided on the upper surface of the transparent substrate 1. Therefore, the material composition in the thickness direction in this portion is almost symmetrical, and therefore, the overall structure is difficult to warp.

ところで、上記製造方法では、透明基板１上に複数の半導体構成体３を配置し、複数の半導体構成体３に対して、上層配線２６および半田ボール２９の形成を一括して行い、その後に分断して複数個の半導体装置を得ているので、製造工程を簡略化することができる。また、図１０に示す製造工程以降では、透明基板１と共に複数の半導体構成体３を搬送することができるので、これによっても製造工程を簡略化することができる。   By the way, in the above manufacturing method, a plurality of semiconductor structures 3 are arranged on the transparent substrate 1, and the upper layer wiring 26 and the solder balls 29 are collectively formed on the plurality of semiconductor structures 3, and then divided. Since a plurality of semiconductor devices are obtained, the manufacturing process can be simplified. Moreover, since the several semiconductor structure 3 can be conveyed with the transparent substrate 1 after the manufacturing process shown in FIG. 10, a manufacturing process can also be simplified by this.

（第２実施形態）
図１５はこの発明の第２実施形態としての半導体装置の断面図を示す。この半導体装置において、図１に示す半導体装置と異なる点は、透明基板１と半導体構成体３との間の周辺部のみにアンダーフィル材１５を設け、且つ、半導体構成体３の下面中央部に対向する部分における透明基板１の上面に座ぐり加工により凹部４１を設けた点である。 (Second Embodiment)
FIG. 15 is a sectional view of a semiconductor device as a second embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that an underfill material 15 is provided only in the peripheral portion between the transparent substrate 1 and the semiconductor structure 3, and the lower surface central portion of the semiconductor structure 3 is provided. This is that a concave portion 41 is provided by spot facing on the upper surface of the transparent substrate 1 in the facing portion.

この半導体装置では、半導体構成体３の下面中央部とそれに対向する部分における透明基板１との間に比較的大きな空洞部４２が形成されるため、半導体構成体３のシリコン基板４の下面中央部に設けられた光電変換デバイス領域５への応力を低減することができる。なお、透明基板１と半導体構成体３との間の周辺部のみにアンダーフィル材１５を設け、透明基板１の上面に凹部４１を設けないようにしてもよい。   In this semiconductor device, since a relatively large cavity 42 is formed between the central portion of the lower surface of the semiconductor structure 3 and the transparent substrate 1 at the portion facing the semiconductor substrate 3, the central portion of the lower surface of the silicon substrate 4 of the semiconductor structure 3 is formed. It is possible to reduce the stress on the photoelectric conversion device region 5 provided in. Note that the underfill material 15 may be provided only in the peripheral portion between the transparent substrate 1 and the semiconductor structure 3, and the concave portion 41 may not be provided on the upper surface of the transparent substrate 1.

（第３実施形態）
図１６はこの発明の第３実施形態としての半導体装置の断面図を示す。この半導体装置において、図１に示す半導体装置と異なる点は、複数の上層配線２６の接続パッド部を上層絶縁膜２３上のほぼ全面にマトリクス状に配置し、複数の半田ボール２９をオーバーコート膜２７上のほぼ全面にマトリクス状に配置した点である。 (Third embodiment)
FIG. 16 is a sectional view of a semiconductor device as a third embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that connection pad portions of a plurality of upper layer wirings 26 are arranged in a matrix on almost the entire surface of the upper layer insulating film 23, and a plurality of solder balls 29 are disposed on the overcoat film. 27 is arranged in a matrix on almost the entire surface.

（第４実施形態）
図１７はこの発明の第４実施形態としての半導体装置の断面図を示す。この半導体装置において、図１に示す半導体装置と大きく異なる点は、半導体構成体３の上面にハードシート２２の一部を設けた点である。この場合、上層絶縁膜２３および絶縁層２１の開口部２４に対応する部分におけるハードシート２２には開口部４３が設けられている。 (Fourth embodiment)
FIG. 17 is a sectional view of a semiconductor device as a fourth embodiment of the present invention. This semiconductor device differs greatly from the semiconductor device shown in FIG. 1 in that a part of the hard sheet 22 is provided on the upper surface of the semiconductor structure 3. In this case, an opening 43 is provided in the hard sheet 22 in a portion corresponding to the opening 24 of the upper insulating film 23 and the insulating layer 21.

なお、この半導体装置では、複数の上層配線２６の接続パッド部はほぼ半導体構成体３上における上層絶縁膜２３上にマトリクス状に配置され、複数の半田ボール２９はほぼ半導体構成体３上におけるオーバーコート膜２７上にマトリクス状に配置されている。   In this semiconductor device, the connection pad portions of the plurality of upper layer wirings 26 are arranged in a matrix on the upper layer insulating film 23 on the semiconductor structure 3, and the plurality of solder balls 29 are substantially over the semiconductor structure 3. The coat film 27 is arranged in a matrix.

（第５実施形態）
図１８はこの発明の第５実施形態としての半導体装置の断面図を示す。この半導体装置において、図１に示す場合と大きく異なる点は、上層絶縁膜および上層配線を２層とした点である。すなわち、第１の上層配線２６Ａを含む第１の上層絶縁膜２３Ａの上面には第１の上層絶縁膜２３Ａと同じ材料からなる第２の上層絶縁膜２３Ｂが設けられている。第２の上層絶縁膜２３Ｂの上面には下地金属層２５Ｂを含む第２の上層配線２６Ｂが設けられている。 (Fifth embodiment)
FIG. 18 is a sectional view of a semiconductor device as a fifth embodiment of the present invention. In this semiconductor device, the main difference from the case shown in FIG. 1 is that the upper insulating film and the upper wiring have two layers. That is, a second upper layer insulating film 23B made of the same material as the first upper layer insulating film 23A is provided on the upper surface of the first upper layer insulating film 23A including the first upper layer wiring 26A. A second upper layer wiring 26B including a base metal layer 25B is provided on the upper surface of the second upper layer insulating film 23B.

下地金属層２５Ａを含む第１の上層配線２６Ａの一端部は、第１の上層絶縁膜２３Ａおよび絶縁層２１の開口部２４Ａを介して下層配線２の外側の接続パッド部上面に接続されている。下地金属層２５Ｂを含む第２の上層配線２６Ｂの一端部は、第２の上層絶縁膜２３Ｂの開口部２４Ｂを介して第１の上層配線２６Ａの接続パッド部上面に接続されている。半田ボール２９は、オーバーコート膜２７の開口部２８を介して第２の上層配線２６Ｂの接続パッド部上面に接続されている。なお、上層絶縁膜および上層配線は３層以上としてもよい。   One end of the first upper layer wiring 26A including the base metal layer 25A is connected to the upper surface of the connection pad portion outside the lower layer wiring 2 through the first upper layer insulating film 23A and the opening 24A of the insulating layer 21. . One end portion of the second upper layer wiring 26B including the base metal layer 25B is connected to the upper surface of the connection pad portion of the first upper layer wiring 26A through the opening 24B of the second upper layer insulating film 23B. The solder ball 29 is connected to the upper surface of the connection pad portion of the second upper layer wiring 26B through the opening 28 of the overcoat film 27. Note that the upper insulating film and the upper wiring may have three or more layers.

（その他の実施形態）
上記各実施形態では、半導体基板４に光電変換デバイス領域５が形成されているものとしたが、光電変換デバイス領域５に限らず、メモリ用や制御用の集積回路、ＭＥＭＳ（Micro Electro Mechanical System）等のセンサ、表面弾性（ＳＡＷ）フィルタ等が形成されているデバイスにも適用可能である。この場合、ベース基板としては、透明にする必要がない場合には、有害な光を遮断するため、不透明なセラミック等の絶縁基板を用いるようにしてもよい。 (Other embodiments)
In each of the embodiments described above, the photoelectric conversion device region 5 is formed on the semiconductor substrate 4, but not limited to the photoelectric conversion device region 5, an integrated circuit for memory or control, MEMS (Micro Electro Mechanical System). The present invention is also applicable to a device in which a sensor such as a sensor, a surface elasticity (SAW) filter, or the like is formed. In this case, if it is not necessary to make the base substrate transparent, an insulating substrate such as an opaque ceramic may be used to block harmful light.

また、上記第１実施形態では、図１４に示す工程後に、互いに隣接する半導体構成体３間において切断したが、これに限らず、２個またはそれ以上の半導体構成体３を１組として切断し、マルチチップモジュール型の半導体装置を得るようにしてもよい。例えば、２個の半導体構成体を１組として切断し、一方の半導体構成体を光電変換デバイス領域を有する光センサとし、他方の半導体構成体を光センサの周辺駆動回路としての機能を有するものとし、両者を下層配線や上層配線で電気的に接続するようにしてもよい。   Further, in the first embodiment, after the step shown in FIG. 14, the semiconductor structures 3 adjacent to each other are cut. However, the present invention is not limited to this, and two or more semiconductor structures 3 are cut as one set. A multichip module type semiconductor device may be obtained. For example, it is assumed that two semiconductor structures are cut as a set, one semiconductor structure is a photosensor having a photoelectric conversion device region, and the other semiconductor structure has a function as a peripheral drive circuit of the photosensor. Both may be electrically connected by lower layer wiring or upper layer wiring.

この発明の第１実施形態としての半導体装置の断面図。1 is a cross-sectional view of a semiconductor device as a first embodiment of the present invention. 図１に示す半導体装置の製造方法の一例において、当初用意したものの断面 図。Sectional drawing of what was prepared initially in an example of the manufacturing method of the semiconductor device shown in FIG. 図２に続く工程の断面図。Sectional drawing of the process following FIG. 図３に続く工程の断面図。Sectional drawing of the process following FIG. 図４に続く工程の断面図。Sectional drawing of the process following FIG. 図５に続く工程の断面図。Sectional drawing of the process following FIG. 図６に続く工程の断面図。Sectional drawing of the process following FIG. 図７に続く工程の断面図。Sectional drawing of the process following FIG. 図８に続く工程の断面図。FIG. 9 is a cross-sectional view of the process following FIG. 8. 図９に続く工程の断面図。Sectional drawing of the process following FIG. 図１０に続く工程の断面図。Sectional drawing of the process following FIG. 図１１に続く工程の断面図。Sectional drawing of the process following FIG. 図１２に続く工程の断面図。Sectional drawing of the process following FIG. 図１３に続く工程の断面図。Sectional drawing of the process following FIG. この発明の第２実施形態を説明するために示す所定の工程の断面図。Sectional drawing of the predetermined process shown in order to demonstrate 2nd Embodiment of this invention. この発明の第３実施形態を説明するために示す所定の工程の断面図。Sectional drawing of the predetermined process shown in order to demonstrate 3rd Embodiment of this invention. この発明の第４実施形態を説明するために示す所定の工程の断面図。Sectional drawing of the predetermined | prescribed process shown in order to demonstrate 4th Embodiment of this invention. この発明の第５実施形態を説明するために示す所定の工程の断面図。Sectional drawing of the predetermined | prescribed process shown in order to demonstrate 5th Embodiment of this invention.

符号の説明Explanation of symbols

１ 透明基板
２ 下層配線
３ 半導体構成体
４ シリコン基板
５ 光電変換デバイス領域
６ 接続パッド
１２ 柱状電極
１３ 封止膜
２１ 絶縁層
２２ ハードシート
２３ 上層絶縁膜
２４ 開口部
２５ 上層配線
２７ オーバーコート膜
２９ 半田ボール DESCRIPTION OF SYMBOLS 1 Transparent substrate 2 Lower layer wiring 3 Semiconductor structure 4 Silicon substrate 5 Photoelectric conversion device area 6 Connection pad 12 Columnar electrode 13 Sealing film 21 Insulating layer 22 Hard sheet 23 Upper layer insulating film 24 Opening part 25 Upper layer wiring 27 Overcoat film 29 Solder ball

Claims (15)

上面に下層配線を有するベース基板と、前記ベース基板上に、半導体基板下に設けられた外部接続用電極を前記下層配線に接続されて設けられた半導体構成体と、前記半導体構成体の周囲における前記ベース基板上に設けられた絶縁層と、少なくとも前記絶縁層上に設けられたハードシートと、前記半導体構成体、前記絶縁層および前記ハードシート上に設けられた上層絶縁膜と、前記上層絶縁膜上に前記下層配線に接続されて設けられた上層配線とを備えていることを特徴とする半導体装置。   A base substrate having a lower layer wiring on the upper surface, a semiconductor structure provided on the base substrate with an external connection electrode provided below the semiconductor substrate connected to the lower layer wiring, and a periphery of the semiconductor structure An insulating layer provided on the base substrate; a hard sheet provided on at least the insulating layer; an upper insulating film provided on the semiconductor structure; the insulating layer; and the hard sheet; and the upper insulating layer. A semiconductor device comprising: an upper layer wiring provided on the film connected to the lower layer wiring. 請求項１に記載の発明において、前記ハードシートは前記ベース基板の熱膨張係数と同じかそれに近い熱膨張係数を有する材料からなることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the hard sheet is made of a material having a thermal expansion coefficient equal to or close to that of the base substrate. 請求項１に記載の発明において、前記ハードシートは前記絶縁層の上面に埋め込まれていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the hard sheet is embedded in an upper surface of the insulating layer. 請求項３に記載の発明において、前記絶縁層および前記ハードシートの上面は前記半導体構成体の上面とほぼ面一であることを特徴とする半導体装置。   4. The semiconductor device according to claim 3, wherein upper surfaces of the insulating layer and the hard sheet are substantially flush with an upper surface of the semiconductor structure. 請求項２に記載の発明において、前記ハードシートの一部は前記半導体構成体の上面に設けられていることを特徴とする半導体装置。   The semiconductor device according to claim 2, wherein a part of the hard sheet is provided on an upper surface of the semiconductor structure. 請求項１に記載の発明において、前記半導体構成体の外部接続用電極は柱状電極であることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the external connection electrode of the semiconductor structure is a columnar electrode. 請求項６に記載の発明において、前記半導体構成体の柱状電極は前記下層配線に半田を介して接続されていることを特徴とする半導体装置。   7. The semiconductor device according to claim 6, wherein the columnar electrode of the semiconductor structure is connected to the lower layer wiring via solder. 請求項７に記載の発明において、前記ベース基板と前記半導体構成体との間にアンダーフィル材が充填されていることを特徴とする半導体装置。   The semiconductor device according to claim 7, wherein an underfill material is filled between the base substrate and the semiconductor structure. 請求項７に記載の発明において、前記ベース基板と前記半導体構成体との間の周辺部のみにアンダーフィル材が設けられていることを特徴とする半導体装置。   8. The semiconductor device according to claim 7, wherein an underfill material is provided only in a peripheral portion between the base substrate and the semiconductor structure. 請求項１に記載の発明において、前記上層配線は前記上層絶縁膜および前記絶縁層に設けられた開口部を介して前記下層配線に接続されていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the upper layer wiring is connected to the lower layer wiring through an opening provided in the upper layer insulating film and the insulating layer. 請求項１に記載の発明において、前記上層配線の接続パッド部を除く部分を覆うオーバーコート膜を有することを特徴とする半導体装置。   2. The semiconductor device according to claim 1, further comprising an overcoat film that covers a portion of the upper wiring except for a connection pad portion. 請求項１１に記載の発明において、前記上層配線の接続パッド部上に半田ボールが設けられていることを特徴とする半導体装置。   12. The semiconductor device according to claim 11, wherein a solder ball is provided on a connection pad portion of the upper layer wiring. 請求項１に記載の発明において、前記ベース基板は透明基板からなり、前記半導体構成体の半導体基板の下面に光電変換デバイス領域が設けられていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the base substrate is made of a transparent substrate, and a photoelectric conversion device region is provided on a lower surface of the semiconductor substrate of the semiconductor structure. 請求項１３に記載の発明において、前記透明基板はガラス基板であることを特徴とする半導体装置。   14. The semiconductor device according to claim 13, wherein the transparent substrate is a glass substrate. 請求項１４に記載の発明において、前記ハードシートは、前記ガラス基板の熱膨張係数と同じかそれに近い熱膨張係数を有するセラミックスシートまたは金属シートであることを特徴とする半導体装置。
15. The semiconductor device according to claim 14, wherein the hard sheet is a ceramic sheet or a metal sheet having a thermal expansion coefficient equal to or close to that of the glass substrate.
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