JP2006128662A - Semiconductor and its mounting body - Google Patents

Semiconductor and its mounting body Download PDF

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JP2006128662A
JP2006128662A JP2005284490A JP2005284490A JP2006128662A JP 2006128662 A JP2006128662 A JP 2006128662A JP 2005284490 A JP2005284490 A JP 2005284490A JP 2005284490 A JP2005284490 A JP 2005284490A JP 2006128662 A JP2006128662 A JP 2006128662A
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columnar
semiconductor device
melting point
electrode
low melting
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Taizo Inoue
泰造 井上
Hisashi Omotani
寿士 重谷
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Taiyo Yuden Co Ltd
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Taiyo Yuden Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device provided with a columnar electrode having a ball-like low-melting point layer bonded to only the upper surface of a columnar section. <P>SOLUTION: If it is assumed that a volume of each low-melting point layer 24 is A and the area of an upper surface in each columnar section is B, the low-melting point layer 24 is prevented from leaking into the side of the columnar section 22 when a ball is formed by the reflowing of the low-melting point layer 24 by adjusting a plating amount of the low-melting point layer 24 and a cross-section of the columnar section 22 so as to meet the relation of A≤1.3×B<SP>1.5</SP>. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は、半導体装置およびその実装体に関し、特に、狭ピッチ化に有効な半導体装置およびその実装体に関する。   The present invention relates to a semiconductor device and a mounting body thereof, and more particularly to a semiconductor device effective for narrowing the pitch and a mounting body thereof.

集積回路の小型化要求に伴って、半導体装置の構造はＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）に代表されるように、ベアチップに限りなく近い形で構成され、この半導体装置をフリップチップ実装によって配線基板に接合する手法が注目されている。   Along with the demand for miniaturization of integrated circuits, the structure of a semiconductor device is configured to be as close as possible to a bare chip, as represented by CSP (Chip Size Package), and this semiconductor device is bonded to a wiring board by flip-chip mounting. The technique to do is attracting attention.

ここで、上記フリップチップ実装による半導体装置と配線基板との接合は、該半導体装置を構成する半導体基板の主面側に設けられたバンプを介して行われるが、このバンプを狭ピッチで配置するためには、バンプの体積を減少させて、隣接するバンプ同士の接触を避ける必要がある。   Here, the bonding between the semiconductor device and the wiring board by the flip-chip mounting is performed via bumps provided on the main surface side of the semiconductor substrate constituting the semiconductor device. The bumps are arranged at a narrow pitch. Therefore, it is necessary to reduce the volume of the bumps and avoid contact between adjacent bumps.

しかし、バンプの体積を減少させると、半導体基板と配線基板とのギャップが小さくなるため、接合の安定化、接続信頼性向上あるいは確保を目的として該ギャップ内に樹脂を充填するアンダーフィルが困難になる。   However, if the volume of the bump is reduced, the gap between the semiconductor substrate and the wiring substrate becomes smaller, so that it is difficult to underfill the resin in the gap for the purpose of stabilizing the bonding, improving the connection reliability, or ensuring it. Become.

そこで、上記のギャップを確保すべく、従来からポスト状の金属柱を利用した接合バンプが検討されており、この種のポスト型接合バンプを利用した半導体装置およびその実装方法としては、例えば、下記の文献が知られている。
特開平５−１３６２０１号公報 特開２００２−３１３９９３号公報 米国特許第６，５９２，０１９号公報 ここで、上記の特許文献１には、同文献の段落００２０および図１に示されたように、ワイヤーボンディング法によって金属柱を備えた接合バンプを形成する手法が開示されている。 Therefore, in order to ensure the above gap, conventionally, a bonding bump using a post-like metal pillar has been studied. As a semiconductor device using this type of post-type bonding bump and a mounting method thereof, for example, The literature is known.
JP-A-5-136201 JP 2002-313993 A US Pat. No. 6,592,019 Here, in the above-mentioned patent document 1, as shown in paragraph 0020 of FIG. 1 and FIG. 1, a bonding bump having a metal column is formed by a wire bonding method. A technique is disclosed.

また、特許文献２には、同文献の段落０００２〜０００７および図１８〜図２４に示されたように、メッキ法によって金属柱を形成するとともに、該金属柱の上面に半田ボールを備えた接合バンプの形成手法が開示されている。   Further, in Patent Document 2, as shown in paragraphs 0002 to 0007 and FIGS. 18 to 24 of the same document, a metal column is formed by a plating method, and a solder ball is provided on the upper surface of the metal column. A method of forming bumps is disclosed.

また、特許文献３には、同文献の第７カラム第１６行〜第５４行および第１図〜第３図に示されたように、メッキ法によって金属柱およびその上面に半田層を形成し、該半田層をそのままの状態で配線基板に接合する手法と、該半田層をリフローにより一旦ボール状としてから配線基板に接合する手法が開示されている。   In Patent Document 3, as shown in the seventh column, lines 16 to 54 and FIGS. 1 to 3 of the same document, a metal column and a solder layer are formed on the upper surface thereof by plating. There are disclosed a method of bonding the solder layer to the wiring substrate as it is, and a method of bonding the solder layer once to a ball shape by reflow and bonding to the wiring substrate.

しかし、上記特許文献１に開示された手法では、各端子ごとにワイヤーバンプを形成する必要があるため、入出力端子数の多い半導体装置への適用が困難になるとともに、各バンプの高さを揃えることが難しく、近年の多ピン狭ピッチ型の半導体装置への適用が困難と考えられる。   However, in the method disclosed in Patent Document 1, since it is necessary to form a wire bump for each terminal, it becomes difficult to apply to a semiconductor device having a large number of input / output terminals, and the height of each bump is reduced. It is difficult to align them, and it is considered difficult to apply to recent multi-pin narrow pitch type semiconductor devices.

また、上記特許文献２に開示された手法では、同文献の段落０００７および図２２に示されたように、金属柱の上面が樹脂に覆われた過程が生じるため、半田ボールを形成する前に金属柱を研磨して図２３に示された状態を作る必要があるとともに、該金属柱が樹脂に埋設された状態で半導体装置が構成されるため、アンダーフィルのギャップが確保できないという課題がある。   Further, in the technique disclosed in Patent Document 2, the process in which the upper surface of the metal column is covered with resin occurs as shown in Paragraph 0007 and FIG. 22 of the same document. Since it is necessary to polish the metal pillar to create the state shown in FIG. 23, and the semiconductor device is configured with the metal pillar embedded in the resin, there is a problem that an underfill gap cannot be secured. .

一方、上記特許文献３に開示された手法では、金属柱と半田層をメッキで形成し、該金属柱が露呈した状態で配線基板に実装されるため、各バンプの高さの均一化とアンダーフィルギャップの確保という点で非常に優れた手法と考えられる。   On the other hand, in the method disclosed in Patent Document 3, the metal pillar and the solder layer are formed by plating, and the metal pillar is mounted on the wiring board in an exposed state. This is considered to be a very good technique in terms of securing the fill gap.

しかし、この特許文献３では、同文献の第７カラム第４７行〜第５３行に示されたように、金属柱の上面に形成した半田層を一旦リフローして半田ボールを形成する場合に生じる各種課題までは言及されておらす、金属柱上に精度良く半田ボールを形成するためには、さらなる検討が必要であった。   However, in Patent Document 3, as shown in the seventh column, lines 47 to 53 of the same document, it occurs when the solder layer formed on the upper surface of the metal column is reflowed to form solder balls. Although various problems have been mentioned, further studies were necessary to form solder balls on metal columns with high accuracy.

そこで、本発明は、柱状部の上面に半田ボールを備えた接合バンプの形成に有効な半導体装置およびその実装体を提供する。   Therefore, the present invention provides a semiconductor device effective for forming a bonding bump having a solder ball on the upper surface of a columnar portion and a mounting body thereof.

上記目的を達成するため、請求項１記載の発明は、半導体基板に設けられた柱状電極を複数備えた半導体装置において、前記柱状電極は、導電材料から成る柱状部と、前記柱状部よりも融点の低い導電材料で形成され、前記柱状部の上面に接合された金属ボール部とを具備し、前記金属ボール部の体積をＡ、前記柱状部の上面の面積をＢ、前記柱状部の上面に形成された起伏部の体積をＥとしたとき、前記柱状電極は、Ａ−Ｅ≦１．３×Ｂ１．５の関係を有することを特徴とする。 In order to achieve the above object, according to a first aspect of the present invention, there is provided a semiconductor device including a plurality of columnar electrodes provided on a semiconductor substrate. And a metal ball portion joined to the upper surface of the columnar portion, the volume of the metal ball portion is A, the area of the upper surface of the columnar portion is B, and the upper surface of the columnar portion is When the volume of the formed undulations is E, the columnar electrode has a relationship of AE ≦ 1.3 × B1.5 .

上記のように、金属ボール部の体積を柱状部の上面の面積および上面に形成された起伏部との関係で所定の体積以下に収めることで、金属ボール部にかかる重力よりも柱状部との接触面で生じる張力の方が大きくなるため、低融点材料のリフローによって金属ボール部が形成される際に、該低融点材料の柱状部側面への濡れが防止される。   As described above, by keeping the volume of the metal ball part below a predetermined volume in relation to the area of the upper surface of the columnar part and the undulations formed on the upper surface, the volume of the columnar part is less than the gravity applied to the metal ball part. Since the tension generated at the contact surface is larger, when the metal ball portion is formed by reflow of the low melting point material, wetting of the low melting point material on the side surface of the columnar portion is prevented.

ここで、柱状部の上面に形成された起伏部とは、柱状部の側面と直角の角度で交差する水平線を該柱状部の上端部分に引いたときに、該水平線より突出した起伏部分を意味する。このような起伏部分はメッキ工程によって自然に形成される場合や意図的に形成する場合があるが、この起伏部分の体積を考慮することで、低融点材料の柱状部側面への濡れが防止できる。   Here, the undulating portion formed on the upper surface of the columnar portion means the undulating portion that protrudes from the horizontal line when a horizontal line intersecting the side surface of the columnar portion at an angle perpendicular to the upper end portion of the columnar portion is drawn. To do. Such undulations may be naturally formed or intentionally formed by a plating process, but by taking into consideration the volume of the undulations, wetting of the low melting point material on the side surfaces of the columnar part can be prevented. .

これら構造を取る場合、前述した柱状部の上面の面積Ｂは、低融点層と接触する部分の表面積で考える。よって、これらの構造を取れば、低融点層と柱状部との接触面積が広く取れるため、低融点層の体積を増加させることができる。   When taking these structures, the area B of the upper surface of the columnar portion described above is considered as the surface area of the portion in contact with the low melting point layer. Therefore, if these structures are taken, the contact area between the low melting point layer and the columnar portion can be widened, so that the volume of the low melting point layer can be increased.

その結果、各柱状電極の高さの均一化が図られるため、配線基板に対する各電極の接合精度が向上するとともに、アンダーフィルギャップを確保しつつも可能な限り電極ピッチを狭小化させた構造の実現が可能になる。   As a result, the height of each columnar electrode is made uniform, so that the bonding accuracy of each electrode to the wiring board is improved, and the electrode pitch is made as narrow as possible while ensuring an underfill gap. Realization is possible.

加えて、本手法によれば、柱状部に余分な側面処理を行うことなく、該柱状部の上面のみで接合された金属ボール部を形成することが可能になるため、簡易な構造で信頼性の高い柱状電極を備えた半導体装置となる。尚、本発明は、柱状部に側面処理を施すことを除外するものではなく、低融点材料の柱状部側面への濡れ防止をより確実に行うために柱状部に側面処理を行っても良い。   In addition, according to the present method, it is possible to form the metal ball portion joined only by the upper surface of the columnar portion without performing extra side surface processing on the columnar portion, so that the reliability can be achieved with a simple structure. It becomes a semiconductor device provided with a high columnar electrode. In addition, this invention does not exclude performing a side surface process to a columnar part, and in order to prevent the wetting to the columnar part side surface of a low melting-point material more reliably, you may perform a side surface process to a columnar part.

ここで、柱状部は、銅のように電気抵抗が低く融点の高い材料で形成することが望ましく、金属ボール部は半田のように融点が低く柱状部を構成する材料と馴染みの良い材料で形成することが望ましい。尚、柱状部は、ニッケル、アルミ、チタン等の導電材料で形成しても良い。   Here, the columnar part is preferably formed of a material having a low electric resistance and a high melting point such as copper, and the metal ball part is formed of a material having a low melting point and a material familiar with the material of the columnar part such as solder. It is desirable to do. The columnar portion may be formed of a conductive material such as nickel, aluminum, or titanium.

また、請求項２記載の発明は、請求項１記載の発明において、前記各柱状電極のピッチの１／２をＣ、前記金属ボール部の高さをＤとしたとき、前記各柱状電極は、Ｄ≦Ｃの関係を有することを特徴とする。   The invention according to claim 2 is the invention according to claim 1, wherein when the pitch of each columnar electrode is 1/2 and C is the height of the metal ball portion, each columnar electrode is It has the relationship of D <= C.

このように、柱状電極のピッチと金属ボール部の高さとの関係をさらに規定することで、本半導体装置を配線基板に実装する際に行われるリフロー時に、隣接した柱状電極間の接触を避けることができる。   In this way, by further defining the relationship between the pitch of the columnar electrodes and the height of the metal ball portions, it is possible to avoid contact between adjacent columnar electrodes during reflow performed when the semiconductor device is mounted on a wiring board. Can do.

また、請求項３記載の発明は、半導体基板に設けられた柱状電極を複数備えた半導体装置が該各柱状電極を介して配線基板上に実装された半導体装置の実装体において、前記柱状電極は、導電材料から成る柱状部と、前記柱状部よりも融点の低い導電材料で形成され、前記柱状部の上面に接合された低融点金属層とを具備し、前記低融点金属層の体積をＡ、前記柱状部の上面の面積をＢ、前記柱状部の上面に形成された起伏部の体積をＥとしたとき、前記柱状電極は、Ａ−Ｅ≦１．３×Ｂ１．５の関係を有することを特徴とする。 According to a third aspect of the present invention, there is provided a semiconductor device mounting body in which a semiconductor device including a plurality of columnar electrodes provided on a semiconductor substrate is mounted on a wiring substrate via each columnar electrode. A columnar portion made of a conductive material and a low melting point metal layer formed of a conductive material having a melting point lower than that of the columnar portion and bonded to the upper surface of the columnar portion, and the volume of the low melting point metal layer is A When the area of the upper surface of the columnar portion is B and the volume of the undulating portion formed on the upper surface of the columnar portion is E, the columnar electrode has a relationship of A−E ≦ 1.3 × B1.5 . It is characterized by having.

上記のように、金属ボール部の体積を柱状部の上面の面積および上面に形成された起伏部との関係で所定の体積以下に収めることで、低融点金属層の柱状部側面への濡れが防止された状態で半導体装置を配線基板に実装することができるため、各柱状電極の高さの均一化が図られ、その結果、配線基板に対する各電極の接合精度が向上するとともに、アンダーフィルギャップを確保しつつも可能な限り電極ピッチを狭小化させた構造の実現が可能になる。   As described above, by keeping the volume of the metal ball portion below a predetermined volume in relation to the area of the upper surface of the columnar portion and the undulating portion formed on the upper surface, the low melting point metal layer can be wetted to the side surface of the columnar portion. Since the semiconductor device can be mounted on the wiring board in a prevented state, the height of each columnar electrode is made uniform, and as a result, the bonding accuracy of each electrode to the wiring board is improved and the underfill gap is increased. It is possible to realize a structure in which the electrode pitch is reduced as much as possible while securing the above.

また、請求項４記載の発明は、請求項３記載の発明において、前記半導体装置と前記配線基板との間には、前記柱状部の側面に直接接した状態で充填されたアンダーフィルを備えたことを特徴とする。   According to a fourth aspect of the present invention, in the third aspect of the present invention, an underfill is provided between the semiconductor device and the wiring board so as to be in direct contact with a side surface of the columnar portion. It is characterized by that.

このように構成することで、アンダーフィルギャップが好適に確保された状態で半導体装置の狭ピッチ実装が可能になる。   With this configuration, the semiconductor device can be mounted at a narrow pitch in a state where an underfill gap is suitably secured.

以上説明したように、本発明によれば、柱状部の上面のみに接合されたボール部を有する柱状電極の形成が可能になる。   As described above, according to the present invention, it is possible to form a columnar electrode having a ball portion bonded only to the upper surface of the columnar portion.

以下、本発明の実施形態を添付図面を参照して詳細に説明する。尚、本発明は、以下説明する実施形態に限らず適宜変更可能である。   Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments described below, and can be modified as appropriate.

図１は、本実施形態に係る半導体装置の実装構造を示す断面図である。同図に示すように、本実装構造は、半導体装置１０が柱状電極２０を介して配線基板３０に実装された構造を有する。   FIG. 1 is a cross-sectional view showing a mounting structure of a semiconductor device according to this embodiment. As shown in the figure, the present mounting structure has a structure in which the semiconductor device 10 is mounted on the wiring board 30 via the columnar electrodes 20.

半導体装置１０は、シリコンから成る半導体基板１２と、該半導体基板１２の主面側に複数設けられたアルミの電極パット１４と、該各電極パット１４を部分的に露呈させた状態で形成されたパッシベーション膜１６とで構成される。   The semiconductor device 10 is formed with a semiconductor substrate 12 made of silicon, a plurality of aluminum electrode pads 14 provided on the main surface side of the semiconductor substrate 12, and the electrode pads 14 partially exposed. And a passivation film 16.

柱状電極２０は、前記各電極パット１４の露呈部にそれぞれ形成された銅から成る柱状部２２と、該柱状部２２の上面に形成された半田から成る低融点層２４とで構成される。尚、この柱状部は１５μｍ以上の高さで形成することが望ましい。   The columnar electrode 20 is composed of a columnar portion 22 made of copper formed on the exposed portion of each electrode pad 14 and a low melting point layer 24 made of solder formed on the upper surface of the columnar portion 22. The columnar portion is preferably formed with a height of 15 μm or more.

配線基板３０は、各種パターンを内層した多層基板３２と、該多層基板３２の表面に形成された配線パターン３４とで構成される。   The wiring board 30 includes a multilayer board 32 in which various patterns are layered, and a wiring pattern 34 formed on the surface of the multilayer board 32.

半導体装置１０と配線基板３０との電気的接合は、柱状電極２０の先端部に位置する低融点層２４を配線パターン３４上で溶融することにより行われ、該半導体装置１０と配線基板３０との間には、アンダーフィル４０が施されて、各柱状電極２０による接合状態が保護される。   The electrical connection between the semiconductor device 10 and the wiring substrate 30 is performed by melting the low melting point layer 24 located at the tip of the columnar electrode 20 on the wiring pattern 34, and the semiconductor device 10 and the wiring substrate 30 are connected to each other. In the meantime, underfill 40 is applied to protect the joined state of each columnar electrode 20.

図２は、本実施形態に係る半導体装置の第１の製造工程を示す断面図である。本実施形態に係る半導体装置を製造する場合には、まず、同図（ａ）に示すように、複数の集積回路が形成されたウェハ１３の主面側に電極パット１４を複数形成し、該各電極パット１４の中央部を露呈させた状態でパッシベーション膜１６を形成する。   FIG. 2 is a cross-sectional view showing a first manufacturing process of the semiconductor device according to this embodiment. When manufacturing the semiconductor device according to the present embodiment, first, as shown in FIG. 2A, a plurality of electrode pads 14 are formed on the main surface side of a wafer 13 on which a plurality of integrated circuits are formed. A passivation film 16 is formed in a state where the central portion of each electrode pad 14 is exposed.

続いて、同図（ｂ）に示すように、パッシベーション膜１６上にフォトレジスト４２を塗布し、その後、同図（ｃ）に示すように、各電極パッド１４の露呈部に対応させてフォトレジスト４２を感光し、各電極パッド１４を露呈させる開口部４４を形成する。ここで各開口部１４の幅はパッシベーション膜１６の開口幅よりも狭い幅とし、かつ、パッシベーション膜１６の端部に触れない状態で各開口部１４を形成する。   Subsequently, as shown in FIG. 4B, a photoresist 42 is applied on the passivation film 16, and then, as shown in FIG. 4C, the photoresist is applied corresponding to the exposed portion of each electrode pad 14. 42 is exposed to form an opening 44 that exposes each electrode pad 14. Here, the width of each opening 14 is narrower than the opening width of the passivation film 16, and each opening 14 is formed without touching the end of the passivation film 16.

図３は、本実施形態に係る半導体装置の第２の製造工程を示す断面図である。同図（ａ）に示すように、前図に示した開口部４４を利用して電極パット１４上に柱状部２２を形成する。この柱状部２２の形成は銅メッキにより行われる。   FIG. 3 is a cross-sectional view showing a second manufacturing process of the semiconductor device according to this embodiment. As shown in FIG. 2A, the columnar portion 22 is formed on the electrode pad 14 using the opening 44 shown in the previous figure. The columnar portion 22 is formed by copper plating.

続いて、同図（ｂ）に示すように、前図に示した開口部４４を利用して柱状部２２の上面に低融点層２４を形成する。この低融点層２４の形成は半田メッキにより行われる。   Subsequently, as shown in FIG. 4B, the low melting point layer 24 is formed on the upper surface of the columnar portion 22 by using the opening 44 shown in the previous figure. The low melting point layer 24 is formed by solder plating.

図４は、本実施形態に係る半導体装置の第３の製造工程を示す断面図である。同図（ａ）に示すように、前図に示したフォトレジスト４２を除去して、ウェハ１３上に形成された複数の柱状電極２０を得る。その後、同図（ｂ）に示すように、低融点層２４を加熱溶融して該低融点層２４をボール状に加工する。この加熱溶融処理は、ウェハ１３をリフロー炉に投入し、所定の温度および時間で加熱処理を施すことにより行われる。尚、リフローに先だって酸化膜除去剤を塗布しておく
図５は、本実施形態に係る半導体装置の第１の実装工程を示す断面図である。同図に示すように、以上説明した一連の工程を経て製造された半導体装置１０を配線基板３０に実装する場合は、該半導体装置１０の主面側を配線基板３０に向け、柱状電極２０の先端に位置するボール状の低融点層２４と配線基板３０上に設けられた配線パターンとの位置合わせを行う。 FIG. 4 is a cross-sectional view showing a third manufacturing process of the semiconductor device according to this embodiment. As shown in FIG. 2A, the photoresist 42 shown in the previous figure is removed to obtain a plurality of columnar electrodes 20 formed on the wafer 13. Thereafter, as shown in FIG. 2B, the low melting point layer 24 is heated and melted to process the low melting point layer 24 into a ball shape. This heat-melting process is performed by putting the wafer 13 into a reflow furnace and performing a heat treatment at a predetermined temperature and time. Note that an oxide film removing agent is applied prior to reflow. FIG. 5 is a cross-sectional view showing a first mounting process of the semiconductor device according to the present embodiment. As shown in the figure, when the semiconductor device 10 manufactured through the series of steps described above is mounted on the wiring board 30, the main surface side of the semiconductor device 10 faces the wiring board 30, and the columnar electrode 20 The ball-shaped low melting point layer 24 located at the tip and the wiring pattern provided on the wiring substrate 30 are aligned.

図６は、本実施形態に係る半導体装置の第２の実装工程を示す断面図である。同図に示すように、前図に示す工程で位置合わせされた半導体装置１０を配線基板３０にマウントし、その後、リフローを行って低融点層２４を配線パターン３４上で溶融固着させる。各低融点層２４の固着を完了させた後、同図中の矢印Ａで示す方向からアンダーフィル樹脂を充填して図１に示した構造を得る。   FIG. 6 is a cross-sectional view showing a second mounting step of the semiconductor device according to this embodiment. As shown in the figure, the semiconductor device 10 aligned in the process shown in the previous figure is mounted on the wiring board 30 and then reflowed to melt and fix the low melting point layer 24 on the wiring pattern 34. After the fixing of the low melting point layers 24 is completed, the structure shown in FIG. 1 is obtained by filling the underfill resin from the direction indicated by the arrow A in FIG.

図７は、本実施形態に係る半導体装置の別の実装構造を示す断面図である。同図に示すように、半導体装置１０が配線基板３０に実装された後であれば、柱状部２２の先端が低融点層２４に埋設した状態であっても良い。   FIG. 7 is a cross-sectional view showing another mounting structure of the semiconductor device according to the present embodiment. As shown in the figure, as long as the semiconductor device 10 is mounted on the wiring substrate 30, the end of the columnar portion 22 may be embedded in the low melting point layer 24.

図８は、接続信頼性が低い柱状電極の状態を示す断面図である。同図（ａ）に示すように、ボール状の低融点層２４が柱状部２２の側面に接触した状態で形成されると、各柱状電極２２の高さにバラツキが生じ、その結果、同図（ｂ）に示すように、配線パターン３４に接合されない柱状電極が発生する。   FIG. 8 is a cross-sectional view showing a state of a columnar electrode having low connection reliability. As shown in FIG. 4A, when the ball-shaped low melting point layer 24 is formed in contact with the side surface of the columnar portion 22, the height of each columnar electrode 22 varies. As a result, as shown in FIG. As shown in (b), columnar electrodes that are not joined to the wiring pattern 34 are generated.

この状態を防止すべく、本実施形態では、図４に示したボール状の低融点層２４を形成する工程において、以下に説明するような手法を適用する。   In order to prevent this state, in the present embodiment, the method described below is applied in the step of forming the ball-shaped low melting point layer 24 shown in FIG.

図９は、図４に示した低融点層の体積と柱状部上面の面積との関係を示す断面図である。同図に示すように、各低融点層２４の体積をＡ、各柱状部２２の上面の面積をＢとしたとき、Ａ≦１．３×Ｂ１．５の関係を満たすように、前述の図２および図３を用いて説明した工程において、開口部４４の断面積と低融点層２４のメッキ量とを調整することで各柱状電極２０を形成する。 FIG. 9 is a cross-sectional view showing the relationship between the volume of the low melting point layer shown in FIG. 4 and the area of the upper surface of the columnar part. As shown in the figure, when the volume of each low melting point layer 24 is A and the area of the upper surface of each columnar portion 22 is B, the above-mentioned relationship is satisfied so as to satisfy the relationship of A ≦ 1.3 × B 1.5 . 2 and 3, each columnar electrode 20 is formed by adjusting the cross-sectional area of the opening 44 and the plating amount of the low melting point layer 24.

図１０は、柱状電極が形成されたウェハのリフロー工程を示した側面図である。同図に示すように、各柱状電極２０を上述の関係で形成した後、該各柱状電極２０が形成されたウェハ１３の裏面側をウェハ支持台５２上に載置し、低融点層２４を上に向けた状態で該ウェハ１３をリフロー炉５０内に設置する。   FIG. 10 is a side view showing a reflow process of a wafer on which columnar electrodes are formed. As shown in the figure, after each columnar electrode 20 is formed in the above-described relationship, the back surface side of the wafer 13 on which each columnar electrode 20 is formed is placed on a wafer support base 52, and the low melting point layer 24 is formed. The wafer 13 is placed in the reflow furnace 50 while facing upward.

そして、この状態で低融点層２４の加熱を行うと、溶融した低融点層２４に下向きの重力が加わるが、柱状部２２の上面の面積との関係で低融点層２４の量が制御されているため、柱状部２２の側面に触れない状態で低融点層２４がボール状に加工される。   When the low melting point layer 24 is heated in this state, downward gravity is applied to the melted low melting point layer 24, but the amount of the low melting point layer 24 is controlled in relation to the area of the upper surface of the columnar portion 22. Therefore, the low melting point layer 24 is processed into a ball shape without touching the side surface of the columnar portion 22.

図１１は、図１０の工程によって形成された半導体装置の電極構造を示す断面図である。同図に示すように、図１０の工程を経た半導体装置１０の各柱状電極２０は、各低融点層２４の体積をＡ、各柱状部２２の上面の面積をＢとしたとき、Ａ≦１．３×Ｂ１．５の関係を満たした状態で形成され、かつ、各柱状電極２０のピッチの１／２をＣ、ボール状の低融点層２４の高さをＤとしたとき、前記各柱状電極は、Ｄ≦Ｃの関係を有する。 FIG. 11 is a cross-sectional view showing the electrode structure of the semiconductor device formed by the process of FIG. As shown in the figure, each columnar electrode 20 of the semiconductor device 10 that has undergone the process of FIG. 10 has A ≦ 1 when the volume of each low melting point layer 24 is A and the area of the upper surface of each columnar portion 22 is B. .3 × B 1.5 satisfying the relationship, and when the pitch of each columnar electrode 20 is C and the height of the ball-shaped low melting point layer 24 is D, The columnar electrode has a relationship of D ≦ C.

図１２は、低融点層の体積Ａと柱状部の上面の面積Ｂとの関係を検証したときの結果を示す表である。同図に示すように、ＡとＢの値を変化させて低融点層の柱状部側面に対する濡れを評価した結果、Ｎｏ．１〜３の条件では柱状部側面への濡れがない状態でボール部が形成できることを確認したが、Ｎｏ．４および５の条件では側面への濡れが生じた。図１３は、柱状電極の好適な構造例を示す断面図である。前述した柱状電極は、同図（ａ）に示すように、柱状部２２の上面を山型で形成した構造や、同図（ｂ）に示すように、起伏を持たせた構造や、同図（ｃ）に示すように、中央部に凸部を持たせた構造や、同図（ｄ）に示すように、上面部分を広く取った構造や、同図（ｅ）のように、湾曲型で形成した構造としても良い。   FIG. 12 is a table showing the results when the relationship between the volume A of the low melting point layer and the area B of the upper surface of the columnar part is verified. As shown in the figure, the values of A and B were changed to evaluate the wetting of the low melting point layer on the side surface of the columnar part. Although it was confirmed that the ball part can be formed without wetting the side surface of the columnar part under the conditions 1 to 3, no. Under the conditions of 4 and 5, wetting to the side surface occurred. FIG. 13 is a cross-sectional view illustrating a preferred structure example of the columnar electrode. The columnar electrode described above has a structure in which the upper surface of the columnar portion 22 is formed in a mountain shape, as shown in FIG. As shown in (c), a structure having a convex part at the center, as shown in FIG. (D), a structure with a wide upper surface part, or as shown in FIG. It is good also as a structure formed by.

また、同図（ａ）、（ｂ）、（ｃ）、（ｅ）のように上面を山形、起伏、凸部を持たせた場合、同図（ａ）、（ｂ）、（ｃ）、（ｅ）に示す点線Ｅ’以上の体積をＥとすると、Ａ−Ｅ≦１．３×Ｂ１．５の関係を満たした状態で形成される。この点線は、柱状部の側面と直角の角度で交差する水平線を該柱状部の上端部分に引いた線であり、この水平線より突出した起伏部分の体積がＥである。このような起伏部分はメッキ工程によって自然に形成される場合や意図的に形成する場合があるが、この起伏部分の体積を考慮することで、低融点材料の柱状部側面への濡れが防止できる。 Further, when the upper surface is provided with chevron shapes, undulations, and convex portions as in FIGS. 9A, 9B, 9C, and 9E, FIGS. When the volume equal to or greater than the dotted line E ′ shown in (e) is E, it is formed in a state satisfying the relationship of AE ≦ 1.3 × B1.5 . This dotted line is a line obtained by drawing a horizontal line intersecting the side surface of the columnar part at an angle perpendicular to the upper end part of the columnar part, and the volume of the undulating portion protruding from the horizontal line is E. Such undulations may be naturally formed or intentionally formed by a plating process, but by taking into consideration the volume of the undulations, wetting of the low melting point material on the side surfaces of the columnar part can be prevented. .

これら構造を取る場合、前述した柱状部２２の上面の面積Ｂは、低融点層２４と接触する部分の表面積で考える。よって、これらの構造を取れば、低融点層２４と柱状部２２との接触面積が広く取れるため、低融点層の体積を増加させることができる。   When taking these structures, the area B of the upper surface of the columnar portion 22 described above is considered as the surface area of the portion in contact with the low melting point layer 24. Therefore, if these structures are taken, since the contact area of the low melting point layer 24 and the columnar part 22 can be taken widely, the volume of the low melting point layer can be increased.

本発明によれば、柱状部の上面のみに接合されたボール状の低融点層を有する柱状電極の形成が可能になるため、より小型狭ピッチが要求される半導体装置への適用が期待される。   According to the present invention, it is possible to form a columnar electrode having a ball-shaped low melting point layer bonded only to the upper surface of the columnar portion, and therefore, application to a semiconductor device requiring a smaller and narrower pitch is expected. .

本実施形態に係る半導体装置の実装構造を示す断面図である。It is sectional drawing which shows the mounting structure of the semiconductor device which concerns on this embodiment. 本実施形態に係る半導体装置の第１の製造工程を示す断面図である。It is sectional drawing which shows the 1st manufacturing process of the semiconductor device which concerns on this embodiment. 本実施形態に係る半導体装置の第２の製造工程を示す断面図である。It is sectional drawing which shows the 2nd manufacturing process of the semiconductor device which concerns on this embodiment. 本実施形態に係る半導体装置の第３の製造工程を示す断面図である。It is sectional drawing which shows the 3rd manufacturing process of the semiconductor device which concerns on this embodiment. 本実施形態に係る半導体装置の第１の実装工程を示す断面図である。It is sectional drawing which shows the 1st mounting process of the semiconductor device which concerns on this embodiment. 本実施形態に係る半導体装置の第２の実装工程を示す断面図である。It is sectional drawing which shows the 2nd mounting process of the semiconductor device which concerns on this embodiment. 本実施形態に係る半導体装置の別の実装構造を示す断面図である。It is sectional drawing which shows another mounting structure of the semiconductor device which concerns on this embodiment. 接続信頼性が低い柱状電極の状態を示す断面図である。It is sectional drawing which shows the state of a columnar electrode with low connection reliability. 図４に示した低融点層の体積と柱状部上面の面積との関係を示す断面図である。FIG. 5 is a cross-sectional view showing the relationship between the volume of the low melting point layer shown in FIG. 4 and the area of the top surface of the columnar part. 柱状電極が形成されたウェハのリフロー工程を示した側面図である。It is the side view which showed the reflow process of the wafer in which the columnar electrode was formed. 図１０の工程によって形成された半導体装置の電極構造を示す断面図である。It is sectional drawing which shows the electrode structure of the semiconductor device formed by the process of FIG. 低融点層の体積Ａと柱状部の上面の面積Ｂとの関係を検証したときの結果を示す表である。It is a table | surface which shows a result when the relationship between the volume A of a low melting point layer and the area B of the upper surface of a columnar part is verified. 柱状電極の好適な構造例を示す断面図である。It is sectional drawing which shows the suitable structural example of a columnar electrode.

符号の説明Explanation of symbols

１０…半導体装置、１２…半導体チップ、１３…ウェハ、１４…電極パッド、１６…パッシベーション膜、２０…柱状電極、２２…柱状部、２４…低融点層、３０…配線基板、３２…多層基板、３４…配線パターン、４０…アンダーフィル、４２…フォトレジスト、４４…開口部、５０…リフロー炉、５２…ウェハ支持台   DESCRIPTION OF SYMBOLS 10 ... Semiconductor device, 12 ... Semiconductor chip, 13 ... Wafer, 14 ... Electrode pad, 16 ... Passivation film, 20 ... Columnar electrode, 22 ... Columnar part, 24 ... Low melting-point layer, 30 ... Wiring board, 32 ... Multilayer substrate, 34 ... Wiring pattern, 40 ... Underfill, 42 ... Photoresist, 44 ... Opening, 50 ... Reflow furnace, 52 ... Wafer support

Claims (4)

半導体基板に設けられた柱状電極を複数備えた半導体装置において、
前記柱状電極は、
導電材料から成る柱状部と、
前記柱状部よりも融点の低い導電材料で形成され、前記柱状部の上面に接合された金属ボール部とを具備し、
前記金属ボール部の体積をＡ、前記柱状部の上面の面積をＢ、前記柱状部の上面に形成された起伏部の体積をＥとしたとき、前記柱状電極は、Ａ−Ｅ≦１．３×Ｂ１．５の関係を有することを特徴とする半導体装置。 In a semiconductor device comprising a plurality of columnar electrodes provided on a semiconductor substrate,
The columnar electrode is
A columnar portion made of a conductive material;
A metal ball portion formed of a conductive material having a melting point lower than that of the columnar portion and bonded to the upper surface of the columnar portion;
When the volume of the metal ball portion is A, the area of the upper surface of the columnar portion is B, and the volume of the undulating portion formed on the upper surface of the columnar portion is E, the columnar electrode has A−E ≦ 1.3. A semiconductor device having a relationship of × B1.5 . 前記各柱状電極のピッチの１／２をＣ、前記金属ボール部の高さをＤとしたとき、前記各柱状電極は、Ｄ≦Ｃの関係を有することを特徴とする請求項１記載の半導体装置。   2. The semiconductor according to claim 1, wherein each columnar electrode has a relationship of D ≦ C, where C is ½ of the pitch of each columnar electrode and D is the height of the metal ball portion. apparatus. 半導体基板に設けられた柱状電極を複数備えた半導体装置が該各柱状電極を介して配線基板上に実装された半導体装置の実装体において、
前記柱状電極は、
導電材料から成る柱状部と、
前記柱状部よりも融点の低い導電材料で形成され、前記柱状部の上面に接合された低融点金属層とを具備し、
前記低融点金属層の体積をＡ、前記柱状部の上面の面積をＢ、前記柱状部の上面に形成された起伏部の体積をＥとしたとき、前記柱状電極は、Ａ−Ｅ≦１．３×Ｂ１．５の関係を有することを特徴とする半導体装置の実装体。 In a semiconductor device mounting body in which a semiconductor device including a plurality of columnar electrodes provided on a semiconductor substrate is mounted on a wiring substrate via each columnar electrode,
The columnar electrode is
A columnar portion made of a conductive material;
A low melting point metal layer formed of a conductive material having a melting point lower than that of the columnar part and bonded to the upper surface of the columnar part;
When the volume of the low melting point metal layer is A, the area of the upper surface of the columnar portion is B, and the volume of the undulating portion formed on the upper surface of the columnar portion is E, the columnar electrode has AE ≦ 1. 3. A semiconductor device package having a relationship of 3 × B 1.5 . 前記半導体装置と前記配線基板との間には、前記柱状部の側面に直接接した状態で充填されたアンダーフィルを備えたことを特徴とする請求項３記載の半導体装置の実装体。   4. The semiconductor device mounting body according to claim 3, further comprising an underfill filled between the semiconductor device and the wiring board in a state of being in direct contact with a side surface of the columnar portion.
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