JP2006126970A - Electronic device, computer, cooling control method and cooling control program - Google Patents

Electronic device, computer, cooling control method and cooling control program Download PDF

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JP2006126970A
JP2006126970A JP2004311358A JP2004311358A JP2006126970A JP 2006126970 A JP2006126970 A JP 2006126970A JP 2004311358 A JP2004311358 A JP 2004311358A JP 2004311358 A JP2004311358 A JP 2004311358A JP 2006126970 A JP2006126970 A JP 2006126970A
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JP4289277B2 (en
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Hideaki Kobayashi
英明 小林
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NEC Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To simultaneously change cooling capability based on the operating circumstances of a device by controlling cooling capability according to the type of an instruction. <P>SOLUTION: A first logical unit 11 is provided with a first number of instruction calculation part 41 for calculating the number of the issue of the first type instructions per unit time and for outputting it to a cooling controller 30,... and a n-th number of instruction calculation part 4n for calculating the number of the issue of the n-th type of instructions per unit time and for outputting it to the cooling controller 30. The first type instructions are instructions to largely affect the operation of the first logical unit 11. The cooling controller 30 includes a control table 301, and controls the cooling capability of the first cooling device 21 to the n-th cooling device 2n based on the number of the issue of the first type instructions per unit time to the number of the issue of the n-th type instructions per unit time inputted from the first logical unit 11. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、電子装置、コンピュータ、冷却制御方法、および、冷却制御プログラムに関し、特に、命令の種類により冷却能力の制御を行う電子装置、コンピュータ、冷却制御方法、および、冷却制御プログラムに関する。   The present invention relates to an electronic device, a computer, a cooling control method, and a cooling control program, and more particularly, to an electronic device, a computer, a cooling control method, and a cooling control program that control the cooling capacity according to the type of instruction.

従来の冷却制御装置としては、たとえば、所定のプロセスを経て画像形成を行う画像形成装置において、前記プロセスに連動して駆動される温度上昇を伴う電装部と、その電装部を冷却する冷却ファンと、その冷却ファンの動作を制御する制御手段とを有し、前記制御手段が前記電装部内の所定個所の温度を推定する温度推定手段を備えると共に、その温度推定手段での推定結果に応じて前記冷却ファンの動作を制御するファン制御装置がある（特許文献１）。   As a conventional cooling control device, for example, in an image forming apparatus that forms an image through a predetermined process, an electrical component that is driven in conjunction with the process and that has a temperature rise, a cooling fan that cools the electrical component, And a control means for controlling the operation of the cooling fan, the control means comprising a temperature estimation means for estimating the temperature at a predetermined location in the electrical component, and according to the estimation result of the temperature estimation means, There is a fan control device that controls the operation of a cooling fan (Patent Document 1).

特開２００３−７６２５１号公報JP 2003-76251 A

上述した従来の冷却制御装置の技術の問題点は、装置の動作状態に基づいて、瞬時に、冷却能力を変化させることがむずかしいことである。   The problem with the technology of the conventional cooling control apparatus described above is that it is difficult to change the cooling capacity instantaneously based on the operating state of the apparatus.

その理由は、冷却装置で装置の冷却を行う場合、周囲の温度を温度センサにより測定し、この温度を１つに要素として考慮し、必要な冷却能力を供給する制御を行っているので、装置の負荷の急変による急な温度変化の場合、温度変化に対し必要な冷却能力が即時的に追従できないからである。   The reason for this is that when the device is cooled by a cooling device, the ambient temperature is measured by a temperature sensor, and this temperature is considered as one factor, and control is performed to supply the necessary cooling capacity. This is because in the case of a sudden temperature change due to a sudden change in the load, the required cooling capacity cannot immediately follow the temperature change.

本発明の目的は、上述した従来の課題を解決する電子装置、コンピュータ、冷却制御方法、および、冷却制御プログラムを提供することである。   An object of the present invention is to provide an electronic apparatus, a computer, a cooling control method, and a cooling control program that solve the above-described conventional problems.

本発明の第１の電子装置は、１以上の単位時間当たりの第ｉ種の命令の発行数、または、実行数を算出する第ｉの命令数算出部を含む第１の論理装置と、１以上の単位時間当たりの前記第ｉ種の命令の発行数、または、実行数に基づいて、第ｉ種の命令の動作により大きく電力を消費する第ｉの論理装置の冷却能力を増大させる制御を行う冷却制御装置とを有することを特徴とする。   A first electronic device according to the present invention includes a first logic device including an i-th instruction number calculation unit that calculates the number of issuances of an i-type instruction per unit time or the number of executions, and 1 Control for increasing the cooling capacity of the i-th logic device that consumes a large amount of power by the operation of the i-type instruction based on the number of issuances or executions of the i-th instruction per unit time. And a cooling control device for performing the operation.

本発明の第２の電子装置は、１以上の単位時間当たりの第ｉ種の命令の発行数、または、実行数を算出する第ｉの命令数算出部を含む第１の論理装置と、１以上の単位時間当たりの前記第ｉ種の命令の発行数、または、実行数に基づいて、第ｉ種の命令の動作により大きく電力を消費する第ｉの論理装置の冷却能力を増大させる制御を行う冷却制御装置と、前記冷却制御装置の制御にしたがい前記第ｉの論理装置の冷却を行う第ｉの冷却装置とを有することを特徴とする。   A second electronic device according to the present invention includes a first logic device including an i-th instruction number calculation unit that calculates the number of issuances of i-type instructions per unit time or the number of executions, and 1 Control for increasing the cooling capacity of the i-th logic device that consumes a large amount of power by the operation of the i-type instruction based on the number of issuances or executions of the i-th instruction per unit time. A cooling control device that performs cooling, and an i-th cooling device that cools the i-th logic device according to the control of the cooling control device.

本発明の第１のコンピュータは、中央処理装置と、主記憶装置と、冷却制御装置とを備え、前記中央処理装置が、単位時間当たりの演算器命令の発行数、または、実行数を算出する演算器命令数算出部と、単位時間当たりの主記憶アクセス命令の発行数、または、実行数を算出する主記憶アクセス命令数算出部とを有し、前記冷却制御装置が、単位時間当たりの演算器命令の発行数、または、実行数と、単位時間当たりの主記憶アクセス命令の発行数、または、実行数とに対応する単位時間当たりの冷却能力増分とを含む制御テーブルにしたがって、前記中央処理装置、前記主記憶装置の冷却を制御する手段を有することを特徴とする。   A first computer according to the present invention includes a central processing unit, a main storage device, and a cooling control unit, and the central processing unit calculates the number of operation unit instructions issued or the number of executions per unit time. An arithmetic unit instruction number calculating unit, and a main memory access instruction number calculating unit for calculating the number of issued main memory access instructions per unit time or the number of executions. The central processing according to a control table including the number of issued or executed instructions and the number of issued main memory access instructions per unit time or an increase in cooling capacity per unit time corresponding to the number of executed instructions And a device for controlling cooling of the main storage device.

本発明の第２のコンピュータは、中央処理装置と、主記憶装置と、入出力装置と、冷却制御装置とを備え、前記中央処理装置が、単位時間当たりの演算器命令の発行数、または、実行数を算出する演算器命令数算出部と、単位時間当たりの主記憶アクセス命令の発行数、または、実行数を算出する主記憶アクセス命令数算出部と、単位時間当たりの入出力命令の発行数、または、実行数を算出する入出力命令数算出部とを有し、前記冷却制御装置が、単位時間当たりの演算器命令の発行数、または、実行数と、単位時間当たりの主記憶アクセス命令の発行数、または、実行数と、単位時間当たりの入出力命令の発行数、または、実行数とに対応する単位時間当たりの冷却能力増分とを含む制御テーブルにしたがって、前記中央処理装置、前記主記憶装置、および、前記入出力装置の冷却を制御する手段を有することを特徴とする。   A second computer according to the present invention includes a central processing unit, a main storage device, an input / output device, and a cooling control device, wherein the central processing unit is configured to issue an arithmetic unit instruction per unit time, or An arithmetic unit instruction number calculation unit that calculates the number of executions, and a main memory access instruction number calculation unit that calculates the number of executions of main memory access instructions per unit time, and issuance of input / output instructions per unit time The number of input / output instructions to calculate the number of executions, or the number of executions, and the cooling control device issues the number of arithmetic unit instructions issued per unit time or the number of executions and main memory access per unit time The central processing unit according to a control table including the number of instructions issued or executed and the number of I / O instructions issued per unit time or a cooling capacity increment per unit time corresponding to the number of executed times, Said Storage and characterized by having a means for controlling the cooling of the output device.

本発明の第３のコンピュータは、前記第２のコンピュータであって、前記演算器命令数算出部が、演算器命令の発行を検出し演算器命令発行検出信号を出力する演算器命令検出回路と、演算器命令発行回数を保持し、演算器命令発行検出信号にしたがい演算器命令発行回数を増加させ、一定時間到達信号により演算器命令発行回数をリセットする命令発行数保持回路と、単位時間値を保持し、毎クロック単位時間値を増加させ、単位時間値が一定の時間に達すると一定時間到達信号を出力する単位時間検出回路と、演算器命令発行回数を保持し、一定時間到達信号にしたがい前記命令発行数保持回路からの演算器命令発行回数を取り込む単位時間当たりの命令発行数保持回路とを有することを特徴とする。   A third computer according to the present invention is the second computer, wherein the arithmetic unit instruction number calculation unit detects an arithmetic unit instruction issuance and outputs an arithmetic unit instruction issuance detection signal; An instruction issuance number holding circuit that holds the number of issuance of operation unit instructions, increases the number of issuance of operation unit instructions in accordance with the operation unit instruction issuance detection signal, and resets the number of operation unit instruction issuances by a fixed time arrival signal, and unit time value The unit time detection circuit that increases the unit time value for each clock and outputs a fixed time arrival signal when the unit time value reaches a fixed time, and the number of operation unit command issuances are held, Accordingly, an instruction issue number holding circuit per unit time for fetching the number of operation unit instruction issues from the instruction issue number holding circuit is provided.

本発明の第４のコンピュータは、前記第２、または、第３のコンピュータであって、前記制御テーブルが、単位時間当たりの演算器命令の発行数、または、実行数の増加に対して前記中央処理装置の冷却能力の増加を大きく、単位時間当たりの主記憶アクセス命令の発行数、または、実行数の増加に対して前記主記憶装置の冷却能力の増加を大きく、単位時間当たりの入出力命令の発行数、または、実行数の増加に対して前記入出力装置の冷却能力の増加を大きくする冷却能力増分を含むことを特徴とする。   The fourth computer according to the present invention is the second or third computer, wherein the control table is configured to increase the number of operation unit instructions issued per unit time or increase in the number of executions. The increase in the cooling capacity of the processing unit is large, and the increase in the cooling capacity of the main storage unit is large with respect to the increase in the number of issued main memory access instructions per unit time or the number of executions. And an increase in the cooling capacity of the input / output device with respect to an increase in the number of issuances or executions.

本発明の第１の冷却制御方法は、第１の論理装置が、１以上の単位時間当たりの第ｉ種の命令の発行数、または、実行数を算出する第ｉの命令数算出手順を含み、冷却制御装置が、１以上の単位時間当たりの前記第ｉ種の命令の発行数、または、実行数に基づいて、第ｉ種の命令の動作により大きく電力を消費する第ｉの論理装置の冷却能力を増大させる制御を行う手順を含むことを特徴とする。   The first cooling control method of the present invention includes an i-th instruction number calculation procedure in which the first logic device calculates the number of issuances of the i-type instruction per unit time or the number of executions. The cooling control device of the i-th logic device that consumes more power by the operation of the i-type instruction based on the number of issuances or executions of the i-type instruction per unit time. It includes a procedure for performing control for increasing the cooling capacity.

本発明の第２の冷却制御方法は、中央処理装置と、主記憶装置と、入出力装置と、冷却制御装置とを利用し、前記中央処理装置が、単位時間当たりの演算器命令の発行数、または、実行数を算出する演算器命令算出手順と、単位時間当たりの主記憶アクセス命令の発行数、または、実行数を算出する主記憶アクセス命令算出手順と、単位時間当たりの入出力命令の発行数、または、実行数を算出する入出力命令算出手順とを含み、前記冷却制御装置が、単位時間当たりの演算器命令の発行数、または、実行数と、単位時間当たりの主記憶アクセス命令の発行数、または、実行数と、単位時間当たりの入出力命令の発行数、または、実行数とに対応する単位時間当たりの冷却能力増分とを含む制御テーブルにしたがって、前記中央処理装置、前記主記憶装置、および、前記入出力装置の冷却を制御する手順を含むことを特徴とする。   A second cooling control method of the present invention uses a central processing unit, a main storage device, an input / output device, and a cooling control unit, and the central processing unit issues the number of arithmetic unit instructions per unit time. Or, an arithmetic unit instruction calculation procedure for calculating the number of executions, a number of main memory access instructions issued per unit time, or a main memory access instruction calculation procedure for calculating the number of executions, and an input / output instruction per unit time An input / output instruction calculation procedure for calculating the number of issued or executed instructions, wherein the cooling control device issues the number of issued operator instructions per unit time or the number of executed instruction and main memory access instructions per unit time. In accordance with a control table including the number of issued or executed and the number of I / O instruction issued per unit time or the cooling capacity increment per unit time corresponding to the executed number. Main memory, and characterized in that it comprises a procedure for controlling the cooling of the output device.

本発明の第３の冷却制御方法は、前記第２の冷却制御方法であって、前記演算器命令算出手順が、演算器命令検出回路に、演算器命令の発行を検出し演算器命令発行検出信号を出力させる手順と、命令発行数保持回路に、演算器命令発行回数を保持し、演算器命令発行検出信号にしたがい演算器命令発行回数を増加させ、一定時間到達信号により演算器命令発行回数をリセットさせる手順と、単位時間検出回路に、単位時間値を保持し、毎クロック単位時間値を増加させ、単位時間値が一定の時間に達すると一定時間到達信号を出力させる手順と、単位時間当たりの命令発行数保持回路に、演算器命令発行回数を保持し、一定時間到達信号にしたがい前記命令発行数保持回路からの演算器命令発行回数を取り込ませる手順とを含むことを特徴とする。   The third cooling control method of the present invention is the second cooling control method, wherein the arithmetic unit instruction calculation procedure detects an arithmetic unit instruction issue to the arithmetic unit instruction detection circuit and detects an arithmetic unit instruction issue detection. The signal output procedure and the instruction issue count holding circuit hold the number of operator instruction issuances, increase the number of operator instruction issuances according to the operator instruction issuance detection signal, and issue the number of operator instruction issuances by a fixed time arrival signal. The unit time detection circuit holds the unit time value, increments the clock unit time value every clock, and outputs a constant time arrival signal when the unit time value reaches a certain time, and unit time And a procedure for holding the number of operation unit instruction issuances in the per instruction issuance number holding circuit, and fetching the number of operation unit instruction issuances from the instruction issuance number holding circuit according to a fixed time arrival signal. To.

本発明の第１の冷却制御プログラムは、第１の論理装置が、１以上の単位時間当たりの第ｉ種の命令の発行数、または、実行数を算出する第ｉの命令数算出手順を含み、冷却制御装置が、１以上の単位時間当たりの前記第ｉ種の命令の発行数、または、実行数に基づいて、第ｉ種の命令の動作により大きく電力を消費する第ｉの論理装置の冷却能力を増大させる制御を行う手順を電子機器に実行させることを特徴とする。   The first cooling control program of the present invention includes an i-th instruction number calculation procedure in which the first logic device calculates the number of issuances of the i-type instruction per unit time or the number of executions. The cooling control device of the i-th logic device that consumes more power by the operation of the i-type instruction based on the number of issuances or executions of the i-type instruction per unit time. The electronic apparatus is caused to execute a procedure for performing control for increasing the cooling capacity.

本発明の第２の冷却制御プログラムは、中央処理装置と、主記憶装置と、入出力装置と、冷却制御装置とを利用し、前記中央処理装置が、単位時間当たりの演算器命令の発行数、または、実行数を算出する演算器命令算出手順と、単位時間当たりの主記憶アクセス命令の発行数、または、実行数を算出する主記憶アクセス命令算出手順と、単位時間当たりの入出力命令の発行数、または、実行数を算出する入出力命令算出手順と、前記冷却制御装置が、単位時間当たりの演算器命令の発行数、または、実行数と、単位時間当たりの主記憶アクセス命令の発行数、または、実行数と、単位時間当たりの入出力命令の発行数、または、実行数とに対応する単位時間当たりの冷却能力増分とを含む制御テーブルにしたがって、前記中央処理装置、前記主記憶装置、および、前記入出力装置の冷却を制御する手順をコンピュータに実行させることを特徴とする。   A second cooling control program of the present invention uses a central processing unit, a main storage device, an input / output device, and a cooling control unit, and the central processing unit issues the number of operation unit instructions per unit time. Or, an arithmetic unit instruction calculation procedure for calculating the number of executions, a number of main memory access instructions issued per unit time, or a main memory access instruction calculation procedure for calculating the number of executions, and an input / output instruction per unit time Input / output instruction calculation procedure for calculating the number of issued or executed, and the cooling control unit issuing the number of arithmetic unit instructions issued per unit time or the number of executed and main memory access instructions per unit time The central processing unit according to a control table including the number or execution number and the number of I / O instructions issued per unit time or the cooling capacity increment per unit time corresponding to the execution number. Main memory, and characterized in that to execute the steps of controlling the cooling of the input device to the computer.

本発明の第３の冷却制御プログラムは、前記第２の冷却制御プログラムであって、前記演算器命令算出手順が、演算器命令検出回路に、演算器命令の発行を検出し演算器命令発行検出信号を出力させる手順と、命令発行数保持回路に、演算器命令発行回数を保持し、演算器命令発行検出信号にしたがい演算器命令発行回数を増加させ、一定時間到達信号により演算器命令発行回数をリセットさせる手順と、単位時間検出回路に、単位時間値を保持し、毎クロック単位時間値を増加させ、単位時間値が一定の時間に達すると一定時間到達信号を出力させる手順と、単位時間当たりの命令発行数保持回路に、演算器命令発行回数を保持し、一定時間到達信号にしたがい前記命令発行数保持回路からの演算器命令発行回数を取り込ませる手順とを含み、上記手順をコンピュータに実行させることを特徴とする。   The third cooling control program of the present invention is the second cooling control program, wherein the computing unit command calculation procedure detects the issuing of the computing unit command to the computing unit command detection circuit and detects the computing unit command issue. The signal output procedure and the instruction issue count holding circuit hold the number of operator instruction issuances, increase the number of operator instruction issuances according to the operator instruction issuance detection signal, and issue the number of operator instruction issuances by a fixed time arrival signal. The unit time detection circuit holds the unit time value, increments the clock unit time value every clock, and outputs a constant time arrival signal when the unit time value reaches a certain time, and unit time And a procedure for holding the number of operation unit instruction issuances in the per-instruction issue number holding circuit and fetching the number of operation unit instruction issuances from the instruction issue number holding circuit according to a fixed time arrival signal. , Characterized in that to perform the above procedure in the computer.

本発明は、装置の動作状態に基づいて、瞬時に、冷却能力を変化できるという効果を持つ。   The present invention has an effect that the cooling capacity can be instantaneously changed based on the operating state of the apparatus.

その理由は、命令の種類により電力を消費する論理装置の冷却能力を増大させる制御を行うからである。   This is because control is performed to increase the cooling capacity of the logic device that consumes power depending on the type of instruction.

次に、本発明を実施するための第１の最良の形態について図面を参照して詳細に説明する。   Next, a first best mode for carrying out the present invention will be described in detail with reference to the drawings.

図１は、本発明を実施するための第１の最良の形態の構成を示すブロック図である。   FIG. 1 is a block diagram showing the configuration of the first best mode for carrying out the present invention.

図１を参照すると、本発明を実施するための第１の最良の形態は、命令を実行する第１の論理装置１１と、第２の論理装置１２と、第３の論理装置１３と、・・・、第ｎの論理装置１ｎと、主に第１の論理装置１１を冷却する第１の冷却装置２１と、主に第２の論理装置１２を冷却する第２の冷却装置２２と、主に第３の論理装置１３を冷却する第３の冷却装置２３と、・・・、主に第ｎの論理装置１ｎを冷却する第ｎの冷却装置２ｎと、冷却制御装置３０とを含んで構成される電子装置１０である。   Referring to FIG. 1, the first best mode for carrying out the present invention is that a first logical unit 11, a second logical unit 12, a third logical unit 13 for executing instructions, The n-th logic device 1n, the first cooling device 21 that mainly cools the first logic device 11, the second cooling device 22 that mainly cools the second logic device 12, and the main , A third cooling device 23 for cooling the third logic device 13,..., Mainly an nth cooling device 2 n for cooling the nth logic device 1 n, and a cooling control device 30. Electronic device 10 to be used.

図２は、命令を実行する第１の論理装置１１、および、冷却制御装置３０の構成を示すブロック図である。   FIG. 2 is a block diagram showing the configuration of the first logic device 11 that executes instructions and the cooling control device 30.

図２を参照すると、第１の論理装置１１は、単位時間当たりの第１種の命令発行数を算出し冷却制御装置３０に出力する第１の命令数算出部４１と、単位時間当たりの第２種の命令発行数を算出し冷却制御装置３０に出力する第２の命令数算出部４２と、単位時間当たりの第３種の命令発行数を算出し冷却制御装置３０に出力する第３の命令数算出部４３と、・・・、単位時間当たりの第ｎ種の命令発行数を算出し冷却制御装置３０に出力する第ｎの命令数算出部４ｎとを含む。ここで、第１種の命令は、第１の論理装置１１の動作に大きな影響を与える命令（たとえば、多く動作し、電力を消費する命令）である。第２種の命令は、第２の論理装置１２の動作に大きな影響を与える命令である。第３種の命令は、第３の論理装置１３の動作に大きな影響を与える命令である。第ｎ種の命令は、第ｎの論理装置１ｎの動作に大きな影響を与える命令である。   Referring to FIG. 2, the first logic device 11 calculates a first type instruction issue number per unit time and outputs it to the cooling control unit 30, and a first instruction unit 41 per unit time. A second command number calculation unit 42 that calculates the number of two types of command issuance and outputs the same to the cooling control device 30; and a third command number that calculates the third type of command issuance per unit time and outputs it to the cooling control device 30. A command number calculation unit 43; and an nth command number calculation unit 4n that calculates the number of nth type of command issuance per unit time and outputs it to the cooling control device 30. Here, the first type instruction is an instruction that greatly affects the operation of the first logic device 11 (for example, an instruction that operates a lot and consumes power). The second type of instruction is an instruction that greatly affects the operation of the second logic device 12. The third type of instruction is an instruction that greatly affects the operation of the third logic device 13. The n-th type of instruction is an instruction that greatly affects the operation of the n-th logic device 1n.

また、冷却制御装置３０は、制御テーブル３０１を含み、第１の論理装置１１から入力した単位時間当たりの第１種の命令発行数〜単位時間当たりの第ｎ種の命令発行数に基づいて第１の冷却装置２１〜第ｎの冷却装置２ｎの冷却能力を制御（たとえば、冷却能力増分を求める）する。   In addition, the cooling control device 30 includes a control table 301, and is based on the number of first type commands issued per unit time to the number n type command issued per unit time input from the first logic device 11. The cooling capacity of the first cooling device 21 to the n-th cooling device 2n is controlled (for example, a cooling capacity increment is obtained).

次に、本発明を実施するための第１の最良の形態の実施例について説明する。   Next, an example of the first best mode for carrying out the present invention will be described.

図３は、本発明を実施するための第１の最良の形態の実施例の構成を示すブロック図である。   FIG. 3 is a block diagram showing a configuration of an embodiment of the first best mode for carrying out the present invention.

図３を参照すると、電子装置１０は、コンピュータ１００である。第１の論理装置１１は、中央処理装置１１０であり、第２の論理装置１２は、主記憶装置１２０であり、第３の論理装置１３は、入出力装置１３０である。また、第１種の命令は、中央処理装置１１０内の演算器（たとえば、加算器、乗算器等）を動作させる演算器命令（たとえば、加算命令、乗算命令等）である。第２種の命令は、主記憶装置１２０を動作（読み出し、書き込み等）させる主記憶アクセス命令（たとえば、主記憶装置１２０からの読み出し命令、主記憶装置１２０への書き込み命令等）である。第３種の命令は、入出力装置１３０を動作（読み出し、書き込み等）させる入出力命令（たとえば、入出力装置１３０からの読み出し命令、入出力装置１３０への書き込み命令等）である。第１の冷却装置２１は、主に中央処理装置１１０を冷却し、第２の冷却装置２２は、主に主記憶装置１２０を冷却し、第３の冷却装置２３は、主に入出力装置１３０を冷却する。   Referring to FIG. 3, the electronic device 10 is a computer 100. The first logical device 11 is a central processing unit 110, the second logical device 12 is a main storage device 120, and the third logical device 13 is an input / output device 130. The first type of instruction is an arithmetic unit instruction (for example, an addition instruction, a multiplication instruction, etc.) for operating an arithmetic unit (for example, an adder, a multiplier, etc.) in the central processing unit 110. The second type of instruction is a main memory access instruction (for example, a read instruction from the main storage apparatus 120, a write instruction to the main storage apparatus 120, etc.) that causes the main storage apparatus 120 to operate (read, write, etc.). The third type of command is an input / output command (for example, a read command from the input / output device 130, a write command to the input / output device 130, etc.) that causes the input / output device 130 to operate (read, write, etc.). The first cooling device 21 mainly cools the central processing unit 110, the second cooling device 22 mainly cools the main storage device 120, and the third cooling device 23 mainly takes care of the input / output device 130. Cool down.

上記の「主に」は、たとえば、第１の冷却装置２１が、完全に、中央処理装置１１０のみを冷却するとは限らないからである（風が主記憶装置１２０に、幾分かは漏れるからである）。   The above “mainly” is because, for example, the first cooling device 21 does not completely cool only the central processing unit 110 (because the wind leaks to the main storage device 120 to some extent). Is).

図４は、図３の中央処理装置１１０の構成を示すブロック図である。   FIG. 4 is a block diagram showing a configuration of the central processing unit 110 of FIG.

図４を参照すると、クロックに同期して動作する中央処理装置１１０は、演算器命令数算出部５１（第１の命令数算出部４１に相当）と、主記憶アクセス命令数算出部５２（第２の命令数算出部４２に相当）と、入出力命令数算出部５３（第３の命令数算出部４３に相当）とを含む。   Referring to FIG. 4, the central processing unit 110 that operates in synchronization with the clock includes an arithmetic unit instruction number calculation unit 51 (corresponding to the first instruction number calculation unit 41) and a main memory access instruction number calculation unit 52 (first number). 2 instruction number calculation unit 42) and input / output instruction number calculation unit 53 (corresponding to the third instruction number calculation unit 43).

図５は、図４の演算器命令数算出部５１の構成を示すブロック図である。   FIG. 5 is a block diagram showing a configuration of the arithmetic unit instruction count calculation unit 51 of FIG.

図５を参照すると、演算器命令数算出部５１は、演算器命令の発行を検出し演算器命令発行検出信号を出力する演算器命令検出回路６１と、演算器命令発行回数を保持し、演算器命令発行検出信号にしたがい演算器命令発行回数を増加させ、一定時間到達信号により演算器命令発行回数を“０”にリセットする命令発行数保持回路６２と、単位時間値を保持し、毎クロック単位時間値を増加させ、単位時間値が一定の時間に達すると一定時間到達信号を命令発行数保持回路６２、および、単位時間当たりの命令発行数保持回路６４に出力する単位時間検出回路６３と、演算器命令発行回数を保持し、一定時間到達信号にしたがい命令発行数保持回路６２からの演算器命令発行回数を取り込む単位時間当たりの命令発行数保持回路６４とを含む。   Referring to FIG. 5, the arithmetic unit instruction number calculating unit 51 detects an issuance of an arithmetic unit instruction and outputs an arithmetic unit instruction issuance detection signal, holds an arithmetic unit instruction issuance count, An instruction issue number holding circuit 62 that increases the number of instructions issued by an arithmetic unit instruction according to the instruction issue detection signal and resets the instruction instruction issue number to “0” by a fixed time arrival signal, and holds a unit time value every clock A unit time value is increased, and when the unit time value reaches a certain time, a certain time arrival signal is output to the instruction issuance number holding circuit 62 and the instruction issuance number holding circuit 64 per unit time. And an instruction issue number holding circuit 64 per unit time for holding the operation instruction issue number and fetching the operator instruction issue number from the instruction issue number holding circuit 62 according to a fixed time arrival signal.

また、命令発行数保持回路６２は、演算器命令発行検出信号、および、一定時間到達信号を同クロックで入力すると、演算器命令発行回数を“０”にする（“１”にする構成も可能である）。   In addition, the instruction issue number holding circuit 62 can be configured to set the number of operator instruction issuances to “0” (“1”) when an arithmetic unit instruction issuance detection signal and a fixed time arrival signal are input with the same clock. Is).

主記憶アクセス命令数算出部５２、入出力命令数算出部５３も、命令発行数保持回路６２と、単位時間検出回路６３と単位時間当たりの命令発行数保持回路６４を含む。演算器命令検出回路６１の替わりに、主記憶アクセス命令数算出部５２は、主記憶アクセス命令の発行を検出し主記憶アクセス命令発行検出信号を出力する主記憶アクセス命令検出回路（図示せず）を含む。また、入出力命令数算出部５３は、入出力命令の発行を検出し入出力命令発行検出信号を出力する入出力命令検出回路（図示せず）を含む。   The main memory access instruction number calculation unit 52 and the input / output instruction number calculation unit 53 also include an instruction issue number holding circuit 62, a unit time detection circuit 63, and an instruction issue number holding circuit 64 per unit time. Instead of the arithmetic unit instruction detection circuit 61, the main memory access instruction number calculator 52 detects a main memory access instruction issue and outputs a main memory access instruction issue detection signal (not shown). including. The input / output command number calculation unit 53 includes an input / output command detection circuit (not shown) that detects the issue of an input / output command and outputs an input / output command issue detection signal.

次に、本発明を実施するための第１の最良の形態の実施例の動作について図面を参照して詳細に説明する。   Next, the operation of the embodiment of the first best mode for carrying out the present invention will be described in detail with reference to the drawings.

図６は、本発明を実施するための第１の最良の形態の実施例の動作を示すタイミングチャートである。   FIG. 6 is a timing chart showing the operation of the embodiment of the first best mode for carrying out the present invention.

図６を参照すると、コンピュータ１００の起動時に演算器命令検出回路６１、命令発行数保持回路６２、単位時間検出回路６３、および、単位時間当たりの命令発行数保持回路６４は、“０”に設定される。単位時間検出回路６３は、一定時間（ここでは、７クロックの時間とする）になるまで、毎クロック、単位時間値を増加させる。   Referring to FIG. 6, when the computer 100 is started, the arithmetic unit instruction detection circuit 61, the instruction issue number holding circuit 62, the unit time detection circuit 63, and the instruction issue number holding circuit 64 per unit time are set to “0”. Is done. The unit time detection circuit 63 increases the unit time value for each clock until a predetermined time (here, a time of 7 clocks) is reached.

演算器命令検出回路６１が演算器命令の発行を検出すると演算器命令発行検出信号を出力する（図６クロックＴ１）。命令発行数保持回路６２は、演算器命令発行検出信号にしたがい演算器命令発行数を増加させ“１”にする（クロックＴ２）。演算器命令検出回路６１が演算器命令の発行を検出すると（クロックＴ４）、命令発行数保持回路６２は、演算器命令発行数を増加させ“２”にする（クロックＴ５）。演算器命令検出回路６１が演算器命令の発行を検出すると（クロックＴ６）、命令発行数保持回路６２は、演算器命令発行数を増加させ“３”にする（クロックＴ７）。演算器命令検出回路６１が演算器命令の発行を検出すると（クロックＴ７）、命令発行数保持回路６２は、演算器命令発行数を増加させ“４”にする（クロックＴ８）。   When the arithmetic unit instruction detection circuit 61 detects the issuance of an arithmetic unit instruction, it outputs an arithmetic unit instruction issuance detection signal (clock T1 in FIG. 6). The instruction issuance number holding circuit 62 increases the arithmetic unit instruction issuance number to “1” according to the arithmetic unit instruction issuance detection signal (clock T2). When the arithmetic unit instruction detection circuit 61 detects the issuance of an arithmetic unit instruction (clock T4), the instruction issuance number holding circuit 62 increases the arithmetic unit instruction issuance number to “2” (clock T5). When the arithmetic unit instruction detection circuit 61 detects the issuance of an arithmetic unit instruction (clock T6), the instruction issuance number holding circuit 62 increases the arithmetic unit instruction issuance number to “3” (clock T7). When the arithmetic unit instruction detection circuit 61 detects the issuance of an arithmetic unit instruction (clock T7), the instruction issue number holding circuit 62 increases the arithmetic unit instruction issue number to “4” (clock T8).

また、単位時間検出回路６３が、単位時間値“７”になり一定時間到達信号を出力すると（クロックＴ８）、命令発行数保持回路６２は、一定時間到達信号にしたがい演算器命令発行数をリセットし“０”にする（クロックＴ９）。また、単位時間検出回路６３は、単位時間値を“０”にする（クロックＴ９）。また、単位時間当たりの命令発行数保持回路６４は、一定時間到達信号にしたがい命令発行数保持回路６２からの演算器命令発行回数“４”を取り込み保持する（クロックＴ９）。   Further, when the unit time detection circuit 63 becomes the unit time value “7” and outputs a fixed time arrival signal (clock T8), the instruction issue number holding circuit 62 resets the arithmetic unit command issue number according to the fixed time arrival signal. And set to "0" (clock T9). The unit time detection circuit 63 sets the unit time value to “0” (clock T9). Further, the instruction issue number holding circuit 64 per unit time fetches and holds the arithmetic unit instruction issue number “4” from the instruction issue number holding circuit 62 according to a fixed time arrival signal (clock T9).

演算器命令検出回路６１が演算器命令の発行を検出すると（クロックＴ９）、命令発行数保持回路６２は、演算器命令発行数を増加させ“１”にする（クロックＴ１０）。演算器命令検出回路６１が演算器命令の発行を検出すると（クロックＴ１０）、命令発行数保持回路６２は、演算器命令発行数を増加させ“２”にする（クロックＴ１１）。演算器命令検出回路６１が演算器命令の発行を検出すると（クロックＴ１１）、命令発行数保持回路６２は、演算器命令発行数を増加させ“３”にする（クロックＴ１２）。演算器命令検出回路６１が演算器命令の発行を検出すると（クロックＴ１３）、命令発行数保持回路６２は、演算器命令発行数を増加させ“４”にする（クロックＴ１４）。演算器命令検出回路６１が演算器命令の発行を検出すると（クロックＴ１５）、命令発行数保持回路６２は、演算器命令発行数を増加させ“５”にする（クロックＴ１６）。   When the arithmetic unit instruction detection circuit 61 detects the issuance of an arithmetic unit instruction (clock T9), the instruction issuance number holding circuit 62 increases the arithmetic unit instruction issuance number to “1” (clock T10). When the arithmetic unit instruction detection circuit 61 detects the issuance of an arithmetic unit instruction (clock T10), the instruction issuance number holding circuit 62 increases the arithmetic unit instruction issuance number to “2” (clock T11). When the arithmetic unit instruction detection circuit 61 detects an issuance of an arithmetic unit instruction (clock T11), the instruction issue number holding circuit 62 increases the arithmetic unit instruction issue number to “3” (clock T12). When the arithmetic unit instruction detection circuit 61 detects the issuance of an arithmetic unit instruction (clock T13), the instruction issue number holding circuit 62 increases the arithmetic unit instruction issue number to “4” (clock T14). When the arithmetic unit instruction detection circuit 61 detects the issuance of an arithmetic unit instruction (clock T15), the instruction issue number holding circuit 62 increases the arithmetic unit instruction issue number to “5” (clock T16).

また、単位時間検出回路６３が、単位時間値“７”になり一定時間到達信号を出力すると（クロックＴ１６）、命令発行数保持回路６２は、一定時間到達信号にしたがい演算器命令発行数をリセットし“０”にする（クロックＴ１７）。また、単位時間検出回路６３は、単位時間値を“０”にする（クロックＴ１７）。また、単位時間当たりの命令発行数保持回路６４は、一定時間到達信号にしたがい命令発行数保持回路６２からの演算器命令発行回数“５”を取り込み保持する（クロックＴ９）。   Further, when the unit time detection circuit 63 becomes the unit time value “7” and outputs a fixed time arrival signal (clock T16), the instruction issue number holding circuit 62 resets the arithmetic unit command issue number according to the fixed time arrival signal. And set to "0" (clock T17). The unit time detection circuit 63 sets the unit time value to “0” (clock T17). The instruction issue number holding circuit 64 per unit time fetches and holds the arithmetic unit instruction issue number “5” from the instruction issue number holding circuit 62 in accordance with a fixed time arrival signal (clock T9).

主記憶アクセス命令数算出部５２、入出力命令数算出部５３も、演算器命令検出回路６１と同様の動作をする。   The main memory access instruction number calculation unit 52 and the input / output instruction number calculation unit 53 also operate in the same manner as the arithmetic unit instruction detection circuit 61.

次に、冷却制御装置３０の動作について図面を参照して説明する。   Next, the operation of the cooling control device 30 will be described with reference to the drawings.

図７は、冷却制御装置３０の動作を示す制御テーブル３０１の説明図である。   FIG. 7 is an explanatory diagram of the control table 301 showing the operation of the cooling control device 30.

冷却制御装置３０は、内部の記憶装置に制御テーブル３０１を含み、制御テーブル３０１にしたがって動作する。   The cooling control device 30 includes a control table 301 in an internal storage device, and operates according to the control table 301.

図７を参照すると、制御テーブル３０１は、第１の冷却装置２１〜第３の冷却装置２３対応に命令種別ごとの単位時間当たりの発行数帯、単位時間当たりの冷却能力増分を含む。   Referring to FIG. 7, the control table 301 includes an issuance band per unit time and a cooling capacity increment per unit time for each instruction type corresponding to the first cooling device 21 to the third cooling device 23.

たとえば、中央処理装置１１０を主に冷却する第１の冷却装置２１では、演算器命令の増加に対して冷却能力の増加が大きく、入出出力命令の増加に対して冷却能力の増加はそれほど大きくない。入出力装置１３０を主に冷却する第３の冷却装置２３では、演算器命令の増加に対しては冷却能力の増加がなく、入出力命令の増加に対して冷却能力の増加が大きい。以上のように、制御テーブル３０１では、冷却される装置が大きく動作する命令に対してはその冷却される装置の冷却を増大させるように命令ごとの重み付けが決定される。   For example, in the first cooling device 21 that mainly cools the central processing unit 110, the increase in the cooling capacity is large with respect to the increase in the arithmetic command, and the increase in the cooling capacity is not so large with respect to the increase in the input / output command. . In the third cooling device 23 that mainly cools the input / output device 130, there is no increase in the cooling capacity with respect to the increase in the arithmetic command, and the increase in the cooling capacity is large with respect to the increase in the input / output commands. As described above, in the control table 301, a weight for each instruction is determined so as to increase the cooling of the apparatus to be cooled for an instruction that causes the apparatus to be cooled to operate greatly.

冷却制御装置３０は、制御テーブル３０１にしたがって、冷却能力制御信号を出力し第１の冷却装置２１〜第３の冷却装置２３を制御する。
この表に従って、各動作命令の単位時間当たりの発行数に応じて、各冷却ユニットの単位時間当たりの冷却能力が変化することで、各ユニットの負荷に応じて必要な冷却能力が即時に供給されるため、装置内を一定の温度に保つことが容易に可能になる。 The cooling control device 30 outputs a cooling capacity control signal according to the control table 301 and controls the first cooling device 21 to the third cooling device 23.
According to this table, the cooling capacity per unit time of each cooling unit changes according to the number of operation commands issued per unit time, and the necessary cooling capacity is immediately supplied according to the load of each unit. Therefore, the inside of the apparatus can be easily maintained at a constant temperature.

また、演算器命令検出回路６１、上記主記憶アクセス命令検出回路、上記入出力命令検出回路が１つの命令検出回路に統合されてもよい。また、上記の説明においては、単位時間当たりの命令発行数について説明したが、単位時間当たりの命令実行数でもよい。   The arithmetic unit instruction detection circuit 61, the main memory access instruction detection circuit, and the input / output instruction detection circuit may be integrated into one instruction detection circuit. In the above description, the number of instructions issued per unit time has been described. However, the number of instructions executed per unit time may be used.

また、冷却制御装置３０は、たとえば、中央処理装置１１０に含まれてもよい。   Further, the cooling control device 30 may be included in the central processing unit 110, for example.

次に、演算器命令数算出部５１の構成について図面を参照してさらに詳細に説明する。   Next, the configuration of the arithmetic unit instruction count calculation unit 51 will be described in more detail with reference to the drawings.

図８は、演算器命令数算出部５１の詳細実施例の構成を示すブロック図である。   FIG. 8 is a block diagram showing the configuration of a detailed embodiment of the arithmetic unit instruction count calculation unit 51.

図８を参照すると、演算器命令検出回路６１は、演算器命令の発行を検出しデコーダ（入力は、命令語の命令指定部分）である。命令発行数保持回路６２は、演算器命令発行数を保持する命令発行数レジスタ６２１と、演算器命令発行数を１加算する加算回路６２２と、選択回路６２３（演算器命令発行検出信号が“０”であると命令発行数レジスタ６２１の出力を選択し、演算器命令発行検出信号が“１”であると加算回路６２２の出力を選択する）とを含む。   Referring to FIG. 8, the arithmetic unit instruction detection circuit 61 detects the issuance of an arithmetic unit instruction and is a decoder (input is an instruction designation portion of an instruction word). The instruction issuance number holding circuit 62 includes an instruction issuance number register 621 that holds an arithmetic unit instruction issuance number, an adder circuit 622 that adds 1 to the arithmetic unit instruction issuance number, and a selection circuit 623 (the arithmetic unit instruction issuance detection signal is “0”). "" Selects the output of the instruction issue number register 621, and selects the output of the adder circuit 622 if the arithmetic unit instruction issue detection signal is "1").

単位時間検出回路６３は、クロックによる単位時間の累積値を保持する単位時間レジスタ６３１と、単位時間の累積値を１加算する加算回路６３２と、一定時間を保持する一定時間レジスタ６３３と、単位時間の累積値と一定時間とを比較し、一致すると一定時間到達信号を出力する比較回路６３４とを含む。   The unit time detection circuit 63 includes a unit time register 631 that holds an accumulated value of unit time by a clock, an adder circuit 632 that adds 1 to the accumulated value of unit time, a constant time register 633 that holds a fixed time, and a unit time And a comparison circuit 634 that outputs a fixed time arrival signal when they coincide with each other.

単位時間当たりの命令発行数保持回路６４は、演算器命令発行数を保持する単位時間当たりの命令発行数レジスタ６４１と、選択回路６４２（一定時間到達信号が“０”であると単位時間当たりの命令発行数レジスタ６４１を選択し、一定時間到達信号が“１”であると命令発行数レジスタ６２１の出力を選択する）とを含む。   The instruction issuance number holding circuit 64 per unit time includes an instruction issuance number register 641 for holding an arithmetic unit instruction issuance number and a selection circuit 642 (if the fixed time arrival signal is “0”, The instruction issue number register 641 is selected, and if the fixed time arrival signal is “1”, the output of the instruction issue number register 621 is selected).

命令発行数レジスタ６２１、単位時間レジスタ６３１は、一定時間到達信号により、リセットされ“０”になる。   The instruction issue number register 621 and the unit time register 631 are reset to “0” by a fixed time arrival signal.

次に、本発明を実施するための第２の最良の形態について図面を参照して詳細に説明する。   Next, a second best mode for carrying out the present invention will be described in detail with reference to the drawings.

本発明を実施するための第２の最良の形態は、図６のフォローチャートの動作をする手順を含む方法である。   A second best mode for carrying out the present invention is a method including a procedure for operating the follow chart of FIG.

次に、本発明を実施するための第３の最良の形態について図面を参照して詳細に説明する。   Next, a third best mode for carrying out the present invention will be described in detail with reference to the drawings.

本発明を実施するための第３の最良の形態は、図６のフォローチャートの動作をする手順を電子装置１０に実行させるプログラムである。プログラムは、ハードウェアを制御するファームウェアとして実現可能である。   The third best mode for carrying out the present invention is a program for causing the electronic apparatus 10 to execute the procedure for performing the operation of the follow chart of FIG. The program can be realized as firmware that controls hardware.

本発明を実施するための第１の最良の形態の構成を示すブロック図。The block diagram which shows the structure of the 1st best form for implementing this invention. 命令を実行する第１の論理装置、および、冷却制御装置の構成を示すブロック図。The block diagram which shows the structure of the 1st logic device which performs a command, and a cooling control apparatus. 本発明を実施するための第１の最良の形態の実施例の構成を示すブロック図。The block diagram which shows the structure of the Example of the 1st best form for implementing this invention. 図３の中央処理装置の構成を示すブロック図。The block diagram which shows the structure of the central processing unit of FIG. 図４の演算器命令数算出部の構成を示すブロック図。FIG. 5 is a block diagram showing a configuration of an arithmetic unit instruction number calculation unit in FIG. 4. 本発明を実施するための第１の最良の形態の実施例の動作を示すタイミングチャート。The timing chart which shows the operation | movement of the Example of the 1st best form for implementing this invention. 冷却制御装置の動作を示す制御テーブルの説明図。Explanatory drawing of the control table which shows operation | movement of a cooling control apparatus. 演算器命令数算出部の詳細実施例の構成を示すブロック図。The block diagram which shows the structure of the detailed Example of an arithmetic unit command number calculation part.

符号の説明Explanation of symbols

１０ 電子装置
１１ 第１の論理装置
１２ 第２の論理装置
１３ 第３の論理装置
１ｎ 第ｎの論理装置
２１ 第１の冷却装置
２２ 第２の冷却装置
２３ 第３の冷却装置
２ｎ 第ｎの冷却装置
４１ 第１の命令数算出部
４２ 第２の命令数算出部
４３ 第３の命令数算出部
４ｎ 第ｎの命令数算出部
５１ 演算器命令数算出部
５２ 主記憶アクセス命令数算出部
５３ 入出力命令数算出部
６１ 演算器命令検出回路
６２ 命令発行数保持回路
６３ 単位時間検出回路
６４ 単位時間当たりの命令発行数保持回路
１００ コンピュータ
１１０ 中央処理装置
１２０ 主記憶装置
１３０ 入出力装置
３０１ 制御テーブル
６２１ 命令発行数レジスタ
６２２ 加算回路
６２３ 選択回路
６３１ 単位時間レジスタ
６３２ 加算回路
６３３ 一定時間レジスタ
６３４ 比較回路
６４１ 命令発行数レジスタ
６４２ 選択回路
DESCRIPTION OF SYMBOLS 10 Electronic device 11 1st logic device 12 2nd logic device 13 3rd logic device 1n nth logic device 21 1st cooling device 22 2nd cooling device 23 3rd cooling device 2n nth cooling Device 41 First instruction number calculation unit 42 Second instruction number calculation unit 43 Third instruction number calculation unit 4n nth instruction number calculation unit 51 arithmetic unit instruction number calculation unit 52 main memory access instruction number calculation unit 53 Output instruction number calculation unit 61 arithmetic unit instruction detection circuit 62 instruction issue number holding circuit 63 unit time detection circuit 64 instruction issue number holding circuit per unit time 100 computer 110 central processing unit 120 main storage unit 130 input / output unit 301 control table 621 Instruction issue number register 622 Adder circuit 623 Selector circuit 631 Unit time register 632 Adder circuit 633 Constant time register 634 Ratio Circuit 641 instruction issue number register 642 select circuit

Claims (12)

１以上の単位時間当たりの第ｉ種の命令の発行数、または、実行数を算出する第ｉの命令数算出部を含む第１の論理装置と、１以上の単位時間当たりの前記第ｉ種の命令の発行数、または、実行数に基づいて、第ｉ種の命令の動作により大きく電力を消費する第ｉの論理装置の冷却能力を増大させる制御を行う冷却制御装置とを有することを特徴とする電子装置。 A first logical unit including an i-th instruction number calculation unit for calculating the number of issuances of i-type instructions per unit time or the number of executions; and the i-th type per unit time And a cooling control device that performs control to increase the cooling capacity of the i-th logic device that consumes a large amount of power due to the operation of the i-th command based on the number of issued or executed instructions. An electronic device. １以上の単位時間当たりの第ｉ種の命令の発行数、または、実行数を算出する第ｉの命令数算出部を含む第１の論理装置と、１以上の単位時間当たりの前記第ｉ種の命令の発行数、または、実行数に基づいて、第ｉ種の命令の動作により大きく電力を消費する第ｉの論理装置の冷却能力を増大させる制御を行う冷却制御装置と、前記冷却制御装置の制御にしたがい前記第ｉの論理装置の冷却を行う第ｉの冷却装置とを有することを特徴とする電子装置。 A first logical unit including an i-th instruction number calculation unit for calculating the number of issuances of i-type instructions per unit time or the number of executions; and the i-th type per unit time A cooling control device that performs control to increase the cooling capacity of the i-th logic device that consumes a large amount of power by the operation of the i-th command based on the number of issued or executed instructions, and the cooling control device And an i-th cooling device that cools the i-th logic device according to the control of the electronic device. 中央処理装置と、主記憶装置と、冷却制御装置とを備え、
前記中央処理装置が、単位時間当たりの演算器命令の発行数、または、実行数を算出する演算器命令数算出部と、単位時間当たりの主記憶アクセス命令の発行数、または、実行数を算出する主記憶アクセス命令数算出部とを有し、
前記冷却制御装置が、単位時間当たりの演算器命令の発行数、または、実行数と、単位時間当たりの主記憶アクセス命令の発行数、または、実行数とに対応する単位時間当たりの冷却能力増分とを含む制御テーブルにしたがって、前記中央処理装置、前記主記憶装置の冷却を制御する手段を有することを特徴とするコンピュータ。 A central processing unit, a main storage device, and a cooling control device;
The central processing unit calculates an operation unit instruction number calculation unit for calculating the number of operation unit instructions issued or executed per unit time, and calculates the number of main memory access instructions issued or executed per unit time. A main memory access instruction number calculation unit
The cooling control device increases the cooling capacity increment per unit time corresponding to the number of issued arithmetic unit instructions per unit time or the number of executions and the number of main memory access instructions issued per unit time or the number of executions. A computer comprising: means for controlling cooling of the central processing unit and the main storage device according to a control table including: 中央処理装置と、主記憶装置と、入出力装置と、冷却制御装置とを備え、
前記中央処理装置が、単位時間当たりの演算器命令の発行数、または、実行数を算出する演算器命令数算出部と、単位時間当たりの主記憶アクセス命令の発行数、または、実行数を算出する主記憶アクセス命令数算出部と、単位時間当たりの入出力命令の発行数、または、実行数を算出する入出力命令数算出部とを有し、
前記冷却制御装置が、単位時間当たりの演算器命令の発行数、または、実行数と、単位時間当たりの主記憶アクセス命令の発行数、または、実行数と、単位時間当たりの入出力命令の発行数、または、実行数とに対応する単位時間当たりの冷却能力増分とを含む制御テーブルにしたがって、前記中央処理装置、前記主記憶装置、および、前記入出力装置の冷却を制御する手段を有することを特徴とするコンピュータ。 A central processing unit, a main storage device, an input / output device, and a cooling control device;
The central processing unit calculates an operation unit instruction number calculation unit for calculating the number of operation unit instructions issued or executed per unit time, and calculates the number of main memory access instructions issued or executed per unit time. A main memory access instruction number calculation unit, and an input / output instruction number calculation unit for calculating the number of I / O instructions issued per unit time or the number of executions,
The cooling control device issues the number of operation unit instructions issued per unit time, or the number of executions, the number of main memory access instructions issued per unit time, or the number of executions, and issuance of input / output instructions per unit time. A means for controlling cooling of the central processing unit, the main storage device, and the input / output device according to a control table including a cooling capacity increment per unit time corresponding to the number or the number of executions A computer characterized by 前記演算器命令数算出部が、
演算器命令の発行を検出し演算器命令発行検出信号を出力する演算器命令検出回路と、
演算器命令発行回数を保持し、演算器命令発行検出信号にしたがい演算器命令発行回数を増加させ、一定時間到達信号により演算器命令発行回数をリセットする命令発行数保持回路と、
単位時間値を保持し、毎クロック単位時間値を増加させ、単位時間値が一定の時間に達すると一定時間到達信号を出力する単位時間検出回路と、
演算器命令発行回数を保持し、一定時間到達信号にしたがい前記命令発行数保持回路からの演算器命令発行回数を取り込む単位時間当たりの命令発行数保持回路とを有することを特徴とする請求項４記載のコンピュータ。 The arithmetic unit instruction count calculation unit
An arithmetic unit instruction detection circuit for detecting an issuance of an arithmetic unit instruction and outputting an arithmetic unit instruction issue detection signal;
An instruction issuance number holding circuit for holding the number of issuance of operation unit instructions, increasing the number of issuance of operation unit instructions according to the operation unit instruction issuance detection signal, and resetting the number of issuance of operation unit instructions by a fixed time arrival signal;
A unit time detection circuit for holding a unit time value, increasing the unit time value for each clock, and outputting a constant time arrival signal when the unit time value reaches a certain time;
5. An instruction issue number holding circuit per unit time for holding an operation instruction issue number and taking an operation instruction issue number from the instruction issue number holding circuit according to a fixed time arrival signal. The listed computer. 前記制御テーブルが、単位時間当たりの演算器命令の発行数、または、実行数の増加に対して前記中央処理装置の冷却能力の増加を大きく、単位時間当たりの主記憶アクセス命令の発行数、または、実行数の増加に対して前記主記憶装置の冷却能力の増加を大きく、単位時間当たりの入出力命令の発行数、または、実行数の増加に対して前記入出力装置の冷却能力の増加を大きくする冷却能力増分を含むことを特徴とする請求項４、または、５記載のコンピュータ。 The control table has a large increase in the cooling capacity of the central processing unit with respect to an increase in the number of operation unit instructions issued per unit time or an increase in the number of executions, and the number of main memory access instructions issued per unit time, or The increase in the cooling capacity of the main storage device with respect to the increase in the number of executions, and the increase in the cooling capacity of the input / output device with respect to the number of I / O commands issued per unit time or the increase in the number of executions. 6. The computer according to claim 4, further comprising an increase in cooling capacity. 第１の論理装置が、１以上の単位時間当たりの第ｉ種の命令の発行数、または、実行数を算出する第ｉの命令数算出手順を含み、冷却制御装置が、１以上の単位時間当たりの前記第ｉ種の命令の発行数、または、実行数に基づいて、第ｉ種の命令の動作により大きく電力を消費する第ｉの論理装置の冷却能力を増大させる制御を行う手順を含むことを特徴とする冷却制御方法。 The first logic unit includes an i-th instruction number calculation procedure for calculating the number of issuances of the i-th type instruction per unit time or the number of executions, and the cooling control unit includes one or more unit times. And a procedure for performing control to increase the cooling capacity of the i-th logic device that consumes a large amount of power due to the operation of the i-type instruction based on the number of issuances or executions of the i-th instruction. A cooling control method characterized by the above. 中央処理装置と、主記憶装置と、入出力装置と、冷却制御装置とを利用し、
前記中央処理装置が、単位時間当たりの演算器命令の発行数、または、実行数を算出する演算器命令算出手順と、単位時間当たりの主記憶アクセス命令の発行数、または、実行数を算出する主記憶アクセス命令算出手順と、単位時間当たりの入出力命令の発行数、または、実行数を算出する入出力命令算出手順とを含み、
前記冷却制御装置が、単位時間当たりの演算器命令の発行数、または、実行数と、単位時間当たりの主記憶アクセス命令の発行数、または、実行数と、単位時間当たりの入出力命令の発行数、または、実行数とに対応する単位時間当たりの冷却能力増分とを含む制御テーブルにしたがって、前記中央処理装置、前記主記憶装置、および、前記入出力装置の冷却を制御する手順を含むことを特徴とする冷却制御方法。 Utilizing a central processing unit, a main storage device, an input / output device, and a cooling control device,
The central processing unit calculates an arithmetic unit instruction calculation procedure for calculating the number of arithmetic unit instructions issued or executed per unit time and the number of main memory access instructions issued or executed per unit time. Including a main memory access instruction calculation procedure and an input / output instruction calculation procedure for calculating the number of I / O instructions issued per unit time or the number of executions,
The cooling control device issues the number of operation unit instructions issued per unit time, or the number of executions, the number of main memory access instructions issued per unit time, or the number of executions, and issuance of input / output instructions per unit time. A procedure for controlling cooling of the central processing unit, the main storage device, and the input / output device according to a control table including a cooling capacity increment per unit time corresponding to the number or the number of executions A cooling control method characterized by the above. 前記演算器命令算出手順が、
演算器命令検出回路に、演算器命令の発行を検出し演算器命令発行検出信号を出力させる手順と、
命令発行数保持回路に、演算器命令発行回数を保持し、演算器命令発行検出信号にしたがい演算器命令発行回数を増加させ、一定時間到達信号により演算器命令発行回数をリセットさせる手順と、
単位時間検出回路に、単位時間値を保持し、毎クロック単位時間値を増加させ、単位時間値が一定の時間に達すると一定時間到達信号を出力させる手順と、
単位時間当たりの命令発行数保持回路に、演算器命令発行回数を保持し、一定時間到達信号にしたがい前記命令発行数保持回路からの演算器命令発行回数を取り込ませる手順とを含むことを特徴とする請求項８記載の冷却制御方法。 The computing unit instruction calculation procedure is:
A procedure for causing the arithmetic unit instruction detection circuit to detect the issuance of an arithmetic unit instruction and to output an arithmetic unit instruction issuance detection signal;
A procedure for holding the number of operation unit instructions issued in the instruction issue number holding circuit, increasing the number of operation unit instructions issued according to the operation unit instruction issue detection signal, and resetting the number of operation unit instructions issued by a fixed time arrival signal;
A procedure for holding a unit time value in the unit time detection circuit, increasing the unit time value for each clock, and outputting a constant time arrival signal when the unit time value reaches a certain time,
A command issue number holding circuit per unit time that holds the number of operation unit command issuance times, and that takes the number of operation unit command issue times from the instruction issue number holding circuit according to a fixed time arrival signal. The cooling control method according to claim 8. 第１の論理装置が、１以上の単位時間当たりの第ｉ種の命令の発行数、または、実行数を算出する第ｉの命令数算出手順を含み、冷却制御装置が、１以上の単位時間当たりの前記第ｉ種の命令の発行数、または、実行数に基づいて、第ｉ種の命令の動作により大きく電力を消費する第ｉの論理装置の冷却能力を増大させる制御を行う手順を電子機器に実行させることを特徴とする冷却制御プログラム。 The first logic unit includes an i-th instruction number calculation procedure for calculating the number of issuances of the i-th type instruction per unit time or the number of executions, and the cooling control unit includes one or more unit times. The procedure for performing control to increase the cooling capacity of the i-th logic device that consumes a large amount of power by the operation of the i-type instruction based on the number of issued or executed i-type instructions per electronic A cooling control program that is executed by a device. 中央処理装置と、主記憶装置と、入出力装置と、冷却制御装置とを利用し、
前記中央処理装置が、単位時間当たりの演算器命令の発行数、または、実行数を算出する演算器命令算出手順と、単位時間当たりの主記憶アクセス命令の発行数、または、実行数を算出する主記憶アクセス命令算出手順と、単位時間当たりの入出力命令の発行数、または、実行数を算出する入出力命令算出手順と、
前記冷却制御装置が、単位時間当たりの演算器命令の発行数、または、実行数と、単位時間当たりの主記憶アクセス命令の発行数、または、実行数と、単位時間当たりの入出力命令の発行数、または、実行数とに対応する単位時間当たりの冷却能力増分とを含む制御テーブルにしたがって、前記中央処理装置、前記主記憶装置、および、前記入出力装置の冷却を制御する手順をコンピュータに実行させることを特徴とする冷却制御プログラム。 Utilizing a central processing unit, a main storage device, an input / output device, and a cooling control device,
The central processing unit calculates an operation unit instruction calculation procedure for calculating the number of operation unit instructions issued or executed per unit time and the number of main memory access instructions issued or executed per unit time. Main memory access instruction calculation procedure, I / O instruction calculation procedure for calculating the number of I / O commands issued per unit time or the number of executions,
The cooling control device issues the number of operation unit instructions issued per unit time, or the number of executions, the number of main memory access instructions issued per unit time, or the number of executions, and issuance of input / output instructions per unit time. A procedure for controlling the cooling of the central processing unit, the main storage device, and the input / output device according to a control table including a cooling capacity increment per unit time corresponding to the number or the number of executions. A cooling control program that is executed. 前記演算器命令算出手順が、
演算器命令検出回路に、演算器命令の発行を検出し演算器命令発行検出信号を出力させる手順と、
命令発行数保持回路に、演算器命令発行回数を保持し、演算器命令発行検出信号にしたがい演算器命令発行回数を増加させ、一定時間到達信号により演算器命令発行回数をリセットさせる手順と、
単位時間検出回路に、単位時間値を保持し、毎クロック単位時間値を増加させ、単位時間値が一定の時間に達すると一定時間到達信号を出力させる手順と、
単位時間当たりの命令発行数保持回路に、演算器命令発行回数を保持し、一定時間到達信号にしたがい前記命令発行数保持回路からの演算器命令発行回数を取り込ませる手順とを含み、上記手順をコンピュータに実行させることを特徴とする請求項１１記載の冷却制御プログラム。
The computing unit instruction calculation procedure is:
A procedure for causing the arithmetic unit instruction detection circuit to detect the issuance of an arithmetic unit instruction and to output an arithmetic unit instruction issuance detection signal;
A procedure for holding the number of operation unit instructions issued in the instruction issue number holding circuit, increasing the number of operation unit instructions issued according to the operation unit instruction issue detection signal, and resetting the number of operation unit instructions issued by a fixed time arrival signal;
A procedure for holding a unit time value in the unit time detection circuit, increasing the unit time value for each clock, and outputting a constant time arrival signal when the unit time value reaches a certain time,
A command issue number holding circuit per unit time is held in the instruction issue number holding circuit, and the instruction issue number is issued from the instruction issue number holding circuit according to a fixed time arrival signal. The cooling control program according to claim 11, which is executed by a computer.
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