JP2006078588A - Liquid crystal display device and driving method of liquid crystal display8 device - Google Patents

Liquid crystal display device and driving method of liquid crystal display8 device Download PDF

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JP2006078588A
JP2006078588A JP2004260009A JP2004260009A JP2006078588A JP 2006078588 A JP2006078588 A JP 2006078588A JP 2004260009 A JP2004260009 A JP 2004260009A JP 2004260009 A JP2004260009 A JP 2004260009A JP 2006078588 A JP2006078588 A JP 2006078588A
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liquid crystal
scanning line
potential
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JP4639702B2 (en
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Tomomi Kamio
知巳 神尾
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Casio Computer Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device whose power consumption is reduced and which does not require a dedicated driver circuit etc., for auxiliary capacity driving and a driving method of the liquid crystal display device as to a liquid crystal display device equipped with a liquid crystal panel where an auxiliary capacitor is driven independently of a common electrode. <P>SOLUTION: In constitution wherein an auxiliary capacitor Cs of a display pixel connected to a scanning line G1 has its other end connected to a scanning line G2 of a trailing stage, the voltage at the common electrode is held at constant level, a TFT 91 turns on when the potential of the scanning line G1 rises to Vgh at time ta1 to apply the voltage of a signal S1 to a liquid crystal capacitor Clc and the auxiliary capacitor Cs, and after the scanning line G1 changes from Vgh to Vgl2 at time ta2 and the TFT 91 turns off, the scanning line G2 connected to the other end of the auxiliary capacitor Cs is changed from Vgl2 to Vgl1 to raise the potential Vpic1 of a pixel electrode, thereby obtaining a desired liquid crystal applied voltage. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明はアクティブマトリクス型ＬＣＤ（Liquid Crystal Display）を用いた液晶表示装置、及び当該液晶表示装置の駆動方法に関する。   The present invention relates to a liquid crystal display device using an active matrix LCD (Liquid Crystal Display) and a driving method of the liquid crystal display device.

液晶を駆動させて画像表示する液晶表示装置が知られている。このような液晶表示装置には、表示パネル上に複数の走査線と複数の信号線とをそれぞれ直交に配置し、各交差点近傍に表示画素を配置するアクティブマトリクス方式のものがある。このアクティブマトリクス型液晶表示装置においては、スイッチング素子（例えばＴＦＴ（Thin Film Transistor：薄膜トランジスタ））を介して信号線に接続される画素電極と、当該画素電極に対向して配置される共通電極との間に液晶が充填されて液晶容量Ｃｌｃが形成され、２つの電極間にて電界が形成されることにより液晶が駆動されるとともに、液晶容量Ｃｌｃの印加電圧を保持する補助容量Ｃｓが液晶容量Ｃｌｃと並列接続されて構成される。   A liquid crystal display device that displays an image by driving a liquid crystal is known. Such a liquid crystal display device includes an active matrix type in which a plurality of scanning lines and a plurality of signal lines are arranged orthogonally on a display panel, and display pixels are arranged in the vicinity of each intersection. In this active matrix type liquid crystal display device, a pixel electrode connected to a signal line via a switching element (for example, a thin film transistor (TFT)) and a common electrode disposed opposite to the pixel electrode A liquid crystal is filled in between to form a liquid crystal capacitor Clc, and an electric field is formed between the two electrodes to drive the liquid crystal, and an auxiliary capacitor Cs that holds the voltage applied to the liquid crystal capacitor Clc is a liquid crystal capacitor Clc. And connected in parallel.

アクティブマトリクス型液晶表示装置は、液晶パネルの構造と駆動方法からＣｓ／Ｖcom一括駆動型、Ｃｓオンゲート型及びＣｓライン別駆動型の３種類に分類される。以下、それぞれの液晶パネルの構造と駆動方法を説明する。 Active matrix liquid crystal display devices are classified into three types: Cs / V com collective drive type, Cs on-gate type, and Cs line-by-line drive type, depending on the structure and driving method of the liquid crystal panel. Hereinafter, the structure and driving method of each liquid crystal panel will be described.

（１）Ｃｓ／Ｖcom一括駆動型
図８（ａ）はＣｓ／Ｖcom一括駆動型の液晶パネルの等価回路を示した図である。Ｃｓ／Ｖcom一括駆動型の液晶パネルは、補助容量の他端が共通電極に接続されて、補助容量が共通電極と同電位に駆動されるものである。図８（ａ）に示すように、行方向に延伸された走査線Ｇ１と列方向に延伸された信号線Ｓ１の交差部にＴＦＴ９１が配置される。ＴＦＴ９１のゲート電極は走査線Ｇ１に接続され、ドレイン電極は信号線Ｓ１に接続される。液晶容量Ｃｌｃの一端はＴＦＴ９１のソース電極に接続され、他端は共通電極Ｖcomに接続される。また補助容量Ｃｓの一端はＴＦＴ９１のソース電極に接続され、他端は走査線Ｇ１と平行して配設されたＣＳ線（補助容量線）９２に接続されて共通電極Ｖcomに接続され、補助容量Ｃｓと共通電極Ｖcomとが一括して駆動される。また、ＴＦＴ９１のゲート−ソース間には寄生容量Ｃｇｓが存在する。 (1) Cs / V com collective drive type FIG. 8A is a diagram showing an equivalent circuit of a Cs / V com collective drive type liquid crystal panel. In the Cs / V com collective drive type liquid crystal panel, the other end of the auxiliary capacitor is connected to the common electrode, and the auxiliary capacitor is driven to the same potential as the common electrode. As shown in FIG. 8A, the TFT 91 is disposed at the intersection of the scanning line G1 extending in the row direction and the signal line S1 extending in the column direction. The gate electrode of the TFT 91 is connected to the scanning line G1, and the drain electrode is connected to the signal line S1. One end of the liquid crystal capacitor Clc is connected to the source electrode of the TFT 91, and the other end is connected to the common electrode Vcom . Also, one end of the auxiliary capacitor Cs is connected to the source electrode of the TFT 91, and the other end is connected to the CS line (auxiliary capacitor line) 92 arranged in parallel with the scanning line G1, and is connected to the common electrode Vcom. The capacitor Cs and the common electrode V com are driven together. Further, a parasitic capacitance Cgs exists between the gate and the source of the TFT 91.

図９はＣｓ／Ｖcom一括駆動型の液晶パネルを備える液晶表示装置の従来の駆動方法における主な信号波形である。ＯＥは階調信号の各信号線への出力を許可するための信号波形、ＧＯＥは走査信号の各走査線への出力を許可するための信号波形である。Ｇ１は走査線Ｇ１の電位、Ｇ２は走査線Ｇ２の電位を示した波形である。走査線Ｇ１の電位は、走査線Ｇ１の選択時はＶgh（ハイレベル）となり、非選択時はＶgl（ロウレベル）となる。走査線Ｇ２も同様である。Ｓ１は信号線Ｓ１の電位を示した波形である。信号線Ｓ１の最高電位はＶshである。 FIG. 9 shows main signal waveforms in a conventional driving method of a liquid crystal display device having a Cs / V com collective driving type liquid crystal panel. OE is a signal waveform for allowing the output of the gradation signal to each signal line, and GOE is a signal waveform for allowing the output of the scanning signal to each scanning line. G1 is a waveform indicating the potential of the scanning line G1, and G2 is a waveform indicating the potential of the scanning line G2. The potential of the scanning line G1 is V gh (high level) when the scanning line G1 is selected, and is V gl (low level) when the scanning line G1 is not selected. The same applies to the scanning line G2. S1 is a waveform showing the potential of the signal line S1. The maximum potential of the signal line S1 is V sh .

Ｖcomは共通電極Ｖcomの電位を示した波形であり、Ｖpic3はＴＦＴ９１のソース電極の電位を示した波形である。ここで、液晶に直流的な電圧を印加しつづけると液晶素子が劣化するため、液晶印加電圧の極性を水平走査毎に反転させるライン反転駆動を行うが、信号線に印加する電圧の振幅を低く抑えるため、水平走査毎に各信号線と共通電極Ｖcomの極性を反転させる反転駆動を行う。共通電極Ｖcomのハイレベルの電圧値をＶcoh、ロウレベルの電圧値をＶcolとする。 V com is a waveform indicating the potential of the common electrode V com , and V pic3 is a waveform indicating the potential of the source electrode of the TFT 91. Here, if a DC voltage is continuously applied to the liquid crystal, the liquid crystal element deteriorates. Therefore, line inversion driving is performed to invert the polarity of the liquid crystal applied voltage every horizontal scanning, but the amplitude of the voltage applied to the signal line is reduced. In order to suppress this, inversion driving is performed to invert the polarity of each signal line and the common electrode V com for each horizontal scanning. The common electrode V com has a high level voltage value V coh and a low level voltage value V col .

時間ｔx1において走査線Ｇ１の電位がＶglからＶghに上がると、ＴＦＴ９１がオン状態となり、信号Ｓ１の電位がＴＦＴ９１を介して液晶容量Ｃｌｃと補助容量Ｃｓに印加される。この時のＶpic3の電圧値をＶsigxとすると、液晶印加電圧Ｖlcdx1は
Ｖlcdx1＝Ｖsigx−Ｖcol
となる。 When the potential of the scanning line G1 rises from V gl to V gh at time t x1 , the TFT 91 is turned on, and the potential of the signal S1 is applied to the liquid crystal capacitor Clc and the auxiliary capacitor Cs via the TFT 91. When a voltage value of V pic3 at this time is V sigx, the liquid crystal application voltage V Lcdx1 the V lcdx1 = V sigx -V col
It becomes.

そして時間ｔx2において走査線Ｇ１の電位がＶghからＶglに下がると、ＴＦＴ９１はオフ状態となる。この時の液晶印加電圧Ｖlcdx2は、寄生容量Ｃｇｓの影響でΔＶx1低下する。
Ｖlcdx2＝Ｖlcdx1−ΔＶx1
但し、ΔＶx1＝（Ｖgh−Ｖgl）×Ｃｇｓ／（Ｃｇｓ＋Ｃｌｃ＋Ｃｓ） When the potential of the scanning line G1 drops from V gh to V gl at time t x2 , the TFT 91 is turned off. At this time, the liquid crystal applied voltage V lcdx2 decreases by ΔV x1 due to the influence of the parasitic capacitance Cgs.
V lcdx2 = V lcdx1 −ΔV x1
Where ΔV x1 = (V gh −V gl ) × Cgs / (Cgs + Clc + Cs)

更に、時間ｔx3において共通電極Ｖcomの電位がＶcolからＶcohに上がると、この時の液晶印加電圧Ｖlcdx3は
Ｖlcdx3＝Ｖlcdx2＋ΔＶx2
但し、ΔＶx2＝（Ｖcoh−Ｖcol）×Ｃｓ／（Ｃｇｓ＋Ｃｌｃ＋Ｃｓ）
となり、以下、液晶容量Ｃｌｃには共通電極Ｖcomがロウレベルの時にＶlcdx2、ハイレベルの時にＶlcdx3の電圧が印加され続け、次の水平走査時まで表示状態が保持される。 Further, when the potential of the common electrode V com rises from V col to V coh at time t x3 , the liquid crystal applied voltage V lcdx3 at this time is V lcdx3 = V lcdx2 + ΔV x2
However, ΔV x2 = (V coh −V col ) × Cs / (Cgs + Clc + Cs)
Next, following, V Lcdx2 when the common electrode V com is at the low level to the liquid crystal capacitance Clc, the voltage of V Lcdx3 continues to be applied when the high level, the display state until the next horizontal scan is retained.

（２）Ｃｓオンゲート型
図８（ｂ）はＣｓオンゲート型の液晶パネルの等価回路を示した図である。以下、（１）Ｃｓ／Ｖcom一括駆動型において説明した構成要素及び信号と同一のものについては、同一の符号を付して説明を省略する。Ｃｓオンゲート型の液晶パネルは、補助容量の他端が次段の走査線に接続されて、補助容量が次段の走査線により駆動されて、共通電極とは別に駆動されるように構成されるものであり、図８（ｂ）に示すように、走査線Ｇ１に接続される表示画素の補助容量Ｃｓの他端が次段の走査線Ｇ２に接続されて、補助容量が次段の走査線Ｇ２により駆動される。これにより、Ｃｓオンゲート型においては、液晶パネル上にＣＳ線（補助容量線）が無いため、液晶パネルの開口率を向上させることができる利点を有する。例えば特許文献１には、Ｃｓオンゲート型の液晶パネルにおけるフリッカを低減するための発明が開示されている。 (2) Cs On-Gate Type FIG. 8B is a diagram showing an equivalent circuit of a Cs on-gate type liquid crystal panel. Hereinafter, the same components and signals as those described in (1) Cs / V com collective drive type will be denoted by the same reference numerals and description thereof will be omitted. The Cs on-gate type liquid crystal panel is configured such that the other end of the auxiliary capacitor is connected to the next-stage scanning line, and the auxiliary capacitor is driven by the next-stage scanning line and driven separately from the common electrode. As shown in FIG. 8B, the other end of the auxiliary capacitor Cs of the display pixel connected to the scanning line G1 is connected to the next-stage scanning line G2, and the auxiliary capacitor is connected to the next-stage scanning line. Driven by G2. Thus, the Cs on-gate type has an advantage that the aperture ratio of the liquid crystal panel can be improved because there is no CS line (auxiliary capacitance line) on the liquid crystal panel. For example, Patent Document 1 discloses an invention for reducing flicker in a Cs on-gate type liquid crystal panel.

図１０はＣｓオンゲート型の液晶パネルを備える液晶表示装置の従来の駆動方法における主な信号波形である。この場合においても、ライン反転駆動を行う際に、信号線に印加する電圧の振幅を低く抑えるため、水平走査毎に各信号線と共通電極Ｖcomの極性を反転させる反転駆動を行う。走査線Ｇ１の電位は走査線Ｇ１の選択時はＶghとなり、非選択時はＶgyとＶglの２電圧間で周期的に変化する。電圧Ｖgl及びＶgyはＴＦＴ９１をオフ状態とする電圧である。 FIG. 10 shows main signal waveforms in a conventional driving method of a liquid crystal display device having a Cs on-gate type liquid crystal panel. Even in this case, in order to keep the amplitude of the voltage applied to the signal line low when performing line inversion driving, inversion driving is performed to invert the polarity of each signal line and the common electrode Vcom every horizontal scanning. The potential of the scanning line G1 becomes V gh when the scanning line G1 is selected, and periodically changes between two voltages V gy and V gl when not selected. The voltages V gl and V gy are voltages that turn off the TFT 91.

時間ｔy1において走査線Ｇ１の電位がＶglからＶghに上がると、ＴＦＴ９１がオン状態となり、信号Ｓ１の電圧がＴＦＴ９１を介して液晶容量Ｃｌｃと補助容量Ｃｓに印加される。この時のＶpic3の電圧値をＶsigyとすると、液晶印加電圧Ｖlcdy1は
Ｖlcdy1＝Ｖsigy−Ｖcol
となる。 When the potential of the scanning line G1 rises from V gl to V gh at time t y1 , the TFT 91 is turned on, and the voltage of the signal S1 is applied to the liquid crystal capacitor Clc and the auxiliary capacitor Cs via the TFT 91. When a voltage value of V pic3 at this time is V sigY, the liquid crystal application voltage V Lcdy1 the V lcdy1 = V sigy -V col
It becomes.

そして時間ｔy2において走査線Ｇ１の電位がＶghからＶglに下がると、ＴＦＴ９１はオフ状態となる。この時の液晶印加電圧Ｖlcdy2は、寄生容量Ｃｇｓの影響でΔＶy1低下する。
Ｖlcdy2＝Ｖlcdy1−ΔＶy1
但し、ΔＶy1＝（Ｖgh−Ｖgl）×Ｃｇｓ／（Ｃｇｓ＋Ｃｌｃ＋Ｃｓ） When the potential of the scanning line G1 drops from V gh to V gl at time t y2 , the TFT 91 is turned off. At this time, the liquid crystal applied voltage V lcdy2 decreases by ΔV y1 due to the influence of the parasitic capacitance Cgs.
V lcdy2 = V lcdy1 -ΔV y1
However, ΔV y1 = (V gh −V gl ) × Cgs / (Cgs + Clc + Cs)

更に、時間ｔy3において共通電極ＶcomがＶcolからＶcohに上がり、走査線Ｇ２の電位がＶglからＶgyに上がると、補助容量Ｃｓの他端の電位が上がる。この時の液晶印加電圧Ｖlcdy3は
Ｖlcdy3＝Ｖlcdy2＋ΔＶy2
但し、ΔＶy2＝（Ｖcoh−Ｖcol）×Ｃｓ／（Ｃｇｓ＋Ｃｌｃ＋Ｃｓ）であり、Ｖgy−Ｖgl＝Ｖcoh−Ｖcolとする。 Further, when the common electrode V com rises from V col to V coh at time t y3 and the potential of the scanning line G2 rises from V gl to V gy , the potential at the other end of the auxiliary capacitor Cs rises. The liquid crystal applied voltage V lcdy3 at this time is V lcdy3 = V lcdy2 + ΔV y2
However, ΔV y2 = (V coh −V col ) × Cs / (Cgs + Clc + Cs), and V gy −V gl = V coh −V col .

続いて、時間ｔy4において走査線Ｇ２の電位がＶgyからＶghに上がると、この時の液晶印加電圧Ｖlcdy4は
Ｖlcdy4＝Ｖlcdy3＋ΔＶy3
但し、ΔＶy3＝（Ｖgh−Ｖgy）×Ｃｓ／（Ｃｇｓ＋Ｃｌｃ＋Ｃｓ）
となる。以下、液晶印加電圧は共通電極Ｖcomがロウレベルの時はＶlcdy2、ハイレベルの時はＶlcdy3となり、次の水平走査時まで表示状態が保持される。 Subsequently, when the potential of the scanning line G2 rises from V gy to V gh at time t y4 , the liquid crystal applied voltage V lcdy4 at this time is V lcdy4 = V lcdy3 + ΔV y3.
However, ΔV y3 = (V gh −V gy ) × Cs / (Cgs + Clc + Cs)
It becomes. Hereinafter, the liquid crystal application voltage is the common electrode V when com is low level V Lcdy2, next V Lcdy3 is at a high level, the display state until the next horizontal scan is retained.

（３）Ｃｓライン別駆動型
図８（ｃ）はＣｓライン別駆動型の液晶パネルの等価回路を示した図である。Ｃｓライン別駆動型の液晶パネルは、補助容量の他端が共通電極に接続されず、補助容量が共通電極とは別に駆動されるものであり、図８（ｃ）に示すように、補助容量Ｃｓの他端が走査線Ｇ１と平行して配設されたＣＳ線（補助容量線）９３に接続され、ＣＳ線９３には専用のＣＳドライバ回路（不図示）によって信号電圧が印加される。例えば特許文献２には、Ｃｓライン別駆動型の液晶パネルにおいて消費電力を削減するために、走査信号が出力された直後、補助容量Ｃｓに印加する信号電圧を変化させる発明が開示されている。 (3) Cs Line Drive Type FIG. 8C is a diagram showing an equivalent circuit of a Cs line drive type liquid crystal panel. In the Cs-line driven type liquid crystal panel, the other end of the auxiliary capacitor is not connected to the common electrode, and the auxiliary capacitor is driven separately from the common electrode. As shown in FIG. The other end of Cs is connected to a CS line (auxiliary capacitance line) 93 disposed in parallel with the scanning line G1, and a signal voltage is applied to the CS line 93 by a dedicated CS driver circuit (not shown). For example, Patent Document 2 discloses an invention in which the signal voltage applied to the auxiliary capacitor Cs is changed immediately after the scanning signal is output in order to reduce the power consumption in the Cs-line driven liquid crystal panel.

図１１はＣｓライン別駆動型の液晶パネルを備える液晶表示装置の従来の駆動方法における主な信号波形である。この場合においては、ライン反転駆動を行う際に、水平走査毎に各信号線の極性を反転させる反転駆動を行うが、共通電極Ｖcomの電圧は一定レベルに設定される。ＣＳ１は、ＣＳ線９３の電位を示す波形である。ＣＳ線９３のハイレベル時の電圧はＶch、ロウレベル時の電圧はＶclとする。ＴＦＴ９１がオン状態からオフ状態に切り替わるタイミングに同期して、液晶容量Ｃｌｃに正極性電圧が印加された時はＣＳ線９３の電位がＶclからＶchに上がり、負極性電圧が印加された時はＶchからＶclに下がるように、専用のＣＳドライバ回路（不図示）からＣＳ線９３に電圧が出力される。 FIG. 11 shows main signal waveforms in a conventional driving method of a liquid crystal display device including a liquid crystal panel driven by Cs lines. In this case, when performing line inversion driving, inversion driving is performed to invert the polarity of each signal line for each horizontal scan, but the voltage of the common electrode Vcom is set to a constant level. CS 1 is a waveform indicating the potential of the CS line 93. The voltage at the high level of the CS line 93 is V ch , and the voltage at the low level is V cl . When the positive polarity voltage is applied to the liquid crystal capacitor Clc in synchronization with the timing when the TFT 91 switches from the on state to the off state, the potential of the CS line 93 rises from V cl to V ch and the negative polarity voltage is applied. A voltage is output from the dedicated CS driver circuit (not shown) to the CS line 93 so that the voltage drops from V ch to V cl .

時間ｔz1において走査線Ｇ１の電位がＶglからＶghに上がると、ＴＦＴ９１がオン状態となり、信号Ｓ１の電位がＴＦＴ９１を介して液晶容量Ｃｌｃと補助容量Ｃｓに印加される。この時の電圧Ｖpic3の電圧値をＶsigzとすると、液晶印加電圧Ｖlcdz1は
Ｖlcdz1＝Ｖsigz−Ｖcom
となる。 When the potential of the scanning line G1 rises from V gl to V gh at time t z1 , the TFT 91 is turned on, and the potential of the signal S1 is applied to the liquid crystal capacitor Clc and the auxiliary capacitor Cs via the TFT 91. When the voltage value of the voltage V pic3 at this time is V sigz, the liquid crystal application voltage V Lcdz1 the V lcdz1 = V sigz -V com
It becomes.

そして時間ｔz2において走査線Ｇ１の電位がＶghからＶglに下がると、ＴＦＴ９１はオフ状態となる。この時の液晶印加電圧Ｖlcdz2は、寄生容量Ｃｇｓの影響でΔＶz1低下する。
Ｖlcdz2＝Ｖlcdz1−ΔＶz1
但し、ΔＶz1＝（Ｖgh−Ｖgl）×Ｃｇｓ／（Ｃｇｓ＋Ｃｌｃ＋Ｃｓ） When the potential of the scanning line G1 drops from V gh to V gl at time t z2 , the TFT 91 is turned off. At this time, the liquid crystal applied voltage V lcdz2 decreases by ΔV z1 due to the influence of the parasitic capacitance Cgs.
V lcdz2 = V lcdz1 -ΔV z1
However, ΔV z1 = (V gh −V gl ) × Cgs / (Cgs + Clc + Cs)

更に、時間ｔz3においてＣＳ線９３の電位がＶclからＶchに上がると、この時の液晶印加電圧Ｖlcdz3は
Ｖlcdz3＝Ｖlcdz2＋ΔＶz2
但し、ΔＶz2＝（Ｖch−Ｖcl）×Ｃｓ／（Ｃｇｓ＋Ｃｌｃ＋Ｃｓ）
となる。以下、液晶容量ＣｌｃにはＶlcdz3の電圧が印加され続け、次の水平走査時まで表示状態が保持される。
特開２００３−１７７７２５号公報 特開２００１−２５５８５１号公報 Further, when the potential of the CS line 93 rises from V cl to V ch at time t z3 , the liquid crystal applied voltage V lcdz3 at this time is V lcdz3 = V lcdz2 + ΔV z2
However, ΔV z2 = (V ch −V cl ) × Cs / (Cgs + Clc + Cs)
It becomes. Hereinafter, the voltage V lcdz3 is continuously applied to the liquid crystal capacitor Clc, and the display state is maintained until the next horizontal scanning.
JP 2003-177725 A JP 2001-255851 A

ところで、上記で説明した従来の各液晶パネルを備えた液晶表示装置には、それぞれ以下のような問題点があった。まず、Ｃｓ／Ｖcom一括駆動型の液晶パネルを備えた液晶表示装置では、共通電極Ｖcomと補助容量Ｃｓにかかる電圧の極性を反転駆動する必要があるため、液晶表示装置の消費電力を低減させることが困難であった。 By the way, the conventional liquid crystal display device provided with each liquid crystal panel described above has the following problems. First, in a liquid crystal display device having a Cs / V com collective drive type liquid crystal panel, it is necessary to invert the polarity of the voltage applied to the common electrode V com and the auxiliary capacitor Cs, thereby reducing the power consumption of the liquid crystal display device. It was difficult to make.

Ｃｓオンゲート型の液晶パネルを備えた液晶表示装置の場合も、共通電極Ｖcomの電圧の極性を反転駆動する必要があり、更に図９に示すように、信号Ｇ２の電圧が周期的に変化して、補助容量Ｃｓにかかる電圧も周期的に変化して、補助容量Ｃｓの充放電に係る無駄な電流が流れるため、液晶パネルの消費電力が増加する問題があった。 Also in the case of a liquid crystal display device having a Cs on-gate type liquid crystal panel, it is necessary to invert the polarity of the voltage of the common electrode V com and, further, as shown in FIG. 9, the voltage of the signal G2 changes periodically. In addition, the voltage applied to the auxiliary capacitor Cs also periodically changes, and a wasteful current related to charging / discharging of the auxiliary capacitor Cs flows, which causes a problem that the power consumption of the liquid crystal panel increases.

また、Ｃｓライン別駆動型の液晶パネルを備えた液晶表示装置の場合には、共通電極Ｖcomを反転駆動する必要がないが、ＣＳ線９３を駆動するための専用のドライバ回路が必要となる。このため、例えばＬＴＰＳ（Low Temperature Poly-Si；低温ポリシリコン）やＣＧＳ（Continuous Grain silicon；ＣＧシリコン結晶）等の液晶パネル上にドライバを構成することのできる製造プロセスであれば実現できる可能性はあるが製造が困難であり、また、アモルファスＴＦＴを用いた液晶パネルを用いる場合は、液晶パネルの外部にＣＳ線とドライバ回路を構成する必要があり、製造コストが増加して、実現が困難であった。 Further, in the case of a liquid crystal display device including a Cs-line driven liquid crystal panel, it is not necessary to invert the common electrode Vcom , but a dedicated driver circuit for driving the CS line 93 is required. . For this reason, there is a possibility that it can be realized if it is a manufacturing process in which a driver can be formed on a liquid crystal panel such as LTPS (Low Temperature Poly-Si) or CGS (Continuous Grain silicon). However, it is difficult to manufacture, and when a liquid crystal panel using amorphous TFTs is used, it is necessary to configure a CS line and a driver circuit outside the liquid crystal panel, which increases the manufacturing cost and is difficult to realize. there were.

本発明は以上の点を考慮してなされたものであり、その目的とするところは、補助容量を共通電極と別駆動する液晶パネルを備える液晶表示装置において、消費電力を低減し、また、補助容量駆動用の専用のドライバ回路等を必要としない液晶表示装置及び液晶表示装置の駆動方法を提供することである。   The present invention has been made in consideration of the above points, and an object of the present invention is to reduce power consumption and assist in a liquid crystal display device including a liquid crystal panel in which an auxiliary capacitor is driven separately from a common electrode. It is an object of the present invention to provide a liquid crystal display device that does not require a dedicated driver circuit or the like for capacitive driving, and a method for driving the liquid crystal display device.

以上の課題を解決するために、請求項１に記載の発明の液晶表示装置は、互いに直交して配置された複数の走査線及び複数の信号線の各交点近傍にマトリクス状に配設され、スイッチング素子と該スイッチング素子の出力端に接続された画素電極と該画素電極に一端が接続された補助容量とを有する複数の表示画素と、前記各画素電極に対向して配設される共通電極と、を有する液晶パネルを備える液晶表示装置において、前記共通電極に一定電圧を印加する共通電圧印加手段と、前記スイッチング素子がオン状態からオフ状態になった後に、前記補助容量の他端に所定の電圧を印加して、前記画素電極と前記共通電極との電位差の絶対値を増加させる電圧印加手段と、を備えることを特徴とする。   In order to solve the above problems, the liquid crystal display device according to the first aspect of the present invention is arranged in a matrix in the vicinity of intersections of a plurality of scanning lines and a plurality of signal lines arranged orthogonal to each other. A plurality of display pixels having a switching element, a pixel electrode connected to the output terminal of the switching element, and an auxiliary capacitor having one end connected to the pixel electrode, and a common electrode disposed to face each pixel electrode A common voltage applying means for applying a constant voltage to the common electrode, and a predetermined voltage is applied to the other end of the auxiliary capacitor after the switching element is turned off. Voltage applying means for increasing the absolute value of the potential difference between the pixel electrode and the common electrode.

請求項２に記載の発明は、請求項１に記載の液晶表示装置において、前記各走査線は前段の前記補助容量の他端に接続され、前記電圧印加手段は、前記複数の走査線を順次走査するための走査信号を出力するとともに、前段の前記補助容量の他端に前記所定の電圧を印加することを特徴とする。   According to a second aspect of the present invention, in the liquid crystal display device according to the first aspect, each of the scanning lines is connected to the other end of the auxiliary capacitor in the previous stage, and the voltage applying unit sequentially connects the plurality of scanning lines. A scanning signal for scanning is output, and the predetermined voltage is applied to the other end of the auxiliary capacitor in the previous stage.

請求項３に記載の発明は、請求項１または２に記載の液晶表示装置において、前記各走査線に接続される前記表示画素の画素電極の前記共通電極に対する電位差の極性は、前記各走査線毎に逆極性に設定され、前記電圧印加手段は、前記電位差の極性が正極性に設定される走査線に接続される前記表示画素の、前記補助容量の他端の電位を上昇させ、前記電位差の極性が負極性に設定される走査線に接続される前記表示画素の、前記補助容量の他端の電位を低下させることを特徴とする。   According to a third aspect of the present invention, in the liquid crystal display device according to the first or second aspect, the polarity of the potential difference with respect to the common electrode of the pixel electrode of the display pixel connected to each of the scanning lines is set to each of the scanning lines. The voltage application means increases the potential of the other end of the auxiliary capacitor of the display pixel connected to the scanning line in which the polarity of the potential difference is set to a positive polarity. The potential of the other end of the auxiliary capacitor of the display pixel connected to the scanning line whose polarity is set to be negative is reduced.

請求項４に記載の発明は、請求項１に記載の液晶表示装置において、前記電圧印加手段による前記補助容量の他端への所定の電圧の印加は、当該走査線に接続される前記表示画素の前記スイッチング素子がオフ状態になった後、次段の走査線に接続される前記表示画素の前記スイッチング素子がオン状態となるまでの間に行われることを特徴とする。   According to a fourth aspect of the present invention, in the liquid crystal display device according to the first aspect, the application of a predetermined voltage to the other end of the auxiliary capacitor by the voltage applying unit is the display pixel connected to the scanning line. This is performed after the switching element is turned off and before the switching element of the display pixel connected to the next scanning line is turned on.

請求項５に記載の発明は、請求項１に記載の液晶表示装置において、前記電圧印加手段による前記補助容量の他端への所定の電圧の印加は、次段の走査線に接続される前記表示画素の前記スイッチング素子がオン状態となるタイミングで行われることを特徴とする。   According to a fifth aspect of the present invention, in the liquid crystal display device according to the first aspect, the application of the predetermined voltage to the other end of the auxiliary capacitor by the voltage applying unit is connected to the next scanning line. It is performed at a timing when the switching element of the display pixel is turned on.

請求項６に記載の発明は、請求項５に記載の液晶表示装置において、前記各走査線に接続される前記表示画素の画素電極の前記共通電極に対する電位差の極性は、前記各走査線毎に逆極性に設定され、前記電圧印加手段は、次段の走査線に接続される前記表示画素の前記スイッチング素子がオン状態となるタイミングにおいて、前記電位差の極性が正極性に設定される前記走査線に接続される前記表示画素の、前記補助容量の他端の電位を第１の電位に設定し、前記電位差の極性が負極性に設定される走査線に接続される前記表示画素の、前記補助容量の他端の電位を、前記第１の電位より低い第２の電位に設定することを特徴とする。   According to a sixth aspect of the present invention, in the liquid crystal display device according to the fifth aspect, the polarity of the potential difference with respect to the common electrode of the pixel electrode of the display pixel connected to each of the scanning lines is different for each of the scanning lines. The scanning line in which the polarity of the potential difference is set to a positive polarity at a timing when the switching element of the display pixel connected to the next scanning line is turned on is set to a reverse polarity. The auxiliary pixel of the display pixel connected to a scanning line in which the potential of the other end of the auxiliary capacitor of the display pixel connected to the first potential is set to a first potential and the polarity of the potential difference is set to a negative polarity is set. A potential of the other end of the capacitor is set to a second potential lower than the first potential.

請求項７に記載の発明は、請求項６に記載の液晶表示装置において、前記電圧印加手段は、前記各走査線間に設けられ、出力端子が当該走査線に接続される前記表示画素の前記補助容量の他端に共通接続され、制御端子が当該走査線に接続され入力端子の電位が前記第１の電位及び前記第２の電位の一方に接続される第１のスイッチング素子と、制御端子が次段の走査線に接続され入力端子の電位が前記第１の電位及び前記第２の電位の他方に接続される第２のスイッチング素子と、を有し、前記電位差の極性が正極性に設定される走査線に接続される前記表示画素において、当該走査線に接続される前記表示画素の前記スイッチング素子がオン状態となるタイミングで、前記第１のスイッチング素子を介して当該表示画素の補助容量の他端の電位を前記第２の電位に設定し、次段の走査線に接続される前記表示画素の前記スイッチング素子がオン状態となるタイミングで、前記第２のスイッチング素子を介して当該表示画素の補助容量の他端の電位を前記第１の電位に設定し、前記電位差の極性が負極性に設定される走査線に接続される前記表示画素において、当該走査線に接続される前記表示画素の前記スイッチング素子がオン状態となるタイミングで、前記第１のスイッチング素子を介して当該表示画素の補助容量の他端の電位を前記第１の電位に設定し、次段の走査線に接続される前記表示画素の前記スイッチング素子がオン状態となるタイミングで、前記第２のスイッチング素子を介して当該表示画素の補助容量の他端の電位を前記第２の電位に設定することを特徴とする。   According to a seventh aspect of the invention, in the liquid crystal display device according to the sixth aspect of the invention, the voltage applying unit is provided between the scanning lines, and the output terminal of the display pixel is connected to the scanning line. A first switching element commonly connected to the other end of the auxiliary capacitor, a control terminal connected to the scanning line, and a potential of the input terminal connected to one of the first potential and the second potential; and a control terminal Is connected to the next-stage scanning line and the potential of the input terminal is connected to the other of the first potential and the second potential, and the polarity of the potential difference is positive In the display pixel connected to the scanning line to be set, the display pixel is assisted through the first switching element at a timing when the switching element of the display pixel connected to the scanning line is turned on. The other end of the capacity An auxiliary capacitance of the display pixel is set via the second switching element at a timing when the potential is set to the second potential and the switching element of the display pixel connected to the next scanning line is turned on. In the display pixel connected to the scanning line in which the potential of the other end of the pixel is set to the first potential and the polarity of the potential difference is set to negative polarity, the switching of the display pixel connected to the scanning line is performed. At the timing when the element is turned on, the potential of the other end of the auxiliary capacitor of the display pixel is set to the first potential via the first switching element, and the display connected to the next scanning line A potential of the other end of the auxiliary capacitor of the display pixel is set to the second potential via the second switching element at a timing when the switching element of the pixel is turned on. .

請求項８に記載の発明の液晶表示装置の駆動方法は、互いに直交して配置された複数の走査線及び複数の信号線の各交点近傍にマトリクス状に配設され、スイッチング素子と該スイッチング素子の出力端に接続された画素電極と該画素電極に一端が接続された補助容量とを有する複数の表示画素と、前記各画素電極に対向して配設される共通電極と、を有する液晶パネルを備える液晶表示装置を駆動する駆動方法であって、前記共通電極に一定電圧を印加する動作と、前記走査線を選択して、選択された走査線に接続される前記表示画素の前記スイッチング素子をオン状態として前記画素電極を表示信号に基づく電位とする動作と、前記走査線を非選択として、前記スイッチング素子をオン状態からオフ状態にした後、前記補助容量の他端に所定の電圧を印加して、前記画素電極と前記共通電極との電位差の絶対値を増加させる動作と、を含むことを特徴とする。   According to an eighth aspect of the present invention, there is provided a driving method for a liquid crystal display device, wherein the switching element and the switching element are arranged in a matrix in the vicinity of intersections of a plurality of scanning lines and a plurality of signal lines arranged orthogonal to each other. A plurality of display pixels each having a pixel electrode connected to an output terminal of the pixel, an auxiliary capacitor having one end connected to the pixel electrode, and a common electrode disposed opposite to the pixel electrodes. A driving method for driving a liquid crystal display device comprising: an operation of applying a constant voltage to the common electrode; and the switching element of the display pixel that is connected to the selected scanning line by selecting the scanning line And turning on the switching element from the on state to the other end of the auxiliary capacitor after the operation of setting the pixel electrode to a potential based on a display signal and turning off the scanning line. By applying a constant voltage, characterized in that it comprises a, the operation for increasing the absolute value of the potential difference between the common electrode and the pixel electrode.

請求項９に記載の発明は、請求項８に記載の液晶表示装置の駆動方法において、前記各走査線に接続される前記表示画素の画素電極の前記共通電極に対する電位差の極性は、前記各走査線毎に逆極性に設定され、前記補助容量の他端に前記所定の電圧を印加する動作は、前記電位差の極性が正極性に設定される走査線に接続される前記表示画素の、前記補助容量の他端の電位を上昇させ、前記電位差の極性が負極性に設定される走査線に接続される前記表示画素の、前記補助容量の他端の電位を低下させる動作を含むことを特徴とする。   According to a ninth aspect of the present invention, in the method for driving a liquid crystal display device according to the eighth aspect, the polarity of the potential difference with respect to the common electrode of the pixel electrode of the display pixel connected to each of the scanning lines is different for each scanning. The operation of applying the predetermined voltage to the other end of the auxiliary capacitor is set to the reverse polarity for each line, and the operation of applying the auxiliary voltage to the display pixel connected to the scanning line in which the polarity of the potential difference is set to positive polarity And an operation of increasing the potential of the other end of the capacitor and decreasing the potential of the other end of the auxiliary capacitor of the display pixel connected to the scanning line in which the polarity of the potential difference is set to a negative polarity. To do.

請求項１０に記載の発明は、請求項８に記載の液晶表示装置の駆動方法において、前記補助容量の他端に前記所定の電圧を印加する動作は、当該走査線が非選択とされた後、次段の走査線が選択されるまでの間のタイミングで行われることを特徴とする。   According to a tenth aspect of the present invention, in the driving method of the liquid crystal display device according to the eighth aspect, the operation of applying the predetermined voltage to the other end of the auxiliary capacitor is performed after the scanning line is not selected. This is characterized in that it is performed at a timing until the next scanning line is selected.

請求項１１に記載の発明は、請求項８に記載の液晶表示装置の駆動方法において、前記補助容量の他端に前記所定の電圧を印加する動作は、次段の走査線が選択されるタイミングで行われることを特徴とする。   According to an eleventh aspect of the present invention, in the driving method of the liquid crystal display device according to the eighth aspect, the operation of applying the predetermined voltage to the other end of the auxiliary capacitor is a timing at which the next scanning line is selected. It is performed by.

請求項１２に記載の発明は、請求項１１に記載の液晶表示装置の駆動方法において、前記各走査線に接続される前記表示画素の画素電極の前記共通電極に対する電位差の極性は、前記各走査線毎に逆極性に設定され、前記補助容量の他端に前記所定の電圧を印加する動作は、前記電位差の極性が正極性に設定される走査線に接続される前記表示画素の、前記補助容量の他端を第１の電位に設定し、前記電位差の極性が負極性に設定される走査線に接続される前記表示画素の、前記補助容量の他端を、前記第１の電位より低い第２の電位に設定する動作を含むことを特徴とする。   According to a twelfth aspect of the invention, in the driving method of the liquid crystal display device according to the eleventh aspect, the polarity of the potential difference with respect to the common electrode of the pixel electrode of the display pixel connected to each of the scanning lines is set to each of the scanning. The operation of applying the predetermined voltage to the other end of the auxiliary capacitor is set to the reverse polarity for each line, and the operation of applying the auxiliary voltage to the display pixel connected to the scanning line in which the polarity of the potential difference is set to positive polarity The other end of the capacitor is set to a first potential, and the other end of the auxiliary capacitor of the display pixel connected to the scanning line in which the polarity of the potential difference is set to a negative polarity is lower than the first potential. It includes an operation of setting the second potential.

本発明によれば、補助容量を共通電極と別駆動する液晶パネルを備える液晶表示装置において、表示画素のスイッチング素子がオフ状態とされた後、補助容量の他端に所定の電圧が印加されることにより、液晶印加電圧を増加させて、所望の液晶印加電圧を得ることができるため、共通電極の電圧を一定レベルとして、共通電極の反転駆動を行う必要がなく、且つ信号線の信号の電圧振幅を大きくする必要もない。これにより、液晶表示装置の消費電力を削減することができる。また、補助容量駆動用の専用のドライバ回路を必要としないため、アモルファスＴＦＴを用いた液晶パネルにおいても実現することができる。   According to the present invention, in a liquid crystal display device including a liquid crystal panel that drives the auxiliary capacitor separately from the common electrode, a predetermined voltage is applied to the other end of the auxiliary capacitor after the switching element of the display pixel is turned off. As a result, the liquid crystal applied voltage can be increased to obtain a desired liquid crystal applied voltage. Therefore, it is not necessary to drive the common electrode at a constant level and to invert the common electrode, and the signal voltage of the signal line There is no need to increase the amplitude. Thereby, the power consumption of the liquid crystal display device can be reduced. Further, since a dedicated driver circuit for driving the auxiliary capacitor is not required, it can be realized also in a liquid crystal panel using an amorphous TFT.

〔第１の実施の形態〕
以下、本発明の第１の実施の形態を図示例と共に説明する。本第１の実施の形態は、Ｃｓオンゲート型の液晶パネルに対して、共通電極Ｖcomの反転駆動を行わず、共通電極Ｖcomの電圧は一定レベルとし、走査線を３つの電圧レベル（Ｖgh、Ｖgl1、Ｖgl2）によって駆動することを特徴とする。 [First Embodiment]
Hereinafter, a first embodiment of the present invention will be described together with illustrated examples. First Embodiment book for Cs-on-gate type liquid crystal panel, without inversion driving of the common electrode V com, the common electrode V voltage com is a constant level, the scanning line three voltage levels (V gh , Vgl1 , Vgl2 ).

図１は、第１の実施の形態における液晶表示装置１の回路構成の一例を示す図である。液晶表示装置１は、液晶パネル１１、ソースドライバ回路１２、反転ＲＧＢ発生回路１３、ゲートドライバ回路１４、Ｖｃｏｍ発生回路１５、ＴＧ部ドライバ制御回路１６及び電圧発生回路１７等によって構成される。   FIG. 1 is a diagram illustrating an example of a circuit configuration of the liquid crystal display device 1 according to the first embodiment. The liquid crystal display device 1 includes a liquid crystal panel 11, a source driver circuit 12, an inverted RGB generation circuit 13, a gate driver circuit 14, a Vcom generation circuit 15, a TG unit driver control circuit 16, a voltage generation circuit 17, and the like.

液晶パネル１１は、Ｃｓオンゲート型であって、前述の図８（ｂ）に示した構成と同様の構成を有し、複数の走査線と複数の信号線とが直交に配置され、走査線と信号線の各交差部にそれぞれ表示画素が形成されている。尚、各走査線はゲートドライバ回路１４に接続され、各信号線はソースドライバ回路１２に接続される。   The liquid crystal panel 11 is a Cs on-gate type, and has the same configuration as that shown in FIG. 8B described above, and a plurality of scanning lines and a plurality of signal lines are arranged orthogonally, A display pixel is formed at each intersection of the signal lines. Each scanning line is connected to the gate driver circuit 14, and each signal line is connected to the source driver circuit 12.

ソースドライバ回路１２は、反転ＲＧＢ発生回路１３から入力される階調信号を各信号線に対応付けて保持するためのデータラッチ回路（不図示）と、そのラッチされた階調信号に基づく信号電圧を生成して、各信号線に印加するドライバ回路（不図示）を有し、ＴＧ部ドライバ制御回路１６から入力される水平制御信号に基づいて各信号線に対して信号電圧を印加する。更にＴＧ部ドライバ制御回路１６から信号ＯＥが入力される。信号ＯＥは階調信号がソースドライバ回路１２から液晶パネル１１に対しての出力を許可するための信号である。   The source driver circuit 12 includes a data latch circuit (not shown) for holding the gradation signal input from the inverted RGB generation circuit 13 in association with each signal line, and a signal voltage based on the latched gradation signal. Is generated and applied to each signal line, and a signal voltage is applied to each signal line based on a horizontal control signal input from the TG driver control circuit 16. Further, the signal OE is input from the TG unit driver control circuit 16. The signal OE is a signal for allowing the gradation signal to be output from the source driver circuit 12 to the liquid crystal panel 11.

反転ＲＧＢ発生回路１３は、ＴＧ部ドライバ制御回路１６から入力される反転制御信号に応答して外部入力される映像信号に含まれるＲＧＢの各階調信号を反転させて反転ＲＧＢ信号（表示信号）を生成し、ソースドライバ回路１２に出力する。   The inversion RGB generation circuit 13 inverts the RGB gradation signals included in the video signal input in response to the inversion control signal input from the TG driver control circuit 16 to generate an inversion RGB signal (display signal). Generate and output to the source driver circuit 12.

ゲートドライバ回路１４は、ＴＧ部ドライバ制御回路１６から入力される垂直制御信号に基づいて走査電圧を生成し、液晶パネル１１の各走査線に順次走査電圧を印加する。更にＴＧ部ドライバ制御回路１６から信号ＧＯＥが入力される。信号ＧＯＥは走査信号がゲートドライバ回路１４から液晶パネル１１に対しての出力を許可するための信号である。   The gate driver circuit 14 generates a scanning voltage based on the vertical control signal input from the TG unit driver control circuit 16 and sequentially applies the scanning voltage to each scanning line of the liquid crystal panel 11. Further, a signal GOE is input from the TG unit driver control circuit 16. The signal GOE is a signal for allowing the scanning signal to be output from the gate driver circuit 14 to the liquid crystal panel 11.

Ｖｃｏｍ発生回路１５は、ＴＧ部ドライバ制御回路から入力される電圧制御信号に応答して、共通電極Ｖcomに印加する電圧を生成する。本実施形態においては、共通電極Ｖcomに印加する電圧は一定レベルに設定される。 The Vcom generation circuit 15 generates a voltage to be applied to the common electrode Vcom in response to a voltage control signal input from the TG unit driver control circuit. In the present embodiment, the voltage applied to the common electrode Vcom is set to a certain level.

ＴＧ部ドライバ制御回路１６は、液晶表示装置１の全体を制御する。例えば外部入力される同期信号に基づいて、液晶パネル１１の各画素の液晶を駆動する水平制御信号及び垂直制御信号、信号ＯＥ及び信号ＧＯＥを生成し、ソースドライバ回路１２やゲートドライバ回路１４に出力する。また、同期信号に基づいて、ＲＧＢの各階調信号を反転させるための反転制御信号を生成して反転ＲＧＢ発生回路１３に出力する。更に電圧制御信号を生成してＶｃｏｍ発生回路１５に出力する。   The TG unit driver control circuit 16 controls the entire liquid crystal display device 1. For example, a horizontal control signal and a vertical control signal for driving the liquid crystal of each pixel of the liquid crystal panel 11, a signal OE, and a signal GOE are generated based on an externally input synchronization signal, and output to the source driver circuit 12 and the gate driver circuit 14. To do. Further, based on the synchronization signal, an inversion control signal for inverting the RGB gradation signals is generated and output to the inversion RGB generation circuit 13. Further, a voltage control signal is generated and output to the Vcom generation circuit 15.

電圧発生回路１７は、液晶表示装置１を備える装置の電源投入に応答して入力される電源入力信号に基づいて、液晶表示装置１を構成する各回路部に必要な電圧を生成して出力する。例えば、内部電源Ｖcc、信号線を駆動するための電圧Ｖsh、走査線を駆動するための電圧Ｖgh、Ｖgl1及びＶgl2等を生成して出力する。そしてソースドライバ回路１２にはＶcc及びＶshの電圧が入力され、ゲートドライバ回路１４にはＶcc、Ｖgh、Ｖgl1及びＶgl2の電圧が入力される。 The voltage generation circuit 17 generates and outputs a necessary voltage to each circuit unit constituting the liquid crystal display device 1 based on a power input signal input in response to power-on of the device including the liquid crystal display device 1. . For example, the internal power supply V cc , the voltage V sh for driving the signal line, the voltages V gh , V gl1 and V gl2 for driving the scanning line are generated and output. And the source driver circuit 12 is input voltage of V cc and V sh, V cc to the gate driver circuit 14, V gh, voltage V gl1 and V gl2 are input.

次に、図２及び図３に示す信号波形を用いて、本実施の形態の液晶表示装置１の回路動作を（Ａ）正極性電圧印加時と（Ｂ）負極性電圧印加時のそれぞれについて説明する。尚、これはライン反転駆動を行う場合において、隣接する走査線での動作に対応する。   Next, using the signal waveforms shown in FIGS. 2 and 3, the circuit operation of the liquid crystal display device 1 of the present embodiment will be described for each of (A) when a positive voltage is applied and (B) when a negative voltage is applied. To do. Note that this corresponds to an operation on an adjacent scanning line when line inversion driving is performed.

（Ａ）正極性電圧印加時
図２は液晶容量Ｃｌｃに対して正極性電圧が印加されるときの液晶表示装置１の本実施形態の駆動方法における主な信号波形である。背景技術において図９〜１１を用いて説明した信号波形と同一の内容の信号波形については説明を省略または簡略化する。ここで、走査線Ｇ１、Ｇ２は隣接する走査線である。走査線Ｇ１及びＧ２の電位はそれぞれの選択時はＶghとなり、非選択時にはＶgl1またはＶgl2となる。Ｖgl1及びＶgl2は、ＴＦＴ９１をオフ状態とする電圧である。また共通電極Ｖcomには一定レベルの電圧が印加され、Ｖpic1は走査線Ｇ１に接続される表示画素のＴＦＴ９１のソース電極の電位を示す。 (A) When Positive Voltage is Applied FIG. 2 shows main signal waveforms in the driving method of the present embodiment of the liquid crystal display device 1 when a positive voltage is applied to the liquid crystal capacitance Clc. The description of the signal waveforms having the same contents as those described in the background art with reference to FIGS. 9 to 11 is omitted or simplified. Here, the scanning lines G1 and G2 are adjacent scanning lines. The potentials of the scanning lines G1 and G2 are V gh when selected, and V gl1 or V gl2 when not selected. V gl1 and V gl2 are voltages that turn the TFT 91 off. Also the common electrode V com is applied a constant level of voltage, V pic1 indicates the potential of the TFT91 source electrodes of the display pixels connected to the scan line G1.

時間ｔa1において走査線Ｇ１の電位がＶghに上がると、ＴＦＴ９１がオン状態となり、信号Ｓ１の電圧がＴＦＴ９１を介して液晶容量Ｃｌｃと補助容量Ｃｓに印加される。この時のＴＦＴ９１のソース電極の電圧Ｖpic1をＶsigaとすると、液晶印加電圧Ｖlcda1は
Ｖlcda1＝Ｖsiga−Ｖcom
となる。 When the potential of the scan line G1 goes up V gh at time t a1, TFT 91 is turned on, the voltage of the signal S1 is applied and to the storage capacitor Cs liquid crystal capacitor Clc through the TFT 91. If the voltage V pic1 of the source electrode of the TFT 91 at this time is V siga , the liquid crystal applied voltage V lcda1 is V lcda1 = V siga −V com
It becomes.

そして時間ｔa2において走査線Ｇ１の電位がＶghからＶgl2に下がると、ＴＦＴ９１はオフ状態となる。この時の液晶印加電圧Ｖlcda2は、寄生容量Ｃｇｓの影響でΔＶa1低下する。
Ｖlcda2＝Ｖlcda1−ΔＶa1
但し、ΔＶa1＝（Ｖgh−Ｖgl2）×Ｃｇｓ／（Ｃｇｓ＋Ｃｌｃ＋Ｃｓ） When the potential of the scanning line G1 falls from V gh to V gl2 at time t a2 , the TFT 91 is turned off. At this time, the liquid crystal applied voltage V lcda2 decreases by ΔV a1 due to the influence of the parasitic capacitance Cgs.
V lcda2 = V lcda1 -ΔV a1
However, ΔV a1 = (V gh −V gl2 ) × Cgs / (Cgs + Clc + Cs)

更に、時間ｔa3において走査線Ｇ２の電位がＶgl2からＶgl1に上がると、補助容量Ｃｓの他端の電位が上がり、Ｖpic1の電位も上がる。この時の液晶印加電圧Ｖlcda3は、
Ｖlcda3＝Ｖlcda2＋ΔＶa2
但し、ΔＶa2＝（Ｖgl1−Ｖgl2）×Ｃｓ／（Ｃｇｓ＋Ｃｌｃ＋Ｃｓ）
・・・（１）
となる。この状態では、走査線Ｇ２は非選択状態であり、走査線Ｇ２に接続されている次段のＴＦＴはオフ状態である。 Further, when the potential of the scanning line G2 rises from V gl2 to V gl1 at time t a3 , the potential of the other end of the auxiliary capacitor Cs rises and the potential of V pic1 also rises. The liquid crystal applied voltage V lcda3 at this time is
V lcda3 = V lcda2 + ΔV a2
However, ΔV a2 = (V gl1 −V gl2 ) × Cs / (Cgs + Clc + Cs)
... (1)
It becomes. In this state, the scanning line G2 is in a non-selected state, and the next stage TFT connected to the scanning line G2 is in an OFF state.

次に時間ｔａ４において、走査線Ｇ２が選択されるべく走査線Ｇ２の電位がＶgl1からＶghに上がると、この時の液晶印加電圧Ｖlcda4は、
Ｖlcda4＝Ｖlcda3＋ΔＶa3
但し、ΔＶa3＝（Ｖgh−Ｖgl1）×Ｃｓ／（Ｃｇｓ＋Ｃｌｃ＋Ｃｓ）
となる。続いて、走査線Ｇ２が非選択となるべく走査線Ｇ２の電位がＶghからＶgl1に下がると、Ｖpic1の電位がΔＶa3低下して、液晶印加電圧はＶlcda3となる。以下、液晶容量ＣｌｃにはＶlcda3の電圧が印加され続け、次の水平走査時まで表示状態が保持される。 Next, when the potential of the scanning line G2 rises from V gl1 to V gh so that the scanning line G2 is selected at time ta4, the liquid crystal applied voltage V lcda4 at this time is
V lcda4 = V lcda3 + ΔV a3
However, ΔV a3 = (V gh −V gl1 ) × Cs / (Cgs + Clc + Cs)
It becomes. Subsequently, when the potential of the scanning line G2 is lowered from V gh to V gl1 so that the scanning line G2 is not selected, the potential of V pic1 decreases by ΔV a3 and the liquid crystal applied voltage becomes V lcda3 . Thereafter, the voltage V lcda3 is continuously applied to the liquid crystal capacitor Clc, and the display state is maintained until the next horizontal scanning.

つまり、時間ｔa2においてＴＦＴ９１がオフ状態となった後、時間ｔa3において補助容量Ｃｓの他端が接続されている走査線Ｇ２の電位をＶgl2からＶgl1に上げることにより、走査線Ｇ２に接続されている次段のＴＦＴはオフ状態のまま、Ｖpic1の電位をΔＶa2だけ上げることができる。これにより、共通電極Ｖcomの反転駆動を行わず、その電圧を一定レベルに設定し、且つ、信号線に印加する電圧の振幅を、前述の図１０に示したような、従来の、共通電極Ｖcomの極性を反転駆動する場合の信号線の電圧振幅と同程度としたままで、液晶印加電圧を大きくして、所望の液晶印加電圧を得ることができる。ΔＶa2はＣｓ／（Ｃｇｓ＋Ｃｌｃ＋Ｃｓ）の比率によって決定される。 That is, after the TFT91 is turned off at time t a2, by raising the potential of the time t scan line and the other end of the auxiliary capacitor Cs are connected in a3 G2 from V gl2 the V gl1, the scanning line G2 next stage of the TFT is connected may be increased remains off, the potential of V pic1 only [Delta] V a2. As a result, the common electrode V com is not inverted and driven, the voltage is set to a constant level, and the amplitude of the voltage applied to the signal line is the same as that shown in FIG. The desired liquid crystal applied voltage can be obtained by increasing the liquid crystal applied voltage while maintaining the same amplitude as the voltage amplitude of the signal line when the polarity of V com is inverted and driven. ΔV a2 is determined by the ratio of Cs / (Cgs + Clc + Cs).

ここで各信号電圧の具体的な電圧値について一例を挙げて説明する。液晶印加電圧Ｖlcdaは、厳密には電圧Ｖpic1の各電圧値Ｖlcda1、Ｖlcda2、Ｖlcda3及びＶlcda4の平均値となるが、Ｖpic1の電圧はＶlcda3である時間が圧倒的に長く、液晶の応答性等の点から考慮して、実質的にＶlcda＝Ｖlcda3として考える。 Here, a specific voltage value of each signal voltage will be described with an example. Liquid crystal applied voltage V LCDA is strictly becomes the average value of voltage values V lcda1, V lcda2, V lcda3 and V Lcda4 voltage V pic1, voltage V pic1 is overwhelmingly time is V Lcda3 longer Considering from the viewpoint of the response of the liquid crystal, etc., it is substantially considered as V lcda = V lcda3 .

例えば、液晶パネルにおいて良好な表示を得るために、最大液晶印加電圧Ｖlcda＝５［Ｖ］必要であって共通電極Ｖcomの電位に対して信号Ｓ１の振幅が最大±２Ｖである場合、液晶印加電圧Ｖlcdaを更に３［Ｖ］上げる必要がある。そこでＣｇｓ＜＜ＣｓとしてＶsiga＝２［Ｖ］、ΔＶa2＝３［Ｖ］とすると、Ｃｓ／（Ｃｇｓ＋Ｃｌｃ＋Ｃｓ）＝１／２とすれば、式（１）よりＶgl1−Ｖgl2＝６［Ｖ］となる。即ち、Ｖgh＝１２［Ｖ］、Ｖgl1＝−１２［Ｖ］とする場合、Ｖgl2＝−１８［Ｖ］と設定すればよい。 For example, in order to obtain a good display in the liquid crystal panel, the maximum liquid crystal applied voltage V lcda = 5 [V] is required, and when the amplitude of the signal S1 is ± 2 V at the maximum with respect to the potential of the common electrode V com , It is necessary to further increase the applied voltage V lcda by 3 [V]. Therefore, when Css << Cs and V siga = 2 [V] and ΔV a2 = 3 [V], if Cs / (Cgs + Clc + Cs) = ½ , V gl1 −V gl2 = 6 [6] V]. That is, when V gh = 12 [V] and V gl1 = −12 [V], V gl2 = −18 [V] may be set.

（Ｂ）負極性電圧印加時
図３は液晶容量Ｃｌｃに対して負極性電圧が印加されるときの液晶表示装置１の本実施形態の駆動方法における主な信号波形である。尚、前述の（Ａ）正極性電圧印加時において図２を用いて説明した信号波形と同一の部分については説明を省略または簡略化する。ここで、図３における走査線Ｇ２は図２に示した走査線Ｇ２に対応し、走査線Ｇ２、Ｇ３は隣接する走査線である。また、同図におけるＶpic1は、走査線Ｇ２に接続される表示画素のＴＦＴ９１のソース電極の電位を示す。 (B) When negative polarity voltage is applied FIG. 3 shows main signal waveforms in the driving method of the present embodiment of the liquid crystal display device 1 when a negative polarity voltage is applied to the liquid crystal capacitance Clc. The description of the same part as the signal waveform described with reference to FIG. 2 when the above-described (A) positive polarity voltage is applied will be omitted or simplified. Here, the scanning line G2 in FIG. 3 corresponds to the scanning line G2 shown in FIG. 2, and the scanning lines G2 and G3 are adjacent scanning lines. Also, V pic1 in the figure shows the potential of the source electrode of the TFT91 of display pixels connected to the scanning line G2.

時間ｔb1において走査線Ｇ２の電位がＶghに上がると、ＴＦＴ９１がオン状態となり、信号Ｓ１の電圧がＴＦＴ９１を介して液晶容量Ｃｌｃと補助容量Ｃｓに印加される。この時のＶpic1の電圧をＶsigbとすると、液晶印加電圧Ｖlcdb1は
Ｖlcdb1＝Ｖsigb−Ｖcom
となる。 When the potential of the scanning line G2 rises V gh at time t b1, TFT 91 is turned on, the voltage of the signal S1 is applied and to the storage capacitor Cs liquid crystal capacitor Clc through the TFT 91. If the voltage of V pic1 at this time is V sigb , the liquid crystal applied voltage V lcdb1 is V lcdb1 = V sigb −V com
It becomes.

そして時間ｔb2において走査線Ｇ２の電位がＶghからＶgl1に下がると、ＴＦＴ９１はオフ状態となる。この時の液晶印加電圧Ｖlcdb2は、寄生容量Ｃｇｓの影響でΔＶb1低下する。
Ｖlcdb2＝Ｖlcdb1−ΔＶb1
但し、ΔＶb1＝（Ｖgh−Ｖgl1）×Ｃｇｓ／（Ｃｇｓ＋Ｃｌｃ＋Ｃｓ） When the potential of the scanning line G2 drops from V gh to V gl1 at time t b2 , the TFT 91 is turned off. At this time, the liquid crystal applied voltage V lcdb2 decreases by ΔV b1 due to the influence of the parasitic capacitance Cgs.
V lcdb2 = V lcdb1 -ΔV b1
However, ΔV b1 = (V gh −V gl1 ) × Cgs / (Cgs + Clc + Cs)

次いで、時間ｔb3において走査線Ｇ３の電位がＶgl1からＶgl2に下がると、補助容量Ｃｓを介してＶpic1の電位も下がる。この時の液晶印加電圧Ｖlcdb3は、
Ｖlcdb3＝Ｖlcdb2−ΔＶb2
但し、ΔＶb2＝（Ｖgl1−Ｖgl2）×Ｃｓ／（Ｃｇｓ＋Ｃｌｃ＋Ｃｓ）
となる。この状態では、走査線Ｇ２は非選択状態であり、走査線Ｇ２に接続されている次段のＴＦＴはオフ状態である。 Then, when the potential of the scanning line G3 is decreased from V gl1 the V gl2 at time t b3, lowers the potential of the V pic1 through an auxiliary capacitor Cs. The liquid crystal applied voltage V lcdb3 at this time is
V lcdb3 = V lcdb2 -ΔV b2
However, ΔV b2 = (V gl1 −V gl2 ) × Cs / (Cgs + Clc + Cs)
It becomes. In this state, the scanning line G2 is in a non-selected state, and the next stage TFT connected to the scanning line G2 is in an OFF state.

次に時間ｔb4において、走査線Ｇ２が選択されるべく走査線Ｇ２の電位がＶgl2からＶghに上がると、この時の液晶印加電圧Ｖlcdb4は、
Ｖlcdb4＝Ｖlcdb3＋ΔＶb3
但し、ΔＶb3＝（Ｖgh−Ｖgl2）×Ｃｓ／（Ｃｇｓ＋Ｃｌｃ＋Ｃｓ）
となる。続いて、時間ｔb5において走査線Ｇ２が非選択となるべく走査線Ｇ２の電位がＶghからＶgl2に下がると、Ｖpic1の電位はΔＶb3低下して、液晶印加電圧はＶlcdb3となる。以下、液晶容量ＣｌｃにはＶlcdb3の電圧が印加され続け、次の水平走査時まで表示状態が保持される。 Next, at time t b4 , when the potential of the scanning line G2 rises from V gl2 to V gh so that the scanning line G2 is selected, the liquid crystal applied voltage V lcdb4 at this time is
V lcdb4 = V lcdb3 + ΔV b3
However, ΔV b3 = (V gh −V gl2 ) × Cs / (Cgs + Clc + Cs)
It becomes. Subsequently, when the potential of the scanning line G2 is lowered from V gh to V gl2 so that the scanning line G2 is not selected at time t b5 , the potential of V pic1 decreases by ΔV b3 and the liquid crystal applied voltage becomes V lcdb3 . Thereafter, the voltage V lcdb3 is continuously applied to the liquid crystal capacitor Clc, and the display state is maintained until the next horizontal scanning.

つまり、液晶容量Ｃｌｃに対して負極性電圧が印加される場合においても、前述の（Ａ）正極性電圧印加の場合と同様に、時間ｔb2においてＴＦＴ９１がオフ状態となった後、時間ｔb3において走査線Ｇ２の電位をＶgl1からＶgl2に下げることにより、補助容量Ｃｓを介してＶpic1の電位をΔＶb2だけ下げることができ、液晶印加電圧の絶対値を大きくして、所望の液晶印加電圧を得ることができる。ここでΔＶb2はＣｓ／（Ｃｇｓ＋Ｃｌｃ＋Ｃｓ）の比率によって決定される。 That is, even when a negative voltage is applied to the liquid crystal capacitor Clc, as in the case of the application of the positive voltage (A) described above, after the TFT 91 is turned off at time t b2 , time t b3 the potential of the scanning line G2 by lowering the V gl1 the V gl2, the potential of V pic1 through the auxiliary capacitance Cs can be reduced by [Delta] V b2, by increasing the absolute value of the voltage applied to the liquid crystal in a desired liquid crystal An applied voltage can be obtained. Here, ΔV b2 is determined by the ratio of Cs / (Cgs + Clc + Cs).

以上説明したように、本実施形態によれば、Ｃｓオンゲート型の液晶パネルを備える液晶表示装置において、走査線を３つの電圧レベル（Ｖgh＞Ｖgl1＞Ｖgl2；ＶghはＴＦＴ９１をオン状態とする電圧であり、Ｖgl1及びＶgl2はＴＦＴ９１をオフ状態とする電圧）を用いて駆動することにより、共通電極Ｖcomの電圧を一定レベルに設定し、且つ信号線の信号の電圧振幅を大きくすることなく、必要な液晶印加電圧を得ることができる。即ち、共通電極Ｖcomの極性の反転駆動を行わず、従来のように走査線の電圧レベルを周期的に変化させる必要もないため、Ｃｓオンゲート型の構造により開口率を向上させることができるというメリットを有したうえで、液晶表示装置の消費電力を削減することができる。 As described above, according to this embodiment, in the liquid crystal display device having a Cs-on-gate type liquid crystal panel, the scanning line three voltage levels (V gh> V gl1> V gl2; V gh is turned on the TFT91 ( Vgl1 and Vgl2 are voltages that turn off the TFT 91), thereby setting the voltage of the common electrode Vcom to a constant level and setting the voltage amplitude of the signal on the signal line to The required liquid crystal applied voltage can be obtained without increasing it. That is, since the polarity inversion drive of the common electrode V com is not performed and it is not necessary to periodically change the voltage level of the scanning line as in the prior art, the aperture ratio can be improved by the Cs on-gate structure. In addition to having the advantage, the power consumption of the liquid crystal display device can be reduced.

〔第２の実施の形態〕
以下、本発明の第２の実施の形態を図示例と共に説明する。本第２の実施の形態は、図５に示した液晶パネルに対して、共通電極Ｖcomの反転駆動を行わず、２つのＣＳ電圧線に各補助容量の他端に印加する２値の電圧レベルをそれぞれ印加し、走査線の電圧レベルに応じて前記２値の電圧レベルの何れか一方が各補助容量の他端に印加されるように駆動することを特徴とする。 [Second Embodiment]
Hereinafter, a second embodiment of the present invention will be described together with illustrated examples. In the second embodiment, the binary voltage applied to the two CS voltage lines to the other end of each auxiliary capacitor without performing the inversion driving of the common electrode V com with respect to the liquid crystal panel shown in FIG. Each level is applied, and driving is performed such that one of the binary voltage levels is applied to the other end of each auxiliary capacitor in accordance with the voltage level of the scanning line.

図４は、本実施の形態における液晶表示装置２の回路構成の一例を示す図である。第１の実施の形態において図１を用いて説明した液晶表示装置１と同一の構成要素については同一の符号を付し、説明を省略する。   FIG. 4 is a diagram illustrating an example of a circuit configuration of the liquid crystal display device 2 in the present embodiment. The same components as those of the liquid crystal display device 1 described with reference to FIG. 1 in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

液晶パネル２１は、概略、複数の走査線と複数の信号線とが直交に配置され、走査線と信号線の各交差点近傍にそれぞれ表示画素が形成されている。表示画素の詳しい説明については、図５を用いて後述する。尚、各走査線はゲートドライバ回路２２に接続され、各信号線はソースドライバ回路１２に接続される。   In the liquid crystal panel 21, a plurality of scanning lines and a plurality of signal lines are roughly arranged orthogonally, and display pixels are formed in the vicinity of intersections between the scanning lines and the signal lines. Detailed description of the display pixel will be described later with reference to FIG. Each scanning line is connected to the gate driver circuit 22, and each signal line is connected to the source driver circuit 12.

ゲートドライバ回路２２は、ＴＧ部ドライバ制御回路１６から入力される垂直制御信号に基づいて走査電圧を発生し、液晶パネル２１の各走査線に順次走査電圧を印加する。更にＴＧ部ドライバ制御回路１６から信号ＧＯＥが入力される。信号ＧＯＥは走査信号のゲートドライバ回路２２から液晶パネル２１への出力を許可するための信号である。   The gate driver circuit 22 generates a scanning voltage based on the vertical control signal input from the TG unit driver control circuit 16 and sequentially applies the scanning voltage to each scanning line of the liquid crystal panel 21. Further, a signal GOE is input from the TG unit driver control circuit 16. The signal GOE is a signal for permitting output of the scanning signal from the gate driver circuit 22 to the liquid crystal panel 21.

電圧発生回路２２は、液晶表示装置２を備える装置の電源投入に応答して入力される電源入力信号に基づいて、液晶表示装置２を構成する各回路部に必要な電圧を生成して出力する。例えば、内部電源Ｖcc、信号線を駆動するための電圧Ｖsh、走査線を駆動するための電圧Ｖgh、Ｖgl、各ＣＳ電圧線を駆動するためのＶcsh及びＶcsl等を生成して出力する。そしてソースドライバ回路１２にはＶcc及びＶshの電圧が入力され、ゲートドライバ回路２２にはＶcc、Ｖgh、Ｖglの電圧が入力され、液晶パネル２１にはＶcsh及びＶcslの電圧が入力される。尚、Ｖcshは各ＣＳ電圧線のハイレベル時の電圧、Ｖcslはロウレベル時の電圧である。ＶcslはＶcshより所定電圧だけ低い電圧である。また、本実施形態においても、Ｖｃｏｍ発生回路１５により生成され、共通電極Ｖcomに印加される電圧は一定レベルに設定される。 The voltage generation circuit 22 generates and outputs a necessary voltage to each circuit unit constituting the liquid crystal display device 2 based on a power input signal input in response to power-on of the device including the liquid crystal display device 2. . For example, an internal power supply V cc , a voltage V sh for driving a signal line, voltages V gh and V gl for driving a scanning line, V csh and V csl for driving each CS voltage line are generated. Output. The source driver circuit 12 receives Vcc and Vsh voltages, the gate driver circuit 22 receives Vcc , Vgh , and Vgl voltages. The liquid crystal panel 21 receives Vcsh and Vcsl voltages. Is entered. V csh is the voltage at the high level of each CS voltage line, and V csl is the voltage at the low level. V csl is a voltage lower than V csh by a predetermined voltage. Also in this embodiment, is generated by the Vcom generation circuit 15, the voltage applied to the common electrode V com is set to a constant level.

図５は、液晶表示装置２が備える液晶パネル２１における、隣接する走査線Ｇ３１、Ｇ３２、Ｇ３３に接続される表示画素の等価回路を示した図である。走査線Ｇ３１に接続される表示画素は、行方向に延伸された走査線Ｇ３１と列方向に延伸された信号線Ｓ３１の交差部に設けられ、ＴＦＴ３１が配置される。ＴＦＴ３１のゲート電極は走査線Ｇ３１に接続され、ドレイン電極は信号線Ｓ３１に接続される。液晶容量Ｃｌｃ１の一端はＴＦＴ３１のソース電極に接続され、他端は共通電極Ｖcomに接続される。また補助容量Ｃｓ１の一端はＴＦＴ３１のソース電極に接続され、他端は走査線Ｇ３１と平行して配設されたＣＳ線（補助容量線）３２に接続される。ＣＳ線３２の一端にはＴＦＴ３３とＴＦＴ３４のドレイン電極が接続される。ＴＦＴ３３のゲート電極は走査線Ｇ３１に接続され、ソース電極はＣＳ電圧線４３に接続される。また、ＴＦＴ３４のゲート電極は走査線Ｇ３２に接続され、ソース電極はＣＳ電圧線４４に接続される。更にＣＳ線３２の他端には容量Ｃｓｐ１の一端が接続される。容量Ｃｓｐ１の他端は共通電極Ｖcomに接続される。ＴＦＴ３１のゲート−ソース間には寄生容量Ｃｇｓ１が存在する。 FIG. 5 is a diagram illustrating an equivalent circuit of display pixels connected to adjacent scanning lines G31, G32, and G33 in the liquid crystal panel 21 included in the liquid crystal display device 2. The display pixel connected to the scanning line G31 is provided at the intersection of the scanning line G31 extending in the row direction and the signal line S31 extending in the column direction, and the TFT 31 is disposed. The gate electrode of the TFT 31 is connected to the scanning line G31, and the drain electrode is connected to the signal line S31. One end of the liquid crystal capacitor Clc1 is connected to the source electrode of the TFT 31, and the other end is connected to the common electrode Vcom . One end of the auxiliary capacitor Cs1 is connected to the source electrode of the TFT 31, and the other end is connected to a CS line (auxiliary capacitor line) 32 arranged in parallel with the scanning line G31. The drain electrode of the TFT 33 and the TFT 34 is connected to one end of the CS line 32. The gate electrode of the TFT 33 is connected to the scanning line G 31, and the source electrode is connected to the CS voltage line 43. The gate electrode of the TFT 34 is connected to the scanning line G 32, and the source electrode is connected to the CS voltage line 44. Further, one end of the capacitor Csp1 is connected to the other end of the CS line 32. The other end of the capacitor Csp1 is connected to the common electrode Vcom . A parasitic capacitance Cgs1 exists between the gate and source of the TFT 31.

走査線Ｇ３１に隣接する走査線Ｇ３２に接続される表示画素は、行方向に延伸された走査線Ｇ３２と列方向に延伸された信号線Ｓ３１の交差部に設けられ、ＴＦＴ３５が配置される。ＴＦＴ３５のゲート電極は走査線Ｇ３２に接続され、ドレイン電極は信号線Ｓ３１に接続される。液晶容量Ｃｌｃ２の一端はＴＦＴ３５のソース電極に接続され、他端は共通電極Ｖcomに接続される。また補助容量Ｃｓ２の一端はＴＦＴ３５のソース電極に接続され、他端は走査線Ｇ３２と平行して配設されたＣＳ線３６に接続される。ＣＳ線３６の一端にはＴＦＴ３７とＴＦＴ３８のドレイン電極が接続される。ＴＦＴ３７のゲート電極は走査線Ｇ３２に接続され、ソース電極はＣＳ電圧線４４に接続される。また、ＴＦＴ３８のゲート電極は走査線Ｇ３３に接続され、ソース電極はＣＳ電圧線４３に接続される。更にＣＳ線３６の他端には容量Ｃｓｐ２の一端が接続される。容量Ｃｓｐ２の他端は共通電極Ｖcomに接続される。ＴＦＴ３５のゲート−ソース間には寄生容量Ｃｇｓ２が存在する。 A display pixel connected to the scanning line G32 adjacent to the scanning line G31 is provided at an intersection of the scanning line G32 extending in the row direction and the signal line S31 extending in the column direction, and the TFT 35 is disposed. The gate electrode of the TFT 35 is connected to the scanning line G32, and the drain electrode is connected to the signal line S31. One end of the liquid crystal capacitor Clc2 is connected to the source electrode of the TFT 35, and the other end is connected to the common electrode Vcom . One end of the auxiliary capacitor Cs2 is connected to the source electrode of the TFT 35, and the other end is connected to the CS line 36 disposed in parallel with the scanning line G32. The drain electrodes of the TFT 37 and the TFT 38 are connected to one end of the CS line 36. The gate electrode of the TFT 37 is connected to the scanning line G 32, and the source electrode is connected to the CS voltage line 44. The gate electrode of the TFT 38 is connected to the scanning line G33, and the source electrode is connected to the CS voltage line 43. Further, one end of the capacitor Csp2 is connected to the other end of the CS line 36. The other end of the capacitor Csp2 is connected to the common electrode Vcom . A parasitic capacitance Cgs2 exists between the gate and the source of the TFT 35.

走査線Ｇ３２に隣接する走査線Ｇ３３に接続される表示画素は走査線Ｇ３１に接続される表示画素と同様の構成を有し、走査線Ｇ３２と信号線Ｓ３１の交差部に設けられてＴＦＴ３９が配置され、ＴＦＴ３９のゲート電極は走査線Ｇ３３に接続され、ドレイン電極は信号線Ｓ３１に接続される。液晶容量Ｃｌｃ３はＴＦＴ３９のソース電極と共通電極Ｖcomに接続され、補助容量Ｃｓ３はＴＦＴ３９のソース電極とＣＳ線４４に接続される。ＣＳ線４４の一端にはＴＦＴ４１とＴＦＴ４２のドレイン電極が接続され、ＴＦＴ４１のゲート電極は走査線Ｇ３３に接続され、ソース電極はＣＳ電圧線４３に接続され、ＴＦＴ４２のゲート電極は走査線Ｇ３４に接続され、ソース電極はＣＳ電圧線４４に接続される。更にＣＳ線４４の他端には容量Ｃｓｐ３の一端が接続され、容量Ｃｓｐ３の他端は共通電極Ｖcomに接続される。ＴＦＴ３９のゲート−ソース間には寄生容量Ｃｇｓ３が存在する。なお、容量Ｃｓｐ１、Ｃｓｐ２、Ｃｓｐ３は補助容量Ｃｓ１、Ｃｓ２、Ｃｓ３やＣＳ線３２、３６、４０の寄生容量に比べて十分大きな容量値に設定される。 The display pixel connected to the scanning line G33 adjacent to the scanning line G32 has the same configuration as the display pixel connected to the scanning line G31, and is provided at the intersection of the scanning line G32 and the signal line S31. The gate electrode of the TFT 39 is connected to the scanning line G33, and the drain electrode is connected to the signal line S31. The liquid crystal capacitor Clc3 is connected to the source electrode of the TFT 39 and the common electrode Vcom , and the auxiliary capacitor Cs3 is connected to the source electrode of the TFT 39 and the CS line 44. The drain electrode of TFT41 and TFT42 is connected to one end of CS line 44, the gate electrode of TFT41 is connected to scanning line G33, the source electrode is connected to CS voltage line 43, and the gate electrode of TFT42 is connected to scanning line G34. The source electrode is connected to the CS voltage line 44. Further, one end of the capacitor Csp3 is connected to the other end of the CS line 44, and the other end of the capacitor Csp3 is connected to the common electrode Vcom . A parasitic capacitance Cgs3 exists between the gate and the source of the TFT 39. The capacitors Csp1, Csp2, and Csp3 are set to have sufficiently large capacitance values compared to the auxiliary capacitors Cs1, Cs2, and Cs3 and the parasitic capacitances of the CS lines 32, 36, and 40.

ＣＳ電圧線４３及び４４に印加される電圧について説明する。ライン反転駆動及びフレーム反転駆動される構成において、後述する図６及び図７に示すように、１フレーム期間内では、例えば、ＣＳ電圧線４３にＶcsl、ＣＳ電圧線４４にＶcshの電圧が電圧発生回路２３より印加される。そして、続く次フレームにおいては、ＣＳ電圧線４３にＶcsh、ＣＳ電圧線４４にＶcslの電圧が印加される。即ち、フレーム毎にＣＳ電圧線４３及び４４の電圧は入れ替えられて印加される。このＣＳ電圧線４３及び４４に対する印加電圧の入れ替えは、液晶パネル２１に含まれる内部回路（不図示）において制御される構成としてもよいし、電圧発生回路２３から入れ替えられた電圧が出力され、直接ＣＳ電圧線４３及び４４にそれぞれ印加される構成としてもよい。 The voltage applied to the CS voltage lines 43 and 44 will be described. In the configuration in which line inversion driving and frame inversion driving are performed, as shown in FIGS. 6 and 7 to be described later, within one frame period, for example, the voltage V csl is applied to the CS voltage line 43 and the voltage V csh is applied to the CS voltage line 44. Applied from the voltage generation circuit 23. In the subsequent frame, a voltage of V csh is applied to the CS voltage line 43 and a voltage of V csl is applied to the CS voltage line 44. That is, the voltages of the CS voltage lines 43 and 44 are switched and applied for each frame. The switching of the applied voltage to the CS voltage lines 43 and 44 may be controlled by an internal circuit (not shown) included in the liquid crystal panel 21. Alternatively, the replaced voltage is output from the voltage generation circuit 23 and directly applied. It is good also as a structure applied to CS voltage line 43 and 44, respectively.

次に、図６及び図７に示す信号波形を用いて、本実施の形態の液晶表示装置２の回路動作を（Ｃ）正極性電圧印加時と（Ｄ）負極性電圧印加時のそれぞれについて説明する。尚、これはライン反転駆動を行う場合において、隣接する走査線での動作に対応する。   Next, using the signal waveforms shown in FIGS. 6 and 7, the circuit operation of the liquid crystal display device 2 of the present embodiment will be described for each of (C) positive voltage application and (D) negative voltage application. To do. Note that this corresponds to an operation on an adjacent scanning line when line inversion driving is performed.

（Ｃ）正極性電圧印加時
図６は液晶容量Ｃｌｃに対して正極性電圧が印加されるときの液晶表示装置２の本実施形態の駆動方法における主な信号波形である。第１の実施の形態において図２を用いて説明した信号波形と同一の部分については説明を省略または簡略化する。 (C) When Positive Voltage is Applied FIG. 6 shows main signal waveforms in the driving method of the present embodiment of the liquid crystal display device 2 when a positive voltage is applied to the liquid crystal capacitance Clc. In the first embodiment, the description of the same portion as the signal waveform described with reference to FIG. 2 is omitted or simplified.

Ｇ３１は走査線Ｇ３１の電位、Ｇ３２は走査線Ｇ３２の電位を示した波形である。走査線Ｇ３１及びＧ３２の電位はそれぞれの選択時はＶghとなり、非選択時にはＶglとなる。ＣＳ３２はＣＳ線３２の電位、ＣＳ３６はＣＳ線３６の電位を示した波形である。Ｓ３１は信号線Ｓ３１の電位を示した波形である。信号線Ｓ３１の最高電位はＶshである。Ｖpic2はＴＦＴ３１のソース電極の電位を示した波形である。また共通電極Ｖcomには一定レベルの電圧が印加され、Ｖpic1は走査線Ｇ３１に接続される表示画素のＴＦＴ３１のソース電極の電位を示す。 G31 is a waveform indicating the potential of the scanning line G31, and G32 is a waveform indicating the potential of the scanning line G32. The potentials of the scanning lines G31 and G32 are V gh when selected, and V gl when not selected. CS 32 is a waveform indicating the potential of the CS line 32, and CS 36 is a waveform indicating the potential of the CS line 36. S31 is a waveform showing the potential of the signal line S31. The maximum potential of the signal line S31 is V sh . V pic2 is a waveform showing the potential of the source electrode of the TFT 31. Also the common electrode V com is applied a constant level of voltage, V pic1 indicates the potential of the TFT31 source electrodes of the display pixels connected to the scan line G31.

時間ｔc1において走査線Ｇ３１の電位がＶghに上がると、ＴＦＴ３１がオン状態となり、信号Ｓ３１の電圧がＴＦＴ３１を介して液晶容量Ｃｌｃ１と補助容量Ｃｓ１に印加される。この時のＶpic2をＶsigcとすると、液晶印加電圧Ｖlcdc1は
Ｖlcdc1＝Ｖsigc−Ｖcom
となる。更にＴＦＴ３３がオン状態となり、ＣＳ電圧線４３の電圧（Ｖcsl）がＴＦＴ３３を介してＣＳ線３２に印加されて、ＣＳ電線３２の電圧がＶcslとなる。 When the potential of the scanning line G31 rises to V gh at time t c1 , the TFT 31 is turned on, and the voltage of the signal S31 is applied to the liquid crystal capacitor Clc1 and the auxiliary capacitor Cs1 via the TFT 31. When V pic2 at this time is V sigc , the liquid crystal applied voltage V lcdc1 is V lcdc1 = V sigc −V com
It becomes. Further, the TFT 33 is turned on, the voltage (V csl ) of the CS voltage line 43 is applied to the CS line 32 via the TFT 33, and the voltage of the CS electric wire 32 becomes V csl .

そして時間ｔc2において走査線Ｇ３１の電位がＶghからＶglに下がると、ＴＦＴ３１及びＴＦＴ３３はオフ状態となる。この時の液晶印加電圧Ｖlcdc2は、寄生容量Ｃｇｓの影響でΔＶc1低下する。
Ｖlcdc2＝Ｖlcdc1−ΔＶc1
但し、ΔＶc1＝（Ｖgh−Ｖgl）×Ｃｇｓ１／（Ｃｇｓ１＋Ｃｌｃ１＋Ｃｓ１）
尚、容量Ｃｓｐ１は補助容量Ｃｓ１やＣＳ線３２の寄生容量に比べて非常に大きな容量であるため、ＣＳ線３２の電位はＶcslに保持される。 When the potential of the scanning line G31 falls from V gh to V gl at time t c2 , the TFT 31 and the TFT 33 are turned off. At this time, the liquid crystal applied voltage V lcdc2 decreases by ΔV c1 due to the influence of the parasitic capacitance Cgs.
V lcdc2 = V lcdc1 -ΔV c1
However, ΔV c1 = (V gh −V gl ) × Cgs1 / (Cgs1 + Clc1 + Cs1)
Since the capacitor Csp1 is much larger than the auxiliary capacitor Cs1 and the parasitic capacitance of the CS line 32, the potential of the CS line 32 is held at V csl .

次に、時間ｔｃ３において走査線Ｇ３２が選択されるべく走査線Ｇ３２の電位がＶglからＶghに上がると、ＴＦＴ３５がオン状態となる。更にＴＦＴ３４もオン状態となり、ＣＳ電圧線４４の電圧（Ｖcsh）がＴＦＴ３４を介してＣＳ線３２に印加されて、ＣＳ電圧線３２の電圧がＶcshとなる。つまりＣＳ線３２の電位はＶcslからＶcshに変化する。この時の液晶印加電圧Ｖlcdc3は、
Ｖlcdc3＝Ｖlcdc2＋ΔＶc2
但し、ΔＶc2＝（Ｖcsh−Ｖcsl）×Ｃｓ１／（Ｃｇｓ１＋Ｃｌｃ１＋Ｃｓ１）
・・・（２）
となる。以下、液晶容量Ｃｌｃ１にはＶlcdc3の電圧が印加され続け、次の水平走査時まで表示状態が保持される。 Next, when the potential of the scan line G32 so the scanning line G32 is selected rises V gh from V gl at time tc3, TFT 35 is turned on. Further, the TFT 34 is also turned on, and the voltage (V csh ) of the CS voltage line 44 is applied to the CS line 32 via the TFT 34, and the voltage of the CS voltage line 32 becomes V csh . That is, the potential of the CS line 32 changes from V csl to V csh . The liquid crystal applied voltage V lcdc3 at this time is
V lcdc3 = V lcdc2 + ΔV c2
However, ΔV c2 = (V csh −V csl ) × Cs 1 / (Cgs 1 + Clc 1 + Cs 1)
... (2)
It becomes. Hereinafter, the voltage V lcdc3 is continuously applied to the liquid crystal capacitor Clc1, and the display state is maintained until the next horizontal scanning.

つまり、時間ｔc2においてＴＦＴ３１がオフ状態となった後、時間ｔｃ３において走査線Ｇ３２の電位がＶglからＶghに上がると同時にＴＦＴ３４を介してＣＳ電圧線４４の電圧（Ｖcsh）がＣＳ線３２に印加されるようにしたことにより、Ｖpic2の電位をΔＶc2だけ上げることができる。これにより液晶印加電圧を大きくして、所望の液晶印加電圧を得ることができる。ΔＶc2はＣｓ１／（Ｃｇｓ１＋Ｃｌｃ１＋Ｃｓ１）の比率によって決定される。 That is, after the TFT 31 is turned off at time t c2 , the voltage (V csh ) of the CS voltage line 44 passes through the TFT 34 at the same time as the potential of the scanning line G32 rises from V gl to V gh at time tc3. As a result, the potential of Vpic2 can be raised by ΔV c2 . Thereby, the liquid crystal applied voltage can be increased to obtain a desired liquid crystal applied voltage. ΔV c2 is determined by the ratio of Cs1 / (Cgs1 + Clc1 + Cs1).

ここで各信号電圧の具体的な電圧値について一例を挙げて説明する。液晶印加電圧Ｖlcdcは、厳密には図６を用いて説明した電圧Ｖpic2の各電圧値Ｖlcdc1、Ｖlcdc2及びＶlcdc3の平均値となるが、Ｖpic2の電圧はＶlcdc3である時間が圧倒的に長く、液晶の応答性等の点から考慮して、電圧Ｖlcdc＝Ｖlcdc3として考える。 Here, a specific voltage value of each signal voltage will be described with an example. Strictly speaking, the liquid crystal applied voltage V lcdc is an average value of the voltage values V lcdc1 , V lcdc2, and V lcdc3 of the voltage V pic2 described with reference to FIG. 6, but the time during which the voltage of V pic2 is V lcdc3 is used. Considering from the viewpoint of overwhelmingly long liquid crystal response and the like, the voltage V lcdc = V lcdc3 is considered.

例えば、良好な表示を得るために、液晶印加電圧Ｖlcdc＝５［Ｖ］必要であって、共通電極Ｖcomの電位に対して信号Ｓ３１の振幅が最大±２Ｖである場合、液晶印加電圧Ｖlcdc2を更に３［Ｖ］上げる必要がある。そこでＣｇｓ１＜＜Ｃｓ１として、Ｖsigc＝２［Ｖ］、ΔＶc2＝３［Ｖ］とすると、Ｃｓ１／（Ｃｇｓ１＋Ｃｌc1＋Ｃｓ１）＝１／２とすれば、式（２）よりＶcsh−Ｖcsl＝６［Ｖ］となる。即ち、Ｖcsh−Ｖcsl＝６［Ｖ］となるようにＶcsh及びＶcslを設定すればよい。 For example, in order to obtain a good display, the liquid crystal applied voltage V lcdc = 5 [V] is required, and when the amplitude of the signal S31 is ± 2 V at the maximum with respect to the potential of the common electrode V com , the liquid crystal applied voltage V It is necessary to further increase lcdc2 by 3 [V]. Therefore, if Cgs1 << Cs1, V sigc = 2 [V], and ΔV c2 = 3 [V], then if Cs1 / (Cgs1 + Cl c1 + Cs1) = 1/2, then V csh −V csl from equation (2). = 6 [V]. That may be set V csh and V csl such that V csh -V csl = 6 [V ].

（Ｄ）負極性電圧印加時
図７は液晶容量Ｃｌｃに対して負極性電圧が印加されるときの液晶表示装置２の本実施形態の駆動方法における主信号波形である。尚、前述の（Ｃ）正極性電圧印加時において図７を用いて説明した信号波形と同一の部分については、説明を省略または簡略化する。同図におけるＶpic1は、図６に示した走査線Ｇ３１に隣接する走査線Ｇ３２に接続される表示画素のＴＦＴ３５のソース電極の電位を示す。 (D) When Negative Voltage is Applied FIG. 7 is a main signal waveform in the driving method of the present embodiment of the liquid crystal display device 2 when a negative voltage is applied to the liquid crystal capacitance Clc. The description of the same part as the signal waveform described with reference to FIG. 7 at the time of applying the positive voltage (C) is omitted or simplified. Vpic1 in the figure indicates the potential of the source electrode of the TFT 35 of the display pixel connected to the scanning line G32 adjacent to the scanning line G31 shown in FIG.

時間ｔd1において走査線Ｇ３２の電位がＶghに上がると、ＴＦＴ３５がオン状態となり、信号Ｓ３１の電圧がＴＦＴ３５を介して液晶容量Ｃｌｃと補助容量Ｃｓ２に印加される。この時のＶpic2の電圧をＶsigdとすると、液晶印加電圧Ｖlcdd1は
Ｖlcdd1＝Ｖsigd−Ｖcom
となる。更にＴＦＴ３７がオン状態となり、ＣＳ電圧線４４の電圧（Ｖcsh）がＴＦＴ３７を介してＣＳ線３６に印加される。 When the potential of the scanning line G32 rises V gh at time t d1, TFT 35 is turned on, the voltage of the signal S31 is applied to the liquid crystal capacitance Clc and the auxiliary capacitance Cs2 through the TFT 35. If the voltage of V pic2 at this time is V sigd , the liquid crystal applied voltage V lcdd1 is V lcdd1 = V sigd −V com
It becomes. Further, the TFT 37 is turned on, and the voltage (V csh ) of the CS voltage line 44 is applied to the CS line 36 via the TFT 37.

そして時間ｔd2において走査線Ｇ３２の電位がＶghからＶglに下がると、ＴＦＴ３５及びＴＦＴ３７はオフ状態となる。この時の液晶印加電圧Ｖlcdd2は、寄生容量Ｃｇｓ１の影響でΔＶd1低下する。
Ｖlcdd2＝Ｖlcdd1−ΔＶd1
但し、ΔＶd1＝（Ｖgh−Ｖgl）×Ｃｇｓ１／（Ｃｇｓ１＋Ｃｌｃ１＋Ｃｓ１） When the potential of the scanning line G32 falls from V gh to V gl at time t d2 , the TFT 35 and the TFT 37 are turned off. At this time, the liquid crystal applied voltage V lcdd2 decreases by ΔV d1 due to the influence of the parasitic capacitance Cgs1.
V lcdd2 = V lcdd1 −ΔV d1
However, ΔV d1 = (V gh −V gl ) × Cgs1 / (Cgs1 + Clc1 + Cs1)

更に、時間ｔd3において走査線Ｇ３３が選択されるべく走査線Ｇ３３の電位がＶglからＶghに上がると、ＴＦＴ３９がオン状態となる。更にＴＦＴ３８もオン状態となり、ＣＳ電圧線４３の電圧（Ｖcsl）がＴＦＴ３８を介してＣＳ線３６に印加される。つまりＣＳ線３６の電位はＶcshからＶcslに変化する。この時の液晶印加電圧Ｖlcdd3は、
Ｖlcdd3＝Ｖlcdd2−ΔＶd2
但し、ΔＶd2＝（Ｖcsh−Ｖcsl）×Ｃｓ１／（Ｃｇｓ１＋Ｃｌｃ１＋Ｃｓ１）
となる。以下、液晶容量Ｃｌｃ１にはＶlcdd3の電圧が印加され続け、次の水平走査時まで表示状態が保持される。 Further, when the potential of the scanning line G33 rises from V gl to V gh so that the scanning line G33 is selected at time t d3 , the TFT 39 is turned on. Further, the TFT 38 is also turned on, and the voltage (V csl ) of the CS voltage line 43 is applied to the CS line 36 via the TFT 38. That is, the potential of the CS line 36 changes from V csh to V csl . The liquid crystal applied voltage V lcdd3 at this time is
V lcdd3 = V lcdd2 −ΔV d2
However, ΔV d2 = (V csh −V csl ) × Cs 1 / (Cgs 1 + Clc 1 + Cs 1)
It becomes. Thereafter, the voltage V lcdd3 is continuously applied to the liquid crystal capacitor Clc1, and the display state is maintained until the next horizontal scanning.

つまり、時間ｔd2においてＴＦＴ３１がオフ状態となった後、時間ｔｄ３において走査線Ｇ３３の電位がＶglからＶghに上がると同時にＴＦＴ３８を介してＣＳ電圧線４３の電圧（Ｖcsl）の電圧がＣＳ線３６に印加される。これにより、Ｖpic2の電位をΔＶd2下げることができ、液晶印加電圧の絶対値を大きくして、所望の液晶印加電圧を得ることができる。ΔＶd2はＣｓ１／（Ｃｇｓ１＋Ｃｌｃ１＋Ｃｓ１）の比率によって決定される。 That is, after the TFT 31 is turned off at time t d2 , the potential of the scanning line G33 rises from V gl to V gh at time td3, and at the same time, the voltage of the CS voltage line 43 (V csl ) is changed via the TFT 38. Applied to the CS line 36. Thus, the potential of V pic2 can be lowered [Delta] V d2, by increasing the absolute value of the voltage applied to the liquid crystal, it is possible to obtain a desired liquid crystal application voltage. ΔV d2 is determined by the ratio of Cs1 / (Cgs1 + Clc1 + Cs1).

以上説明したように、本実施形態においては、ハイレベルの電圧Ｖcshとロウレベルの電圧Ｖcslが印加される２つのＣＳ電圧線を有し、ゲート電極が当段の走査線に接続されたＴＦＴと、ゲート電極が次段の走査線に接続されたＴＦＴとのスイッチングにより、ハイレベルの電圧及びロウレベルの電圧何れかの電圧を当段の走査線に接続された表示画素のＣＳ線（補助容量線）に印加する構成を備え、液晶容量に正極性電圧が印加される場合は当該液晶容量の補助容量の他端にハイレベルの電圧Ｖcshの電圧が印加され、負極性電圧が印加される場合はロウレベルの電圧Ｖcslの電圧が印加されるようにしたことにより、ＣＳ線駆動のためのドライバ回路を設置することなく、ＣＳ線の駆動が可能となり、ＣＳ線駆動のためのドライバ回路の必要がないため、アモルファスＴＦＴを用いた液晶パネルにおいても実現可能である。 As described above, in the present embodiment, a TFT having two CS voltage lines to which a high level voltage V csh and a low level voltage V csl are applied, and a gate electrode connected to the scanning line at this stage. By switching between the gate electrode and the TFT connected to the next scanning line, either the high level voltage or the low level voltage is applied to the CS line (auxiliary capacitance) of the display pixel connected to the scanning line of this stage. When a positive voltage is applied to the liquid crystal capacitor, a high-level voltage V csh is applied to the other end of the auxiliary capacitor of the liquid crystal capacitor, and a negative voltage is applied. In this case, since the low level voltage V csl is applied, the CS line can be driven without installing a driver circuit for driving the CS line. necessary Therefore, it can be realized even in a liquid crystal panel using an amorphous TFT.

尚、本実施形態では、次段の走査線が選択状態となり、ゲート電極が次段の走査線に接続されたＴＦＴ（例えば、図５のＴＦＴ３４）がオン状態となるタイミングで、ハイレベルの電圧及びロウレベルの電圧何れかの電圧が当段の走査線に接続された表示画素のＣＳ線（補助容量線；例えば、図５のＣＳ線３２）に印加されることとした。この実施形態に関わらず、次のようにしてもよい。即ち、図５において、ゲート電極が次段の走査線に接続されたＴＦＴ（例えば、図５のＴＦＴ３４）の当該ゲート電極を次段の走査線に接続するのではなく、別途配設された電圧線に接続し、この電圧線への電圧印加制御によってＣＳ線に電圧を印加するようにしてもよい。これにより、当段の走査線が非選択状態となってから、次段の走査線が選択状態となるまでの間（即ち、図５において、例えば走査線Ｇ３１が選択されてＴＦＴ３１がオフ状態となった後、走査線Ｇ３２が選択されてＴＦＴ３５がオン状態となるまでの間）に別途配設された電圧線に所定の電圧を印加して該電圧線にゲート電極が接続されたＴＦＴをオン状態とし、ＣＳ線に電圧を印加することができる。   In the present embodiment, the high-level voltage is applied at the timing when the next scanning line is selected and the TFT whose gate electrode is connected to the next scanning line (for example, the TFT 34 in FIG. 5) is turned on. One of the low-level voltage and the low-level voltage is applied to the CS line (auxiliary capacitance line; for example, the CS line 32 in FIG. 5) of the display pixel connected to the scanning line at this stage. Regardless of this embodiment, the following may be performed. That is, in FIG. 5, the gate electrode of the TFT whose gate electrode is connected to the next scanning line (for example, TFT 34 in FIG. 5) is not connected to the next scanning line, but is provided separately. A voltage may be applied to the CS line by connecting to the line and controlling voltage application to the voltage line. As a result, the scanning line at the current stage is not selected and until the scanning line at the next stage is selected (that is, in FIG. 5, for example, the scanning line G31 is selected and the TFT 31 is turned off. Then, a predetermined voltage is applied to a voltage line separately provided until the TFT 35 is turned on after the scanning line G32 is selected to turn on the TFT whose gate electrode is connected to the voltage line. A voltage can be applied to the CS line.

第１の実施の形態における液晶表示装置の回路構成の一例を示す図。1 is a diagram illustrating an example of a circuit configuration of a liquid crystal display device according to a first embodiment. 第１の実施の形態における液晶表示装置の液晶パネルを構成する液晶に正極性電圧が印加されたときの信号波形の一例を示す図。The figure which shows an example of a signal waveform when a positive voltage is applied to the liquid crystal which comprises the liquid crystal panel of the liquid crystal display device in 1st Embodiment. 第１の実施の形態における液晶表示装置の液晶パネルを構成する液晶に負極性電圧が印加されたときの信号波形の一例を示す図。FIG. 3 is a diagram illustrating an example of a signal waveform when a negative voltage is applied to liquid crystal that forms the liquid crystal panel of the liquid crystal display device according to the first embodiment. 第２の実施の形態における液晶表示装置の回路構成の一例を示す図。FIG. 10 illustrates an example of a circuit configuration of a liquid crystal display device according to a second embodiment. 第２の実施の形態における液晶表示装置の液晶パネルの等価回路を示した図。The figure which showed the equivalent circuit of the liquid crystal panel of the liquid crystal display device in 2nd Embodiment. 第２の実施の形態における液晶表示装置の液晶パネルを構成する液晶に正極性電圧が印加されたときの信号波形の一例を示す図。The figure which shows an example of a signal waveform when a positive voltage is applied to the liquid crystal which comprises the liquid crystal panel of the liquid crystal display device in 2nd Embodiment. 第２の実施の形態における液晶表示装置の液晶パネルを構成する液晶に負極性電圧が印加されたときの信号波形の一例を示す図。The figure which shows an example of the signal waveform when the negative polarity voltage is applied to the liquid crystal which comprises the liquid crystal panel of the liquid crystal display device in 2nd Embodiment. 従来の液晶パネルの等価回路を示した図。The figure which showed the equivalent circuit of the conventional liquid crystal panel. 従来のＣｓ／Ｖcom一括型の液晶パネルを備える液晶表示装置の信号波形の一例を示す図。The figure which shows an example of the signal waveform of a liquid crystal display device provided with the conventional Cs / Vcom collective type liquid crystal panel. 従来のＣｓオンゲート型の液晶パネルを備える液晶表示装置の信号波形の一例を示す図。The figure which shows an example of the signal waveform of a liquid crystal display device provided with the conventional Cs on-gate type liquid crystal panel. 従来のＣｓライン駆動型の液晶パネルを備える液晶表示装置の信号波形の一例を示す図。The figure which shows an example of the signal waveform of a liquid crystal display device provided with the conventional Cs line drive type liquid crystal panel.

符号の説明Explanation of symbols

１、２ 液晶表示装置
１１、２１ 液晶パネル
１２ ソースドライバ回路
１３ 反転ＲＧＢ発生回路
１４、２２ ゲートドライバ回路
１５ Ｖｃｏｍ発生回路
１６ ＴＧ部ドライバ制御回路
１７、２３ 電圧発生回路 DESCRIPTION OF SYMBOLS 1, 2 Liquid crystal display device 11, 21 Liquid crystal panel 12 Source driver circuit 13 Inversion RGB generation circuit 14, 22 Gate driver circuit 15 Vcom generation circuit 16 TG part driver control circuit 17, 23 Voltage generation circuit

Claims (12)

互いに直交して配置された複数の走査線及び複数の信号線の各交点近傍にマトリクス状に配設され、スイッチング素子と該スイッチング素子の出力端に接続された画素電極と該画素電極に一端が接続された補助容量とを有する複数の表示画素と、前記各画素電極に対向して配設される共通電極と、を有する液晶パネルを備える液晶表示装置において、
前記共通電極に一定電圧を印加する共通電圧印加手段と、
前記スイッチング素子がオン状態からオフ状態になった後に、前記補助容量の他端に所定の電圧を印加して、前記画素電極と前記共通電極との電位差の絶対値を増加させる電圧印加手段と、
を備えることを特徴とする液晶表示装置。 A switching element, a pixel electrode connected to the output end of the switching element, and one end of the pixel electrode are arranged in the vicinity of the intersections of the plurality of scanning lines and the plurality of signal lines arranged orthogonal to each other. In a liquid crystal display device comprising a liquid crystal panel having a plurality of display pixels having connected auxiliary capacitors and a common electrode disposed to face each of the pixel electrodes,
Common voltage applying means for applying a constant voltage to the common electrode;
Voltage application means for applying a predetermined voltage to the other end of the auxiliary capacitor after the switching element is turned off to increase the absolute value of the potential difference between the pixel electrode and the common electrode;
A liquid crystal display device comprising: 前記各走査線は前段の前記補助容量の他端に接続され、
前記電圧印加手段は、前記複数の走査線を順次走査するための走査信号を出力するとともに、前段の前記補助容量の他端に前記所定の電圧を印加することを特徴とする請求項１に記載の液晶表示装置。 Each of the scanning lines is connected to the other end of the auxiliary capacitor in the previous stage,
2. The voltage applying unit outputs a scanning signal for sequentially scanning the plurality of scanning lines, and applies the predetermined voltage to the other end of the auxiliary capacitor in the previous stage. Liquid crystal display device. 前記各走査線に接続される前記表示画素の画素電極の前記共通電極に対する電位差の極性は、前記各走査線毎に逆極性に設定され、
前記電圧印加手段は、
前記電位差の極性が正極性に設定される走査線に接続される前記表示画素の、前記補助容量の他端の電位を上昇させ、
前記電位差の極性が負極性に設定される走査線に接続される前記表示画素の、前記補助容量の他端の電位を低下させることを特徴とする請求項１または２に記載の液晶表示装置。 The polarity of the potential difference with respect to the common electrode of the pixel electrode of the display pixel connected to each scanning line is set to a reverse polarity for each scanning line,
The voltage applying means includes
Increasing the potential of the other end of the auxiliary capacitor of the display pixel connected to the scanning line in which the polarity of the potential difference is set to positive polarity,
3. The liquid crystal display device according to claim 1, wherein the potential of the other end of the auxiliary capacitor of the display pixel connected to the scanning line in which the polarity of the potential difference is set to negative polarity is lowered. 前記電圧印加手段による前記補助容量の他端への所定の電圧の印加は、当該走査線に接続される前記表示画素の前記スイッチング素子がオフ状態になった後、次段の走査線に接続される前記表示画素の前記スイッチング素子がオン状態となるまでの間に行われることを特徴とする請求項１に記載の液晶表示装置。   The application of the predetermined voltage to the other end of the auxiliary capacitor by the voltage applying means is connected to the next scanning line after the switching element of the display pixel connected to the scanning line is turned off. The liquid crystal display device according to claim 1, which is performed until the switching element of the display pixel is turned on. 前記電圧印加手段による前記補助容量の他端への所定の電圧の印加は、次段の走査線に接続される前記表示画素の前記スイッチング素子がオン状態となるタイミングで行われることを特徴とする請求項１に記載の液晶表示装置。   The application of the predetermined voltage to the other end of the auxiliary capacitor by the voltage applying unit is performed at a timing when the switching element of the display pixel connected to the next scanning line is turned on. The liquid crystal display device according to claim 1. 前記各走査線に接続される前記表示画素の画素電極の前記共通電極に対する電位差の極性は、前記各走査線毎に逆極性に設定され、
前記電圧印加手段は、次段の走査線に接続される前記表示画素の前記スイッチング素子がオン状態となるタイミングにおいて、前記電位差の極性が正極性に設定される前記走査線に接続される前記表示画素の、前記補助容量の他端の電位を第１の電位に設定し、前記電位差の極性が負極性に設定される走査線に接続される前記表示画素の、前記補助容量の他端の電位を、前記第１の電位より低い第２の電位に設定することを特徴とする請求項５に記載の液晶表示装置。 The polarity of the potential difference with respect to the common electrode of the pixel electrode of the display pixel connected to each scanning line is set to a reverse polarity for each scanning line,
The voltage application means is configured to display the display connected to the scanning line in which the polarity of the potential difference is set to a positive polarity at a timing when the switching element of the display pixel connected to the next scanning line is turned on. A potential at the other end of the auxiliary capacitance of the display pixel connected to a scanning line in which the potential of the other end of the auxiliary capacitance of the pixel is set to a first potential and the polarity of the potential difference is set to a negative polarity. The liquid crystal display device according to claim 5, wherein the second potential is set to a second potential lower than the first potential. 前記電圧印加手段は、前記各走査線間に設けられ、出力端子が当該走査線に接続される前記表示画素の前記補助容量の他端に共通接続され、制御端子が当該走査線に接続され入力端子の電位を前記第１の電位及び前記第２の電位の一方に設定される第１のスイッチング素子と、制御端子が次段の走査線に接続され入力端子の電位を前記第１の電位及び前記第２の電位の他方に設定される第２のスイッチング素子と、を有し、前記電位差の極性が正極性に設定される走査線に接続される前記表示画素において、当該走査線に接続される前記表示画素の前記スイッチング素子がオン状態となるタイミングで、前記第１のスイッチング素子を介して当該表示画素の補助容量の他端の電位を前記第２の電位に設定し、次段の走査線に接続される前記表示画素の前記スイッチング素子がオン状態となるタイミングで、前記第２のスイッチング素子を介して当該表示画素の補助容量の他端の電位を前記第１の電位に設定し、
前記電位差の極性が負極性に設定される走査線に接続される前記表示画素において、当該走査線に接続される前記表示画素の前記スイッチング素子がオン状態となるタイミングで、前記第１のスイッチング素子を介して当該表示画素の補助容量の他端の電位を前記第１の電位に設定し、次段の走査線に接続される前記表示画素の前記スイッチング素子がオン状態となるタイミングで、前記第２のスイッチング素子を介して当該表示画素の補助容量の他端の電位を前記第２の電位に設定することを特徴とする請求項６に記載の液晶表示装置。 The voltage application means is provided between the scanning lines, and an output terminal is commonly connected to the other end of the auxiliary capacitor of the display pixel connected to the scanning line, and a control terminal is connected to the scanning line and input. A first switching element having a terminal potential set to one of the first potential and the second potential; a control terminal connected to a next scanning line; and a potential of an input terminal being the first potential and A second switching element that is set to the other of the second potentials, and the display pixel that is connected to a scanning line in which the polarity of the potential difference is set to positive polarity is connected to the scanning line. At the timing when the switching element of the display pixel is turned on, the potential of the other end of the auxiliary capacitor of the display pixel is set to the second potential via the first switching element, and the next scanning is performed. The table connected to the line At a timing when the switching element of a pixel is turned on, via the second switching element to set the potential of the other end of the auxiliary capacitor of the display pixel to the first potential,
In the display pixel connected to the scanning line in which the polarity of the potential difference is set to a negative polarity, the first switching element at a timing when the switching element of the display pixel connected to the scanning line is turned on. The potential at the other end of the auxiliary capacitor of the display pixel is set to the first potential via the first pixel, and the switching element of the display pixel connected to the next scanning line is turned on, The liquid crystal display device according to claim 6, wherein the potential of the other end of the auxiliary capacitor of the display pixel is set to the second potential via two switching elements. 互いに直交して配置された複数の走査線及び複数の信号線の各交点近傍にマトリクス状に配設され、スイッチング素子と該スイッチング素子の出力端に接続された画素電極と該画素電極に一端が接続された補助容量とを有する複数の表示画素と、前記各画素電極に対向して配設される共通電極と、を有する液晶パネルを備える液晶表示装置を駆動する駆動方法であって、
前記共通電極に一定電圧を印加する動作と、
前記走査線を選択して、選択された走査線に接続される前記表示画素の前記スイッチング素子をオン状態として前記画素電極を表示信号に基づく電位とする動作と、
前記走査線を非選択として、前記スイッチング素子をオン状態からオフ状態にした後、前記補助容量の他端に所定の電圧を印加して、前記画素電極と前記共通電極との電位差の絶対値を増加させる動作と、
を含むことを特徴とする液晶表示装置の駆動方法。 A switching element, a pixel electrode connected to the output end of the switching element, and one end of the pixel electrode are arranged in the vicinity of the intersections of the plurality of scanning lines and the plurality of signal lines arranged orthogonal to each other. A driving method for driving a liquid crystal display device including a liquid crystal panel having a plurality of display pixels having connected auxiliary capacitors and a common electrode disposed to face each of the pixel electrodes,
An operation of applying a constant voltage to the common electrode;
Selecting the scanning line, turning on the switching element of the display pixel connected to the selected scanning line, and setting the pixel electrode to a potential based on a display signal;
After deselecting the scanning line and switching the switching element from an on state to an off state, a predetermined voltage is applied to the other end of the auxiliary capacitor to obtain an absolute value of a potential difference between the pixel electrode and the common electrode. An increase in movement,
A method for driving a liquid crystal display device, comprising: 前記各走査線に接続される前記表示画素の画素電極の前記共通電極に対する電位差の極性は、前記各走査線毎に逆極性に設定され、
前記補助容量の他端に前記所定の電圧を印加する動作は、前記電位差の極性が正極性に設定される走査線に接続される前記表示画素の、前記補助容量の他端の電位を上昇させ、前記電位差の極性が負極性に設定される走査線に接続される前記表示画素の、前記補助容量の他端の電位を低下させる動作を含むことを特徴とする請求項８に記載の液晶表示装置の駆動方法。 The polarity of the potential difference with respect to the common electrode of the pixel electrode of the display pixel connected to each scanning line is set to a reverse polarity for each scanning line,
The operation of applying the predetermined voltage to the other end of the auxiliary capacitor raises the potential of the other end of the auxiliary capacitor of the display pixel connected to the scanning line in which the polarity of the potential difference is set to positive polarity. 9. The liquid crystal display according to claim 8, further comprising an operation of lowering the potential of the other end of the auxiliary capacitor of the display pixel connected to a scanning line in which the polarity of the potential difference is set to a negative polarity. Device driving method. 前記補助容量の他端に前記所定の電圧を印加する動作は、当該走査線が非選択とされた後、次段の走査線が選択されるまでの間のタイミングで行われることを特徴とする請求項８に記載の液晶表示装置の駆動方法。   The operation of applying the predetermined voltage to the other end of the auxiliary capacitor is performed at a timing after the scanning line is deselected and until the next scanning line is selected. The method for driving a liquid crystal display device according to claim 8. 前記補助容量の他端に前記所定の電圧を印加する動作は、次段の走査線が選択されるタイミングで行われることを特徴とする請求項８に記載の液晶表示装置の駆動方法。   9. The method of driving a liquid crystal display device according to claim 8, wherein the operation of applying the predetermined voltage to the other end of the auxiliary capacitor is performed at a timing when a next scanning line is selected. 前記各走査線に接続される前記表示画素の画素電極の前記共通電極に対する電位差の極性は、前記各走査線毎に逆極性に設定され、
前記補助容量の他端に前記所定の電圧を印加する動作は、前記電位差の極性が正極性に設定される走査線に接続される前記表示画素の、前記補助容量の他端を第１の電位に設定し、前記電位差の極性が負極性に設定される走査線に接続される前記表示画素の、前記補助容量の他端を、前記第１の電位より低い第２の電位に設定する動作を含むことを特徴とする請求項１１に記載の液晶表示装置の駆動方法。 The polarity of the potential difference with respect to the common electrode of the pixel electrode of the display pixel connected to each scanning line is set to a reverse polarity for each scanning line,
In the operation of applying the predetermined voltage to the other end of the auxiliary capacitor, the other end of the auxiliary capacitor of the display pixel connected to the scanning line in which the polarity of the potential difference is set to positive polarity is set to the first potential. And setting the other end of the auxiliary capacitor of the display pixel connected to the scanning line whose polarity of the potential difference is set to a negative polarity to a second potential lower than the first potential. The method for driving a liquid crystal display device according to claim 11, further comprising:
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