JP2006040995A - Wiring board and semiconductor device - Google Patents

Wiring board and semiconductor device Download PDF

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Publication number
JP2006040995A
JP2006040995A JP2004215278A JP2004215278A JP2006040995A JP 2006040995 A JP2006040995 A JP 2006040995A JP 2004215278 A JP2004215278 A JP 2004215278A JP 2004215278 A JP2004215278 A JP 2004215278A JP 2006040995 A JP2006040995 A JP 2006040995A
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Prior art keywords
wiring board
copper foil
main surface
chip
semiconductor device
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JP2004215278A
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Japanese (ja)
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Satoshi Chinda
聡 珍田
Hiroshi Sugimoto
洋 杉本
Kiyoshi Shimojima
清志 下嶋
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors

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Abstract

<P>PROBLEM TO BE SOLVED: To make the cracking hardly occur in a conductor pattern formed outside a bending region of a wiring board to be bent. <P>SOLUTION: The wiring board is such that conductor patterns 2A and 2B are formed on a first principal plane 1A and a second principal plane 1B of an insulating substrate 1, respectively. After mounting a plurality of semiconductor chips on the wiring board, the wiring board is bent to manufacture a semiconductor device with a multilayer structure of the semiconductor chips. Out of the conductor patterns formed on the individual principal planes, the one which faces outward when bending the wiring board is formed of rolled copper foil or electrolytic copper foil having a high flexibility. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、配線板及びその製造方法、ならびに半導体装置に関し、特に、配線板を折り曲げて前記配線板上に実装した半導体チップを積層する半導体装置に適用して有効な技術に関するものである。   The present invention relates to a wiring board, a method for manufacturing the same, and a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device in which a semiconductor chip is mounted by bending the wiring board and mounting the semiconductor chip on the wiring board.

従来、絶縁基板に導体パターンを設けた配線板（インターポーザ）に半導体チップを実装した半導体装置には、前記半導体チップを積層した半導体装置（以下、積層型半導体装置と称する。）がある。また、前記積層型装置には、例えば、１枚のインターポーザ上の複数の領域に半導体チップ等のチップ状部品を実装しておき、前記インターポーザを折り曲げて前記チップ状部品を積層した装置がある（例えば、特許文献１，特許文献２を参照。）。   Conventionally, a semiconductor device in which a semiconductor chip is mounted on a wiring board (interposer) provided with a conductor pattern on an insulating substrate includes a semiconductor device in which the semiconductor chip is stacked (hereinafter referred to as a stacked semiconductor device). In addition, the stacked device includes, for example, a device in which chip-shaped components such as semiconductor chips are mounted in a plurality of regions on one interposer, and the chip-shaped components are stacked by bending the interposer ( For example, see Patent Document 1 and Patent Document 2.)

前記積層型半導体装置は、積層する半導体チップの数の増加や、各半導体チップの高機能化，多ピン化が進んでいる。そのため、前記インターポーザ上の配線の数（密度）も増加する傾向にある。そこで、近年では、前記絶縁基板の第１主面及び第２主面の両面に導体パターンを設けたインターポーザを用いることが検討されている。   In the stacked semiconductor device, the number of semiconductor chips to be stacked is increasing, the functions of each semiconductor chip are increased, and the number of pins is increased. For this reason, the number (density) of wiring on the interposer also tends to increase. Therefore, in recent years, it has been studied to use an interposer in which conductor patterns are provided on both the first main surface and the second main surface of the insulating substrate.

前記絶縁基板の両面に導体パターンを設けたインターポーザは、例えば、ＬＧＡ（Land Grid Array）と呼ばれる形態の半導体装置のインターポーザ等に用いられる両面配線板を製造するときと同様の手順で製造することができる。すなわち、前記絶縁基板の両主面に導体膜を貼り合わせ、あらかじめ定められた位置に、各主面の導体膜を電気的に接続するビアやスルーホール等の層間接続導体を形成した後、前記各主面の導体膜をパターニングすればよい。   The interposer in which the conductor pattern is provided on both surfaces of the insulating substrate can be manufactured in the same procedure as that for manufacturing a double-sided wiring board used for an interposer of a semiconductor device called LGA (Land Grid Array), for example. it can. That is, after a conductor film is bonded to both main surfaces of the insulating substrate and an interlayer connection conductor such as a via or a through hole that electrically connects the conductor film on each main surface is formed at a predetermined position, What is necessary is just to pattern the conductor film of each main surface.

前記両面配線板（インターポーザ）を用いて、例えば、２個の半導体チップを積層した半導体装置を製造するときには、まず、例えば、図８（ａ）に示すように、第１チップ実装領域に第１半導体チップ３Ａを実装し、第２チップ実装領域に第２半導体チップ３Ｂを実装する。このとき、前記第１半導体チップ３Ａ及び第２半導体チップ３Ｂは、例えば、前記絶縁基板１の第１主面１Ａ側に実装する。また、前記各半導体チップ３Ａ，３Ｂの外部電極（図示しない）と前記第１主面１Ａ上の導体パターン（配線）２Ａは、金，はんだ接合材等のバンプ４で電気的に接続する。   For example, when manufacturing a semiconductor device in which two semiconductor chips are stacked using the double-sided wiring board (interposer), first, for example, as shown in FIG. The semiconductor chip 3A is mounted, and the second semiconductor chip 3B is mounted in the second chip mounting region. At this time, the first semiconductor chip 3A and the second semiconductor chip 3B are mounted on the first main surface 1A side of the insulating substrate 1, for example. The external electrodes (not shown) of the semiconductor chips 3A and 3B and the conductor pattern (wiring) 2A on the first main surface 1A are electrically connected by bumps 4 such as gold and solder bonding material.

次に、図８（ｂ）に示すように、前記第１チップ実装領域と前記第２チップ実装領域の間に設けられた折り曲げ領域を折り曲げて、前記第１半導体チップ３Ａと第２半導体チップ３Ｂを重ね合わせ、例えば、エポキシ樹脂等の接着材５で接着する。その後、図示は省略するが、前記各半導体チップ３Ａ，３Ｂの周囲を、封止材で封止する。   Next, as shown in FIG. 8B, the first semiconductor chip 3A and the second semiconductor chip 3B are bent by bending a bending area provided between the first chip mounting area and the second chip mounting area. Are bonded together with an adhesive 5 such as an epoxy resin. Thereafter, although not shown, the periphery of each of the semiconductor chips 3A and 3B is sealed with a sealing material.

このように、両面配線板を用いて前記積層型半導体装置を製造した場合、前記配線板の折り曲げ領域で外側を向く導体パターン、すなわち、前記絶縁基板１の第２主面１Ｂ側に設けられた導体パターン２Ｄには、折り曲げによる引っ張り応力が加わる。   As described above, when the stacked semiconductor device is manufactured using the double-sided wiring board, the conductive pattern facing outward in the folded region of the wiring board, that is, provided on the second main surface 1B side of the insulating substrate 1. A tensile stress due to bending is applied to the conductor pattern 2D.

前記両面配線板を製造するとき、前記絶縁基板１の各主面の導体パターン２Ａ，２Ｄは、一般に、電解銅箔を用いて形成している。前記電解銅箔は、その製造工程において、厚み方向に結晶組織が成長するので、厚み方向と垂直な方向への引っ張りに対する強度が低い。そのため、折り曲げ領域の外側を向く面、すなわち前記絶縁基板１の第２主面１Ｂ側に導体パターン２Ｄが設けられていると、図９に示すように、前記外側を向く導体パターン２Ｄにクラック６が入りやすいという問題がある。
特開２０００−３０７０３７号公報 特開２００１−７７２９４号公報 When the double-sided wiring board is manufactured, the conductor patterns 2A and 2D on each main surface of the insulating substrate 1 are generally formed using electrolytic copper foil. Since the crystal structure grows in the thickness direction in the manufacturing process, the electrolytic copper foil has a low strength against pulling in the direction perpendicular to the thickness direction. Therefore, when the conductor pattern 2D is provided on the surface facing the outside of the bent region, that is, on the second main surface 1B side of the insulating substrate 1, the conductor pattern 2D facing the outside is cracked 6 as shown in FIG. There is a problem that it is easy to enter.
JP 2000-3007037 A JP 2001-77294 A

本発明が解決しようとする問題点は、前記背景技術で説明したように、従来の折り曲げて用いる配線板では、折り曲げたときに、絶縁基板の折り曲げ領域の外側を向く面に導体パターンが設けられていると、前記外側の導体パターンにクラックが入りやすく、断線しやすいという点である。   The problem to be solved by the present invention is that, as described in the background art, in the conventional wiring board used by bending, a conductor pattern is provided on the surface facing the outside of the bent region of the insulating substrate when bent. In this case, the outer conductor pattern is easily cracked and easily disconnected.

本発明の目的は、折り曲げ加工をする配線板において、折り曲げ領域の外側に設けた導体パターンにクラックが入りにくくすることが可能な技術を提供することにある。   An object of the present invention is to provide a technique capable of preventing cracks from being formed in a conductor pattern provided outside a bent region in a wiring board that is bent.

本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本発明は、絶縁基板の第１主面及びその裏面（以下、第２主面と称する）に導体パターンが設けられてなり、前記絶縁基板のあらかじめ定められた領域を折り曲げて用いる配線板であって、前記各主面の導体パターンのうち、前記絶縁基板を折り曲げたときに外側を向く主面の導体パターンは、圧延銅箔又は高屈曲性の電解銅箔でなることを最も主要な特徴とする。このとき、内側を向く主面の導体パターンは、電解銅箔でなる導体パターンであってもよいし、他の導体箔あるいはめっきでなる導体パターンであってもよい。   The present invention is a wiring board in which a conductor pattern is provided on a first main surface and a back surface (hereinafter referred to as a second main surface) of an insulating substrate, and a predetermined region of the insulating substrate is bent and used. Among the conductor patterns of each main surface, the main feature is that the conductor pattern of the main surface facing outward when the insulating substrate is bent is made of a rolled copper foil or a highly flexible electrolytic copper foil. To do. At this time, the conductor pattern of the main surface facing inward may be a conductor pattern made of electrolytic copper foil, or may be another conductor foil or a conductor pattern made of plating.

本発明の配線板は、前記絶縁基板を折り曲げたときに、外側を向く主面の導体パターンは、圧延銅箔又は高屈曲性の電解銅箔を用いて形成している。前記圧延銅箔は、一般的な電解銅箔よりも展延性に富む。そこで、折り曲げたときに外側を向く面の導体パターンを前記圧延銅箔で形成すれば、折り曲げ加工により、折り曲げる領域の導体パターンに厚み方向と直交する方向の引っ張り応力が加わってもクラックが入りにくい。そのため、前記絶縁基板の外側を向く主面の折り曲げ領域にも導体パターンを設けることができ、導体パターンの数の増加に対応しやすくなる。前記導体パターンの数の増加に対応しやすくなれば、実装する半導体チップの高機能化（多ピン化）に対応しやすくなる。また、その他にも、例えば、実装する半導体チップの数の増加にも対応しやすくなるので、半導体チップの多層化に対応しやすい。これらのことから、積層型半導体装置の高機能化、小型化が容易になる。   In the wiring board of the present invention, when the insulating substrate is bent, the conductor pattern on the main surface facing outward is formed using a rolled copper foil or a highly flexible electrolytic copper foil. The rolled copper foil is more extensible than a general electrolytic copper foil. Therefore, if the rolled copper foil is used to form a conductor pattern that faces outward when bent, cracks are less likely to occur even if a tensile stress in the direction perpendicular to the thickness direction is applied to the conductor pattern in the bending region by bending. . Therefore, a conductor pattern can also be provided in the bent region of the main surface facing the outside of the insulating substrate, and it becomes easy to cope with an increase in the number of conductor patterns. If it becomes easy to cope with the increase in the number of the conductor patterns, it becomes easy to cope with higher functionality (multiple pins) of the semiconductor chip to be mounted. In addition, for example, since it becomes easy to cope with an increase in the number of semiconductor chips to be mounted, it is easy to deal with the multi-layered semiconductor chips. For these reasons, it is easy to increase the functionality and size of the stacked semiconductor device.

また、前記積層型半導体装置の高機能化、小型化とは別に、前記外側を向く主面の導体パターンを、グラウンド電位あるいは電源電位のベタパターンにすれば、折り曲げた領域も含めたマイクロストリップになる。そのため、実装する半導体装置が高周波動作をする場合でも、高周波特性が劣化することを防げる。このことから、前記積層型半導体装置の動作の高速化（高周波化）が容易になる。   In addition to the enhancement and miniaturization of the stacked semiconductor device, if the conductor pattern on the main surface facing outward is a solid pattern of ground potential or power supply potential, the microstrip including the bent region can be formed. Become. Therefore, even when the semiconductor device to be mounted operates at a high frequency, the high frequency characteristics can be prevented from deteriorating. This facilitates high speed operation (high frequency) of the stacked semiconductor device.

以下、本発明について、図面を参照して実施の形態（実施例）とともに詳細に説明する。   Hereinafter, the present invention will be described in detail together with embodiments (examples) with reference to the drawings.

なお、実施例を説明するための全図において、同一機能を有するものは、同一符号を付け、その繰り返しの説明は省略する。   In all the drawings for explaining the embodiments, parts having the same function are given the same reference numerals and their repeated explanation is omitted.

本発明の配線板は、半導体チップ等のチップ状の部品を実装したあと、折り曲げて、前記チップ状の部品を積層する半導体装置を製造するときに用いる配線板である。このとき、絶縁基板の、折り曲げたときに外側を向く主面の導体パターンを圧延銅箔又は高屈曲性の電解銅箔で設けることで、外側を向く主面の折り曲げ領域に設けた導体パターンにクラックが入りにくくする。   The wiring board of the present invention is a wiring board used when manufacturing a semiconductor device in which a chip-shaped component such as a semiconductor chip is mounted and then bent to stack the chip-shaped component. At this time, by providing the conductive pattern of the main surface facing the outside when the insulating substrate is bent with the rolled copper foil or the highly flexible electrolytic copper foil, the conductive pattern provided in the bent region of the main surface facing the outside Makes cracks difficult.

図１は、本発明による実施例１の配線板の概略構成を示す模式図である。   FIG. 1 is a schematic diagram illustrating a schematic configuration of a wiring board according to a first embodiment of the present invention.

図１において、１は絶縁基板、１Ａは絶縁基板の第１主面、１Ｂは絶縁基板の第２主面、２Ａは第１導体パターン（電解銅）、２Ｂは第２導体パターン（圧延銅）、２Ｃは層間接続導体である。   In FIG. 1, 1 is an insulating substrate, 1A is a first main surface of the insulating substrate, 1B is a second main surface of the insulating substrate, 2A is a first conductor pattern (electrolytic copper), and 2B is a second conductor pattern (rolled copper). Reference numeral 2C denotes an interlayer connection conductor.

本実施例１の配線板は、図１に示すように、絶縁基板１の第１主面１Ａに第１導体パターン２Ａが設けられ、前記第１主面１Ａの裏面（以下、第２主面と称する）１Ｂに第２導体パターン２Ｂが設けられている。このとき、前記第１導体パターン２Ａと前記第２導体パターン２Ｂは、図１に示したように、あらかじめ定められた位置で、ビアやスルーホール等の層間接続導体２Ｃにより電気的に接続されている。   As shown in FIG. 1, the wiring board of the first embodiment is provided with a first conductor pattern 2A on the first main surface 1A of the insulating substrate 1, and the back surface of the first main surface 1A (hereinafter referred to as the second main surface). 1B) is provided with a second conductor pattern 2B. At this time, as shown in FIG. 1, the first conductor pattern 2A and the second conductor pattern 2B are electrically connected by an interlayer connection conductor 2C such as a via or a through hole at a predetermined position. Yes.

また、本実施例１の配線板は、複数個の半導体チップを積層させた積層型の半導体装置を製造するときに用いられる配線板であり、例えば、図１に示すように、第１チップ実装領域，第２チップ実装領域，折り曲げ領域の３つの領域に分けられている。このとき、前記第１チップ実装領域及び前記第２チップ実装領域は、半導体チップ、あるいは容量素子や抵抗素子等のチップ状の電子部品を実装する領域である。また、前記第１チップ実装領域の導体パターンと、前記第２チップ実装領域の導体パターンとは、前記折り曲げ領域を通して電気的に接続されている。   The wiring board of the first embodiment is a wiring board used when manufacturing a stacked semiconductor device in which a plurality of semiconductor chips are stacked. For example, as shown in FIG. The region is divided into three regions: a region, a second chip mounting region, and a bending region. At this time, the first chip mounting region and the second chip mounting region are regions for mounting a semiconductor chip or a chip-shaped electronic component such as a capacitor element or a resistance element. The conductor pattern in the first chip mounting area and the conductor pattern in the second chip mounting area are electrically connected through the bent area.

また、本実施例１の配線板は、前記第１導体パターン２Ａが電解銅箔でなり、前記第２導体パターン２Ｂが圧延銅でなる。   In the wiring board of the first embodiment, the first conductor pattern 2A is made of electrolytic copper foil, and the second conductor pattern 2B is made of rolled copper.

本実施例１の配線板は、従来の、ＬＧＡと呼ばれる形態の半導体装置等で用いられる両面配線板と同様の手順で製造することができる。そのため、詳細な説明は省略し、手順のみを簡単に説明する。   The wiring board of the first embodiment can be manufactured in the same procedure as a conventional double-sided wiring board used in a semiconductor device having a form called LGA. Therefore, detailed description is omitted and only the procedure is briefly described.

本実施例１の配線板を製造するときには、例えば、まず、前記絶縁基板１の第１主面１Ａに電解銅箔を貼り合わせ、第２主面１Ｂに圧延銅箔を貼り合わせる。次に、前記絶縁基板のあらかじめ定められた位置に開口部を形成し、前記電解銅箔と圧延銅箔を電気的に接続するビアやスルーホール等の層間接続導体２Ｃを形成する。その後、前記電解銅箔及び圧延銅箔の不要な部分を除去して第１導体パターン２Ａ及び第２導体パターン２Ｂを形成する。そして、必要に応じて、前記第１導体パターン２Ａ及び第２導体パターン２Ｂの表面に、金めっき，すずめっき等の機能めっきや、はんだ保護膜等の保護膜を形成する。   When manufacturing the wiring board of the first embodiment, for example, first, an electrolytic copper foil is bonded to the first main surface 1A of the insulating substrate 1, and a rolled copper foil is bonded to the second main surface 1B. Next, an opening is formed at a predetermined position of the insulating substrate, and an interlayer connection conductor 2C such as a via or a through hole for electrically connecting the electrolytic copper foil and the rolled copper foil is formed. Thereafter, unnecessary portions of the electrolytic copper foil and the rolled copper foil are removed to form the first conductor pattern 2A and the second conductor pattern 2B. Then, if necessary, a functional film such as gold plating or tin plating or a protective film such as a solder protective film is formed on the surfaces of the first conductor pattern 2A and the second conductor pattern 2B.

図２及び図３は、本実施例１の配線板を用いた半導体装置の製造方法の一例を説明するための模式図であり、図２（ａ）は半導体チップを実装する工程の図、図２（ｂ）は半導体チップを積層する工程の図である。   2 and 3 are schematic views for explaining an example of a manufacturing method of a semiconductor device using the wiring board of the first embodiment, and FIG. 2A is a diagram of a process for mounting a semiconductor chip. FIG. 2B is a diagram of a process of stacking semiconductor chips.

図２（ａ）及び図２（ｂ）において、３Ａは第１半導体チップ、３０１Ａは第１半導体チップの非回路形成面、３Ｂは第２半導体チップ、３０１Ｂは第２半導体チップの非回路形成面、４はバンプ、５は接着材である。   2A and 2B, 3A is a first semiconductor chip, 301A is a non-circuit formation surface of the first semiconductor chip, 3B is a second semiconductor chip, and 301B is a non-circuit formation surface of the second semiconductor chip. 4 is a bump, and 5 is an adhesive.

本実施例１の配線板を用いて半導体装置を製造するときには、例えば、図２（ａ）に示すように、前記配線板の第１チップ実装領域及び第２チップ実装領域のそれぞれに、第１半導体チップ３Ａ及び第２半導体チップ３Ｂを実装する。このとき、前記第１半導体チップ３Ａ及び第２半導体チップ３Ｂは、前記絶縁基板１の第１主面１Ａ側、すなわち、電解銅でなる前記第１導体パターン２Ａが設けられた面に実装する。またこのとき、前記第１半導体チップ３Ａ及び前記第２半導体チップ３Ｂの外部電極（図示しない）には、金，はんだ接合材等でなるバンプ４を形成しておく。   When a semiconductor device is manufactured using the wiring board according to the first embodiment, for example, as shown in FIG. 2A, the first chip mounting area and the second chip mounting area of the wiring board are each provided with the first chip mounting area. The semiconductor chip 3A and the second semiconductor chip 3B are mounted. At this time, the first semiconductor chip 3A and the second semiconductor chip 3B are mounted on the first main surface 1A side of the insulating substrate 1, that is, on the surface provided with the first conductor pattern 2A made of electrolytic copper. At this time, bumps 4 made of gold, solder joint material or the like are formed on the external electrodes (not shown) of the first semiconductor chip 3A and the second semiconductor chip 3B.

次に、図２（ｂ）に示すように、前記配線板の折り曲げ領域を、前記絶縁基板１の第１主面１Ａが向かい合うように折り曲げて、前記第１半導体チップ３Ａの非回路形成面３０１Ａと前記第２半導体チップ３０１の非回路形成面３０１Ｂを向かい合わせる。このとき、前記第１半導体チップ３Ａと前記第２半導体チップ３Ｂは、例えば、図２（ｂ）に示したように、エポキシ樹脂等の接着材５で接着する。その後、図示は省略するが、前記半導体チップの周囲をエポキシ樹脂等の封止材で封止すると、積層型の半導体装置が得られる。   Next, as shown in FIG. 2 (b), the bent region of the wiring board is bent so that the first main surface 1A of the insulating substrate 1 faces the non-circuit forming surface 301A of the first semiconductor chip 3A. And the non-circuit forming surface 301B of the second semiconductor chip 301 face each other. At this time, the first semiconductor chip 3A and the second semiconductor chip 3B are bonded with an adhesive 5 such as an epoxy resin as shown in FIG. 2B, for example. Thereafter, although illustration is omitted, when the periphery of the semiconductor chip is sealed with a sealing material such as epoxy resin, a stacked semiconductor device is obtained.

なお、前記第１半導体チップ３Ａと前記第２半導体チップ３Ｂは、前記接着材５で接着せずに、前記封止材で接着固定してもよい。また、必要に応じて、例えば、前記第１チップ実装領域の第２導体パターン２Ｂ上に、はんだ接合材でなるボール状の外部端子を形成してもよい。   The first semiconductor chip 3 </ b> A and the second semiconductor chip 3 </ b> B may be bonded and fixed with the sealing material without being bonded with the bonding material 5. In addition, for example, a ball-shaped external terminal made of a solder bonding material may be formed on the second conductor pattern 2B in the first chip mounting region as necessary.

図３は、本実施例１の配線板の作用効果を説明するための模式図である。   FIG. 3 is a schematic diagram for explaining the function and effect of the wiring board according to the first embodiment.

本実施例１の配線板を用いて、図２（ｂ）に示したような積層型の半導体装置を製造した場合、前記折り曲げ領域で、絶縁基板１の外側を向く面、すなわち前記第２主面１Ｂに設けられた第２導体パターン２Ｂには、折り曲げによる引っ張り応力が加わる。そのため、電解銅箔のように、厚み方向に結晶組織が成長する導体箔を用いて前記第２導体パターン２Ｂを形成すると、クラックが入りやすい。   When a laminated semiconductor device as shown in FIG. 2B is manufactured using the wiring board of the first embodiment, the surface facing the outside of the insulating substrate 1 in the bent region, that is, the second main device. A tensile stress due to bending is applied to the second conductor pattern 2B provided on the surface 1B. Therefore, if the second conductor pattern 2B is formed using a conductor foil in which a crystal structure grows in the thickness direction, such as an electrolytic copper foil, cracks are likely to occur.

一方、前記圧延銅箔は、圧延直後の厚み方向に層状に積層した結晶組織であるが、その後の加熱処理（アニール）により、図３に示すように、等方的な結晶組織を呈する。本実施例１の配線板のように、圧延銅箔を用いて前記第２導体パターン２Ｂを形成することで、前記第２導体パターン２Ｂにクラックが入りにくくなる。   On the other hand, the rolled copper foil has a crystal structure laminated in layers in the thickness direction immediately after rolling, and exhibits an isotropic crystal structure as shown in FIG. 3 by subsequent heat treatment (annealing). By forming the second conductor pattern 2B using a rolled copper foil as in the wiring board of the first embodiment, cracks are less likely to occur in the second conductor pattern 2B.

以上説明したように、本実施例１の配線板によれば、折り曲げたときに、折り曲げ領域で、絶縁基板１の外側を向く面に設けられた導体パターンにクラックが入りにくくすることができる。   As described above, according to the wiring board of the first embodiment, when bent, the conductor pattern provided on the surface facing the outside of the insulating substrate 1 can be prevented from cracking in the bent region.

また、折り曲げ領域で外側を向く導体パターンにクラックが入りにくくなるので、前記折り曲げ領域の外側を向く面にも導体パターンを設けることができ、導体パターンの数の増加に対応しやすくなる。そのため、実装する半導体チップの高機能化（多ピン化）に対応しやすくなり、前記積層型半導体装置の高機能化が容易になる。   Further, since it is difficult for cracks to be formed in the conductor pattern facing outward in the bent region, a conductor pattern can be provided on the surface facing outward of the bent region, and it becomes easy to cope with an increase in the number of conductor patterns. For this reason, it becomes easy to cope with an increase in the function (multiple pins) of a semiconductor chip to be mounted, and an increase in the function of the stacked semiconductor device is facilitated.

図４及び図５は、前記実施例１の配線板を用いた半導体装置の製造方法の応用例を説明するための模式図であり、図４（ａ）は半導体チップを実装する工程の図、図４（ｂ）は第１折り曲げ工程の図、図５は第２折り曲げ工程の図である。   4 and 5 are schematic views for explaining an application example of the method of manufacturing a semiconductor device using the wiring board of the first embodiment, and FIG. 4A is a diagram of a process of mounting a semiconductor chip. FIG. 4B is a diagram of the first folding process, and FIG. 5 is a diagram of the second folding process.

前記実施例１では、図１に示したように、折り曲げ領域が１箇所の配線板及びその配線板を用いた半導体装置の製造方法を例に挙げたが、これに限らず、折り曲げ領域が複数箇所に設けられている配線板であってもよい。   In the first embodiment, as shown in FIG. 1, a wiring board having a single bending region and a method of manufacturing a semiconductor device using the wiring board are described as an example. The wiring board provided in the location may be sufficient.

ここでは、例えば、図４（ａ）に示すように、第１チップ実装領域，第２チップ実装領域，第３チップ実装領域，第１折り曲げ領域，第２折り曲げ領域の５つの領域に分けられる配線板を用いて、前記積層型半導体装置を製造する方法について説明する。   Here, for example, as shown in FIG. 4 (a), the wiring is divided into five areas: a first chip mounting area, a second chip mounting area, a third chip mounting area, a first bent area, and a second bent area. A method for manufacturing the stacked semiconductor device using a plate will be described.

前記５つの領域からなる配線板を用いて、積層型の半導体装置を製造するときには、まず、図４（ａ）に示すように、前記第１チップ実装領域，第２チップ実装領域，第３チップ実装領域のそれぞれに第１半導体チップ３Ａ，第２半導体チップ３Ｂ，第３半導体チップ３Ｃを実装する。このとき、前記各半導体チップ３Ａ，３Ｂ，３Ｃは、前記実施例１で説明したように、電解銅箔で形成された第１導体パターン２Ａが形成された面、すなわち前記絶縁基板１の第１主面１Ａ側に実装する。   When a stacked semiconductor device is manufactured using the wiring board having the five regions, first, as shown in FIG. 4A, the first chip mounting region, the second chip mounting region, and the third chip are used. The first semiconductor chip 3A, the second semiconductor chip 3B, and the third semiconductor chip 3C are mounted in each of the mounting regions. At this time, each semiconductor chip 3A, 3B, 3C has a surface on which the first conductor pattern 2A formed of electrolytic copper foil is formed, that is, the first of the insulating substrate 1, as described in the first embodiment. Mount on the main surface 1A side.

次に、例えば、図４（ｂ）に示すように、前記第２折り曲げ領域を折り曲げて、前記第２半導体チップ３Ｂと前記第３半導体チップ３Ｃを積層する。このとき、前記第２折り曲げ領域は、前記絶縁基板１の第１主面１Ａが向かい合うように、すなわち前記第２導体パターン２Ｂが外側を向くように折り曲げる。   Next, for example, as shown in FIG. 4B, the second bent region is bent to stack the second semiconductor chip 3B and the third semiconductor chip 3C. At this time, the second bent region is bent so that the first main surface 1A of the insulating substrate 1 faces, that is, the second conductor pattern 2B faces outward.

その後、図５に示すように、前記第１折り曲げ領域を折り曲げて、すでに積層された前記第２半導体チップ３Ｂ及び第３半導体チップ３Ｃと、前記第１半導体チップ３Ａを積層する。このとき、前記第１折り曲げ領域も、図５に示したように、前記第２導体パターン２Ｂが外側を向くように折り曲げれば、前記第１折り曲げ領域及び前記第２折り曲げ領域ともに、圧延銅でなる第２導体パターン２Ｂが外側を向く。そのため、折り曲げによる引っ張り応力が加わってもクラックが入りにくい。   After that, as shown in FIG. 5, the first bent region is bent, and the second semiconductor chip 3B and the third semiconductor chip 3C that have already been stacked, and the first semiconductor chip 3A are stacked. At this time, as shown in FIG. 5, if the second conductor pattern 2B is bent so that it faces outward, both the first bent region and the second bent region are made of rolled copper. The second conductor pattern 2B is directed outward. Therefore, even if tensile stress due to bending is applied, cracks are unlikely to occur.

このように、前記実施例１の配線板は、半導体チップを３層に積層するときにも適用することができる。また、詳細な説明は省略するが、４層以上に積層する場合も、同様の手法で積層することができる。   Thus, the wiring board of Example 1 can also be applied when semiconductor chips are stacked in three layers. Although a detailed description is omitted, the same technique can be used for stacking four or more layers.

また、図２（ａ）及び図４（ａ）では、１つのチップ実装領域に１個の半導体チップを実装する例を挙げているが、これに限らず、１つのチップ実装領域に、２個以上の半導体チップ，あるいは容量素子や抵抗素子等のチップ状の電子部品を実装してもよいことは言うまでもない。   2A and 4A show an example in which one semiconductor chip is mounted on one chip mounting area, but the present invention is not limited to this, and two chips are mounted on one chip mounting area. Needless to say, the above-described semiconductor chip or chip-shaped electronic components such as a capacitive element and a resistive element may be mounted.

図６は、前記実施例１の配線板の応用例を説明するための模式図である。   FIG. 6 is a schematic diagram for explaining an application example of the wiring board of the first embodiment.

前記実施例１では、例えば、前記絶縁基板の第２主面側にも信号配線を設けることで、半導体チップの高機能化に伴う導体パターンの増加に対応しやすくする例について説明している。   In the first embodiment, for example, a signal wiring is also provided on the second main surface side of the insulating substrate to facilitate an increase in the number of conductor patterns accompanying an increase in the functionality of the semiconductor chip.

しかしながら、前記積層型の半導体装置では、高機能化とは別に、例えば、動作の高速化（高周波化）の要請も高まっている。そこで、例えば、図６に示すように、第１導体パターン２Ａは信号導体とし、第２導体パターン２Ｂの一部をグラウンド電位あるいは電源電位等のベタパターンにすれば、マイクロストリップになり、高周波特性の劣化を低減することができる。この場合も、折り曲げ領域で外側を向く第２導体パターン（ベタパターン）に圧延銅箔を用いていれば、折り曲げたときにクラックが入ってマイクロストリップの効果が低減することを防げる。   However, in the stacked semiconductor device, in addition to high functionality, for example, there is an increasing demand for high speed operation (high frequency). Therefore, for example, as shown in FIG. 6, if the first conductor pattern 2A is a signal conductor and a part of the second conductor pattern 2B is a solid pattern such as a ground potential or a power supply potential, a microstrip is formed, and high frequency characteristics are obtained. Can be reduced. Also in this case, if the rolled copper foil is used for the second conductor pattern (solid pattern) facing outward in the folding region, it is possible to prevent cracks from entering and reducing the effect of the microstrip.

図７は、本発明による実施例２の半導体装置の製造方法を説明するための模式図であり、図７（ａ）は半導体チップを実装する工程の図、図７（ｂ）は半導体チップを積層する工程の図である。   FIGS. 7A and 7B are schematic views for explaining a method of manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 7A is a diagram of a process for mounting a semiconductor chip, and FIG. It is a figure of the process to laminate | stack.

前記実施例１では、前記配線板を用いて積層型の半導体装置を製造するときに、図４（ａ）に示したように、前記第１チップ実装領域及び第２チップ実装領域ともに、前記絶縁基板１の第１主面１Ａ側のみに半導体チップ３Ａ，３Ｂを実装する例を挙げて説明した。しかしながら、本発明の配線板のように、前記絶縁基板１の両主面１Ａ，１Ｂに導体パターン２Ａ，２Ｂが設けられている場合、前記第１主面１Ａ側だけでなく、前記第２主面１Ｂ側にも半導体チップ３Ｃを実装することができる。   In the first embodiment, when a stacked semiconductor device is manufactured using the wiring board, both the first chip mounting area and the second chip mounting area are both insulated as shown in FIG. The example in which the semiconductor chips 3A and 3B are mounted only on the first main surface 1A side of the substrate 1 has been described. However, when the conductor patterns 2A and 2B are provided on both main surfaces 1A and 1B of the insulating substrate 1 as in the wiring board of the present invention, not only the first main surface 1A side but also the second main surface 1A. The semiconductor chip 3C can also be mounted on the surface 1B side.

つまり、前記配線板を製造するときに、例えば、前記第２チップ実装領域の第２主面１Ｂ側に、半導体チップの外部電極と接続するためのパッドを形成しておけば、図７（ａ）に示すように、前記第１チップ実装領域の第１主面１Ａ側に第１半導体チップ３Ａ、前記第２チップ実装領域の第１主面１Ａ側に第２半導体チップ３Ｂ、前記第２チップ実装領域の第２主面１Ｂ側に第３半導体チップ３Ｃを実装することができる。   That is, when the wiring board is manufactured, for example, if a pad for connecting to the external electrode of the semiconductor chip is formed on the second main surface 1B side of the second chip mounting region, FIG. ), The first semiconductor chip 3A on the first main surface 1A side of the first chip mounting region, the second semiconductor chip 3B on the first main surface 1A side of the second chip mounting region, and the second chip The third semiconductor chip 3C can be mounted on the second main surface 1B side of the mounting region.

このように、前記第１半導体チップ３Ａ，前記第２半導体チップ３Ｂ，前記第３半導体チップ３Ｃを実装した後、前記実施例１で説明したように、前記配線板（絶縁基板１）の第１主面１Ａが向かい合うように折り曲げれば、図７（ｂ）に示すように、３つの半導体チップ３Ａ，３Ｂ，３Ｃが３層に積層された半導体装置を得ることができる。このとき、前記配線板の折り曲げ領域で外側を向く第２導体パターン２Ｂが圧延銅であれば、折り曲げによる引っ張り応力が加わっても、クラックが入りにくい。   Thus, after mounting the first semiconductor chip 3A, the second semiconductor chip 3B, and the third semiconductor chip 3C, as described in the first embodiment, the first of the wiring board (insulating substrate 1). If the main surface 1A is bent so as to face each other, as shown in FIG. 7B, a semiconductor device in which three semiconductor chips 3A, 3B, 3C are stacked in three layers can be obtained. At this time, if the second conductor pattern 2B facing outward in the bent region of the wiring board is rolled copper, even if tensile stress due to bending is applied, cracks are unlikely to occur.

従来、１枚の配線板を折り曲げて３個の半導体チップを３層に積層するときには、例えば、図４（ａ）及び図４（ｂ）に示したように、前記配線板の第１主面１Ａ側に３個の半導体チップ３Ａ，３Ｂ，３Ｃを実装し、２カ所を折り曲げて積層することが多かった。この場合、前記配線板には、３カ所のチップ実装領域と２カ所の折り曲げ領域が必要であり、配線板の面積が大型化してしまう。   Conventionally, when one wiring board is bent and three semiconductor chips are stacked in three layers, for example, as shown in FIGS. 4A and 4B, the first main surface of the wiring board is used. In many cases, three semiconductor chips 3A, 3B, and 3C are mounted on the 1A side, and the two portions are bent and stacked. In this case, the wiring board requires three chip mounting areas and two bending areas, which increases the area of the wiring board.

一方、本実施例２の半導体装置の製造方法では、チップ実装領域が２カ所で折り曲げ領域が１カ所の配線板で、３個の半導体チップ３Ａ，３Ｂ，３Ｃを３層に積層することができる。そのため、前記積層型半導体装置に用いる配線板の製造コストの低コスト化、前記積層型半導体装置の薄型化が容易になる。   On the other hand, in the method of manufacturing the semiconductor device according to the second embodiment, three semiconductor chips 3A, 3B, and 3C can be stacked in three layers by using a wiring board having two chip mounting regions and one bending region. . Therefore, it is easy to reduce the manufacturing cost of the wiring board used in the stacked semiconductor device and to reduce the thickness of the stacked semiconductor device.

以上説明したように、本実施例２の配線板によれば、折り曲げたときに絶縁基板の外側を向く面の導体パターンを圧延銅箔で設けることにより、外側の導体パターンにクラックが入りにくくすることができる。   As explained above, according to the wiring board of the second embodiment, the outer conductive pattern is less likely to be cracked by providing the conductive pattern on the surface facing the outside of the insulating substrate with the rolled copper foil when bent. be able to.

また、前記配線板の両主面に導体パターンを設けることができるので、導体パターンの数の増加に対応しやすくなり、前記配線板を用いた半導体装置の高機能化が容易になる。   In addition, since conductor patterns can be provided on both main surfaces of the wiring board, it becomes easy to cope with an increase in the number of conductor patterns, and it becomes easy to enhance the functionality of a semiconductor device using the wiring board.

また、前記配線板の両主面に半導体チップを実装することが可能になるので、前記配線板を用いた半導体装置の薄型化が容易になる。   In addition, since semiconductor chips can be mounted on both main surfaces of the wiring board, it is easy to reduce the thickness of a semiconductor device using the wiring board.

また、図７では、３個の半導体チップを３層に積層する場合の例を示したが、これに限らず、４個以上の半導体チップを３層以上に積層するときにも、同様の手法を適用することができることは言うまでもない。   FIG. 7 shows an example in which three semiconductor chips are stacked in three layers. However, the present invention is not limited to this, and the same technique can be used when four or more semiconductor chips are stacked in three or more layers. It goes without saying that can be applied.

また、本実施例２のような半導体装置を製造するときにも、前記各チップ実装領域の各実装面には、１つの実装面に１個の半導体チップを実装する場合に限らず、１つの実装面に複数個の半導体チップやチップ状の受動部品を実装してもよいことは言うまでもない。   Further, when a semiconductor device as in the second embodiment is manufactured, each mounting surface of each chip mounting region is not limited to the case where one semiconductor chip is mounted on one mounting surface. It goes without saying that a plurality of semiconductor chips and chip-like passive components may be mounted on the mounting surface.

また、実施例１および２で適用した圧延銅箔を、高屈曲性を加味して開発された電解銅箔に置き換えてもよい。一般に電解銅箔は厚み方向に結晶が成長するので、銅の結晶組織が柱状になりやすい。そのため、折り曲げた際に結晶粒界が機械的に破断しやすく、屈曲性の悪さが指摘されている。そこで、銅めっき液の添加剤や電析条件を変更し、柱状組織とならないようにコントロールした高屈曲性の電解銅箔が開発されている。一例を挙げると、グールドエレクトロニクス社（米国）のＪＴＣＤＦ箔である。この銅箔は、柱状晶の生成が少なく、また折り曲げ試験において、従来の電解銅箔よりもクラック発生までの時間が長く、屈曲性に優れている。   Moreover, you may replace the rolled copper foil applied in Example 1 and 2 with the electrolytic copper foil developed considering the high flexibility. In general, since an electrolytic copper foil grows in the thickness direction, the copper crystal structure tends to be columnar. For this reason, it is pointed out that the crystal grain boundaries are easily broken mechanically when bent, and that the flexibility is poor. Therefore, a highly flexible electrolytic copper foil that has been controlled so as not to have a columnar structure by changing the additive and electrodeposition conditions of the copper plating solution has been developed. An example is JTCDF foil from Gould Electronics (USA). This copper foil produces less columnar crystals, and in the bending test, it takes a longer time to generate a crack than the conventional electrolytic copper foil, and is excellent in flexibility.

表１は、ＪＩＳ Ｃ５０１６におけるの規格に準拠したＭＩＴ耐折試験の結果を表したものである。より具体的には、ＪＩＳ Ｃ５０１６−１９９４の「８．７．１ 装置」の欄の図１４に示すような耐折性試験機を使用して測定した。図１４に示されている導線は試材の断線を検知するためのものであり、予め試材に通電しておき、曲げ部にクラックが入り電気的導通が遮断されると、耐折性試験機の振り子運動が停止する。表１に示された数値は、その振り子運動が停止するまでの往復回数を破断回数として表示している。測定条件は、先端半径Ｒ＝０．３８mm、開きＴ＝０．２５mm、左右への折り曲げ角度が夫々１３５°（全体で２７０°）、折り曲げ速度が１７５ｃｐｍである。この表１の結果によると、厚さ１２μｍの高耐折性圧延銅箔を用いた本実施形態に係る試材Ｎｏ.１の場合、および厚さ１２μｍの高耐折性電解銅箔を用いた本実施形態に係る試材Ｎｏ.２の場合については、夫々８１回目、７０回目に耐折性試験機によって破断に至ったことから、良好な耐屈曲性があることがわかる。これに対し、厚さ１２μｍの従来の圧延銅箔を用いた従来例に係る試材Ｎｏ.３の場合、および厚さ１２μｍの従来の電解銅箔を用いた従来例に係る試材Ｎｏ.４の場合については、夫々４４回目、３８回目に耐折性試験機によって破断に至ったことから、所望の耐屈曲性を得ることができないことがわかる。

Figure 2006040995
以上、本発明を、前記実施例に基づき具体的に説明したが、本発明は、前記実施例に限定されるものではなく、その要旨を逸脱しない範囲において、種々変更可能であることはもちろんである。 Table 1 shows the result of the MIT folding endurance test based on the standard of JIS C5016. More specifically, the measurement was performed using a fold resistance tester as shown in FIG. 14 in the column “8.7.1 device” of JIS C5016-1994. The conductor shown in FIG. 14 is for detecting disconnection of the specimen. When the specimen is energized in advance and a crack occurs in the bent portion and electrical conduction is cut off, the bending resistance test is performed. The pendulum movement of the machine stops. The numerical values shown in Table 1 indicate the number of reciprocations until the pendulum motion stops as the number of breaks. The measurement conditions are a tip radius R = 0.38 mm, an opening T = 0.25 mm, a lateral bending angle of 135 ° (total 270 °), and a bending speed of 175 cpm. According to the results of Table 1, in the case of the sample No. 1 according to the present embodiment using the high folding resistance rolled copper foil having a thickness of 12 μm, the high folding resistance electrolytic copper foil having a thickness of 12 μm was used. In the case of sample No. 2 according to the present embodiment, it was found that there was good bending resistance because it was broken at the 81st and 70th times by the folding resistance tester. On the other hand, in the case of the sample No. 3 according to the conventional example using the conventional rolled copper foil having a thickness of 12 μm, and the sample No. 4 according to the conventional example using the conventional electrolytic copper foil having a thickness of 12 μm. In the case of, it was found that the desired bending resistance could not be obtained because the rupture resistance tester led to breakage at the 44th and 38th times, respectively.
Figure 2006040995
 The present invention has been specifically described above based on the above-described embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. is there.

本発明による実施例１の配線板の概略構成を示す模式図である。It is a schematic diagram which shows schematic structure of the wiring board of Example 1 by this invention. 本実施例１の配線板を用いた半導体装置の製造方法の一例を説明するための模式図であり、図２（ａ）は半導体チップを実装する工程の図、図２（ｂ）は半導体チップを積層する工程の図である。FIGS. 2A and 2B are schematic views for explaining an example of a manufacturing method of a semiconductor device using the wiring board of Example 1, FIG. 2A is a diagram of a process of mounting a semiconductor chip, and FIG. 2B is a semiconductor chip. It is a figure of the process of laminating | stacking. 本実施例１の配線板の作用効果を説明するための図である。It is a figure for demonstrating the effect of the wiring board of the present Example 1. FIG. 前記実施例１の配線板を用いた半導体装置の製造方法の応用例を説明するための模式図であり、図４（ａ）は半導体チップを実装する工程の図、図４（ｂ）は第１折り曲げ工程の図である。FIGS. 4A and 4B are schematic views for explaining an application example of a method of manufacturing a semiconductor device using the wiring board of Example 1, FIG. 4A is a diagram of a process of mounting a semiconductor chip, and FIG. It is a figure of 1 folding process. 前記実施例１の配線板を用いた半導体装置の製造方法の応用例を説明するための模式図であり、第２折り曲げ工程の図である。It is a schematic diagram for demonstrating the application example of the manufacturing method of the semiconductor device using the wiring board of the said Example 1, and is a figure of a 2nd bending process. 前記実施例１の配線板の応用例を説明するための模式図である。It is a schematic diagram for demonstrating the application example of the wiring board of the said Example 1. FIG. 本発明による実施例２の半導体装置の製造方法を説明するための模式図であり、図７（ａ）は半導体チップを実装する工程の図、図７（ｂ）は半導体チップを積層する工程の図である。FIGS. 7A and 7B are schematic views for explaining a method for manufacturing a semiconductor device according to a second embodiment of the present invention. FIG. 7A is a diagram of a process of mounting a semiconductor chip, and FIG. FIG. 従来の積層型半導体装置の製造方法を説明するための模式図であり、図８（ａ）は半導体チップを実装する工程の図、図８（ｂ）は半導体チップを積層する工程の図である。8A and 8B are schematic diagrams for explaining a conventional method for manufacturing a stacked semiconductor device, in which FIG. 8A is a diagram of a process for mounting a semiconductor chip, and FIG. 8B is a diagram of a process for stacking semiconductor chips. . 従来の積層型半導体装置の問題点を説明するための模式図である。It is a schematic diagram for demonstrating the problem of the conventional laminated semiconductor device.

符号の説明Explanation of symbols

１ 絶縁基板
１Ａ 絶縁基板の第１主面
１Ｂ 絶縁基板の第２主面
２Ａ 第１導体パターン（電解銅）
２Ｂ 第２導体パターン（圧延銅）
２Ｃ 層間接続導体
２Ｄ 導体パターン（電解銅）
３Ａ 第１半導体チップ
３Ｂ 第２半導体チップ
３Ｃ 第３半導体チップ
４ バンプ
５ 接着材
６ クラック DESCRIPTION OF SYMBOLS 1 Insulating substrate 1A 1st main surface of an insulating substrate 1B 2nd main surface of an insulating substrate 2A 1st conductor pattern (electrolytic copper)
2B Second conductor pattern (rolled copper)
2C Interlayer connection conductor 2D Conductor pattern (Electrolytic copper)
3A First semiconductor chip 3B Second semiconductor chip 3C Third semiconductor chip 4 Bump 5 Adhesive 6 Crack

Claims (5)

絶縁基板の第１主面及び第２主面に導体パターンが設けられてなり、複数個の半導体チップを実装した後、折り曲げて前記半導体チップが積層された半導体装置の製造に用いる配線板であって、
前記各主面の導体パターンのうち、折り曲げたときに外側を向く面の導体パターンが、圧延銅箔または高屈曲性の電解銅箔でなることを特徴とする配線板。 A wiring board used for manufacturing a semiconductor device in which a conductor pattern is provided on a first main surface and a second main surface of an insulating substrate, and a plurality of semiconductor chips are mounted and then bent and stacked. And
2. A wiring board according to claim 1, wherein, among the conductor patterns on each main surface, the conductor pattern on the surface facing outward when bent is made of a rolled copper foil or a highly flexible electrolytic copper foil. 前記圧延銅箔または前記高屈曲性の電解銅箔は、ＪＩＳ Ｃ５０１６規格に準拠した耐折試験による耐折値が、５０回以上であることを特徴とする請求項１に記載の配線板。   2. The wiring board according to claim 1, wherein the rolled copper foil or the highly flexible electrolytic copper foil has a folding resistance value of 50 times or more according to a folding test according to JIS C5016 standard. 絶縁基板の第１主面及び第２主面に導体パターンが設けられた配線板と、前記配線板上に実装された複数個のチップ状の電子部品とを備え、前記配線板を折り曲げて前記複数個のチップ状の電子部品を積層した半導体装置であって、
前記配線板の各主面の導体パターンのうち、折り曲げた領域で外側を向く面の導体パターンが、圧延銅箔または高屈曲性の電解銅箔でなることを特徴とする半導体装置。 A wiring board having conductor patterns provided on the first main surface and the second main surface of the insulating substrate; and a plurality of chip-like electronic components mounted on the wiring board; A semiconductor device in which a plurality of chip-shaped electronic components are stacked,
Of the conductor patterns on each main surface of the wiring board, the conductor pattern on the surface facing outward in the bent region is made of a rolled copper foil or a highly flexible electrolytic copper foil. 前記配線板は、複数箇所の前記チップ状の電子部品を実装する領域、及び折り曲げる領域を有し、少なくとも１箇所の前記チップ状の電子部品を実装する領域は、前記絶縁基板の第１主面側及び第２主面側の両面に、前記チップ状の電子部品が実装されていることを特徴とする請求項２に記載の半導体装置。   The wiring board has a plurality of regions where the chip-shaped electronic components are mounted and a region where the chip-shaped electronic components are bent, and at least one region where the chip-shaped electronic components are mounted is a first main surface of the insulating substrate. The semiconductor device according to claim 2, wherein the chip-shaped electronic components are mounted on both sides of the side and the second main surface side. 前記圧延銅箔または前記高屈曲性の電解銅箔は、ＪＩＳ Ｃ５０１６規格に準拠した耐折試験による耐折値が、５０回以上であることを特徴とする請求項３又は４に記載の半導体装置。   5. The semiconductor device according to claim 3, wherein the rolled copper foil or the highly flexible electrolytic copper foil has a folding resistance value of 50 times or more according to a folding test according to JIS C5016 standard. .
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007273582A (en) * 2006-03-30 2007-10-18 Toshiba Corp Printed-wiring board, manufacturing method thereof, and electronic equipment
JP2013236108A (en) * 2009-08-11 2013-11-21 Murata Mfg Co Ltd Multilayer substrate
WO2021059693A1 (en) * 2019-09-27 2021-04-01 株式会社村田製作所 Antenna substrate, antenna module, and antenna substrate manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007273582A (en) * 2006-03-30 2007-10-18 Toshiba Corp Printed-wiring board, manufacturing method thereof, and electronic equipment
JP2013236108A (en) * 2009-08-11 2013-11-21 Murata Mfg Co Ltd Multilayer substrate
WO2021059693A1 (en) * 2019-09-27 2021-04-01 株式会社村田製作所 Antenna substrate, antenna module, and antenna substrate manufacturing method

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