JP2006039812A - Dc stabilized power supply circuit - Google Patents

Dc stabilized power supply circuit Download PDF

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JP2006039812A
JP2006039812A JP2004216992A JP2004216992A JP2006039812A JP 2006039812 A JP2006039812 A JP 2006039812A JP 2004216992 A JP2004216992 A JP 2004216992A JP 2004216992 A JP2004216992 A JP 2004216992A JP 2006039812 A JP2006039812 A JP 2006039812A
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Yoshihisa Irikawa
佳久 入川
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NEC Electronics Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a DC stabilized power supply circuit equipped with an overcurrent protection circuit for protecting an output transistor by operating overcurrent protection not by indirectly detecting output currents by a sense MOS transistor but by directly detecting the decrease of an output voltage. <P>SOLUTION: An output voltage VG of an error amplifier AMP for amplifying a difference voltage between a first reference voltage VR1 and a voltage VM and a partial voltage VG1 to such extents that an output MOS transistor MP is not completely turned off are switched by a switch to be controlled by an output from a comparator CP which compares a second reference voltage VR2 with an output voltage VO. When the output voltage VO is larger than the second reference voltage VR2, an output voltage VG of the error amplifier AMP is supplied to the gate of the output MOS transistor MP, and in the other case, the partial voltage VG1 is supplied to the gate of the output MOS transistor MP so that the breakdown of the output MOS transistor due to overcurrents can be prevented. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、直流安定化電源回路に関し、特に電圧制御用出力トランジスタを保護する過電流保護回路を備えた直流安定化電源回路に関する。   The present invention relates to a DC stabilized power supply circuit, and more particularly to a DC stabilized power supply circuit including an overcurrent protection circuit that protects a voltage control output transistor.

直流安定化電源回路には３端子レギュレータが、今なお多く採用されている。この理由として、所望の性能を容易に選定し利用できること、安定化電源に必要な各種の保護回路が集積されており信頼性が高いことなどがあげられる。例えば電源投入時の過電流保護や短絡からの保護として、過電流保護回路がある。   Many three-terminal regulators are still used in the stabilized DC power supply circuit. This is because the desired performance can be easily selected and used, and various protection circuits necessary for the stabilized power supply are integrated, and the reliability is high. For example, there is an overcurrent protection circuit as protection against overcurrent at power-on or short circuit protection.

このような３端子レギュレータの過電流保護回路例として、出力トランジスタに流れる電流に比例して流れる電流を利用したセンスＭＯＳトランジスタを用いたものが一般的に知られている。   As an example of such an overcurrent protection circuit for a three-terminal regulator, a circuit using a sense MOS transistor that utilizes a current flowing in proportion to a current flowing through an output transistor is generally known.

以下、センスＭＯＳトランジスタを用いた従来の直流安定化電源回路２００を、図２を参照して次に示す。図において、ＶＤＤは電源端子（電圧をＶＤＤとする）、ＧＮＤは接地端子、ＡＭＰは誤差増幅器、ＶＲ１は第1基準電圧源、ＶＯは出力端子（電圧をＶＯとする）、ＣＰ１は比較器、ＣＣは容量である。ＭＰは出力ＭＯＳトランジスタ、ＭＳはセンスＭＯＳトランジスタ、Ｍ２は第２ＭＯＳトランジスタ、Ｒ１は第１抵抗、Ｒ２は第２抵抗、Ｒ５は第５抵抗である。   A conventional DC stabilized power supply circuit 200 using sense MOS transistors will be described below with reference to FIG. In the figure, VDD is a power supply terminal (voltage is VDD), GND is a ground terminal, AMP is an error amplifier, VR1 is a first reference voltage source, VO is an output terminal (voltage is VO), CP1 is a comparator, CC is a capacity. MP is an output MOS transistor, MS is a sense MOS transistor, M2 is a second MOS transistor, R1 is a first resistor, R2 is a second resistor, and R5 is a fifth resistor.

出力ＭＯＳトランジスタＭＰのソースは電源端子ＶＤＤに、ドレインは出力端子ＶＯにそれぞれ接続されている。第１抵抗Ｒ１の一端が出力端子ＶＯに、第２抵抗Ｒ２の一端が接地端子ＧＮＤにそれぞれ接続され、第１抵抗Ｒ１と第２抵抗Ｒ２の各他端が直列接続されると共に誤差増幅器ＡＭＰの非反転入力に接続されている（電圧をＶＭとする）。   The source of the output MOS transistor MP is connected to the power supply terminal VDD, and the drain is connected to the output terminal VO. One end of the first resistor R1 is connected to the output terminal VO, one end of the second resistor R2 is connected to the ground terminal GND, the other ends of the first resistor R1 and the second resistor R2 are connected in series, and the error amplifier AMP It is connected to the non-inverting input (the voltage is VM).

誤差増幅器ＡＭＰの反転入力には第1基準電圧源ＶＲ１からの第1基準電圧ＶＲ１が入力され、出力（電圧をＶＧとする）が出力ＭＯＳトランジスタＭＰのゲートに接続されている。センスＭＯＳトランジスタＭＳは出力ＭＯＳトランジスタＭＰのＮ（Ｎは自然数）分の1のサイズで、ソースは電源端子ＶＤＤに、ゲートは誤差増幅器ＡＭＰの出力にそれぞれ接続され、ドレインは第５抵抗Ｒ５を介して接地端子ＧＮＤに接続されると共に比較器ＣＰ１の反転入力に接続されている（電圧をＶＧ３とする）。   The first reference voltage VR1 from the first reference voltage source VR1 is input to the inverting input of the error amplifier AMP, and the output (voltage is VG) is connected to the gate of the output MOS transistor MP. The sense MOS transistor MS is 1 / N (N is a natural number) of the output MOS transistor MP, the source is connected to the power supply terminal VDD, the gate is connected to the output of the error amplifier AMP, and the drain is connected via the fifth resistor R5. To the ground terminal GND and to the inverting input of the comparator CP1 (the voltage is VG3).

比較器ＣＰ１の非反転入力には第1基準電圧ＶＲ１が入力され、出力が第２ＭＯＳトランジスタＭ２のゲートに接続されている。第２ＭＯＳトランジスタＭ２のソースは電源端子ＶＤＤに、ドレインは出力ＭＯＳトランジスタＭＰのゲートにそれぞれ接続されている。容量ＣＣは３端子レギュレータの出力部の発振防止用容量で出力端子ＶＯと接地端子ＧＮＤの間に接続されている。   The first reference voltage VR1 is input to the non-inverting input of the comparator CP1, and the output is connected to the gate of the second MOS transistor M2. The source of the second MOS transistor M2 is connected to the power supply terminal VDD, and the drain is connected to the gate of the output MOS transistor MP. The capacitor CC is an oscillation preventing capacitor at the output of the three-terminal regulator and is connected between the output terminal VO and the ground terminal GND.

以上のように構成された従来の直流安定化電源回路２００の過電流保護回路について動作の説明をする。電源電圧ＶＤＤ立ち上がり時において、電圧ＶＭが第1基準電圧ＶＲ１を越えるまでは誤差増幅器ＡＭＰが出力ＭＯＳトランジスタＭＰのゲート電圧を下げるように動作し、この時、第１抵抗Ｒ１と第２抵抗Ｒ２以外に容量ＣＣを充電するため出力ＭＯＳトランジスタＭＰには大きな電流Ｉｏが流れる。   The operation of the overcurrent protection circuit of the conventional DC stabilized power supply circuit 200 configured as described above will be described. When the power supply voltage VDD rises, the error amplifier AMP operates to lower the gate voltage of the output MOS transistor MP until the voltage VM exceeds the first reference voltage VR1, and at this time, except for the first resistor R1 and the second resistor R2. In order to charge the capacitor CC, a large current Io flows through the output MOS transistor MP.

この出力ＭＯＳトランジスタＭＰに流れる大電流ＩｏのＮ分の１の電流ＩｓがセンスＭＯＳトランジスタＭＳに流れ、このＮ分の１の電流Ｉｓと第５抵抗Ｒ５によって発生する電圧ＶＧ３と第1基準電圧ＶＲ１を比較器ＣＰ１で比較する。   The current Is 1 / N of the large current Io flowing through the output MOS transistor MP flows through the sense MOS transistor MS, and the voltage VG3 generated by the 1 / N current Is and the fifth resistor R5 and the first reference voltage VR1. Are compared by the comparator CP1.

ここで、電圧ＶＧ３が第1基準電圧ＶＲ１より高くなるまで上昇すると比較器ＣＰ１が第２ＭＯＳトランジスタＭ２のゲート電圧を下げるように動作し、この結果、第２ＭＯＳトランジスタＭ２をＯＮさせて出力ＭＯＳトランジスタＭＰをＯＦＦさせる。   Here, when the voltage VG3 increases until it becomes higher than the first reference voltage VR1, the comparator CP1 operates so as to decrease the gate voltage of the second MOS transistor M2. As a result, the second MOS transistor M2 is turned on and the output MOS transistor MP is turned on. Is turned off.

しかし、出力ＭＯＳトランジスタＭＰがＯＦＦすると電圧ＶＭが降下するため誤差増幅器ＡＭＰが出力ＭＯＳトランジスタＭＰのゲート電圧を下げるように動作し、出力ＭＯＳトランジスタＭＰをＯＮさせる。なお、出力ＭＯＳトランジスタＭＰがＯＦＦのときは、センスＭＯＳトランジスタＭＳもＯＦＦとなるため電圧ＶＧ３が降下し、比較器ＣＰ１は第２ＭＯＳトランジスタＭ２をＯＦＦさせるる。   However, when the output MOS transistor MP is turned off, the voltage VM drops, so that the error amplifier AMP operates to lower the gate voltage of the output MOS transistor MP, and turns on the output MOS transistor MP. When the output MOS transistor MP is OFF, the sense MOS transistor MS is also OFF, so that the voltage VG3 drops and the comparator CP1 turns off the second MOS transistor M2.

こうして、電圧ＶＭが下がると通常動作に復帰し、電源投入時に発振防止用容量ＣＣに過電流が流れることを防止し出力トランジスタを保護している（例えば、特許文献１参照。）。なお、発振防止用容量ＣＣに替え負荷を接続した場合で、負荷が何らかの原因で短絡したときに流れる過電流に対しても上記の保護動作を行うことがわかる。
特開２００４−７０４７２号公報（第２、３頁、図１） Thus, when the voltage VM decreases, the normal operation is resumed, and an overcurrent is prevented from flowing through the oscillation prevention capacitor CC when the power is turned on to protect the output transistor (see, for example, Patent Document 1). It can be seen that the protection operation is performed even when an overcurrent flows when the load is short-circuited for some reason when a load is connected instead of the oscillation prevention capacitor CC.
Japanese Patent Application Laid-Open No. 2004-70472 (pages 2, 3 and 1)

しかしながら、上記従来の過電流保護回路の直流安定化電源回路２００では、出力ＭＯＳトランジスタＭＰに流れる大電流のＮ分の１の電流Ｉｓにより、第２ＭＯＳトランジスタＭ２及び出力ＭＯＳトランジスタＭＰをＯＮ／ＯＦＦ制御させているため、センスＭＯＳトランジスタとしてのセンスＭＯＳトランジスタＭＳの製造ばらつきにより電流Ｉｓが変動し、過電流保護が動作する電流値がばらつくという問題があった。   However, in the above-described DC stabilized power supply circuit 200 of the conventional overcurrent protection circuit, the second MOS transistor M2 and the output MOS transistor MP are ON / OFF controlled by the current Is 1 / N of the large current flowing through the output MOS transistor MP. Therefore, there is a problem that the current Is fluctuates due to manufacturing variations of the sense MOS transistor MS as the sense MOS transistor, and the current value at which the overcurrent protection operates varies.

例えば、所定以上の大きな電流が出力ＭＯＳトランジスタＭＰに流れている場合に、センスＭＯＳトランジスタＭＳには設計した所望の電流が流れず第２ＭＯＳトランジスタＭ２がＯＮせず、出力ＭＯＳトランジスタＭＰがＯＦＦしない状態で破壊に至る場合である。   For example, when a current larger than a predetermined value is flowing through the output MOS transistor MP, a desired current does not flow through the sense MOS transistor MS, the second MOS transistor M2 is not turned on, and the output MOS transistor MP is not turned off. This is the case when it leads to destruction.

本発明の目的は、上記した従来の欠点を改良し、センスＭＯＳトランジスタによる出力電流の間接的な検出ではなく、出力電圧の低下を直接検出することで過電流保護が動作し出力トランジスタを保護する過電流保護回路を備えた直流安定化電源回路を提供するものである。   The object of the present invention is to improve the above-mentioned conventional drawbacks and not directly detect the output current by the sense MOS transistor, but directly detect a drop in the output voltage, so that the overcurrent protection operates and protects the output transistor. A DC stabilized power supply circuit provided with an overcurrent protection circuit is provided.

請求項１記載の発明は、電源端子と、接地端子と、出力端子と、ソースが電源端子に接続され、ドレインが出力端子に接続されると共に直列接続された第１、第２の抵抗を介して接地端子に接続されたＰｃｈ型出力ＭＯＳトランジスタと、反転入力に入力される第1の基準電圧と非反転入力に入力される第１、第２の抵抗の直列接続点より取り出される第１の分電圧との差電圧を増幅する誤差増幅器とを有する直流安定化電源回路において、
出力ＭＯＳトランジスタを完全にＯＦＦさせない程度の第２の分電圧を発生する分電圧発生回路と、反転入力に入力される第２の基準電圧と非反転入力に入力される出力端子の電圧とを比較する比較器と、制御信号として入力される比較器の出力により誤差増幅器の出力電圧と第２の分電圧とを切替て出力ＭＯＳトランジスタのゲートに供給するスイッチとを備え、スイッチが、第２の基準電圧よりも出力端子の電圧が大きい場合に誤差増幅器の出力電圧を、第２の基準電圧よりも出力端子の電圧が小さい場合に第２の分電圧を出力ＭＯＳトランジスタのゲートに供給することで、出力ＭＯＳトランジスタの過電流を防止することを特徴とする直流安定化電源回路である。 According to the first aspect of the present invention, the power source terminal, the ground terminal, the output terminal, the source is connected to the power source terminal, the drain is connected to the output terminal, and the first and second resistors are connected in series. A first channel extracted from a series connection point of a Pch-type output MOS transistor connected to the ground terminal, a first reference voltage input to the inverting input, and first and second resistors input to the non-inverting input. In a DC stabilized power supply circuit having an error amplifier for amplifying a difference voltage from a divided voltage,
A voltage dividing circuit that generates a second divided voltage that does not completely turn off the output MOS transistor is compared with the second reference voltage that is input to the inverting input and the voltage of the output terminal that is input to the non-inverting input. And a switch that switches the output voltage of the error amplifier and the second divided voltage to be supplied to the gate of the output MOS transistor according to the output of the comparator that is input as a control signal. By supplying the output voltage of the error amplifier to the gate of the output MOS transistor when the voltage at the output terminal is larger than the reference voltage, and the second divided voltage when the voltage at the output terminal is smaller than the second reference voltage. A DC-stabilized power supply circuit characterized by preventing an overcurrent of the output MOS transistor.

請求項２記載の発明は、分電圧発生回路が、第２の基準電圧よりも出力端子の電圧が小さい場合にのみ第２の分電圧を発生することを特徴とする請求項１記載の直流安定化電源回路である。   The invention according to claim 2 is characterized in that the divided voltage generating circuit generates the second divided voltage only when the voltage at the output terminal is smaller than the second reference voltage. Power supply circuit.

請求項３記載の発明は、分電圧発生回路が、直列接続された第３、第４の抵抗と、電源端子と接地端子間で第３、第４の抵抗に直列接続された第１のＭＯＳトランジスタとを有し、出力端子の電圧が第２の基準電圧より低いとき、第１のＭＯＳトランジスタがＯＮ制御されて第２の分電圧が第３、第４の抵抗の直列接続点より取り出されることを特徴とする請求項１記載の直流安定化電源回路である。   According to a third aspect of the present invention, there is provided a voltage dividing circuit comprising: a third and a fourth resistor connected in series; and a first MOS connected in series to the third and fourth resistors between a power supply terminal and a ground terminal. When the output terminal voltage is lower than the second reference voltage, the first MOS transistor is turned on and the second divided voltage is taken out from the series connection point of the third and fourth resistors. The DC stabilized power supply circuit according to claim 1.

請求項４記載の発明は、スイッチが、誤差増幅器の出力電圧および第２の分電圧を２つの入力とし、出力ＭＯＳトランジスタのゲートへの出力を有し、各入出力間が相補的に開閉制御されるトランスファーゲートで構成されていることを特徴とする請求項１記載の直流安定化電源回路である。   According to a fourth aspect of the present invention, the switch receives the output voltage of the error amplifier and the second divided voltage as two inputs, has an output to the gate of the output MOS transistor, and the input / output is complementarily controlled to open / close. 2. The stabilized DC power supply circuit according to claim 1, wherein the DC stabilized power supply circuit is constituted by a transfer gate.

請求項１〜４の発明によれば、出力トランジスタの過電流検出をセンスＭＯＳトランジスタに流れる電流による間接的な検出ではなく、出力電圧を直接判定する構成としたため、確実に出力トランジスタの過電流保護を動作させることができる。また、出力トランジスタの過電流検出にセンスＭＯＳトランジスタを用いていないため、センスＭＯＳトランジスタの製造ばらつきによる過電流保護が動作する電流値のばらつきの問題を解消することができる。   According to the first to fourth aspects of the invention, since the overcurrent detection of the output transistor is not indirectly detected by the current flowing through the sense MOS transistor, but the output voltage is directly determined, the overcurrent protection of the output transistor is ensured. Can be operated. In addition, since the sense MOS transistor is not used to detect the overcurrent of the output transistor, it is possible to solve the problem of variation in the current value at which the overcurrent protection is activated due to manufacturing variation of the sense MOS transistor.

負荷短絡の際の過電流から出力トランジスタを保護するという目的を、出力電圧の低下を直接検出して動作する過電流保護回路を設けることにより実現した。   The purpose of protecting the output transistor from overcurrent when the load is short-circuited is realized by providing an overcurrent protection circuit that operates by directly detecting a drop in the output voltage.

以下に、請求項１〜４記載に係る本発明の第１実施例の直流安定化電源回路１００について、図１を参照して説明する。尚、図２と同一部分には同一符号を付してその説明を省略する。図２と相違する主な点は、過電流時に出力ＭＯＳトランジスタＭＰを完全にＯＦＦさせないゲート電圧に切り替えて制御する構成とした点である。   A DC stabilized power circuit 100 according to a first embodiment of the present invention according to claims 1 to 4 will be described below with reference to FIG. The same parts as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted. The main difference from FIG. 2 is that the control is performed by switching to a gate voltage that does not completely turn off the output MOS transistor MP at the time of overcurrent.

図において、ＣＰは比較器、ＬＤは負荷、ＳＷはスイッチ、Ｍ１は第１ＭＯＳトランジスタ、Ｒ３は第３抵抗、Ｒ４は第４抵抗である。   In the figure, CP is a comparator, LD is a load, SW is a switch, M1 is a first MOS transistor, R3 is a third resistor, and R4 is a fourth resistor.

第１抵抗Ｒ１の一端が出力端子ＶＯに、第２抵抗Ｒ２の一端が接地端子ＧＮＤにそれぞれ接続され、第１抵抗Ｒ１と第２抵抗Ｒ２の各他端が直列接続されると共に誤差増幅器ＡＭＰの非反転入力に接続されている（電圧をＶＭとする）。誤差増幅器ＡＭＰの反転入力には第１基準電圧ＶＲ１が入力され、出力（電圧をＶＧとする）がスイッチＳＷの一方の入力に接続されている。   One end of the first resistor R1 is connected to the output terminal VO, one end of the second resistor R2 is connected to the ground terminal GND, the other ends of the first resistor R1 and the second resistor R2 are connected in series, and the error amplifier AMP It is connected to the non-inverting input (the voltage is VM). The first reference voltage VR1 is input to the inverting input of the error amplifier AMP, and the output (voltage is VG) is connected to one input of the switch SW.

第１ＭＯＳトランジスタＭ１のソースは電源端子ＶＤＤに、ドレインは第３抵抗Ｒ３の一端にそれぞれ接続されている。そして、第４抵抗Ｒ４の一端が接地端子ＧＮＤに接続され、第３抵抗Ｒ３と第４抵抗Ｒ４の各他端が直列接続されると共にスイッチＳＷの他方の入力に接続されて分電圧発生回路ＤＶを構成している（電圧をＶＧ１とする）。   The source of the first MOS transistor M1 is connected to the power supply terminal VDD, and the drain is connected to one end of the third resistor R3. Then, one end of the fourth resistor R4 is connected to the ground terminal GND, and the other ends of the third resistor R3 and the fourth resistor R4 are connected in series and connected to the other input of the switch SW, so that the voltage dividing circuit DV. (The voltage is VG1).

比較器ＣＰの非反転入力には出力電圧ＶＯが、反転入力には第２基準電圧ＶＲ２がそれぞれ入力され、出力がスイッチＳＷの制御入力に接続されると共に第１ＭＯＳトランジスタＭ１のゲートに接続されている。そして、スイッチＳＷの出力は出力ＭＯＳトランジスタＭＰのゲートに接続され、負荷ＬＤは出力端子ＶＯと接地端子ＧＮＤの間に接続されている。スイッチＳＷの一方の入力と出力間及び他方の入力と出力間は、制御入力によりそれぞれ相補的に開閉制御されるトランスファーゲートで構成されている。   The output voltage VO is input to the non-inverting input of the comparator CP, the second reference voltage VR2 is input to the inverting input, and the output is connected to the control input of the switch SW and to the gate of the first MOS transistor M1. Yes. The output of the switch SW is connected to the gate of the output MOS transistor MP, and the load LD is connected between the output terminal VO and the ground terminal GND. Between the one input and the output of the switch SW and between the other input and the output, a transfer gate that is complementarily controlled to open and close by a control input is constituted.

次に、本実施形態の直流安定化電源回路１００の動作について説明する。   Next, the operation of the stabilized DC power supply circuit 100 of this embodiment will be described.

負荷ＬＤが短絡していない場合は、誤差増幅器ＡＭＰの出力電圧ＶＧがスイッチＳＷを介して出力ＭＯＳトランジスタＭＰのゲートに供給され、所望の出力電圧ＶＯで安定制御されている。   When the load LD is not short-circuited, the output voltage VG of the error amplifier AMP is supplied to the gate of the output MOS transistor MP via the switch SW, and is stably controlled with the desired output voltage VO.

次に、負荷ＬＤが短絡した場合には、出力電圧ＶＯが降下し、出力ＭＯＳトランジスタＭＰの電流能力を超える大きな電流が出力ＭＯＳトランジスタＭＰに流れようとする。出力電圧ＶＯが第２基準電圧ＶＲ２を下回ると、比較器ＣＰの出力がロー側に反転し第１ＭＯＳトランジスタＭ１がＯＮして電圧ＶＧ１が発生すると共にこの電圧ＶＧ１がスイッチＳＷの入力の切替により出力ＭＯＳトランジスタＭＰのゲートに供給される。   Next, when the load LD is short-circuited, the output voltage VO drops, and a large current exceeding the current capability of the output MOS transistor MP tends to flow through the output MOS transistor MP. When the output voltage VO falls below the second reference voltage VR2, the output of the comparator CP is inverted to the low side, the first MOS transistor M1 is turned on to generate the voltage VG1, and this voltage VG1 is output by switching the input of the switch SW. It is supplied to the gate of the MOS transistor MP.

この電圧ＶＧ１は、第１ＭＯＳトランジスタＭ１及び第３、第４抵抗Ｒ３、Ｒ４による分電圧で、出力ＭＯＳトランジスタＭＰを完全にＯＦＦさせない程度の電圧に設定されているため、出力ＭＯＳトランジスタＭＰに流れようとする過大な電流が制限される。   This voltage VG1 is a voltage divided by the first MOS transistor M1 and the third and fourth resistors R3 and R4, and is set to a voltage that does not completely turn off the output MOS transistor MP, so that it will flow to the output MOS transistor MP. The excessive current is limited.

負荷ＬＤが通常の状態に戻り、負荷ＬＤが要求する電流がそれまで出力ＭＯＳトランジスタＭＰに流れていた制限された電流よりも小さくなると、出力ＭＯＳトランジスタＭＰの出力電圧ＶＯが上昇する。そして、出力電圧ＶＯが第２基準電圧ＶＲ２を上回ると、比較器ＣＰの出力が再度ハイ側に反転し、第１ＭＯＳトランジスタＭ１がＯＦＦすると共にスイッチＳＷの一方の入力である電圧ＶＧが出力ＭＯＳトランジスタＭＰのゲートに供給されるようになり、通常動作に復帰する。   When the load LD returns to a normal state and the current required by the load LD becomes smaller than the limited current that has been flowing through the output MOS transistor MP, the output voltage VO of the output MOS transistor MP increases. When the output voltage VO exceeds the second reference voltage VR2, the output of the comparator CP is inverted again to the high side, the first MOS transistor M1 is turned off, and the voltage VG as one input of the switch SW is changed to the output MOS transistor. The signal is supplied to the gate of the MP and returns to normal operation.

こうして、負荷ＬＤが短絡した場合に出力ＭＯＳトランジスタＭＰに過電流が流れることを防止し接続される負荷と共に出力ＭＯＳトランジスタＭＰを保護している。なお、負荷ＬＤに加え直流安定化電源回路１００の発振防止用容量を接続する場合が通常であるが、電源投入時にこの容量に流れ込む過電流に対しても上記の保護回路が動作する。   Thus, when the load LD is short-circuited, an overcurrent is prevented from flowing through the output MOS transistor MP, and the output MOS transistor MP is protected together with the connected load. Note that, in general, a capacitor for preventing oscillation of the DC stabilized power supply circuit 100 is connected in addition to the load LD. However, the protection circuit operates against an overcurrent flowing into this capacitor when the power is turned on.

以上説明したように、第１実施例の直流安定化電源回路１００によれば、出力ＭＯＳトランジスタＭＰの過電流検出を出力電圧ＶＯを直接判定する構成としたため、確実に出力トランジスタの過電流保護を動作させることができる。   As described above, according to the DC stabilized power supply circuit 100 of the first embodiment, the overcurrent detection of the output MOS transistor MP is configured to directly determine the output voltage VO, so that the overcurrent protection of the output transistor is ensured. It can be operated.

また、上記従来の過電流保護回路の直流安定化電源回路２００のようにセンスＭＯＳトランジスタを用いていないため、センスＭＯＳトランジスタの製造ばらつきによる過電流保護が動作する電流値がばらつくという従来の問題も解消することができる。   Further, since the sense MOS transistor is not used unlike the DC stabilized power supply circuit 200 of the conventional overcurrent protection circuit, the conventional problem that the current value at which the overcurrent protection operates due to manufacturing variations of the sense MOS transistor varies. Can be resolved.

尚、電圧ＶＧ１の分電圧発生回路ＤＶは、電源電圧ＶＤＤに依存しているものであればよく、例えば、第１ＭＯＳトランジスタＭ１をＮｃｈ型に替え、そのソースを接地端子ＧＮＤに、ドレインを第３抵抗Ｒ３、第４抵抗Ｒ４に相当する直列接続された抵抗を介して電源端子に、ゲートをインバータのような反転回路を介して比較器ＣＰの出力にそれぞれ接続する構成でもよい。   The voltage generation circuit DV of the voltage VG1 may be any circuit as long as it depends on the power supply voltage VDD. For example, the first MOS transistor M1 is changed to the Nch type, the source is the ground terminal GND, and the drain is the third. A configuration may be employed in which the gate is connected to the output of the comparator CP via an inverting circuit such as an inverter via a resistor connected in series corresponding to the resistor R3 and the fourth resistor R4.

本発明の直流安定化電源回路は、安定した直流電源が必要とされる種々の電子機器における過電流保護を備えた電源回路として広く適用できる。   The DC stabilized power supply circuit of the present invention can be widely applied as a power supply circuit having overcurrent protection in various electronic devices that require a stable DC power supply.

本発明の第１実施例の直流安定化電源回路１００を示す回路図。1 is a circuit diagram showing a DC stabilized power supply circuit 100 according to a first embodiment of the present invention. 従来の直流安定化電源回路２００を示す回路図。The circuit diagram which shows the conventional direct current | flow stabilized power supply circuit 200. FIG.

符号の説明Explanation of symbols

ＡＭＰ 誤差増幅器
Ｒ１、Ｒ２、Ｒ３、Ｒ４、Ｒ５ 抵抗
ＭＰ 出力ＭＯＳトランジスタ
Ｍ１、Ｍ２ ＭＯＳトランジスタ
ＭＳ センスＭＯＳトランジスタ
ＣＰ、ＣＰ１ 比較器
ＳＷ スイッチ
ＤＶ 分電圧発生回路
ＣＣ 容量
ＬＤ 負荷
ＶＤＤ 電源端子
ＶＯ 出力端子
ＧＮＤ 接地端子
ＶＲ１ 基準電圧源
１００、２００ 直流安定化電源回路 AMP Error amplifier R1, R2, R3, R4, R5 Resistance MP Output MOS transistor M1, M2 MOS transistor MS Sense MOS transistor CP, CP1 Comparator SW Switch DV Voltage divider circuit CC Capacitance LD Load VDD Power supply terminal VO Output terminal GND Ground Terminal VR1 Reference voltage source 100, 200 DC stabilized power supply circuit

Claims (4)

電源端子と、接地端子と、出力端子と、ソースが前記電源端子に接続され、ドレインが前記出力端子に接続されると共に直列接続された第１、第２の抵抗を介して接地端子に接続されたＰｃｈ型出力ＭＯＳトランジスタと、反転入力に入力される第1の基準電圧と非反転入力に入力される前記第１、第２の抵抗の直列接続点より取り出される第１の分電圧との差電圧を増幅する誤差増幅器とを有する直流安定化電源回路において、
前記出力ＭＯＳトランジスタを完全にＯＦＦさせない程度の第２の分電圧を発生する分電圧発生回路と、
反転入力に入力される第２の基準電圧と非反転入力に入力される前記出力端子の電圧とを比較する比較器と、
制御信号として入力される前記比較器の出力により前記誤差増幅器の出力電圧と前記第２の分電圧とを切替えて前記出力ＭＯＳトランジスタのゲートに供給するスイッチとを備え、
前記スイッチが、前記第２の基準電圧よりも前記出力端子の電圧が大きい場合に前記誤差増幅器の出力電圧を、前記第２の基準電圧よりも前記出力端子の電圧が小さい場合に前記第２の分電圧を前記出力ＭＯＳトランジスタのゲートに供給することで、前記出力ＭＯＳトランジスタの過電流を防止することを特徴とする直流安定化電源回路。 A power supply terminal, a ground terminal, an output terminal, a source is connected to the power supply terminal, a drain is connected to the output terminal, and is connected to the ground terminal via first and second resistors connected in series. The difference between the Pch-type output MOS transistor, the first reference voltage input to the inverting input, and the first divided voltage extracted from the series connection point of the first and second resistors input to the non-inverting input In a DC stabilized power supply circuit having an error amplifier for amplifying a voltage,
A voltage divider circuit for generating a second voltage divider that does not completely turn off the output MOS transistor;
A comparator for comparing the second reference voltage input to the inverting input and the voltage of the output terminal input to the non-inverting input;
A switch for switching the output voltage of the error amplifier and the second divided voltage to be supplied to the gate of the output MOS transistor according to the output of the comparator input as a control signal;
When the switch has a voltage at the output terminal greater than the second reference voltage, the switch outputs the output voltage of the error amplifier, and when the voltage at the output terminal is less than the second reference voltage, A direct-current stabilized power supply circuit that prevents an overcurrent of the output MOS transistor by supplying a divided voltage to the gate of the output MOS transistor. 前記分電圧発生回路は、前記第２の基準電圧よりも前記出力端子の電圧が小さい場合にのみ前記第２の分電圧を発生することを特徴とする請求項１記載の直流安定化電源回路。   2. The stabilized DC power supply circuit according to claim 1, wherein the divided voltage generation circuit generates the second divided voltage only when the voltage of the output terminal is smaller than the second reference voltage. 前記分電圧発生回路は、直列接続された第３、第４の抵抗と、
前記電源端子と接地端子間で前記第３、第４の抵抗に直列接続された第１のＭＯＳトランジスタとを有し、
前記出力端子の電圧が前記第２の基準電圧より低いとき、前記第１のＭＯＳトランジスタがＯＮ制御されて前記第２の分電圧が前記第３、第４の抵抗の直列接続点より取り出されることを特徴とする請求項１記載の直流安定化電源回路。 The voltage dividing circuit includes third and fourth resistors connected in series;
A first MOS transistor connected in series with the third and fourth resistors between the power supply terminal and the ground terminal;
When the voltage at the output terminal is lower than the second reference voltage, the first MOS transistor is ON-controlled and the second divided voltage is taken out from the series connection point of the third and fourth resistors. The DC stabilized power supply circuit according to claim 1. 前記スイッチは、前記誤差増幅器の出力電圧および前記第２の分電圧を２つの入力とし、前記出力ＭＯＳトランジスタのゲートへの出力を有し、各入出力間が相補的に開閉制御されるトランスファーゲートで構成されていることを特徴とする請求項１記載の直流安定化電源回路。   The switch receives the output voltage of the error amplifier and the second divided voltage as two inputs, has an output to the gate of the output MOS transistor, and is a transfer gate whose input and output are complementarily controlled to open and close The DC stabilized power supply circuit according to claim 1, comprising:
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JP2008257493A (en) * 2007-04-05 2008-10-23 Rohm Co Ltd Power supply device and electric equipment using this
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