JP2006038546A - Capacitance detection device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a good capacitance detection device capable of operating stably, capable of saving needless energy or labor at the manufacturing, and capable of forming other than a single crystal silicon substrate. <P>SOLUTION: The device comprises the M-lines of rows, N-lines of columns of M×N matrix, and capacitance detection elements arranged on the cross points. The capacitance detection element comprises a signal detection element, signal amplifying element and reset element. The signal detection element comprises capacitance detection electrode and capacitance detection dielectric film. The signal amplifying element is a signal amplifying thin film semiconductor device provided with a source electrode, drain electrode and gate electrode. The reset element is composed of thin film semiconductor device for resetting provided with the source electrode, drain electrode, and gate electrode. The gate electrode of the signal amplifying electrode, capacitance detection electrode and drain electrode of the reset element are connected. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本願発明は指紋等の微細な凹凸を有する対象物の表面形状を、対象物表面との距離に応じて変化する静電容量を検出する事に依り読み取る静電容量検出装置に関する。   The present invention relates to a capacitance detection device that reads the surface shape of an object having fine irregularities such as fingerprints by detecting the capacitance that changes according to the distance from the object surface.

従来、指紋センサ等に用いられる静電容量検出装置はセンサ電極と当該センサ電極上に設けられた誘電体膜とを単結晶硅素基板に形成していた（特開平１１−１１８４１５、特開２０００−３４６６０８、特開２００１−５６２０４、特開２００１−１３３２１３等）。図１は従来の静電容量検出装置の動作原理を説明している。センサ電極と誘電体膜とがコンデンサの一方の電極と誘電体膜とを成し、人体が接地された他方の電極と成る。このコンデンサーの静電容量Ｃ_Fは誘電体膜表面に接した指紋の凹凸に応じて変化する。一方、半導体基板には静電容量Ｃ_Sを成すコンデンサーを準備し、此等二つのコンデンサーを直列接続して、所定の電圧を印可する。斯うする事で二つのコンデンサーの間には指紋の凹凸に応じた電荷Ｑが発生する。この電荷Ｑを通常の半導体技術を用いて検出し、対象物の表面形状を読み取っていた。
特開平１１−１１８４１５ 特開２０００−３４６６０８ 特開２００１−５６２０４ 特開２００１−１３３２１３ Conventionally, a capacitance detection device used for a fingerprint sensor or the like has formed a sensor electrode and a dielectric film provided on the sensor electrode on a single crystal silicon substrate (Japanese Patent Laid-Open Nos. 11-118415 and 2000-). 346608, JP-A-2001-56204, JP-A-2001-133213, etc.). FIG. 1 illustrates the principle of operation of a conventional capacitance detection device. The sensor electrode and the dielectric film form one electrode of the capacitor and the dielectric film, and the other body is grounded. The capacitance C _F of this capacitor changes according to the unevenness of the fingerprint in contact with the dielectric film surface. On the other hand, a capacitor having a capacitance C _S is prepared on the semiconductor substrate, and these two capacitors are connected in series to apply a predetermined voltage. As a result, a charge Q corresponding to the unevenness of the fingerprint is generated between the two capacitors. This electric charge Q was detected using ordinary semiconductor technology, and the surface shape of the object was read.
JP 11-118415 A JP 2000-346608 A JP 2001-56204 A JP 2001-133213 A

しかしながら此等従来の静電容量検出装置は、当該装置が単結晶硅素基板上に形成されて居る為に、指紋センサとして用いると指を強く押しつけた際に当該装置が割れて仕舞うとの課題を有して居た。   However, since these conventional capacitance detection devices are formed on a single crystal silicon substrate, when the device is used as a fingerprint sensor, when the finger is pressed strongly, the device breaks down. I had it.

更に指紋センサはその用途から必然的に２０ｍｍ×２０ｍｍ程度の大きさが求められ、静電容量検出装置面積の大部分はセンサ電極にて占められる。センサ電極は無論単結晶硅素基板上に作られるが、膨大なエネルギーと労力とを費やして作成された単結晶硅素基板の大部分（センサ電極下部）は単なる支持体としての役割しか演じてない。即ち従来の静電容量検出装置は高価なだけでは無く、多大なる無駄と浪費の上に形成されて居るとの課題を有する。   Furthermore, the fingerprint sensor is inevitably required to have a size of about 20 mm × 20 mm depending on its use, and most of the capacitance detection device area is occupied by the sensor electrode. Of course, the sensor electrode is made on a single crystal silicon substrate, but most of the single crystal silicon substrate (bottom part of the sensor electrode) produced by expending enormous energy and labor plays only a role as a support. That is, the conventional capacitance detection device is not only expensive, but has a problem that it is formed on a great deal of waste and waste.

加えて近年、クレジットカードやキャッシュカード等のカード上に個人認証機能を設けてカードの安全性を高めるべきとの指摘が強い。然るに従来の単結晶硅素基板上に作られた静電容量検出装置は柔軟性に欠ける為に、当該装置をプラスティック基板上に作成し得ないとの課題を有している。   In addition, in recent years, it is strongly pointed out that a personal authentication function should be provided on a card such as a credit card or a cash card to enhance the safety of the card. However, since a conventional capacitance detection device made on a single crystal silicon substrate lacks flexibility, there is a problem that the device cannot be made on a plastic substrate.

そこで本発明は上述の諸事情を鑑み、その目的とする所は安定に動作し、更に製造時に不要なエネルギーや労力を削減し得、又単結晶硅素基板以外にも作成し得る優良な静電容量検出装置を提供する事に有る。より具体的には薄膜半導体装置を用いて優良に動作する静電容量検出装置を提供する事に有る。   In view of the above-mentioned circumstances, the present invention is intended to operate stably, further reduce unnecessary energy and labor at the time of manufacture, and excellent electrostatic capacity that can be created other than a single crystal silicon substrate. To provide a capacity detection device. More specifically, it is to provide a capacitance detection device that operates favorably using a thin film semiconductor device.

本発明は対象物との距離に応じて変化する静電容量を検出する事に依り、此等対象物の表面形状を読み取る静電容量検出装置を薄膜半導体装置を用いてガラス基板上等に作成する。斯うした静電容量検出装置はＭ行Ｎ列の行列状に配置されたＭ本の行線とＮ本の列線、及び各行線と各列線との交点に設けられたＭ×Ｎ個の静電容量検出素子とを具備する。各静電容量検出素子は信号検出素子と信号増幅素子とリセット素子とを含む。信号検出素子は容量検出電極と容量検出誘電体膜とを少なくとも含む。信号増幅素子はソース電極とドレイン電極とゲート電極とを有する信号増幅用薄膜半導体装置から成る。同様にリセット素子もソース電極とドレイン電極とゲート電極とを有するリセット用薄膜半導体装置から成る。本発明は信号増幅素子のゲート電極と容量検出電極とリセット素子のドレイン電極とが接続されて居る事を特徴と為す。此のリセット素子がスイッチオン状態になった際には、信号増幅素子のゲート電極と容量検出電極とが接地電位となり得る事をも本発明の特徴と為す。更にはリセット素子がスイッチオン状態となって居る間に信号増幅素子のドレイン電極をも接地電位とし得る事を本発明の特徴と為す。本発明はリセット素子のソース電極が行線に接続されて居る事を特徴と為す。又、本発明はリセット素子のゲート電極が、リセット素子の属する静電容量検出素子を位置づける行線の隣接段に位置する行線に接続されて居る事をも特徴と為す。更に本発明は信号増幅用薄膜半導体装置のドレイン電極が、静電容量検出素子を選択状態とした時に行線と電気的に導通される事を特徴とする。本発明は静電容量検出装置が出力線を含み、信号増幅用薄膜半導体装置のソース電極が、静電容量検出素子を選択状態とした時に出力線と電気的に導通される事をも特徴と為す。又、本発明は信号増幅素子とリセット素子とが同一導電型の薄膜半導体装置である事を特徴と為す。   The present invention creates a capacitance detection device on a glass substrate or the like by using a thin film semiconductor device for detecting the surface shape of an object by detecting the capacitance that changes according to the distance to the object. To do. Such a capacitance detection device has M rows and N column lines arranged in a matrix of M rows and N columns, and M × N pieces provided at the intersections of the row lines and the column lines. And a capacitance detection element. Each capacitance detection element includes a signal detection element, a signal amplification element, and a reset element. The signal detection element includes at least a capacitance detection electrode and a capacitance detection dielectric film. The signal amplifying element comprises a signal amplifying thin film semiconductor device having a source electrode, a drain electrode, and a gate electrode. Similarly, the reset element includes a reset thin film semiconductor device having a source electrode, a drain electrode, and a gate electrode. The present invention is characterized in that the gate electrode of the signal amplification element, the capacitance detection electrode, and the drain electrode of the reset element are connected. It is also a feature of the present invention that when the reset element is switched on, the gate electrode and the capacitance detection electrode of the signal amplifying element can be at the ground potential. Furthermore, it is a feature of the present invention that the drain electrode of the signal amplifying element can be set to the ground potential while the reset element is in the switch-on state. The present invention is characterized in that the source electrode of the reset element is connected to the row line. The present invention is also characterized in that the gate electrode of the reset element is connected to a row line positioned adjacent to the row line for positioning the capacitance detection element to which the reset element belongs. Furthermore, the present invention is characterized in that the drain electrode of the thin film semiconductor device for signal amplification is electrically connected to the row line when the capacitance detection element is selected. The present invention is also characterized in that the capacitance detection device includes an output line, and the source electrode of the signal amplification thin film semiconductor device is electrically connected to the output line when the capacitance detection element is selected. Do it. Further, the present invention is characterized in that the signal amplifying element and the reset element are thin film semiconductor devices of the same conductivity type.

本発明は対象物との距離に応じて変化する静電容量を検出する事に依り、此等対象物の表面形状を読み取る静電容量検出装置を薄膜半導体装置を用いてガラス基板上等に作成する。斯うした静電容量検出装置はＭ行Ｎ列の行列状に配置されたＭ本の行線とＮ本の列線、及び各行線と各列線との交点に設けられたＭ×Ｎ個の静電容量検出素子とを具備する。各静電容量検出素子は信号検出素子と信号増幅素子とリセット素子とを含む。信号検出素子は容量検出電極と容量検出誘電体膜と基準コンデンサとを含む。基準コンデンサは基準コンデンサ第一電極と基準コンデンサ誘電体膜と基準コンデンサ第二電極とから成る。一方、信号増幅素子はソース電極とドレイン電極とゲート電極とを有する信号増幅用薄膜半導体装置から成る。同様にリセット素子もソース電極とドレイン電極とゲート電極とを有するリセット用薄膜半導体装置から成る。本発明は信号増幅素子のゲート電極と容量検出電極と基準コンデンサ第二電極とリセット素子のドレイン電極とが接続されて居る事を特徴と為す。本発明では基準コンデンサ第一電極と行線とが電気的に接続されて居る事を特徴となす。此のリセット素子がスイッチオン状態になった際には、信号増幅素子のゲート電極と容量検出電極と基準コンデンサ第二電極とが接地電位となり得る事をも本発明の特徴と為す。更にはリセット素子がスイッチオン状態となって居る間に信号増幅素子のドレイン電極をも接地電位とし得る事を本発明の特徴と為す。又、基準コンデンサ第一電極が接地電位となっている間にリセット素子をスイッチオン状態とし得る事を本発明の特徴と為す。本発明はリセット素子のソース電極が行線に接続されて居る事を特徴と為す。又、本発明はリセット素子のゲート電極が、リセット素子の属する静電容量検出素子を位置づける行線の隣接段に位置する行線に接続されて居る事をも特徴と為す。更に本発明は信号増幅用薄膜半導体装置のドレイン電極が、静電容量検出素子を選択状態とした時に行線と電気的に導通される事を特徴とする。本発明は静電容量検出装置が出力線を含み、信号増幅用薄膜半導体装置のソース電極が、静電容量検出素子を選択状態とした時に出力線と電気的に導通される事をも特徴と為す。又、本発明は信号増幅素子とリセット素子とが同一導電型の薄膜半導体装置である事を特徴と為す。   The present invention creates a capacitance detection device on a glass substrate or the like by using a thin film semiconductor device for detecting the surface shape of an object by detecting the capacitance that changes according to the distance to the object. To do. Such a capacitance detection device has M rows and N column lines arranged in a matrix of M rows and N columns, and M × N pieces provided at the intersections of the row lines and the column lines. And a capacitance detection element. Each capacitance detection element includes a signal detection element, a signal amplification element, and a reset element. The signal detection element includes a capacitance detection electrode, a capacitance detection dielectric film, and a reference capacitor. The reference capacitor includes a reference capacitor first electrode, a reference capacitor dielectric film, and a reference capacitor second electrode. On the other hand, the signal amplifying element comprises a signal amplifying thin film semiconductor device having a source electrode, a drain electrode, and a gate electrode. Similarly, the reset element includes a reset thin film semiconductor device having a source electrode, a drain electrode, and a gate electrode. The present invention is characterized in that the gate electrode, the capacitance detection electrode, the reference capacitor second electrode, and the drain electrode of the reset element are connected to each other. The present invention is characterized in that the reference capacitor first electrode and the row line are electrically connected. It is also a feature of the present invention that when the reset element is switched on, the gate electrode, the capacitance detection electrode, and the reference capacitor second electrode of the signal amplification element can be at the ground potential. Furthermore, it is a feature of the present invention that the drain electrode of the signal amplifying element can be set to the ground potential while the reset element is in the switch-on state. It is also a feature of the present invention that the reset element can be switched on while the reference capacitor first electrode is at ground potential. The present invention is characterized in that the source electrode of the reset element is connected to the row line. The present invention is also characterized in that the gate electrode of the reset element is connected to a row line positioned adjacent to the row line for positioning the capacitance detection element to which the reset element belongs. Furthermore, the present invention is characterized in that the drain electrode of the thin film semiconductor device for signal amplification is electrically connected to the row line when the capacitance detection element is selected. The present invention is also characterized in that the capacitance detection device includes an output line, and the source electrode of the signal amplification thin film semiconductor device is electrically connected to the output line when the capacitance detection element is selected. Do it. Further, the present invention is characterized in that the signal amplifying element and the reset element are thin film semiconductor devices of the same conductivity type.

更に本発明は静電容量検出素子が信号検出素子と信号増幅素子と列選択素子とリセット素子とを含む事をも特徴と為す。先と同様に信号検出素子は容量検出電極と容量検出誘電体膜と基準コンデンサとを含み、基準コンデンサは基準コンデンサ第一電極と基準コンデンサ誘電体膜と基準コンデンサ第二電極とから成る。信号増幅素子はソース電極とドレイン電極とゲート電極とを有する信号増幅用薄膜半導体装置から成り、列選択素子もソース電極とドレイン電極とゲート電極とを有する列選択用薄膜半導体装置から成り、リセット素子もソース電極とドレイン電極とゲート電極とを有するリセット用薄膜半導体装置から成る。信号増幅用薄膜半導体装置と列選択用薄膜半導体装置とは直列に接続される。本発明は信号増幅素子のゲート電極と容量検出電極と基準コンデンサ第二電極とリセット素子のドレイン電極とが接続されて居る事を特徴と為す。本発明では基準コンデンサ第一電極と行線とが電気的に接続されて居る事を特徴となす。此のリセット素子がスイッチオン状態になった際には、信号増幅素子のゲート電極と容量検出電極と基準コンデンサ第二電極とが接地電位となり得る事をも本発明の特徴と為す。更にはリセット素子がスイッチオン状態となって居る間に信号増幅素子のドレイン電極をも接地電位とし得る事を本発明の特徴と為す。又、基準コンデンサ第一電極が接地電位となっている間にリセット素子をスイッチオン状態とし得る事を本発明の特徴と為す。本発明はリセット素子のソース電極が行線に接続されて居る事を特徴と為す。又、本発明はリセット素子のゲート電極が、リセット素子の属する静電容量検出素子を位置づける行線の隣接段に位置する行線に接続されて居る事をも特徴と為す。更に本発明は信号増幅用薄膜半導体装置のドレイン電極が、静電容量検出素子を選択状態とした時に行線と電気的に導通される事を特徴とする。本発明は静電容量検出装置が出力線を含み、信号増幅用薄膜半導体装置のソース電極が、静電容量検出素子を選択状態とした時に出力線と電気的に導通される事をも特徴と為す。又、本発明は信号増幅素子とリセット素子とが同一導電型の薄膜半導体装置である事を特徴と為す。更に本発明は静電容量検出素子が列選択素子を含む場合には、列選択用薄膜半導体装置のゲート電極が列線に接続される事をも特徴とする。   Furthermore, the present invention is characterized in that the capacitance detection element includes a signal detection element, a signal amplification element, a column selection element, and a reset element. As before, the signal detection element includes a capacitance detection electrode, a capacitance detection dielectric film, and a reference capacitor, and the reference capacitor includes a reference capacitor first electrode, a reference capacitor dielectric film, and a reference capacitor second electrode. The signal amplifying element includes a signal amplifying thin film semiconductor device having a source electrode, a drain electrode, and a gate electrode. The column selecting element also includes a column selecting thin film semiconductor device having a source electrode, a drain electrode, and a gate electrode. Also includes a reset thin film semiconductor device having a source electrode, a drain electrode, and a gate electrode. The thin film semiconductor device for signal amplification and the thin film semiconductor device for column selection are connected in series. The present invention is characterized in that the gate electrode, the capacitance detection electrode, the reference capacitor second electrode, and the drain electrode of the reset element are connected to each other. The present invention is characterized in that the reference capacitor first electrode and the row line are electrically connected. It is also a feature of the present invention that when the reset element is switched on, the gate electrode, the capacitance detection electrode, and the reference capacitor second electrode of the signal amplification element can be at the ground potential. Furthermore, it is a feature of the present invention that the drain electrode of the signal amplifying element can be set to the ground potential while the reset element is in the switch-on state. It is also a feature of the present invention that the reset element can be switched on while the reference capacitor first electrode is at ground potential. The present invention is characterized in that the source electrode of the reset element is connected to the row line. The present invention is also characterized in that the gate electrode of the reset element is connected to a row line positioned adjacent to the row line for positioning the capacitance detection element to which the reset element belongs. Furthermore, the present invention is characterized in that the drain electrode of the thin film semiconductor device for signal amplification is electrically connected to the row line when the capacitance detection element is selected. The present invention is also characterized in that the capacitance detection device includes an output line, and the source electrode of the signal amplification thin film semiconductor device is electrically connected to the output line when the capacitance detection element is selected. Do it. Further, the present invention is characterized in that the signal amplifying element and the reset element are thin film semiconductor devices of the same conductivity type. Furthermore, the present invention is characterized in that, when the capacitance detecting element includes a column selecting element, the gate electrode of the column selecting thin film semiconductor device is connected to the column line.

本発明は、基準コンデンサの誘電体膜と信号増幅用薄膜半導体装置のゲート絶縁膜とが同一素材にて形成されて居る事を特徴とする。此等の膜は同一層上に形成されていても良い。基準コンデンサの一方の電極は信号増幅用薄膜半導体装置のドレイン領域と同一素材にて形成され得、此の電極と信号増幅用薄膜半導体装置のドレイン領域とが同一層上に形成されて居る事をも特徴とする。基準コンデンサの他方の電極は信号増幅用薄膜半導体装置のゲート電極と同一素材にて形成されて居る事を特徴とする。此等の電極は同一層上に形成されていても良い。   The present invention is characterized in that the dielectric film of the reference capacitor and the gate insulating film of the thin film semiconductor device for signal amplification are formed of the same material. These films may be formed on the same layer. One electrode of the reference capacitor can be formed of the same material as the drain region of the signal amplifying thin film semiconductor device, and this electrode and the drain region of the signal amplifying thin film semiconductor device are formed on the same layer. Also features. The other electrode of the reference capacitor is formed of the same material as the gate electrode of the signal amplification thin film semiconductor device. These electrodes may be formed on the same layer.

本発明は基準コンデンサの電極面積をＳ_R（μｍ²）、基準コンデンサ誘電体膜の厚みをｔ_R（μｍ）、基準コンデンサ誘電体膜の比誘電率をε_R、信号増幅用薄膜半導体装置のゲート電極面積をＳ_T（μｍ²）、ゲート絶縁膜の厚みをｔ_ox（μｍ）、ゲート絶縁膜の比誘電率をε_oxとして、基準コンデンサ容量Ｃ_Rと信号増幅用薄膜半導体装置のトランジスタ容量Ｃ_Tとを其々
Ｃ_R＝ε₀・ε_R・Ｓ_R／ｔ_R
Ｃ_T＝ε₀・ε_ox・Ｓ_T／ｔ_ox
にて定義し（ε₀は真空の誘電率）、容量検出電極の面積をＳ_D（μｍ²）、容量検出誘電体膜の厚みをｔ_D（μｍ）、容量検出誘電体膜の比誘電率をε_Dとして信号検出素子の素子容量Ｃ_Dを
Ｃ_D＝ε₀・ε_D・Ｓ_D／ｔ_D
と定義した時に（ε₀は真空の誘電率）、此の素子容量Ｃ_Dは、基準コンデンサ容量Ｃ_Rとトランジスタ容量Ｃ_Tとの和であるＣ_R＋Ｃ_Tよりも十分に大きい事を特徴とする。更に基準コンデンサ容量Ｃ_Rがトランジスタ容量Ｃ_Tよりも十分に大きいのが理想的である。従って素子容量Ｃ_Dは基準コンデンサ容量Ｃ_R単体よりも十分に大きい事をも特徴とする。容量検出誘電体膜は静電容量検出装置の最表面に位置する事をも特徴と為す。又、本発明は測定されるべき対象物が容量検出誘電体膜に接しずに対象物距離ｔ_Aを以て離れて居り、対象物容量Ｃ_Aを真空の誘電率ε₀と空気の比誘電率ε_Aと容量検出電極の面積Ｓ_Dとを用いて、
Ｃ_A＝ε₀・ε_A・Ｓ_D／ｔ_A
と定義した時に、基準コンデンサ容量Ｃ_Rは対象物容量Ｃ_Aよりも十分に大きい事を特徴とする。此処でも基準コンデンサ容量Ｃ_Rがトランジスタ容量Ｃ_Tよりも十分に大きいのが理想的である。 In the present invention, the electrode area of the reference capacitor is S _R (μm ² ), the thickness of the reference capacitor dielectric film is t _R (μm), the relative dielectric constant of the reference capacitor dielectric film is ε _R , and the thin film semiconductor device for signal amplification the gate electrode area S _T (μm ^2), the thickness of the gate insulating film t _ox (μm), the relative dielectric constant of the gate insulating film as epsilon _ox, the reference capacitor capacitance C _R and the transistor capacitance of the signal amplifying thin-film semiconductor device C _T and C _R = ε ₀ · ε _R · S _R / t _{R respectively}
C _T = ε ₀ · ε _ox · S _T / t _ox
(Ε ₀ is the dielectric constant of vacuum), the area of the capacitance detection electrode is S _D (μm ² ), the thickness of the capacitance detection dielectric film is t _D (μm), and the relative dielectric constant of the capacitance detection dielectric film the element capacitance C _D of the signal detection element as _{ε D C D = ε 0 ·} ε D · S D / t D
(Ε ₀ is the dielectric constant of vacuum), the element capacitance C _D is characterized by being sufficiently larger than C _R + C _T which is the sum of the reference capacitor capacitance C _R and the transistor capacitance C _T. To do. Further, it is ideal that the reference capacitor capacitance C _R is sufficiently larger than the transistor capacitance C _T. Therefore the element capacitance C _D is also characterized in that the sufficiently larger than the reference capacitance C _R alone. The capacitance detection dielectric film is also characterized by being located on the outermost surface of the capacitance detection device. Further, according to the present invention, the object to be measured is not in contact with the capacitance detection dielectric film but is separated by the object distance t _A , and the object capacitance C _A is divided into the dielectric constant ε _{0 of} vacuum and the relative dielectric constant ε of air. _{Using A} and the area _SD of the capacitance detection electrode,
C _A = ε ₀ · ε _A · S _D / t _A
The reference capacitor capacity C _R is characterized by being sufficiently larger than the object capacity C _A. Here the reference capacitance C _R also that sufficiently larger than the transistor capacitance C _T is ideal.

又、本発明は容量検出誘電体膜が静電容量検出装置の最表面に位置し、基準コンデンサの電極面積をＳ_R（μｍ²）、基準コンデンサ誘電体膜の厚みをｔ_R（μｍ）、基準コンデンサ誘電体膜の比誘電率をε_R、信号増幅用薄膜半導体装置のゲート電極面積をＳ_T（μｍ²）、ゲート絶縁膜の厚みをｔ_ox（μｍ）、ゲート絶縁膜の比誘電率をε_oxとして基準コンデンサ容量Ｃ_Rと信号増幅用薄膜半導体装置のトランジスタ容量Ｃ_Tとを其々
Ｃ_R＝ε₀・ε_R・Ｓ_R／ｔ_R
Ｃ_T＝ε₀・ε_ox・Ｓ_T／ｔ_ox
にて定義し（ε₀は真空の誘電率）、容量検出電極の面積をＳ_D（μｍ²）、容量検出誘電体膜の厚みをｔ_D（μｍ）、容量検出誘電体膜の比誘電率をε_Dとして信号検出素子の素子容量Ｃ_Dを
Ｃ_D＝ε₀・ε_D・Ｓ_D／ｔ_D
と定義した時に（ε₀は真空の誘電率）、
此の素子容量Ｃ_Dは、基準コンデンサ容量Ｃ_Rとトランジスタ容量Ｃ_Tとの和であるＣ_R＋Ｃ_Tよりも十分に大きく、且つ対象物が容量検出誘電体膜に接しずに対象物距離ｔ_Aを以て離れて居り、対象物容量Ｃ_Aを真空の誘電率ε₀と空気の比誘電率ε_Aと容量検出電極の面積Ｓ_Dとを用いて、
Ｃ_A＝ε₀・ε_A・Ｓ_D／ｔ_A
と定義した時に、基準コンデンサ容量Ｃ_Rが対象物容量Ｃ_Aよりも十分に大きい事を特徴とする。此処でも基準コンデンサ容量Ｃ_Rがトランジスタ容量Ｃ_Tよりも十分に大きいのが理想的である。従って素子容量Ｃ_Dは基準コンデンサ容量Ｃ_R単体よりも十分に大きく、且つ基準コンデンサ容量Ｃ_R単体が対象物容量Ｃ_Aよりも十分に大きい事をも特徴とする。 In the present invention, the capacitance detection dielectric film is positioned on the outermost surface of the capacitance detection device, the reference capacitor electrode area is S _R (μm ² ), the reference capacitor dielectric film thickness is t _R (μm), The dielectric constant of the reference capacitor dielectric film is ε _R , the gate electrode area of the thin film semiconductor device for signal amplification is S _T (μm ² ), the thickness of the gate insulating film is t _ox (μm), and the relative dielectric constant of the gate insulating film _{Is the} reference capacitor capacitance C _R and the transistor capacitance C _{T of the} signal amplification thin film semiconductor device is C _R = ε ₀ · ε _R · S _R / t _R
C _T = ε ₀ · ε _ox · S _T / t _ox
(Ε ₀ is the dielectric constant of vacuum), the area of the capacitance detection electrode is S _D (μm ² ), the thickness of the capacitance detection dielectric film is t _D (μm), and the relative dielectric constant of the capacitance detection dielectric film the element capacitance C _D of the signal detection element as _{ε D C D = ε 0 ·} ε D · S D / t D
Where ε ₀ is the dielectric constant of the vacuum,
This element capacitance C _D is sufficiently larger than C _R + C _T, which is the sum of the reference capacitor capacitance C _R and the transistor capacitance C _T , and the object is not in contact with the capacitance detection dielectric film and the object distance t _A is separated from the object capacitance C _A using the dielectric constant ε _{0 of} vacuum, the relative dielectric constant ε _{A of} air, and the area _{SD of the} capacitance detection electrode,
C _A = ε ₀ · ε _A · S _D / t _A
When defined as the reference capacitance C _R is wherein a is sufficiently larger than the object capacitance C _A. Here the reference capacitance C _R also that sufficiently larger than the transistor capacitance C _T is ideal. Therefore the element capacitance C _D is sufficiently larger than the reference capacitance C _R alone, and the reference capacitance C _R alone is also characterized in that is sufficiently larger than the object capacitance C _A.

本願発明により高精度で且つ高速に対象物の静電容量を検出可能な静電容量検出装置を薄膜半導体装置にて作成する事が実現した。従来の単結晶硅素基板を用いた技術では数ｍｍ×数ｍｍ程度の小さな静電容量検出装置しかプラスティック基板上に形成出来なかったが、本願発明に依るとその百倍もの面積を有する静電容量検出装置をプラスティク基板上に作成する事が実現し、しかも対象物の凹凸情報を窮めて高精度に検出出来る様になった。薄膜半導体装置からなる静電容量検出装置はプラスティック基板上に転写できる。此の技術を用いると例えはスマートカードに指紋センサを搭載出来、カードのセキュリティーレベルを著しく向上せしめるとの効果が認められる。又、単結晶硅素基板を用いた従来の静電容量検出装置は装置面積の極一部しか単結晶硅素半導体を利用して居らず、莫大なエネルギーと労力とを無駄に費やしていた。これに対し本願発明では斯様な浪費を排除し、地球環境の保全に役立つとの効果を有する。   According to the present invention, it has been realized that a capacitance detection device capable of detecting the capacitance of an object with high accuracy and at high speed is produced by a thin film semiconductor device. In the conventional technology using a single crystal silicon substrate, only a small capacitance detecting device of about several mm × several mm can be formed on a plastic substrate. However, according to the present invention, the capacitance detection has a hundred times the area. It was possible to create a device on a plastic substrate, and it was possible to detect the unevenness information of the object with high accuracy. A capacitance detection device made of a thin film semiconductor device can be transferred onto a plastic substrate. Using this technology, for example, a fingerprint sensor can be mounted on a smart card, and the effect of significantly improving the security level of the card is recognized. Further, the conventional capacitance detection device using a single crystal silicon substrate uses a single crystal silicon semiconductor for only a very small part of the device area, and wastes enormous energy and labor. In contrast, the present invention has the effect of eliminating such waste and helping to preserve the global environment.

本発明は対象物との距離に応じて変化する静電容量を検出する事に依り、此等対象物の表面形状を読み取る静電容量検出装置を金属−絶縁膜−半導体膜から成る薄膜半導体装置にて作成する。薄膜半導体装置は通常硝子基板上に作成される為に、大面積を要する半導体集積回路を安価に製造する技術として知られ、具体的に昨今では液晶表示装置等に応用されている。従って指紋センサ等に適応される静電容量検出装置を薄膜半導体装置にて作成すると、単結晶硅素基板と云った多大なエネルギーを消費して作られた高価な基板を使用する必要がなく、貴重な地球資源を浪費する事なく安価に当該装置を作成し得る。又、薄膜半導体装置はＳＵＦＴＬＡ（特開平１１−３１２８１１やS. Utsunomiya et. al. Society for Information Display p. 916 (2000)）と呼ばれる転写技術を適応する事で、半導体集積回路をプラスティック基板上に作成出来るので、静電容量検出装置も単結晶硅素基板から解放されてプラスティック基板上に形成し得るので有る。   The present invention relates to a thin film semiconductor device comprising a metal-insulating film-semiconductor film by detecting a capacitance changing according to the distance to the object, and reading the surface shape of the object. Create with. Since a thin film semiconductor device is usually formed on a glass substrate, it is known as a technique for manufacturing a semiconductor integrated circuit requiring a large area at a low cost. Specifically, it has recently been applied to a liquid crystal display device or the like. Therefore, when a capacitance detection device adapted to a fingerprint sensor or the like is made with a thin film semiconductor device, it is not necessary to use an expensive substrate made by consuming a great amount of energy such as a single crystal silicon substrate. Therefore, the apparatus can be produced at low cost without wasting valuable earth resources. Thin film semiconductor devices adopt a transfer technique called SUFTLA (Japanese Patent Laid-Open No. 11-312811 and S. Utsunomiya et. Al. Society for Information Display p. 916 (2000)), so that a semiconductor integrated circuit is formed on a plastic substrate. Since it can be made, the capacitance detecting device can be released from the single crystal silicon substrate and formed on the plastic substrate.

さて、図１に示すが如き従来の動作原理を適応した静電容量検出装置を薄膜半導体装置にて作成するのは、現在の薄膜半導体装置の技術を以てしては不可能である。二つの直列接続されたコンデンサー間に誘起される電荷Ｑは非常に小さい為に、高精度感知を可能とする単結晶硅素ＬＳＩ技術を用いれば電荷Ｑを正確に読み取れるが、薄膜半導体装置ではトランジスタ特性が単結晶硅素ＬＳＩ技術程には優れず、又薄膜半導体装置間の特性偏差も大きいが故に電荷Ｑを正確に読み取れない。   Now, as shown in FIG. 1, it is impossible to produce a capacitance detecting device to which a conventional operation principle is applied using a thin film semiconductor device with the current technology of the thin film semiconductor device. Since the charge Q induced between two capacitors connected in series is very small, the charge Q can be accurately read using single crystal silicon LSI technology that enables high-precision sensing. However, the charge Q cannot be read accurately because it is not as good as single crystal silicon LSI technology and the characteristic deviation between thin film semiconductor devices is large.

そこで本発明の静電容量検出装置はＭ行Ｎ列の行列状に配置されたＭ本（Ｍは１以上の整数）の行線と、Ｎ本（Ｎは１以上の整数）の列線、及び各行線と各列線との交点に設けられたＭ×Ｎ個の静電容量検出素子とを具備せしめ、此等の各静電容量検出素子は信号検出素子と信号増幅素子とリセット素子とを含むとの構成とする。信号検出素子は容量検出電極と容量検出誘電体膜とを少なくとも含む。後に詳述する様に低電圧で検出感度を上げるには信号検出素子が更に基準コンデンサを含む事が望まれる。基準コンデンサを信号検出素子が含む場合、基準コンデンサは基準コンデンサ第一電極と基準コンデンサ誘電体膜と基準コンデンサ第二電極とから成る。指紋等の対象物が容量検出誘電体膜に接したり或いは接近すると、容量検出電極には対象物との静電容量に応じて電位Ｖ_Gが発生する。本発明ではこの電位Ｖ_Gを各静電容量検出素子に設けられた信号増幅素子にて増幅し、増幅された電流又は電圧に変換する。具体的には信号増幅素子はゲート電極とゲート絶縁膜と半導体膜とから成り、ソース電極とドレイン電極とゲート電極とを有する信号増幅用薄膜半導体装置から成る。同様にリセット素子もゲート電極とゲート絶縁膜と半導体膜とから成り、ソース電極とドレイン電極とゲート電極とを有するリセット用薄膜半導体装置から成る。信号増幅素子のゲート電極と容量検出電極とリセット素子のドレイン電極とは互いに接続されて居る。又、信号検出素子が基準コンデンサを含む場合、基準コンデンサの一方の電極は行線に接続されており、他方の電極は容量検出電極と信号増幅用薄膜半導体装置のゲート電極とリセット素子のドレイン電極とに接続される。例えば基準コンデンサ第一電極と行線とが電気的に接続されている場合には、基準コンデンサ第二電極が容量検出電極と信号増幅用薄膜半導体装置のゲート電極とリセット素子のドレイン電極とに電気的に接続される。反対に基準コンデンサ第二電極と行線とが電気的に接続されている場合には、基準コンデンサ第一電極が容量検出電極と信号増幅用薄膜半導体装置のゲート電極とリセット素子のドレイン電極とに電気的に接続される。尚、本願では薄膜半導体装置のソース電極とドレイン電極とを便宜上区別しない。一方の電極をソース電極と名付け、他方の電極をドレイン電極と名付ける。物理的に厳密を帰すならば、トランジスタのソース電極とドレイン電極とは、Ｎ型トランジスタでは電位の低い方がソース電極と定義され、Ｐ型トランジスタでは電位の高い方がソース電極と定義される。而るにどちらの電極の電位が高くなるかは動作状態に応じて変化する。その為に厳密にはソース電極とドレイン電極とは一つのトランジスタ内で常に入れ替わり得る。本願は説明を明瞭とする目的で斯うした厳密性を排し、便宜上一方の電極をソース電極と呼び、他方の電極をドレイン電極と呼ぶ。 Therefore, the capacitance detection device of the present invention includes M (M is an integer of 1 or more) row lines and N (N is an integer of 1 or more) column lines arranged in a matrix of M rows and N columns, And M × N capacitance detection elements provided at the intersections of the row lines and the column lines, each of the capacitance detection elements including a signal detection element, a signal amplification element, and a reset element. Is included. The signal detection element includes at least a capacitance detection electrode and a capacitance detection dielectric film. As will be described in detail later, in order to increase the detection sensitivity at a low voltage, it is desirable that the signal detection element further includes a reference capacitor. When the signal detection element includes a reference capacitor, the reference capacitor includes a reference capacitor first electrode, a reference capacitor dielectric film, and a reference capacitor second electrode. When an object such as a fingerprint or or close contact with the capacitance detection dielectric film, the capacitance detecting electrode potential V _G is generated in response to the capacitance of the object. The present invention is amplified by the signal amplifying element which is provided with the potential V _G to each of the electrostatic capacitance detection element, and converts the amplified current or voltage. Specifically, the signal amplifying element includes a gate electrode, a gate insulating film, and a semiconductor film, and includes a signal amplifying thin film semiconductor device having a source electrode, a drain electrode, and a gate electrode. Similarly, the reset element includes a gate electrode, a gate insulating film, and a semiconductor film, and includes a reset thin film semiconductor device having a source electrode, a drain electrode, and a gate electrode. The gate electrode, the capacitance detection electrode, and the drain electrode of the reset element are connected to each other. When the signal detection element includes a reference capacitor, one electrode of the reference capacitor is connected to the row line, and the other electrode is a capacitance detection electrode, a gate electrode of the signal amplification thin film semiconductor device, and a drain electrode of the reset element. And connected to. For example, when the reference capacitor first electrode and the row line are electrically connected, the reference capacitor second electrode is electrically connected to the capacitance detection electrode, the gate electrode of the signal amplification thin film semiconductor device, and the drain electrode of the reset element. Connected. Conversely, when the reference capacitor second electrode and the row line are electrically connected, the reference capacitor first electrode is connected to the capacitance detection electrode, the gate electrode of the signal amplification thin film semiconductor device, and the drain electrode of the reset element. Electrically connected. In the present application, the source electrode and the drain electrode of the thin film semiconductor device are not distinguished for convenience. One electrode is named a source electrode, and the other electrode is named a drain electrode. In terms of physical strictness, the source electrode and drain electrode of a transistor are defined as a source electrode when the potential is low in an N-type transistor, and as a source electrode when a potential is high in a P-type transistor. Thus, which electrode has a higher potential changes depending on the operating state. Therefore, strictly speaking, the source electrode and the drain electrode can always be interchanged in one transistor. The present application eliminates such strictness for the purpose of clarifying the explanation, and for convenience, one electrode is called a source electrode and the other electrode is called a drain electrode.

まず斯様な構成とした際の本願発明の基本動作原理を図２を用いて説明する。対象物の表面形状に応じて変化する静電容量Ｃ_Fを有するコンデンサと、静電容量Ｃ_Rを持つ基準コンデンサ及びトランジスタ容量Ｃ_Tを有する信号増幅用薄膜半導体装置との合成容量Ｃ_R＋Ｃ_Tとの間に誘起された電位Ｖ_Gは信号増幅用薄膜半導体装置のゲート電極（図中Ｇ）に印可され、半導体装置のゲート電位を変化させる。斯うして此の薄膜半導体装置のドレイン領域（図中Ｄ）に所定の電圧を付与すると、誘起されたゲート電位Ｖ_Gに応じて薄膜半導体装置のソースドレイン間に流れる電流Ｉ_dsは著しく変調される。ゲート電極等には電位Ｖ_Gに応じて電荷Ｑが発生しているが、此等の電荷は何処にも流れずに保存されるので、電流値Ｉ_dsは一定となる。それ故にドレイン電圧を高くしたり、或いは測定時間を長くする等で電流Ｉ_dsの測定も容易になり、斯くして薄膜半導体装置を用いても対象物の表面形状を十分正確に計測し得るのである。対象物の静電容量情報を増幅した信号（電流や電圧）は出力線を介して読み取られる。対象物の静電容量を測定するには信号増幅素子を介する電流Ｉ_dsを計測しても良いし、斯うした電流Ｉ_dsに対応する信号増幅素子を介した電圧Ｖを測定しても良い。基準コンデンサを設けぬ場合には上述の議論でＣ_Rをゼロとし、対象物の表面形状に応じて変化する静電容量Ｃ_Fとトランジスタ容量Ｃ_Tとを用いて全く同じ原理が働く。以下、発明の実施の形態として基準コンデンサを設けた例を用いて説明するが、本願発明は基準コンデンサを設けずに、基準コンデンサを信号増幅素子のトランジスタ容量で兼用する場合にも有効である。 First, the basic operation principle of the present invention in such a configuration will be described with reference to FIG. A capacitor having a capacitance C _F, which changes according to the surface shape of the object, the combined capacitance of the signal amplifying thin-film semiconductor device having a reference capacitor and the transistor capacitance C _T having a capacitance C _R C _R + C _T induced potential V _G between is applied to the gate electrode of the signal amplifying thin-film semiconductor device (figure G), to change the gate voltage of the semiconductor device. Thus, when a predetermined voltage is applied to the drain region (D in the figure) of this thin film semiconductor device, the current I _ds flowing between the source and drain of the thin film semiconductor device is significantly modulated according to the induced gate potential V _G. The Although the gate electrodes and the like are charge Q is generated in accordance with the potential V _G, the charge of these things are stored without flowing anywhere, current I _ds is constant. Therefore, it becomes easy to measure the current I _ds by increasing the drain voltage or extending the measurement time, and thus the surface shape of the object can be measured sufficiently accurately even using a thin film semiconductor device. is there. A signal (current or voltage) obtained by amplifying the capacitance information of the object is read through the output line. In order to measure the capacitance of the object, the current I _ds through the signal amplifying element may be measured, or the voltage V through the signal amplifying element corresponding to the current I _ds may be measured. . If, not provided with reference capacitor is a C _R to be zero in the above discussion, work exactly the same principle by using the electrostatic capacitance C _F and the transistor capacitance C _T, which changes according to the surface shape of the object. Hereinafter, an example in which a reference capacitor is provided will be described as an embodiment of the invention. However, the present invention is also effective when the reference capacitor is shared by the transistor capacity of the signal amplifying element without providing the reference capacitor.

次に本発明を具現化する静電容量検出素子の回路構成を図３を用いて説明する。尚、図３では本願発明の要旨が分かり易くなる様にトランジスタのソースやドレインを其々ＳとＤとで表し、基準コンデンサ第一電極を（１）と、基準コンデンサ第二電極を（２）と表してある。而るにトランジスタのソースとドレインとは入れ替え可能であるし、基準コンデンサでどちらの電極を第一電極或いは第二電極と呼ぶかも任意である。前述の如く各静電容量検出素子は信号増幅素子と信号検出素子とを必要不可欠な構成要素と為し、此等に加えてリセット素子をも含有する。信号検出素子は容量検出電極と容量検出誘電体膜とを少なくとも有し、望ましくは更に基準コンデンサを含む。基準コンデンサは基準コンデンサ第一電極と基準コンデンサ誘電体膜と基準コンデンサ第二電極とから成る。信号増幅素子のゲート電極と容量検出電極と基準コンデンサの一方の電極（第二電極とする）とリセット素子のドレイン電極とが接続されて居る。此はリセット素子が選択されてスイッチオン状態となった際に信号増幅素子のゲート電極と基準コンデンサ第二電極と容量検出電極とが接地電位と成り得る様に設定する為である。具体的にはリセット素子のソース電極を接地電位源に繋げ、リセット素子のゲート電極にリセット選択信号を入力してスイッチオン状態にすると、リセット素子のドレイン電極が接地電位になり得る様に素子を配置する。斯うするとリセット選択信号が付与された期間に信号増幅素子のゲート電極や容量検出電極、基準コンデンサ第二電極が接地電位に落ち得る。リセット素子にリセット選択信号を付与する際には、基準コンデンサ第一電極も接地電位に在るべく素子配置と配線とを施す。斯様な素子配置と配線とを為す事で、静電容量検出素子を選択して対象物の静電容量を測定する前に不要な電荷を信号増幅素子のゲート電極や容量検出電極から排除出来、その結果として検出精度が著しく向上するに至る。斯うした効果を実現するには各リセット素子にリセット選択信号を供給する専用のリセット線を静電容量検出装置内に設けても良いし、同様に各リセット素子のソース電極に接続される専用の接地線を静電容量検出装置内に設けても良い。これ以外の優れた一例として本願ではリセット素子（i行ｊ列の静電容量検出素子ＥＣＳＥ_ij内に設けられたリセット素子ＲＥ_ij）のソース電極を自身が属する静電容量検出素子（ＥＣＳＥ_ij）を位置づける行線（i行目の行線ＲＬ_i）に接続し、ゲート電極を静電容量検出素子を位置づける行線の隣接段に位置する行線に接続する。即ちｉ行目に位置する静電容量検出素子（ＥＣＳＥ_ij）内のリセット素子（ＲＥ_ij）のソース電極をｉ行目の行線（ＲＬ_i）に接続し、ゲート電極を隣接段たるｉ＋１行目（後段行ＲＬ_i+1）乃至はｉ−１行目（前段行ＲＬ_i-1）の行線に接続する（図３）。斯うした構成にすると静電容量検出装置内の配線数を減らし、容量検出電極の面積を増大させ、容量検出電極と各配線との間に生ずる寄生容量を最小とする事が可能になるので、高精度に対象物の静電容量を検出出来る様になる。 Next, a circuit configuration of a capacitance detection element embodying the present invention will be described with reference to FIG. In FIG. 3, the source and drain of the transistor are represented by S and D, respectively, so that the gist of the present invention can be easily understood, the reference capacitor first electrode is (1), and the reference capacitor second electrode is (2). It is expressed. Thus, the source and drain of the transistor can be interchanged, and which electrode is called the first electrode or the second electrode in the reference capacitor is arbitrary. As described above, each capacitance detection element includes the signal amplification element and the signal detection element as indispensable components, and additionally includes a reset element. The signal detection element has at least a capacitance detection electrode and a capacitance detection dielectric film, and preferably further includes a reference capacitor. The reference capacitor includes a reference capacitor first electrode, a reference capacitor dielectric film, and a reference capacitor second electrode. The gate electrode of the signal amplification element, the capacitance detection electrode, one electrode (referred to as a second electrode) of the reference capacitor, and the drain electrode of the reset element are connected. This is to set the gate electrode, the reference capacitor second electrode, and the capacitance detection electrode of the signal amplifying element to be at the ground potential when the reset element is selected and switched on. Specifically, when the source electrode of the reset element is connected to the ground potential source and the reset selection signal is input to the gate electrode of the reset element to switch it on, the element is connected so that the drain electrode of the reset element can be at the ground potential. Deploy. In this case, the gate electrode, the capacitance detection electrode, and the reference capacitor second electrode of the signal amplification element can fall to the ground potential during the period when the reset selection signal is applied. When the reset selection signal is applied to the reset element, the element arrangement and the wiring are applied so that the reference capacitor first electrode is also at the ground potential. By making such element arrangement and wiring, unnecessary charges can be eliminated from the gate electrode and capacitance detection electrode of the signal amplification element before selecting the capacitance detection element and measuring the capacitance of the object. As a result, the detection accuracy is significantly improved. In order to realize such an effect, a dedicated reset line for supplying a reset selection signal to each reset element may be provided in the capacitance detection device, and similarly, a dedicated reset line connected to the source electrode of each reset element is provided. May be provided in the capacitance detection device. Other outstanding reset element is in this application as an example an electrostatic capacitance detection element that the source electrode itself belongs (i row and j-th column of the electrostatic capacitance detection element reset element RE _ij provided ECSE the _ij) (ECSE _ij) Is connected to the row line (i-th row line RL _i ), and the gate electrode is connected to the row line located at the adjacent stage of the row line positioning the capacitance detection element. That is, the source electrode of the reset element (RE _ij ) in the capacitance detection element (ECSE _ij ) located in the i-th row is connected to the _i-th row line (RL _i ), and the gate electrode is an adjacent row i + 1 row. It connects to the row line of the 1st row (rear row RL _{i + 1} ) to the i-1th row (front row RL _i-1 ) (FIG. 3). With such a configuration, the number of wires in the capacitance detection device can be reduced, the area of the capacitance detection electrode can be increased, and the parasitic capacitance generated between the capacitance detection electrode and each wiring can be minimized. It becomes possible to detect the capacitance of the object with high accuracy.

信号増幅素子は行線と出力線との間に設置される。一例としては信号増幅用薄膜半導体装置のドレイン電極が行線に電気的に接続され、ソース電極が出力線に電気的に接続される。電気的に接続するとは、スイッチ素子などを介して電気的に導通し得る状態に成る事を意味する。換言すると当該静電容量検出素子が選択状態とされた時に信号増幅用薄膜半導体装置のドレイン電極が行線と電気的に導通状態となり、ソース電極が出力線と電気的に導通状態になる事を意味する。無論、ソース電極が直接に出力線と接続されても良いし、ドレイン電極が直接に行線と接続されても良い。静電容量検出装置内に設けられる出力線は列線と同数のＮ本として列方向に取り出す事も可能であるし、行線と同数のＭ本として行方向に取り出す事も可能である。更には二列に一本の出力線を設けたり、或いは二行に一本の出力線を設けても良い。本発明では各静電容量検出素子を一つずつ選択して行くので出力線は斯様に多様な形態を有し得る。図３の例では出力線の数を列線と同数のＮ本とし、列方向に出力線を取り出している。   The signal amplifying element is installed between the row line and the output line. As an example, the drain electrode of the thin film semiconductor device for signal amplification is electrically connected to the row line, and the source electrode is electrically connected to the output line. The term “electrically connected” means that a state is established in which electrical conduction can be achieved through a switch element or the like. In other words, when the capacitance detection element is in the selected state, the drain electrode of the signal amplification thin film semiconductor device is electrically connected to the row line, and the source electrode is electrically connected to the output line. means. Of course, the source electrode may be directly connected to the output line, or the drain electrode may be directly connected to the row line. The number of output lines provided in the capacitance detection device can be taken out in the column direction as the same number N as the column lines, or can be taken out in the row direction as the same number M as the row lines. Furthermore, one output line may be provided in two columns, or one output line may be provided in two rows. In the present invention, since each capacitance detection element is selected one by one, the output line can have such various forms. In the example of FIG. 3, the number of output lines is N, which is the same as the number of column lines, and the output lines are taken out in the column direction.

i行ｊ列に位置する静電容量検出素子（ＥＣＳＥ_ij）内に設けられた基準コンデンサの一方の電極はi行目の行線（ＲＬ_i）に接続され、他方の電極は容量検出電極と信号増幅用ＭＩＳ型半導体装置のゲート電極とに接続される。先にも述べた様に行線が選択された状態で行線には高電位が付与されるので、行線に直接接続された基準コンデンサの一方の電極には高電位（Ｖ_dd）が印可され、対象物の静電容量に応じた電位が信号増幅素子のゲート電極に加わる。斯うして信号増幅用薄膜半導体装置のソースドレイン間の電気伝導度が変化し、此を検出して指紋情報と云った対象物の表面凹凸情報が取得される。 One electrode of a reference capacitor provided in the capacitance detection element (ECSE _ij ) located in the i row and j column is connected to the row line (RL _i ) of the i row, and the other electrode is a capacitance detection electrode. It is connected to the gate electrode of the signal amplification MIS type semiconductor device. As described above, since a high potential is applied to the row line when the row line is selected, a high potential (V _dd ) is applied to one electrode of the reference capacitor directly connected to the row line. Then, a potential corresponding to the capacitance of the object is applied to the gate electrode of the signal amplification element. Thus, the electrical conductivity between the source and drain of the thin film semiconductor device for signal amplification changes, and this is detected to obtain surface unevenness information of the object such as fingerprint information.

基本的には斯様な構成にて精度の良く静電容量を検出可能であるが、静電容量検出素子間の情報干渉を防いで高速にて高精度検出を実現させるには、静電容量検出素子が列選択素子を含む事が望ましい。列選択素子はゲート電極とゲート絶縁膜と半導体膜とから成る列選択用薄膜半導体装置から成る。信号増幅素子を成す信号増幅用薄膜半導体装置と列選択用薄膜半導体装置とは直列に接続されて行線と出力線との間に配置される。図３では列選択素子にＰ型半導体装置を用い、Ｎ型半導体装置の信号増幅素子との間にＰＮ接合ダイオードを設けている。ＰＮ接合ダイオードは行線から出力線の方向が順方向になるように設置する。即ち直列接続された列選択素子と信号選択素子との内でＰ型トランジスタを用いた列選択素子が行線側に位置し、Ｎ型トランジスタを用いた信号増幅素子が出力線側に位置する。各静電容量検出素子内に列選択素子を設けることで列選択が一意的に為され、列間の情報干渉を防げられる。更に各静電容量検出素子内にダイオードを設ける事に依り出力線から行線への情報逆流を防止出来、精度良く静電容量を検出出来る様になる。図３に示す様にi行ｊ列に位置する静電容量検出素子（ＥＣＳＥ_ij）が列選択素子を含む場合には、列選択用薄膜半導体装置のゲート電極はｊ列目の列線（ＣＬ_i）に接続される。Ｍ本の行線の内で特定の行線（例えばi行目の行線）が選択され、その行線（i行目の行線）に高電位が印可される。この状態にてＮ本の列線の内で特定の列線（例えばｊ列目の列線）に選択信号が入って来ると、その列線（ｊ列目の列線）に接続された列選択素子の電気伝導度が上がりトランジスタ・オン状態となる。図３の例では列選択素子にＰ型トランジスタを使用しているので、列線には非選択状態で高電位が加わり、選択状態の時にのみ低電位（Ｖ_ss）が付与される。勿論この構成と反対に列選択素子にＮ型トランジスタを使用し、非選択状態にＮ型トランジスタのゲート電極に低電位を加え、選択時に高電位を付与しても良い。この結果、行線に印可された高電位が信号増幅素子のドレイン電極に印可され、対象物の凹凸情報に応じたゲート電圧にて変調されたソースドレイン電流が信号増幅素子に発生する。斯くして選択された行（i行）と列（ｊ列）との交点に位置する静電容量検出素子（i行ｊ列に位置する静電容量検出素子ＥＣＳＥ_ij）のみがＭ×Ｎ個の静電容量検出素子群の中から選択されて、その位置に於ける対象物の静電容量を測定することになる。 Basically, it is possible to detect the capacitance with high accuracy with such a configuration, but in order to prevent information interference between the capacitance detection elements and realize high-precision detection at high speed, the capacitance It is desirable that the detection element includes a column selection element. The column selection element comprises a column selection thin film semiconductor device comprising a gate electrode, a gate insulating film, and a semiconductor film. The signal amplifying thin film semiconductor device and the column selecting thin film semiconductor device which form the signal amplifying element are connected in series and arranged between the row line and the output line. In FIG. 3, a P-type semiconductor device is used as the column selection element, and a PN junction diode is provided between the signal selection element of the N-type semiconductor device. The PN junction diode is installed so that the direction from the row line to the output line is the forward direction. That is, among the column selection element and the signal selection element connected in series, a column selection element using a P-type transistor is located on the row line side, and a signal amplification element using an N-type transistor is located on the output line side. By providing a column selection element in each capacitance detection element, column selection is uniquely performed and information interference between columns can be prevented. Furthermore, by providing a diode in each capacitance detection element, information backflow from the output line to the row line can be prevented, and the capacitance can be detected with high accuracy. As shown in FIG. 3, when the capacitance detection element (ECSE _ij ) located in i row and j column includes a column selection element, the gate electrode of the thin film semiconductor device for column selection is the column line (CL _i ) connected. A specific row line (for example, the i-th row line) is selected from among the M row lines, and a high potential is applied to the row line (i-th row line). In this state, when a selection signal enters a specific column line (for example, the jth column line) among the N column lines, the column connected to that column line (jth column line). The electrical conductivity of the selection element is increased and the transistor is turned on. In the example of FIG. 3, since a P-type transistor is used for the column selection element, a high potential is applied to the column line in a non-selected state, and a low potential (V _ss ) is applied only in the selected state. Of course, an N-type transistor may be used as the column selection element in contrast to this configuration, and a low potential may be applied to the gate electrode of the N-type transistor in a non-selected state to apply a high potential during selection. As a result, a high potential applied to the row line is applied to the drain electrode of the signal amplifying element, and a source / drain current modulated with a gate voltage corresponding to the unevenness information of the object is generated in the signal amplifying element. Thus, only M × N capacitance detection elements (capacitance detection elements ECSE _ij located in i rows and j columns) located at the intersections of the selected rows (i rows) and columns (j columns). The electrostatic capacitance of the object at that position is measured from the electrostatic capacitance detection element group.

各静電容量検出素子が列選択素子を含んでいると、上述の如くＭ×Ｎ個の静電容量検出素子群の中から特定の一静電容量検出素子のみを確実に選択するとの利点が認められる。その一方で、もし基準コンデンサが無ければ、信号増幅素子のトランジスタ容量と対象物の容量とが容量結合して、その容量比とドレイン電圧との積が信号増幅素子のゲート電極に印可される。所が列選択素子と信号増幅素子とが直列に接続されているので、信号増幅素子のドレイン電位は行線に印可される高電位（Ｖ_dd）よりも列選択素子が存在する分だけ下がって仕舞う。例えば列選択素子と信号増幅素子のオン状態に於ける電気伝導度が同程度と仮定すると、行線にＶ_ddが印可された際に信号増幅素子のドレイン電位はＶ_ddの約半分であるＶ_dd/２程度に下がって仕舞う。それ故に測定対象物の静電容量が変化しても、信号増幅素子のゲート電位変化量は最大でもＶ_dd/２程度と小さくなり、検出精度が低下したり或いはＶ_ddの値を大きくせねばならなくなる。斯うした課題を解決すべく本願発明では基準コンデンサを設け、この基準コンデンサの一方の電極を行線に直接接続させる。此に依り喩え列選択素子が存在しても、基準コンデンサの一方の電極には確実に高電位（Ｖ_dd）が印可され、それ故に信号増幅素子のゲート電位は最小でゼロ付近、最大でＶ_dd付近と成り得る。即ち本発明の構成とすると、喩え列選択素子が信号増幅素子と直列接続されて行線と出力線との間に設けられていても、信号増幅素子のゲート電位は負電源電位（Ｖ_ss：ゼロボルト）付近から正電源電位（Ｖ_dd：高電位）付近迄測定対象物の静電容量に応じて変化し得る様になる。信号増幅素子のゲート電位が負電源電位付近にあると、信号増幅用薄膜半導体装置はオフ状態になり、信号増幅素子の電気伝導度は著しく小さくなる。反対に信号増幅素子のゲート電位が正電源電位付近になると、信号増幅用薄膜半導体装置はオン状態になり、信号増幅素子の電気伝導度は窮めて大きくなる。斯うした電気伝導度の変化を出力線経由で測定する事で対象物表面の凹凸情報を採取出来るのである。 When each capacitance detection element includes a column selection element, there is an advantage that only one specific capacitance detection element is reliably selected from the M × N capacitance detection element group as described above. Is recognized. On the other hand, if there is no reference capacitor, the transistor capacitance of the signal amplification element and the capacitance of the object are capacitively coupled, and the product of the capacitance ratio and the drain voltage is applied to the gate electrode of the signal amplification element. Since the column selection element and the signal amplification element are connected in series, the drain potential of the signal amplification element is lower than the high potential (V _dd ) applied to the row line by the presence of the column selection element. Conclude. For example, assuming that the electrical conductivity in the ON state of the column selection element and the signal amplifying element is the same, the drain potential of the signal amplifying element is approximately half of V _dd when V _dd is applied to the row line. _dd / 2 and finish. Therefore, even if the capacitance of the measurement object changes, the amount of change in the gate potential of the signal amplifying element becomes as small as V _dd / 2 at the maximum, and the detection accuracy must be lowered or the value of V _dd must be increased. No longer. In order to solve such a problem, in the present invention, a reference capacitor is provided, and one electrode of the reference capacitor is directly connected to the row line. Therefore, even if there is a column selection element, a high potential (V _dd ) is surely applied to one electrode of the reference capacitor, so that the gate potential of the signal amplification element is at least near zero and at most V _{Can be} near _dd . That is, in the configuration of the present invention, even if the analog column selection element is connected in series with the signal amplification element and provided between the row line and the output line, the gate potential of the signal amplification element is the negative power supply potential (V _ss : From near zero volts) to near the positive power supply potential (V _dd : high potential), it can change according to the capacitance of the measurement object. When the gate potential of the signal amplification element is in the vicinity of the negative power supply potential, the thin film semiconductor device for signal amplification is turned off, and the electrical conductivity of the signal amplification element is significantly reduced. On the contrary, when the gate potential of the signal amplifying element is close to the positive power supply potential, the signal amplifying thin film semiconductor device is turned on, and the electric conductivity of the signal amplifying element is increased. By measuring such a change in electrical conductivity via an output line, it is possible to collect unevenness information on the surface of the object.

上述の構成にて本願発明の信号増幅用薄膜半導体装置が効果的に信号増幅の機能を果たす為には、信号増幅用薄膜半導体装置のトランジスタ容量Ｃ_Tや基準コンデンサ容量Ｃ_R、及び信号検出素子の素子容量Ｃ_Dを適切に定めねばならない。次に此等の関係を図４乃至図５を用いて説明する。 In order to effectively perform the signal amplification function of the signal amplification thin film semiconductor device of the present invention with the above-described configuration, the transistor capacitance C _T and the reference capacitor capacitance C _R of the signal amplification thin film semiconductor device, and the signal detection element It must be properly determined the element capacitance C _D. Next, these relationships will be described with reference to FIGS.

まず、測定対処物の凸部が容量検出誘電体膜に接しており、対象物が電気的に接地されて居る状況を考える。具体的には静電容量検出装置を指紋センサとして用い、この静電容量検出装置表面に指紋の山が接している状態の検出を想定する。基準コンデンサの電極面積をＳ_R（μｍ²）、基準コンデンサ誘電体膜の厚みをｔ_R（μｍ）、基準コンデンサ誘電体膜の比誘電率をε_R、信号増幅用薄膜半導体装置のゲート電極面積をＳ_T（μｍ²）、ゲート絶縁膜の厚みをｔ_ox（μｍ）、ゲート絶縁膜の比誘電率をε_oxとして基準コンデンサ容量Ｃ_Rと信号増幅用薄膜半導体装置のトランジスタ容量Ｃ_Tとを其々
Ｃ_R＝ε₀・ε_R・Ｓ_R／ｔ_R
Ｃ_T＝ε₀・ε_ox・Ｓ_T／ｔ_ox
と定義する（ε₀は真空の誘電率）。又、容量検出電極の面積をＳ_D（μｍ²）、容量検出誘電体膜の厚みをｔ_D（μｍ）、容量検出誘電体膜の比誘電率をε_Dとして信号検出素子の素子容量Ｃ_Dを
Ｃ_D＝ε₀・ε_D・Ｓ_D／ｔ_D
と定義する（ε₀は真空の誘電率）。対象物表面が素子容量Ｃ_Dの接地電極となり、容量検出電極が容量検出誘電体膜を挟んで他方の電極に相当する。容量検出電極は信号増幅用薄膜半導体装置のゲート電極と基準コンデンサの一方の電極とに接続されて居るので、素子容量Ｃ_Dを持つコンデンサとトランジスタ容量Ｃ_Tを持つコンデンサとが直列に接続され、同時に素子容量Ｃ_Dを持つコンデンサは基準コンデンサ容量Ｃ_Rを持つコンデンサとも直列に接続される事に成る。基準コンデンサの他方の電極は行線に接続され、行線が選択された際には電圧Ｖ_ddが印可される。一方、信号増幅素子は列選択素子と直列接続されて行線と出力線との間に配置されているので、行線が選択された際に於ける信号増幅用ＭＩＳ薄膜半導体装置のドレイン電位はＶ_ddのｋ倍（０＜ｋ≦１）となる（図４）。ｋの値は列選択素子の抵抗値と信号増幅素子の抵抗値にて定まり、具体的にはゼロよりも大きく、１以下である。列選択素子を設けぬ場合にｋの値は１になる。行線への印可電圧と信号増幅素子のドレイン電位は此等３つのコンデンサの静電容量に応じて分割されるから、この状態にて信号増幅用薄膜半導体装置のゲート電極に掛かる電圧（凸部が接した時のゲート電圧）Ｖ_GTは

となる。従って、素子容量Ｃ_Dが基準コンデンサ容量Ｃ_Rとトランジスタ容量Ｃ_Tとの和であるＣ_R＋Ｃ_Tよりも十分に大きい時

には、ゲート電圧Ｖ_GTは

と近似され、ゲート電極には殆ど電圧が掛からない。その結果、信号増幅用薄膜半導体装置はオフ状態となり、電流Ｉは窮めて小さくなる。結局、指紋の山に相当する対象物の凸部が静電容量検出装置に接した時に信号増幅素子が殆ど電流を流さない為には、静電容量検出素子を構成するゲート電極面積（ゲート長やゲート幅）やゲート絶縁膜材質、ゲート絶縁膜厚、基準コンデンサ電極面積（コンデンサ電極長やコンデンサ電極幅）、基準コンデンサ誘電体膜材質、基準コンデンサ誘電体膜厚、容量検出電極面積、容量検出誘電体膜材質、容量検出誘電体膜厚などを、素子容量Ｃ_Dが基準コンデンサ容量Ｃ_Rとトランジスタ容量Ｃ_Tとの和であるＣ_R＋Ｃ_Tよりも十分に大きくなる様に設定せねばならない訳で有る。一般に「十分に大きい」とは１０倍程度の相違を意味する。換言すれば素子容量Ｃ_Dは基準コンデンサ容量Ｃ_Rとトランジスタ容量Ｃ_Tとの和であるＣ_R＋Ｃ_Tと
Ｃ_D＞１０×(Ｃ_R+Ｃ_T)
との関係を満たせば良い。この場合、Ｖ_GT／Ｖ_ddは０．１程度以下となり薄膜半導体装置はオン状態には成り得ない。対象物の凸部を確実に検出するには、対象物の凸部が静電容量検出装置に接した時に、信号増幅用薄膜半導体装置がオフ状態に成る事が重要である。従って電源電圧Ｖ_ddに正電源を用いる場合には信号増幅用薄膜半導体装置として、ゲート電圧がゼロ近傍でドレイン電流が流れないエンハンスメント型（ノーマリーオフ型）Ｎ型トランジスタを用いるのが好ましい。より理想的には、伝達特性に於けるドレイン電流が最小値となるゲート電圧（最小ゲート電圧）をＶ_minとして、この最小ゲート電圧が
０＜０．１×Ｖ_dd＜Ｖ_min
又は
０＜Ｖ_GT＜Ｖ_min
との関係を満たす様な信号増幅用Ｎ型ＭＩＳ薄膜半導体装置を使用する。反対に電源電圧Ｖ_ddに負電源を用いる場合には信号増幅用薄膜半導体装置として、ゲート電圧がゼロ近傍でドレイン電流が流れないエンハンスメント型（ノーマリーオフ型）Ｐ型トランジスタを用いる。理想的には信号増幅用Ｐ型ＭＩＳ薄膜半導体装置の最小ゲート電圧Ｖ_minが
Ｖ_min＜０．１×Ｖ_dd＜０
又は
Ｖ_min＜Ｖ_GT＜０
との関係を満たす信号増幅用Ｐ型ＭＩＳ薄膜半導体装置を使用する事である。斯うする事に依り対象物の凸部を、電流値Ｉが非常に小さいとの形態にて確実に検出し得るので有る。 First, consider a situation where the convex portion of the measurement object is in contact with the capacitance detection dielectric film and the object is electrically grounded. Specifically, it is assumed that a capacitance detection device is used as a fingerprint sensor, and that a state in which a crest of fingerprints is in contact with the surface of the capacitance detection device is assumed. The electrode area of the reference capacitor is S _R (μm ² ), the thickness of the reference capacitor dielectric film is t _R (μm), the relative dielectric constant of the reference capacitor dielectric film is ε _R , and the gate electrode area of the thin film semiconductor device for signal amplification the S _T (μm ^2), the thickness of the gate insulating film t _ox (μm), and the transistor capacitance C _T of the reference capacitance C _R and the signal amplifying thin-film semiconductor device the dielectric constant of the gate insulating film as epsilon _ox C _R = ε ₀・ ε _R・ S _R / t _R
C _T = ε ₀ · ε _ox · S _T / t _ox
(Ε ₀ is the dielectric constant of vacuum). The capacitance of the signal detection element is C _D , where S _D (μm ² ) is the area of the capacitance detection electrode, t _D (μm) is the thickness of the capacitance detection dielectric film, and ε _D is the relative dielectric constant of the capacitance detection dielectric film. C _D = ε ₀ · ε _D · S _D / t _D
(Ε ₀ is the dielectric constant of vacuum). The object surface becomes the ground electrode of the element capacitance C _D, the capacitance detecting electrode is equivalent to the other electrode across the capacitance detecting dielectric layer. Since the capacitance detection electrodes have been connected to one electrode of the gate electrode and the reference capacitor of the signal amplifying thin-film semiconductor device, a capacitor having a capacitor and the transistor capacitance C _T with element capacitance C _D is connected in series, capacitors will be connected in series with a capacitor having a reference capacitance C _R at the same time with an element capacitance C _D. The other electrode of the reference capacitor is connected to the row line, and a voltage V _dd is applied when the row line is selected. On the other hand, since the signal amplifying element is connected in series with the column selection element and arranged between the row line and the output line, the drain potential of the signal amplifying MIS thin film semiconductor device when the row line is selected is It becomes k times _Vdd (0 <k ≦ 1) (FIG. 4). The value of k is determined by the resistance value of the column selection element and the resistance value of the signal amplifying element, and specifically is greater than zero and equal to or less than 1. If no column selection element is provided, the value of k is 1. Since the voltage applied to the row line and the drain potential of the signal amplifying element are divided according to the capacitance of these three capacitors, the voltage (convex portion) applied to the gate electrode of the signal amplifying thin film semiconductor device in this state the gate voltage) V _GT of when is in contact

It becomes. Therefore, when the element capacitance C _D is sufficiently larger than C _R + C _T which is the sum of the reference capacitor capacitance C _R and the transistor capacitance C _T.

The gate voltage V _GT is

And almost no voltage is applied to the gate electrode. As a result, the signal amplifying thin film semiconductor device is turned off, and the current I is reduced. Eventually, in order for the signal amplifying element to hardly pass current when the convex portion of the object corresponding to the peak of the fingerprint is in contact with the capacitance detecting device, the area of the gate electrode (gate length constituting the capacitance detecting element) Gate width), gate insulating film material, gate insulating film thickness, reference capacitor electrode area (capacitor electrode length and capacitor electrode width), reference capacitor dielectric film material, reference capacitor dielectric film thickness, capacitance detection electrode area, capacitance detection The dielectric film material, the capacitance detection dielectric film thickness, etc. must be set so that the element capacitance C _D is sufficiently larger than C _R + C _T which is the sum of the reference capacitor capacitance C _R and the transistor capacitance C _T. There is a translation. In general, “sufficiently large” means a difference of about 10 times. In other words, the element capacitance C _D is the sum of the reference capacitor capacitance C _R and the transistor capacitance C _T C _R + C _T and C _D > 10 × (C _R + C _T )
Satisfy the relationship with. In this case, V _GT / V _dd is about 0.1 or less, and the thin film semiconductor device cannot be turned on. In order to reliably detect the convex portion of the target object, it is important that the thin film semiconductor device for signal amplification is turned off when the convex portion of the target object contacts the capacitance detection device. Therefore, when a positive power supply is used for the power supply voltage V _dd, it is preferable to use an enhancement type (normally off type) N-type transistor in which the drain current does not flow when the gate voltage is near zero as the thin film semiconductor device for signal amplification. More ideally, let V _min be the gate voltage (minimum gate voltage) at which the drain current in the transfer characteristic is the minimum value, and this minimum gate voltage is 0 <0.1 × V _dd <V _min
Or 0 <V _GT <V _min
An N-type MIS thin film semiconductor device for signal amplification that satisfies the above relationship is used. On the contrary, when a negative power supply is used for the power supply voltage _Vdd , an enhancement type (normally off type) P-type transistor in which the drain current does not flow when the gate voltage is near zero is used as the signal amplification thin film semiconductor device. Ideally, the minimum gate voltage V _min of the P-type MIS thin film semiconductor device for signal amplification is V _min <0.1 × V _dd <0.
Or V _min <V _GT <0
The signal amplification P-type MIS thin film semiconductor device satisfying the relationship is used. As a result, the convex portion of the object can be reliably detected in the form that the current value I is very small.

次に対象物が容量検出誘電体膜に接しずに対象物距離ｔ_Aを以て容量検出誘電体膜から離れて居る状況を考える。即ち測定対処物の凹部が容量検出誘電体膜上に有り、更に対象物が電気的に接地されて居る状況で有る。具体的には静電容量検出装置を指紋センサとして用いた時に、静電容量検出装置表面に指紋の谷が来て居る状態の検出を想定する。先にも述べた様に、本発明の静電容量検出装置では容量検出誘電体膜が静電容量検出装置の最表面に位置するのが望ましい。この時の等価回路図を図５に示す。容量検出誘電体膜に対象物表面が接していないので、容量検出誘電体膜と対象物表面との間には空気を誘電体とした新たなコンデンサーが形成される。此を対象物容量Ｃ_Aと名付け、真空の誘電率ε₀と空気の比誘電率ε_Aと容量検出電極の面積Ｓ_Dとを用いて、
Ｃ_A＝ε₀・ε_A・Ｓ_D／ｔ_A
と定義する。斯うして対象物が容量検出誘電体膜から離れた状態では、素子容量Ｃ_Dと対象物容量Ｃ_Aとが直列に接続され、更に此等のコンデンサに互いに並列接続されたトランジスタ容量Ｃ_Tと基準コンデンサ容量Ｃ_Rとが直列に接続される事になる。基準コンデンサには電圧Ｖ_ddが印可され、信号増幅素子のドレイン電極にはｋＶ_ddの電圧が印可される（図５）。印可電圧は静電容量に応じて四つのコンデンサー間で分割されるので、この条件下にて信号増幅用薄膜半導体装置のゲート電極に掛かる電圧（谷が来たときのゲート電圧）Ｖ_GVは

となる。一方、本発明では対象物が静電容量検出装置に接した時にドレイン電流が非常に小さくなる様に

との条件を満たすべく静電容量検出素子を作成して在るので、Ｖ_GVは

と近似される。此処で基準コンデンサ容量Ｃ_Rを対象物容量Ｃ_Aよりも十分に大きくなる様に設定すると、

ゲート電圧Ｖ_GVは

と更に簡略化される。斯うしてｋの値が１に近ければ、ゲート電圧Ｖ_GVは電源電圧Ｖ_ddに略等しくなる。基準コンデンサ容量Ｃ_Rがトランジスタ容量Ｃ_Tよりも十分に大きくなるよう設定しておくと、

ｋの値の大小に関わらず、ゲート電圧Ｖ_GVは

となり、電源電圧Ｖ_ddにほぼ等しくなる。この結果、信号増幅用薄膜半導体装置をオン状態と出来、電流Ｉは窮めて大きくなる。指紋の谷に相当する対象物の凹部が静電容量検出装置上に来た時に信号増幅素子が大電流を通す為には、基準コンデンサ容量Ｃ_Rが対象物容量Ｃ_Aよりも十分に大きくなる様に構成付ける必要がある。先に述べた如く、１０倍程度の相違が認められると一般に十分に大きいと言えるので、基準コンデンサ容量Ｃ_Rと対象物容量Ｃ_Aとが
Ｃ_R＞１０×Ｃ_A
との関係を満たせば良い。又、ｋの値如何に関わらず指紋の谷等が接近した時にトランジスタがオン状態になるには基準コンデンサ容量Ｃ_Rがトランジスタ容量Ｃ_Tよりも十倍以上大きくしておけば良い。 Then the object is considered a situation where there away from the capacitance detecting dielectric layer with a subject distance t _A without contacting the capacitance detecting dielectric layer. That is, there is a situation in which the concave portion of the measurement object is on the capacitance detection dielectric film and the object is electrically grounded. Specifically, it is assumed that a fingerprint valley is present on the surface of the capacitance detection device when the capacitance detection device is used as a fingerprint sensor. As described above, in the capacitance detection device of the present invention, it is desirable that the capacitance detection dielectric film is located on the outermost surface of the capacitance detection device. An equivalent circuit diagram at this time is shown in FIG. Since the object surface is not in contact with the capacitance detection dielectric film, a new capacitor using air as a dielectric is formed between the capacitance detection dielectric film and the object surface. This is named the object capacitance C _A, and using the vacuum dielectric constant ε ₀ , the relative dielectric constant ε _{A of} air and the area _{SD of the} capacitance detection electrode,
C _A = ε ₀ · ε _A · S _D / t _A
It is defined as Thus, in a state where the object is away from the capacitance detection dielectric film, the element capacitor C _D and the object capacitor C _A are connected in series, and further, the transistor capacitor C _T connected in parallel to these capacitors are connected to each other. The reference capacitor capacitance C _R is connected in series. A voltage V _dd is applied to the reference capacitor, and a voltage kV _dd is applied to the drain electrode of the signal amplifying element (FIG. 5). Since the applied voltage is divided among the four capacitors according to the electrostatic capacity, the voltage applied to the gate electrode of the thin film semiconductor device for signal amplification under this condition (gate voltage when the valley comes) V _GV is

It becomes. On the other hand, in the present invention, the drain current becomes very small when the object contacts the capacitance detection device.

Since the capacitance detection element has been created to satisfy the condition, V _GV is

Is approximated by Here, if the reference capacitor capacity C _R is set to be sufficiently larger than the object capacity C _A ,

The gate voltage V _GV is

And is further simplified. Thus, if the value of k is close to 1, the gate voltage V _GV is substantially equal to the power supply voltage V _dd . If the reference capacitor capacitance C _R is set to be sufficiently larger than the transistor capacitance C _T ,

Regardless of the value of k, the gate voltage V _GV is

Thus, it becomes almost equal to the power supply voltage V _dd . As a result, the signal amplification thin film semiconductor device can be turned on, and the current I is given up and increased. To pass the signal amplifying element a large current when a recessed portion of the object corresponding to a valley of a fingerprint came on an electrostatic capacitance detection device, the reference capacitance C _R is sufficiently larger than the object capacitance C _A It is necessary to configure like this. As described above, if a difference of about 10 times is recognized, it can be generally said that the difference is large enough, so that the reference capacitor capacitance C _R and the object capacitance C _A are C _R > 10 × C _A.
Satisfy the relationship with. In addition, the reference capacitor capacitance C _R may be made ten times or more larger than the transistor capacitance C _{T in} order to turn on the transistor when the valley of the fingerprint approaches, regardless of the value of k.

Ｃ_R＞１０×Ｃ_T
此等の条件を満たすと、Ｖ_GT／Ｖ_ddは０．９程度以上となり薄膜半導体装置は容易にオン状態と化す。対象物の凹部を確実に検出するには、対象物の凹部が静電容量検出装置に近づいた時に、信号増幅用薄膜半導体装置がオン状態に成る事が重要である。電源電圧Ｖ_ddに正電源を用いる場合には信号増幅用薄膜半導体装置としてエンハンスメント型（ノーマリーオフ型）Ｎ型トランジスタを用いており、このトランジスタの閾値電圧Ｖ_thがＶ_GVよりも小さいのが好ましい。より理想的には、
０＜Ｖ_th＜０．９１×Ｖ_dd
との関係を満たす様な信号増幅用Ｎ型ＭＩＳ薄膜半導体装置を使用する。反対に電源電圧Ｖ_ddに負電源を用いる場合には信号増幅用薄膜半導体装置としてエンハンスメント型（ノーマリーオフ型）Ｐ型トランジスタを用ており、理想的には信号増幅用Ｐ型ＭＩＳ薄膜半導体装置の閾値電圧Ｖ_thがＶ_GVよりも大きいのが好ましい。より理想的には、
０．９１×Ｖ_dd＜Ｖ_th＜０
との関係を満たす信号増幅用Ｐ型ＭＩＳ薄膜半導体装置を使用する事である。斯うする事に依り対象物の凹部が、電流値Ｉが非常に大きいとの形態にて確実に検出されるに至る。 C _R > 10 × C _T
When these conditions are satisfied, V _GT / V _dd is about 0.9 or more, and the thin film semiconductor device is easily turned on. In order to reliably detect the concave portion of the target object, it is important that the signal amplification thin film semiconductor device is turned on when the concave portion of the target object approaches the capacitance detection device. When a positive power supply is used for the power supply voltage _Vdd , an enhancement type (normally off type) N-type transistor is used as the thin film semiconductor device for signal amplification, and the threshold voltage _{Vth of} this transistor is smaller than V _GV. preferable. More ideally,
0 <V _th <0.91 × V _dd
An N-type MIS thin film semiconductor device for signal amplification that satisfies the above relationship is used. On the other hand, when a negative power supply is used for the power supply voltage _Vdd , an enhancement type (normally-off type) P-type transistor is used as the signal amplification thin film semiconductor device, and ideally a signal amplification P type MIS thin film semiconductor device. It is preferable that the threshold voltage _Vth is greater than _VGV . More ideally,
0.91 × V _dd <V _th <0
The signal amplification P-type MIS thin film semiconductor device satisfying the relationship is used. As a result, the concave portion of the object is reliably detected in a form that the current value I is very large.

結局、指紋の山等に相当する対象物の凸部が静電容量検出装置に接した時に信号増幅素子が殆ど電流を通さず、同時に指紋の谷等に相当する対象物の凹部が静電容量検出装置に近づいた時に信号増幅素子が大きな電流を通して対象物の凹凸を正しく認識するには、静電容量検出素子にて容量検出誘電体膜が静電容量検出装置の最表面に位置し、信号増幅用薄膜半導体装置のゲート電極面積Ｓ_T（μｍ²）やゲート絶縁膜の厚みｔ_ox（μｍ）、ゲート絶縁膜の比誘電率ε_ox、基準コンデンサの電極面積Ｓ_R（μｍ²）、基準コンデンサ誘電体膜の厚みｔ_R（μｍ）、基準コンデンサ誘電体膜の比誘電率ε_R、容量検出電極面積Ｓ_D（μｍ²）、容量検出誘電体膜の厚みｔ_D（μｍ）、容量検出誘電体膜の比誘電率ε_D等を素子容量Ｃ_Dが基準コンデンサ容量Ｃ_Rとトランジスタ容量Ｃ_Tとの和であるＣ_R＋Ｃ_Tよりも十分に大きくなる様に設定する必要があり、且つ対象物が容量検出誘電体膜に接しずに対象物距離ｔ_Aを以て離れて居る際に基準コンデンサ容量Ｃ_Rが対象物容量Ｃ_Aよりも十分に大きく成る様に静電容量検出装置を構成づける必要がある。更に基準コンデンサ容量Ｃ_Rがトランジスタ容量Ｃ_Tよりも十分大きいのが理想的と言える。より具体的には基準コンデンサ容量Ｃ_Rとトランジスタ容量Ｃ_Tとが
Ｃ_R＞１０×Ｃ_T
との関係式を満たした上で、素子容量Ｃ_Dと基準コンデンサ容量Ｃ_Rと対象物容量Ｃ_Aとが
Ｃ_D＞１０×Ｃ_R
Ｃ_R＞１０×Ｃ_A
との関係を満たす様に静電容量検出装置を特徴付ける。又、電源電圧Ｖ_ddに正電源を用いる場合には信号増幅用薄膜半導体装置としてエンハンスメント型（ノーマリーオフ型）Ｎ型トランジスタを用いるのが好ましく、此のＮ型トランジスタの最小ゲート電圧Ｖ_minは
０＜０．１×Ｖ_dd＜Ｖ_min 又は０＜Ｖ_GT＜Ｖ_min
との関係を満たし、更に閾値電圧Ｖ_thがＶ_GVよりも小さく、具体的には
０＜Ｖ_th＜０．９１×Ｖ_dd 又は０＜Ｖ_th＜Ｖ_GV
との関係を満たしているエンハンスメント型Ｎ型トランジスタを用いるのが理想的である。反対に電源電圧Ｖ_ddに負電源を用いる場合には信号増幅用薄膜半導体装置としてエンハンスメント型（ノーマリーオフ型）Ｐ型トランジスタを用いるのが好ましく、此のＰ型トランジスタの最小ゲート電圧Ｖ_minは
Ｖ_min＜０．１×Ｖ_dd＜０ 又はＶ_min＜Ｖ_GT＜０
との関係を満たし、更に閾値電圧Ｖ_thがＶ_GVよりも大きく、具体的には
０．９１×Ｖ_dd＜Ｖ_th＜０ 又はＶ_GV＜Ｖ_th＜０
との関係を満たしているエンハンスメント型Ｐ型トランジスタを用いるのが理想的である。 Eventually, when the convex part of the object corresponding to the fingerprint crest etc. is in contact with the capacitance detection device, the signal amplification element hardly conducts current, and at the same time the concave part of the object corresponding to the fingerprint trough etc. In order for the signal amplification element to correctly recognize the unevenness of the object through a large current when approaching the detection device, the capacitance detection dielectric film is positioned on the outermost surface of the capacitance detection device and the signal The gate electrode area S _T (μm ² ) of the thin film semiconductor device for amplification, the thickness t _ox (μm) of the gate insulating film, the relative dielectric constant ε _ox of the gate insulating film, the electrode area S _R (μm ² ) of the reference capacitor, and the reference Capacitor dielectric film thickness t _R (μm), reference capacitor dielectric film relative dielectric constant ε _R , capacitance detection electrode area S _D (μm ² ), capacitance detection dielectric film thickness t _D (μm), capacitance detection a dielectric film having a relative dielectric constant epsilon _D or the like element capacitance C _D is the reference capacitor Must be set so as to be sufficiently larger than C _R + C _T is the sum of the capacitance C _R and the transistor capacitance C _T, and the object with a subject distance t _A without contacting the capacitance detecting dielectric layer it is necessary to reference capacitor capacitance C _R when there apart characterize constituting the electrostatic capacitance detection device as made sufficiently larger than the object capacitance C _a. Further reference capacitor capacitance C _R that sufficiently larger than the transistor capacitance C _T is said to be ideal. More specifically, the reference capacitor capacitance C _R and the transistor capacitance C _T are C _R > 10 × C _T
In addition, the element capacitance C _D , the reference capacitor capacitance C _R, and the object capacitance C _A satisfy C _D > 10 × C _R.
C _R > 10 × C _A
Characterize the capacitance detection device to satisfy the relationship. When a positive power supply is used for the power supply voltage V _dd , an enhancement type (normally off type) N-type transistor is preferably used as the signal amplification thin film semiconductor device, and the minimum gate voltage V _min of this N-type transistor is 0 <0.1 × V _dd <V _min or 0 <V _GT <V _min
And the threshold voltage V _th is smaller than V _GV , specifically, 0 <V _th <0.91 × V _dd or 0 <V _th <V _GV
It is ideal to use an enhancement type N-type transistor that satisfies the above relationship. It is preferred to use an enhancement type (normally off type) P type transistor as a signal amplifying thin-film semiconductor device in the case of using a negative power supply voltage V _dd Conversely, the minimum gate voltage V _min of此the P-type transistor V _min <0.1 × V _dd <0 or V _min <V _GT <0
And the threshold voltage V _th is larger than V _GV , specifically 0.91 × V _dd <V _th <0 or V _GV <V _th <0.
It is ideal to use an enhancement type P-type transistor that satisfies the relationship

次に斯うした発明を具現化する静電容量検出素子の構造を図６を用いて説明する。静電容量検出素子の信号増幅素子を成す信号増幅用薄膜半導体装置はソース領域とチャンネル形成領域とドレイン領域とを含む半導体膜とゲート絶縁膜とゲート電極とを不可欠な構成要件としている。同様に列選択素子を成す列選択用薄膜半導体装置もソース領域とチャンネル形成領域とドレイン領域とを含む半導体膜とゲート絶縁膜とゲート電極とを不可欠な構成要件としている。更にリセット素子を為すリセット用薄膜半導体装置もソース領域とチャンネル形成領域とドレイン領域とを含む半導体膜とゲート絶縁膜とゲート電極とを不可欠な構成要件としている。後述する様にリセット素子と信号増幅素子とは同一導電型の薄膜半導体装置であるのが好ましいので、トランジスタサイズやソースドレイン領域の不純物濃度を除いて断面構造は両者とも同一になる。それ故に図６ではリセット素子を省略し、列選択素子と信号増幅素子とを表示する。図６の構成例では信号増幅用薄膜半導体装置をＮＭＯＳで作成し、列選択用薄膜半導体装置をＰＭＯＳにて作成し、ＰＭＯＳのドレイン領域とＮＭＯＳのドレイン領域とが接合して、ＰＮ接合ダイオードを形成している。図６には示さないが、基準コンデンサ第一電極は信号増幅用薄膜半導体装置のドレイン領域と同じ素材であるＮ型半導体膜から成っている。基準コンデンサ第一電極も薄膜半導体装置のドレイン領域も同じ下地保護膜上に形成されている。基準コンデンサの誘電体膜は信号増幅用薄膜半導体装置のゲート絶縁膜（図中ＧＩ）と同一素材である酸化珪素膜から成り、共に同一層上（半導体膜上）に形成される。基準コンデンサ第二電極は信号増幅用薄膜半導体装置のゲート電極と同一素材である金属膜（具体的にはタンタル薄膜）にて形成されている。   Next, the structure of a capacitance detecting element embodying such an invention will be described with reference to FIG. A signal amplifying thin film semiconductor device constituting a signal amplifying element of a capacitance detecting element has a semiconductor film including a source region, a channel forming region, and a drain region, a gate insulating film, and a gate electrode as indispensable components. Similarly, a column selecting thin film semiconductor device that forms a column selecting element has a semiconductor film including a source region, a channel forming region, and a drain region, a gate insulating film, and a gate electrode as indispensable components. In addition, a reset thin film semiconductor device serving as a reset element also has a semiconductor film including a source region, a channel formation region, and a drain region, a gate insulating film, and a gate electrode as indispensable constituent requirements. As will be described later, since the reset element and the signal amplifying element are preferably thin film semiconductor devices of the same conductivity type, the cross-sectional structures are the same except for the transistor size and the impurity concentration of the source / drain region. Therefore, in FIG. 6, the reset element is omitted, and the column selection element and the signal amplification element are displayed. In the configuration example of FIG. 6, the signal amplifying thin film semiconductor device is made of NMOS, the column selecting thin film semiconductor device is made of PMOS, the PMOS drain region and the NMOS drain region are joined, and a PN junction diode is formed. Forming. Although not shown in FIG. 6, the reference capacitor first electrode is made of an N-type semiconductor film which is the same material as the drain region of the signal amplification thin film semiconductor device. The reference capacitor first electrode and the drain region of the thin film semiconductor device are formed on the same base protective film. The dielectric film of the reference capacitor is composed of a silicon oxide film that is the same material as the gate insulating film (GI in the figure) of the signal amplification thin film semiconductor device, and both are formed on the same layer (on the semiconductor film). The second reference capacitor electrode is formed of a metal film (specifically, a tantalum thin film) that is the same material as the gate electrode of the signal amplification thin film semiconductor device.

次に本願発明の静電容量検出装置の駆動方法を説明する。本願発明ではリセット素子（ＲＥ_ij）のソース電極を自身が属する静電容量検出素子（ＥＣＳＥ_ij）を位置づける行線（ＲＬ_i）に接続し、ゲート電極を隣接段の行線（後段行ＲＬ_i+1乃至は前段行ＲＬ_i-1）に接続する。此処ではリセット素子（ＲＥ_ij）のゲート電極を前段行ＲＬ_i-1に接続した場合（図３）を説明するが、後段行ＲＬ_i+1に接続した場合も容量検出電極の電位をリセットするタイミングが静電容量を検出する前になるか後になるかの相違だけで、本願発明の基本原理は同一で有る。Ｍ行Ｎ列の行列状に配置されたＭ×Ｎ個の静電容量検出素子は行と列とを順次走査する事で対象物の静電容量を反映した凹凸画像を取得する。例えばｉ行目の行線が選択された状態で列線を順次走査してｉ行目に位置する静電容量検出素子群から対象物の静電容量に応じた信号を得る。次にｉ＋１行目を選択し、同様にｉ＋１行目に位置する静電容量検出素子群から対象物の静電容量に応じた信号を得る。以下同じ動作を繰り返し、Ｍ行Ｎ列の行列状に配置されたＭ×Ｎ個の静電容量検出素子群を総て走査して一枚の凹凸情報画像を得る。信号増幅素子がＮ型半導体装置の場合、行線には選択時に行選択信号としての高電位Ｖ_dd（例えば＋２．５Ｖとか＋３．３Ｖ）が付与され、非選択期間は接地電位Ｖ_ssに維持される。斯うすると基準コンデンサ容量乃至は信号増幅素子のトランジスタ容量と、対象物の静電容量（Ｃ_F）とが容量結合して例えば指紋の谷（対象物の凹部）が容量検出電極上に来た時に信号増幅素子には正電位が加わり、信号増幅素子のドレインコンダクタンスは増大する。行線には次行のリセット素子のゲート電極が繋がれており、行線（ＲＬ_i）に印可される行選択信号が次行（後段行ＲＬ_i+1）のリセット信号を兼用するので、高電位にてリセット素子はスイッチオン状態にならねばならない。リセット素子を信号増幅素子と反対の極性のトランジスタとし、前行とリセット素子との間にインバータを設けてスイッチオン状態とする事も可能だが、最も簡便容易にリセット素子を前述の動作をさせるには、リセット素子と信号増幅素子とを同一導電型のトランジスタとする事で有る。斯うすると余計なインバータや配線などを省略出来、容量検出電極面積を大きくして検出感度を高められる。図３では静電容量検出素子（ＥＣＳＥ_ij）内の信号増幅素子もリセット素子もＮ型薄膜半導体装置にて形成されて居る。 Next, a method for driving the capacitance detection device of the present invention will be described. In the present invention, the source electrode of the reset element (RE _ij ) is connected to the row line (RL _i ) for positioning the capacitance detection element (ECSE _ij ) to which the reset element (RE _ij ) belongs, and the gate electrode is connected to the row line of the adjacent stage (rear stage row RL _{i). +1} to the previous row RL _i-1 ). Here, the case where the gate electrode of the reset element (RE _ij ) is connected to the preceding row RL _i-1 will be described (FIG. 3), but the potential of the capacitance detection electrode is also reset when connected to the succeeding row RL _{i + 1.} The basic principle of the present invention is the same only by the difference in timing before or after detecting the capacitance. The M × N capacitance detection elements arranged in a matrix of M rows and N columns acquire an uneven image reflecting the capacitance of the object by sequentially scanning rows and columns. For example, the column line is sequentially scanned in a state where the i-th row line is selected, and a signal corresponding to the capacitance of the object is obtained from the capacitance detection element group located in the i-th row. Next, the i + 1th row is selected, and similarly, a signal corresponding to the capacitance of the object is obtained from the capacitance detection element group located in the i + 1th row. Thereafter, the same operation is repeated, and all the M × N capacitance detection element groups arranged in a matrix of M rows and N columns are scanned to obtain one uneven information image. When the signal amplifying element is an N-type semiconductor device, a high potential V _dd (eg, +2.5 V or +3.3 V) as a row selection signal is applied to the row line when selected, and the ground potential V _ss is maintained during the non-selection period. Is done. As a result, the reference capacitor capacitance or the transistor capacitance of the signal amplifying element and the electrostatic capacitance (C _F ) of the object are capacitively coupled, and, for example, a fingerprint valley (a concave portion of the object) comes on the capacitance detection electrode. Sometimes a positive potential is applied to the signal amplifying element, and the drain conductance of the signal amplifying element increases. Since the gate electrode of the reset element of the next row is connected to the row line, and the row selection signal applied to the row line (RL _i ) is also used as the reset signal of the next row (subsequent row RL _{i + 1} ), The reset element must be switched on at high potential. Although it is possible to set the reset element to a transistor having the opposite polarity to the signal amplification element and to set the switch on by providing an inverter between the previous row and the reset element, the simplest and easiest way to make the reset element operate as described above The reset element and the signal amplifying element are transistors of the same conductivity type. In this case, unnecessary inverters and wiring can be omitted, and the detection sensitivity can be increased by increasing the capacitance detection electrode area. In FIG. 3, both the signal amplification element and the reset element in the capacitance detection element (ECSE _ij ) are formed by an N-type thin film semiconductor device.

まずi−１行の行線が選択されるとi行目のリセット素子（ＲＥ_ij）はスイッチ・オン状態になり、i行目の静電容量検出素子（ＥＣＳＥ_ij）内の容量検出電極や基準コンデンサ第二電極、信号増幅素子のゲート電極をi行目の行線と導通させる。この際にi行目の行線は非選択状態（Ｖ_ss）にあるからリセット素子を通じて此等の電極は接地電位に落ちる。一方でi行目の静電容量検出素子（ＥＣＳＥ_ij）内の基準コンデンサ第一電極もi行目の行線に接続されているので、基準コンデンサ第一電極も接地電位となる。更にi−１行の行線が選択されて居る間に各列線が順次選択され、ｊ列目の列線が選択される期間（静電容量検出素子ＥＣＳＥ_i-1jが選択されている期間）にi行目の静電容量検出素子（ＥＣＳＥ_ij）内の列選択素子もオン状態となり、直列接続されている信号増幅素子のドレイン電極を接地電位に落とす。斯うしてｉ−１行ｊ列の静電容量検出素子（ＥＣＳＥ_i-1j）が選択されている期間にｉ行ｊ列の静電容量検出素子（ＥＣＳＥ_ij）内の基準コンデンサ第一電極も基準コンデンサ第二電極も容量検出電極も信号増幅素子のゲート電極も信号増幅素子のドレイン電極も総て接地電位となり、容量検出電極から測定感度を落とす電荷を取り除く事が可能となる。i−１行上の静電容量検出素子群の走査が終了すると、次にi行目の行線が選択される。この時にはi−１行目の行線が接地電位となるから、i行目のリセット素子（ＲＥ_ij）はスイッチ・オフ状態となってi行目の行線とi行目の静電容量検出素子（ＥＣＳＥ_ij）内の容量検出電極や基準コンデンサ第二電極、信号増幅素子のゲート電極とを電気的に分離する。i行目の行線は高電位（Ｖ_dd）に在るのでi行目の静電容量検出素子（ＥＣＳＥ_ij）内の基準コンデンサ第一電極も高電位となり、ｊ列目が選択された際に測定すべき静電容量応じた出力を出力線に提供する事になる。以降同じ動作を繰り返して、指紋情報などの対象物の静電容量情報を高感度で検出するに至る。 First, when the i-1 row line is selected, the reset element (RE _ij ) in the i row is switched on, and the capacitance detection electrode in the capacitance detection element (ECSE _ij ) in the i row The second electrode of the reference capacitor and the gate electrode of the signal amplifying element are electrically connected to the i-th row line. At this time, since the row line of the i-th row is in a non-selected state (V _ss ), these electrodes fall to the ground potential through the reset element. On the other hand, since the reference capacitor first electrode in the capacitance detection element (ECSE _ij ) in the i-th row is also connected to the row line in the i-th row, the reference capacitor first electrode is also at the ground potential. Further, each column line is sequentially selected while the ( _i−1 ) _th row line is selected, and a period during which the jth column line is selected (a period during which the capacitance detection element ECSE _i−1j is selected). ), The column selection element in the capacitance detection element (ECSE _ij ) in the i-th row is also turned on, and the drain electrode of the signal amplification element connected in series is dropped to the ground potential. Thus, the reference capacitor first electrode in the i-th row and j-th column capacitance detecting element (ECSE _ij ) is also selected during the period when the i-th row and j-th column capacitance detecting element (ECSE _i-1j ) is selected. The reference capacitor second electrode, the capacitance detection electrode, the gate electrode of the signal amplification element, and the drain electrode of the signal amplification element are all at the ground potential, and it is possible to remove charges that reduce the measurement sensitivity from the capacitance detection electrode. When scanning of the capacitance detection element group on the (i-1) th row is completed, the i-th row line is then selected. At this time, since the row line of the (i−1) th row becomes the ground potential, the reset element (RE _ij ) of the i-th row is switched off and the capacitance of the i-th row and the i-th row is detected. The capacitance detection electrode in the element (ECSE _ij ), the reference capacitor second electrode, and the gate electrode of the signal amplification element are electrically separated. Since the i-th row line is at a high potential (V _dd ), the reference capacitor first electrode in the capacitance detection element (ECSE _ij ) in the i-th row is also at a high potential, and the j-th column is selected. The output corresponding to the capacitance to be measured is provided to the output line. Thereafter, the same operation is repeated until the capacitance information of the object such as fingerprint information is detected with high sensitivity.

斯様な静電容量検出素子は前述のＳＵＦＴＬＡ技術を用いて、プラスティック基板上に形成され得る。単結晶硅素技術に基づく指紋センサはプラスティック上では直ぐに割れて仕舞ったり、或いは十分な大きさを有さぬが為に実用性に乏しい。これに対して本願発明に依るプラスティック基板上の静電容量検出素子は、プラスティック基板上で指を被うに十分に大きい面積としても静電容量検出素子が割れる心配もなく、プラスティック基板上での指紋センサとして利用し得る。具体的には本願発明により個人認証機能を兼ね備えたスマートカードが実現される。個人認証機能を備えたスマートカードはキャッシュカード（bank card）やクレジットカード（credit card）、身分証明書(Identity card)等で使用され、此等のセキュリティーレベルを著しく高めた上で尚、個人指紋情報をカード外に流出させずに保護するとの優れた機能を有する。   Such a capacitance detection element can be formed on a plastic substrate using the above-described SUFTLA technology. A fingerprint sensor based on single-crystal silicon technology is not practical because it does not break down on a plastic, or does not have a sufficient size. On the other hand, the capacitance detection element on the plastic substrate according to the present invention does not have to worry about the capacitance detection element being cracked even if the area is large enough to cover the finger on the plastic substrate, and the fingerprint on the plastic substrate. It can be used as a sensor. Specifically, a smart card having a personal authentication function is realized by the present invention. Smart cards with a personal authentication function are used for bank cards, credit cards, identity cards, etc., and with their security level significantly increased, personal fingerprints are also used. It has an excellent function of protecting information without leaking out of the card.

ガラス基板上に薄膜半導体装置からなる静電容量検出装置を製造した上で、此の静電容量検出装置をＳＵＦＴＬＡ技術を用いてプラスティック基板上に転写し、プラスティック基板上に静電容量検出装置を作成した。静電容量検出装置は３０４行３０４列の行列状に並んだ静電容量検出素子から構成される。行列部の大きさは２０ｍｍ角の正方形である。   After manufacturing a capacitance detection device made of a thin film semiconductor device on a glass substrate, the capacitance detection device is transferred onto a plastic substrate using SUFTLA technology, and the capacitance detection device is placed on the plastic substrate. Created. The capacitance detection device is composed of capacitance detection elements arranged in a matrix of 304 rows and 304 columns. The size of the matrix portion is a 20 mm square.

基板は厚み２００μｍのポリエーテルスルフォン（ＰＥＳ）である。信号増幅素子とリセット素子はＮ型薄膜半導体装置で形成され、列選択素子はＰ型薄膜半導体装置で形成された。此等薄膜半導体装置はソースドレイン領域の導電タイプを除いて同じ断面構造を有する。薄膜半導体装置は図６に示すトップゲート型で工程最高温度４２５℃の低温工程にて作成される。半導体膜はレーザー結晶化にて得られた多結晶硅素薄膜でその厚みは５０ｎｍである。又、ゲート絶縁膜は化学気相堆積法（ＣＶＤ法）にて形成された４５ｎｍ厚の酸化硅素膜で、ゲート電極は厚み４００ｎｍのタンタル薄膜から成る。ゲート絶縁膜を成す酸化硅素膜の比誘電率はＣＶ測定により略３．９と求められた。基準コンデンサ第一電極は信号増幅用Ｎ型薄膜半導体装置のドレイン領域と同じＮ型半導体膜にて形成され、基準コンデンサ誘電体膜は信号増幅用Ｎ型薄膜半導体装置のゲート絶縁膜と同じ酸化珪素膜で作られ、基準コンデンサ第二電極は信号増幅用Ｎ型薄膜半導体装置のゲート電極と同じタンタル薄膜から成る。基準コンデンサ第一電極はコンタクトホールを介して行線に接続され、第二電極は信号増幅用Ｎ型薄膜半導体装置のゲート電極と容量検出電極とに接続されている。静電容量検出素子の回路構成は図３と同一である。列選択素子のドレイン電極と信号増幅素子のドレイン電極とは直接接合し、ＰＮダイオードをなしている。   The substrate is polyethersulfone (PES) having a thickness of 200 μm. The signal amplification element and the reset element are formed of an N-type thin film semiconductor device, and the column selection element is formed of a P-type thin film semiconductor device. These thin film semiconductor devices have the same cross-sectional structure except for the conductivity type of the source / drain regions. The thin film semiconductor device is a top gate type shown in FIG. 6 and is manufactured in a low temperature process having a maximum process temperature of 425 ° C. The semiconductor film is a polycrystalline silicon thin film obtained by laser crystallization and has a thickness of 50 nm. The gate insulating film is a 45 nm thick silicon oxide film formed by chemical vapor deposition (CVD), and the gate electrode is a 400 nm thick tantalum thin film. The relative dielectric constant of the silicon oxide film constituting the gate insulating film was determined to be approximately 3.9 by CV measurement. The reference capacitor first electrode is formed of the same N-type semiconductor film as the drain region of the signal amplification N-type thin film semiconductor device, and the reference capacitor dielectric film is the same silicon oxide as the gate insulating film of the signal amplification N-type thin film semiconductor device. The second electrode of the reference capacitor is made of the same tantalum thin film as the gate electrode of the N-type thin film semiconductor device for signal amplification. The reference capacitor first electrode is connected to the row line through the contact hole, and the second electrode is connected to the gate electrode and the capacitance detection electrode of the N-type thin film semiconductor device for signal amplification. The circuit configuration of the capacitance detection element is the same as in FIG. The drain electrode of the column selection element and the drain electrode of the signal amplification element are directly joined to form a PN diode.

本実施例では静電容量検出装置を成す行列のピッチを６６μｍとし、解像度を３８５ｄｐｉ（dots per inch）としている。この結果、容量検出電極面積は１５２９μｍ²となった。容量検出誘電体膜は厚み３００ｎｍの窒化硅素膜にて形成された。ＣＶ測定からこの窒化硅素膜の比誘電率は略７．５であったから、素子容量Ｃ_Dは凡そ３３８ｆＦ（フェムトファラッド）となる。本実施例の静電容量検出装置を指紋センサと想定すると、指紋の凹凸は５０μｍ程度なので、静電容量検出装置表面に指紋の谷が来た時の対象物容量Ｃ_Aは０．２７ｆＦと計算される。一方、信号増幅用ＭＩＳ薄膜半導体装置のゲート電極長Ｌを２μｍとし、ゲート電極幅Ｗを２μｍとしたから、トランジスタ容量Ｃ_Tは凡そ３．０７ｆＦとなる。又、基準コンデンサ電極面積Ｓ_Rを４２μｍ²とした。この結果、基準コンデンサ容量Ｃ_Rは３２ｆＦとなった。斯うして本実施例に示す静電容量検出素子は
Ｃ_D＞１０×Ｃ_R
Ｃ_R＞１０×Ｃ_T
Ｃ_R＞１０×Ｃ_A
との関係を満たす。斯くして電源電圧Ｖ_ddを３．３Ｖとすると、指紋の山が静電容量検出装置表面に接した時に信号増幅用ＭＩＳ薄膜半導体装置のゲート電極に印可される電圧Ｖ_GTは０．３０Ｖとなり、指紋の谷が来た時に此のゲート電極に印可される電圧Ｖ_GVは３．１１Ｖとなる。本実施例にて用いた信号増幅用Ｎ型薄膜半導体装置の最小ゲート電圧Ｖ_minは０．３５Ｖで有り、指紋の山が接した時のゲート電圧Ｖ_GTの０．３０Ｖよりも大きいために、信号増幅用Ｎ型薄膜半導体装置は完全にオフ状態となった。一方、閾値電圧Ｖ_thは１．４２Ｖであり、指紋の谷が来た時に得られるゲート電圧Ｖ_GVの３．１１Ｖより小さいために、信号増幅用Ｎ型薄膜半導体装置は完全にオン状態となった。この結果、指紋の山が静電容量検出装置表面に接した時に信号増幅素子から出力される電流値は４．５×１０^-13Ａと窮めて微弱となる。反対に指紋の谷が来た時には信号増幅素子から２．６×１０^-5Ａと大きな電流が出力され、指紋等の凹凸情報を精度良く検出するに至った。 In this embodiment, the pitch of the matrix forming the capacitance detection device is 66 μm, and the resolution is 385 dpi (dots per inch). As a result, the capacitance detection electrode area was 1529 μm ² . The capacitance detection dielectric film was formed of a silicon nitride film having a thickness of 300 nm. Since the dielectric constant of the silicon nitride film from the CV measurement was substantially 7.5, the element capacitance C _D is approximately 338FF (femtofarad). Assuming the capacitance detection device of the present embodiment with a fingerprint sensor, since the irregularities of the fingerprint is a about 50 [mu] m, the object capacitance C _A when a valley of a fingerprint comes the surface of the electrostatic capacitance detection device and 0.27fF calculation Is done. On the other hand, since the gate electrode length L of the signal amplifying MIS thin film semiconductor device is 2 μm and the gate electrode width W is 2 μm, the transistor capacitance C _T is about 3.07 fF. The reference capacitor electrode area S _R was set to 42 μm ² . As a result, the reference capacitor capacitance C _R was 32 fF. Thus, the capacitance detection element shown in this embodiment has C _D > 10 × C _R
C _R > 10 × C _T
C _R > 10 × C _A
Satisfaction with the relationship. Thus, when the power supply voltage V _dd is 3.3 V, the voltage V _GT applied to the gate electrode of the MIS thin film semiconductor device for signal amplification when the peak of the fingerprint contacts the surface of the capacitance detection device is 0.30 V. When the fingerprint valley comes, the voltage V _GV applied to this gate electrode is 3.11V. The minimum gate voltage V _min of the N-type thin film semiconductor device for signal amplification used in this example is 0.35 V, which is larger than 0.30 V of the gate voltage V _GT when the crest of the fingerprint touches. The N-type thin film semiconductor device for signal amplification was completely turned off. On the other hand, the threshold voltage V _th is 1.42 V, which is smaller than the gate voltage V _GV of 3.11 V obtained when the valley of the fingerprint comes, so that the N-type thin film semiconductor device for signal amplification is completely turned on. It was. As a result, the current value output from the signal amplifying element when the crest of the fingerprint comes into contact with the surface of the capacitance detection device is as weak as 4.5 × 10 ⁻¹³ A. On the contrary, when the valley of the fingerprint comes, a large current of 2.6 × 10 ⁻⁵ A is output from the signal amplifying element, and the concave and convex information such as the fingerprint is accurately detected.

本発明は指紋等の微細な凹凸を有する対象物の表面形状を、対象物表面との距離に応じて変化する静電容量を検出する事に依り読み取る静電容量検出装置に利用される。具体的には指紋センサに利用される。   INDUSTRIAL APPLICABILITY The present invention is used in a capacitance detection device that reads the surface shape of an object having fine irregularities such as fingerprints by detecting the capacitance that changes according to the distance from the object surface. Specifically, it is used for a fingerprint sensor.

従来技術に於ける動作原理を説明した図。The figure explaining the operation principle in a prior art. 本願発明に於ける動作原理を説明した図。The figure explaining the principle of operation in this invention. 本願発明に於ける静電容量検出素子の回路構成を説明した図。The figure explaining the circuit structure of the electrostatic capacitance detection element in this invention. 本願発明の原理を説明した図。The figure explaining the principle of this invention. 本願発明の原理を説明した図。The figure explaining the principle of this invention. 本願発明の素子構造を説明した図。The figure explaining the element structure of this invention.

Claims (22)

対象物との距離に応じて変化する静電容量を検出する事に依り、該対象物の表面形状を読み取る静電容量検出装置に於いて、
該静電容量検出装置はＭ行Ｎ列の行列状に配置されたＭ本の行線とＮ本の列線、及び該行線と該列線との交点に設けられた静電容量検出素子とを具備し、
該静電容量検出素子は信号検出素子と信号増幅素子とリセット素子とを含み、
該信号検出素子は容量検出電極と容量検出誘電体膜とを含み、
該信号増幅素子はソース電極とドレイン電極とゲート電極とを有する信号増幅用薄膜半導体装置から成り、
該リセット素子はソース電極とドレイン電極とゲート電極とを有するリセット用薄膜半導体装置から成り、
該信号増幅素子のゲート電極と該容量検出電極と該リセット素子のドレイン電極とが接続されて居る事を特徴とする静電容量検出装置。 In the capacitance detection device that reads the surface shape of the object by detecting the capacitance that changes according to the distance to the object,
The capacitance detection device includes M row lines and N column lines arranged in a matrix of M rows and N columns, and capacitance detection elements provided at intersections of the row lines and the column lines. And
The capacitance detection element includes a signal detection element, a signal amplification element, and a reset element,
The signal detection element includes a capacitance detection electrode and a capacitance detection dielectric film,
The signal amplifying element comprises a signal amplifying thin film semiconductor device having a source electrode, a drain electrode, and a gate electrode,
The reset element comprises a reset thin film semiconductor device having a source electrode, a drain electrode, and a gate electrode,
A capacitance detection device, wherein the gate electrode of the signal amplification element, the capacitance detection electrode, and the drain electrode of the reset element are connected. 前記リセット素子がスイッチオン状態になった際に前記信号増幅素子のゲート電極と前記容量検出電極とを接地電位とし得る事を特徴とする請求項１記載の静電容量検出装置。   2. The capacitance detection device according to claim 1, wherein when the reset element is switched on, the gate electrode of the signal amplification element and the capacitance detection electrode can be set to a ground potential. 前記リセット素子がスイッチオン状態となって居る間に前記信号増幅素子のドレイン電極を接地電位とし得る事を特徴とする請求項１乃至２記載の静電容量検出装置。   3. The capacitance detection device according to claim 1, wherein the drain electrode of the signal amplification element can be set to a ground potential while the reset element is in a switch-on state. 前記リセット素子のソース電極が前記行線に接続されて居る事を特徴とする請求項１乃至３記載の静電容量検出装置。   4. The capacitance detection device according to claim 1, wherein a source electrode of the reset element is connected to the row line. 前記リセット素子のゲート電極が前記行線の隣接段に位置する行線に接続されて居る事を特徴とする請求項１乃至４記載の静電容量検出装置。   5. The capacitance detection device according to claim 1, wherein the gate electrode of the reset element is connected to a row line located in an adjacent stage of the row line. 前記信号増幅用薄膜半導体装置のドレイン電極は、前記静電容量検出素子が選択状態とされた時に前記行線と電気的に導通される事を特徴とする請求項１乃至５記載の静電容量検出装置。   6. The capacitance according to claim 1, wherein the drain electrode of the thin film semiconductor device for signal amplification is electrically connected to the row line when the capacitance detection element is in a selected state. Detection device. 前記静電容量検出装置は出力線を含み、前記信号増幅用薄膜半導体装置のソース電極は、前記静電容量検出素子が選択状態とされた時に該出力線と電気的に導通される事を特徴とする請求項１乃至６記載の静電容量検出装置。   The capacitance detection device includes an output line, and the source electrode of the signal amplification thin film semiconductor device is electrically connected to the output line when the capacitance detection element is in a selected state. The capacitance detection device according to claim 1. 前記信号増幅素子と前記リセット素子とが同一導電型の薄膜半導体装置である事を特徴とする請求項１乃至７記載の静電容量検出装置。   8. The capacitance detecting device according to claim 1, wherein the signal amplifying element and the reset element are thin film semiconductor devices of the same conductivity type. 対象物との距離に応じて変化する静電容量を検出する事に依り、該対象物の表面形状を読み取る静電容量検出装置に於いて、
該静電容量検出装置はＭ行Ｎ列の行列状に配置されたＭ本の行線とＮ本の列線、及び該行線と該列線との交点に設けられた静電容量検出素子とを具備し、
該静電容量検出素子は信号検出素子と信号増幅素子とリセット素子とを含み、
該信号検出素子は容量検出電極と容量検出誘電体膜と基準コンデンサとを含み、
該基準コンデンサは基準コンデンサ第一電極と基準コンデンサ誘電体膜と基準コンデンサ第二電極とから成り、
該信号増幅素子はソース電極とドレイン電極とゲート電極とを有する信号増幅用薄膜半導体装置から成り、
該リセット素子はソース電極とドレイン電極とゲート電極とを有するリセット用薄膜半導体装置から成り、
該信号増幅素子のゲート電極と該容量検出電極と該基準コンデンサ第二電極と該リセット素子のドレイン電極とが接続されて居る事を特徴とする静電容量検出装置。 In the capacitance detection device that reads the surface shape of the object by detecting the capacitance that changes according to the distance to the object,
The capacitance detection device includes M row lines and N column lines arranged in a matrix of M rows and N columns, and capacitance detection elements provided at intersections of the row lines and the column lines. And
The capacitance detection element includes a signal detection element, a signal amplification element, and a reset element,
The signal detection element includes a capacitance detection electrode, a capacitance detection dielectric film, and a reference capacitor,
The reference capacitor comprises a reference capacitor first electrode, a reference capacitor dielectric film, and a reference capacitor second electrode,
The signal amplifying element comprises a signal amplifying thin film semiconductor device having a source electrode, a drain electrode, and a gate electrode,
The reset element comprises a reset thin film semiconductor device having a source electrode, a drain electrode, and a gate electrode,
A capacitance detection device comprising: a gate electrode of the signal amplification element; a capacitance detection electrode; the reference capacitor second electrode; and a drain electrode of the reset element. 前記基準コンデンサ第一電極と前記行線とが接続されて居る事を特徴とする請求項９記載の静電容量検出装置。   10. The capacitance detecting device according to claim 9, wherein the reference capacitor first electrode and the row line are connected. 前記リセット素子がスイッチオン状態になった際に前記信号増幅素子のゲート電極と前記容量検出電極と前記基準コンデンサ第二電極とを接地電位とし得る事を特徴とする請求項９乃至１０記載の静電容量検出装置。   11. The static electricity according to claim 9, wherein when the reset element is switched on, the gate electrode, the capacitance detection electrode, and the reference capacitor second electrode of the signal amplification element can be set to the ground potential. Capacitance detection device. 前記リセット素子がスイッチオン状態となって居る間に前記信号増幅素子のドレイン電極を接地電位とし得る事を特徴とする請求項９乃至１１記載の静電容量検出装置。   12. The capacitance detection device according to claim 9, wherein the drain electrode of the signal amplification element can be set to a ground potential while the reset element is in a switch-on state. 前記基準コンデンサ第一電極が接地電位となっている間に前記リセット素子をスイッチオン状態とし得る事を特徴とする請求項９乃至１２記載の静電容量検出装置。   13. The capacitance detection device according to claim 9, wherein the reset element can be switched on while the reference capacitor first electrode is at a ground potential. 前記リセット素子のソース電極が前記行線に接続されて居る事を特徴とする請求項９乃至１３記載の静電容量検出装置。   14. The capacitance detection device according to claim 9, wherein a source electrode of the reset element is connected to the row line. 前記リセット素子のゲート電極が前記行線の隣接段に位置する行線に接続されて居る事を特徴とする請求項９乃至１４記載の静電容量検出装置。   15. The capacitance detection device according to claim 9, wherein a gate electrode of the reset element is connected to a row line located in an adjacent stage of the row line. 前記信号増幅用薄膜半導体装置のドレイン電極は、前記静電容量検出素子が選択状態とされた時に前記行線と電気的に導通される事を特徴とする請求項９乃至１５記載の静電容量検出装置。   16. The capacitance according to claim 9, wherein the drain electrode of the thin film semiconductor device for signal amplification is electrically connected to the row line when the capacitance detection element is in a selected state. Detection device. 前記静電容量検出装置は出力線を含み、前記信号増幅用薄膜半導体装置のソース電極は、前記静電容量検出素子が選択状態とされた時に該出力線と電気的に導通される事を特徴とする請求項９乃至１６記載の静電容量検出装置。   The capacitance detection device includes an output line, and the source electrode of the signal amplification thin film semiconductor device is electrically connected to the output line when the capacitance detection element is in a selected state. The capacitance detection device according to claim 9 to 16. 前記信号増幅素子と前記リセット素子とが同一導電型の薄膜半導体装置である事を特徴とする請求項９乃至１７記載の静電容量検出装置。   18. The capacitance detection device according to claim 9, wherein the signal amplification element and the reset element are thin film semiconductor devices of the same conductivity type. 前記基準コンデンサの電極面積をＳ_R（μｍ²）、前記基準コンデンサ誘電体膜の厚みをｔ_R（μｍ）、前記基準コンデンサ誘電体膜の比誘電率をε_R、前記信号増幅用薄膜半導体装置のゲート電極面積をＳ_T（μｍ²）、前記ゲート絶縁膜の厚みをｔ_ox（μｍ）、前記ゲート絶縁膜の比誘電率をε_oxとして、前記基準コンデンサ容量Ｃ_Rと前記信号増幅用薄膜半導体装置のトランジスタ容量Ｃ_Tとを
Ｃ_R＝ε₀・ε_R・Ｓ_R／ｔ_R
Ｃ_T＝ε₀・ε_ox・Ｓ_T／ｔ_ox
にて定義し（ε₀は真空の誘電率）、
前記容量検出電極の面積をＳ_D（μｍ²）、前記容量検出誘電体膜の厚みをｔ_D（μｍ）、前記容量検出誘電体膜の比誘電率をε_Dとして前記信号検出素子の素子容量Ｃ_Dを
Ｃ_D＝ε₀・ε_D・Ｓ_D／ｔ_D
と定義した時に（ε₀は真空の誘電率）、
該素子容量Ｃ_Dは、該基準コンデンサ容量Ｃ_Rと該トランジスタ容量Ｃ_Tとの和であるＣ_R＋Ｃ_Tよりも十分に大きい事を特徴とする請求項９至乃１８記載の静電容量検出装置。 The electrode area of the reference capacitor is S _R (μm ² ), the thickness of the reference capacitor dielectric film is t _R (μm), the relative dielectric constant of the reference capacitor dielectric film is ε _R , and the thin film semiconductor device for signal amplification the gate electrode area of S _T (μm ^2), the thickness of the gate insulating film t _ox (μm), the dielectric constant of the gate insulating film as epsilon _ox, the signal amplifying thin film and the reference capacitor capacitance C _R The transistor capacitance C _T of the semiconductor device is expressed as C _R = ε ₀ · ε _R · S _R / t _R
C _T = ε ₀ · ε _ox · S _T / t _ox
(Ε ₀ is the dielectric constant of the vacuum)
The capacitance of the signal detection element is S _D (μm ² ), the thickness of the capacitance detection dielectric film is t _D (μm), and the relative dielectric constant of the capacitance detection dielectric film is ε _D. C _D C _D = ε ₀ · ε _D · S _D / t _D
Where ε ₀ is the dielectric constant of the vacuum,
19. The capacitance detection according to claim 9, wherein the element capacitance C _D is sufficiently larger than C _R + C _T which is a sum of the reference capacitor capacitance C _R and the transistor capacitance C _T. apparatus. 前記容量検出誘電体膜は前記静電容量検出装置の最表面に位置する事を特徴とする請求項１９記載の静電容量検出装置。   The capacitance detection device according to claim 19, wherein the capacitance detection dielectric film is located on an outermost surface of the capacitance detection device. 前記対象物が前記容量検出誘電体膜に接しずに対象物距離ｔ_Aを以て離れて居り、対象物容量Ｃ_Aを真空の誘電率ε₀と空気の比誘電率ε_Aと前記容量検出電極の面積Ｓ_Dとを用いて、
Ｃ_A＝ε₀・ε_A・Ｓ_D／ｔ_A
と定義した時に、
前記基準コンデンサ容量Ｃ_Rは該対象物容量Ｃ_Aよりも十分に大きい事を特徴とする請求項９乃至２０記載の静電容量検出装置。 The object is not in contact with the capacitance detection dielectric film and is separated by an object distance t _A , and the object capacitance C _A is divided into a vacuum dielectric constant ε ₀ , an air relative dielectric constant ε _A, and the capacitance detection electrode. Using area _SD ,
C _A = ε ₀ · ε _A · S _D / t _A
When defined as
The reference capacitance C _R is the electrostatic capacitance detection device according to claim 9 or 20, wherein it is sufficiently larger than the object capacitance C _A. 前記容量検出誘電体膜は前記静電容量検出装置の最表面に位置し、前記基準コンデンサの電極面積をＳ_R（μｍ²）、前記基準コンデンサ誘電体膜の厚みをｔ_R（μｍ）、基準コンデンサ誘電体膜の比誘電率をε_R、前記信号増幅用薄膜半導体装置のゲート電極面積をＳ_T（μｍ²）、前記ゲート絶縁膜の厚みをｔ_ox（μｍ）、ゲート絶縁膜の比誘電率をε_oxとして前記基準コンデンサ容量Ｃ_Rと前記信号増幅用薄膜半導体装置のトランジスタ容量Ｃ_Tとを
Ｃ_R＝ε₀・ε_R・Ｓ_R／ｔ_R
Ｃ_T＝ε₀・ε_ox・Ｓ_T／ｔ_ox
にて定義し（ε₀は真空の誘電率）、
前記容量検出電極の面積をＳ_D（μｍ²）、前記容量検出誘電体膜の厚みをｔ_D（μｍ）、前記容量検出誘電体膜の比誘電率をε_Dとして前記信号検出素子の素子容量Ｃ_Dを
Ｃ_D＝ε₀・ε_D・Ｓ_D／ｔ_D
と定義した時に（ε₀は真空の誘電率）、
該素子容量Ｃ_Dは、該基準コンデンサ容量Ｃ_Rと該トランジスタ容量Ｃ_Tとの和であるＣ_R＋Ｃ_Tよりも十分に大きく、
前記対象物が前記容量検出誘電体膜に接しずに対象物距離ｔ_Aを以て離れて居り、対象物容量Ｃ_Aを真空の誘電率ε₀と空気の比誘電率ε_Aと前記容量検出電極の面積Ｓ_Dとを用いて、
Ｃ_A＝ε₀・ε_A・Ｓ_D／ｔ_A
と定義した時に、
該基準コンデンサ容量Ｃ_Rは該対象物容量Ｃ_Aよりも十分に大きい事を特徴とする請求項９至乃１８記載の静電容量検出装置。
The capacitance detection dielectric film is positioned on the outermost surface of the capacitance detection device, the electrode area of the reference capacitor is S _R (μm ² ), the thickness of the reference capacitor dielectric film is t _R (μm), and the reference The dielectric constant of the capacitor dielectric film is ε _R , the gate electrode area of the signal amplifying thin film semiconductor device is S _T (μm ² ), the thickness of the gate insulating film is t _ox (μm), and the dielectric constant of the gate insulating film wherein the rate as epsilon _ox reference capacitor capacitance C _R and the transistor capacitance C _T of the signal amplifying thin-film semiconductor device _{C R = ε 0 · ε R} · S R / t R
C _T = ε ₀ · ε _ox · S _T / t _ox
(Ε ₀ is the dielectric constant of the vacuum)
The capacitance of the signal detection element is S _D (μm ² ), the thickness of the capacitance detection dielectric film is t _D (μm), and the relative dielectric constant of the capacitance detection dielectric film is ε _D. C _D C _D = ε ₀ · ε _D · S _D / t _D
Where ε ₀ is the dielectric constant of the vacuum,
The element capacitance C _D is sufficiently larger than C _R + C _T which is the sum of the reference capacitor capacitance C _R and the transistor capacitance C _T.
The object is not in contact with the capacitance detection dielectric film and is separated by an object distance t _A , and the object capacitance C _A is divided into a vacuum dielectric constant ε ₀ , an air relative dielectric constant ε _A, and the capacitance detection electrode. Using area _SD ,
C _A = ε ₀ · ε _A · S _D / t _A
When defined as
The reference capacitor capacitance C _R is the electrostatic capacitance detection device according to claim 9 Itari乃18, wherein a is sufficiently larger than the object capacitance C _A.

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