JP2006008755A - Epoxy resin composition, semiconductor device using the same and method for assembling the device - Google Patents

Epoxy resin composition, semiconductor device using the same and method for assembling the device Download PDF

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JP2006008755A
JP2006008755A JP2004184499A JP2004184499A JP2006008755A JP 2006008755 A JP2006008755 A JP 2006008755A JP 2004184499 A JP2004184499 A JP 2004184499A JP 2004184499 A JP2004184499 A JP 2004184499A JP 2006008755 A JP2006008755 A JP 2006008755A
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epoxy resin
resin composition
epoxy
stage
assembling
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JP4729873B2 (en
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Yuji Sakamoto
有史 坂本
Satoru Katsurayama
悟 桂山
Kazuya Nagatomi
和哉 永富
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Sumitomo Bakelite Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

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  • Compositions Of Macromolecular Compounds (AREA)
  • Epoxy Resins (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with a bump whose sealing layer has no void and a method for assembling the same, in which the production process can be significantly improved by an epoxy resin composition capable of developing a B-stage state. <P>SOLUTION: The epoxy resin composition comprises an epoxy resin (A) which contains two or more epoxy groups per a molecule and is liquid at 25°C, an epoxy resin (B) which contains two or more epoxy groups per a molecule, is solid at 25°C, and has an epoxy equivalent of 200 or more, and a curing agent (C) which has both an aromatic carboxy group and an aromatic hydroxy group and has a melting point of 180°C or higher. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体素子の封止樹脂、特に、バンプ接合方式で基板と接合する半導体素子用のエポキシ樹脂組成物、半導体装置及び半導体素子の組立方法に関する。   The present invention relates to a semiconductor element sealing resin, particularly to an epoxy resin composition for a semiconductor element that is bonded to a substrate by a bump bonding method, a semiconductor device, and a method for assembling the semiconductor element.

半導体素子の高集積化、高密度化と半導体装置の小型化という要求からフリップチップ実装方式が登場した。同実装方式はこれまでのワイヤーボンディングによる接続ではなく、半導体素子表面とプリント基板とを金属バンプで電気的接続することで小型、薄型化を可能としている。しかしチップ、プリント配線基板、半田の熱膨張係数が異なるために冷熱衝撃試験時に熱ストレスが発生する。特に素子中央から遠いコーナー近辺の金属バンプには局所的に熱ストレスが集中する。このため接合部位にクラックが生じ、回路の作動信頼性は大きく低下する。   Flip chip mounting methods have emerged due to demands for higher integration and higher density of semiconductor elements and miniaturization of semiconductor devices. The mounting system is not connected by wire bonding so far, but the semiconductor element surface and the printed circuit board are electrically connected by metal bumps, thereby enabling a reduction in size and thickness. However, thermal stress is generated during the thermal shock test because the thermal expansion coefficients of the chip, the printed wiring board, and the solder are different. In particular, thermal stress is concentrated locally on metal bumps near corners far from the element center. For this reason, a crack is generated at the joining portion, and the operation reliability of the circuit is greatly lowered.

そこで、熱ストレスを緩和する目的から液状封止アンダーフィル材による封止が行われる。しかしこの方法はチップとプリント配線基板との隙間にアンダーフィル材を注入、硬化して、封止する方法が採られるため工程が煩雑であり、コストもかかる。更にこのような半導体素子の場合は、ウエハー作製工程、ウエハー上への電気回路形成工程、個片化工程、バンプ形成工程、バンプ接合工程、アンダーフィル封止工程が必要であり、個々の工程は製造会社又は工場が異なる場合が多くデリバリーコストがかかってしまうので問題があった。 Therefore, sealing with a liquid sealing underfill material is performed for the purpose of reducing thermal stress. However, this method employs a method of injecting and curing an underfill material into the gap between the chip and the printed wiring board and sealing it, so that the process is complicated and costly. Furthermore, in the case of such a semiconductor element, a wafer fabrication process, an electric circuit formation process on the wafer, a singulation process, a bump formation process, a bump bonding process, and an underfill sealing process are required. Since there are many cases where the manufacturing company or factory is different, there is a problem because the delivery cost is increased.

そこでウエハーに電気回路を形成し個片化せずバンプを形成し、その後個片化する方法が考え出された。この方法はウエハー製造から一環のラインでバンプ付半導体素子を作ることも可能であり、大幅に素子のコストが下がる可能性がある。しかしこの方法であっても信頼性を上げるためにはアンダーフィル封止工程又はバンプ補強封止工程が必要であり、コストに反映してしまう問題が残っていた。これらを解決する方法としてＢ−ステージ化可能樹脂をウエハーに塗布する方法がある（参考文献１）。ここでＢ−ステージとは該樹脂がその前の状態が液状の形態をなし、部分的反応もしくは乾燥を行い、25℃付近でタックフリー状態（べたつきの無い事）になること、更に該樹脂が加熱により一旦溶融し硬化する特性のことであり、更にはＢ−ステージ後にその特性が、ある一定期間維持されることが必要である。この方法に従うと接合と封止を同時にできるため、更にパッケージ製造工程を短縮することができる。しかし、半田バンプの場合、接続性を向上させるためにはフラックス作用を有する化合物を添加又は予め接合する基板又は半田バンプに塗布しておく必要があった。従来のフラックス作用を有する化合物はロジン系に代表され、硬化物中に残存すると物性の低下や界面層の密着性が損たり、電気的不良を起こす可能性があった。更にＢ−ステージ化するためには、Ｂ−ステージ前では樹脂が液状の状態、その後タックフリー化する必要がある。
このような状態を発現さのせるためには一般的には固形の樹脂を溶剤に希釈しＢ−ステージ工程により乾燥または部分反応を行いタックフリー化させる。この場合、工程のばらつきにより溶剤が残存し、後工程での組立時において、溶剤の揮散によるボイドの発生の恐れがあった。 Therefore, a method has been devised in which an electric circuit is formed on a wafer, bumps are formed without being separated into individual pieces, and then separated into individual pieces. In this method, it is possible to produce a semiconductor device with bumps on a part of a line from wafer manufacture, which may greatly reduce the cost of the device. However, even with this method, an underfill sealing step or a bump reinforcement sealing step is necessary to increase the reliability, and there remains a problem of reflecting the cost. As a method for solving these problems, there is a method of applying a B-stageable resin to a wafer (Reference Document 1). Here, the B-stage means that the resin is in a liquid form in the previous state, undergoes partial reaction or drying, and becomes tack-free (no stickiness) at around 25 ° C. It is a property that is once melted and cured by heating, and it is necessary that the property be maintained for a certain period after the B-stage. According to this method, since bonding and sealing can be performed simultaneously, the package manufacturing process can be further shortened. However, in the case of a solder bump, in order to improve the connectivity, it is necessary to add a compound having a flux action or apply it to a substrate or solder bump to be bonded in advance. Conventional compounds having a flux action are represented by rosin type, and if they remain in the cured product, the physical properties may be deteriorated, the adhesion of the interface layer may be impaired, and an electrical failure may occur. Further, in order to make a B-stage, it is necessary to make the resin in a liquid state before the B-stage and then to make it tack-free.
In order to develop such a state, generally, a solid resin is diluted in a solvent and dried or partially reacted by a B-stage process to make it tack-free. In this case, the solvent remained due to variations in the process, and there was a risk of generation of voids due to the volatilization of the solvent during assembly in the subsequent process.

また、はんだバンプ付半導体装置の製造工程短縮技術としてノンフローアンダーフィル材がある。これは、基板又はバンプ付チップのバンプ面に樹脂を塗布しチップと基板を重ね、封止と接合を同時に行う技術である（参考文献２）。しかし、前記のように樹脂にフラックス機能を有する化合物を添加するため信頼性において問題であった。そこでフラックス作用を有する硬化剤を適用することにより信頼性のあるノンフローアンダーフィル材が見いだされている(参考文献3) Further, there is a non-flow underfill material as a technique for shortening the manufacturing process of the semiconductor device with solder bumps. This is a technique in which resin is applied to a bump surface of a substrate or a chip with bumps, the chip and the substrate are stacked, and sealing and bonding are performed simultaneously (Reference Document 2). However, since a compound having a flux function is added to the resin as described above, there is a problem in reliability. Therefore, a reliable non-flow underfill material has been found by applying a curing agent having a flux action (Reference 3).

そこで本発明者らはこのような硬化剤をＢ−ステージ樹脂系に適用することを検討した。しかしＢ−ステージ状態を発現させるのは困難であった。その理由として、フラックス作用を有する硬化剤がエポキシ樹脂との反応性が高くＢ−ステージ状態を維持することが困難であった。
特開2000-195904号公報 特許第2589239号公報 特開2001-106770号公報 Therefore, the present inventors examined the application of such a curing agent to a B-stage resin system. However, it was difficult to develop the B-stage state. The reason is that the curing agent having a flux action has high reactivity with the epoxy resin and it is difficult to maintain the B-stage state.
JP 2000-195904 A Japanese Patent No. 2589239 Japanese Patent Laid-Open No. 2001-106770

本発明の課題は、Ｂ−ステージ化可能なエポキシ樹脂組成物により製造工程を大幅に改良でき、かつ封止層にボイドが無いバンプ付半導体装置及び組立工程を提供することにある。   An object of the present invention is to provide a semiconductor device with bumps and an assembling process in which a manufacturing process can be greatly improved by an epoxy resin composition that can be made into a B-stage, and a void is not present in a sealing layer.

本発明者らは前述の解決法に関し鋭意検討を行い、液状樹脂組成物において液状エポキシ樹脂と特定のエポキシ樹脂且つ特定の硬化剤の組合せが溶剤の含まないＢ−ステージ化樹脂を可能とし、バンプ付き半導体装置の組立において、ボイドの無い封止を可能とし、且つ製造工程を大幅に短縮できること見出し、本発明を完成させるに至った。   The present inventors have intensively studied on the above-mentioned solution, and in the liquid resin composition, a combination of a liquid epoxy resin and a specific epoxy resin and a specific curing agent enables a B-staged resin containing no solvent, and a bump. In the assembly of the attached semiconductor device, it has been found that sealing without voids is possible and the manufacturing process can be greatly shortened, and the present invention has been completed.

本発明の目的は、以下の（１）〜（７）に記載の本発明により達成できる。
（１）１分子あたりエポキシ基を２個以上含む２５℃で液状のエポキシ樹脂（Ａ）、１分子あたりエポキシ基を２個以上含み２５℃で固体であり且つエポキシ当量が２００以上のエポキシ樹脂（Ｂ）、芳香族カルボキシル基、芳香族水酸基をともに有し、且つ融点が１８０℃以上の硬化剤（Ｃ）を含むことを特徴とするエポキシ樹脂組成物。
（２）硬化剤（Ｃ）が、１分子あたり少なくとも２個以上の芳香族水酸基と１分子当たり少なくとも１個以上の芳香族カルボキシル基を有する化合物である請求項１記載のエポキシ樹脂組成物。
（３）請求項１〜２に記載のエポキシ樹脂組成物が更に、平均粒径が０．５μｍから１２μｍ、かつ最大粒径が５０μｍ 以下である無機フィラーを含むものであるエポキシ樹脂組成物。
（４）請求項１〜３に記載のエポキシ樹脂組成物を用いて製作された半導体装置。
（５） １）基板と電気的接合させるための半田バンプを有する多数個の半導体素子が形成されたウエハーに請求項１〜３に記載のエポキシ樹脂組成物を塗布する工程、２）該エポキシ樹脂組成物をＢ−ステージにする工程、３）該ウエハーをダイシングし、半導体素子を個片化する工程、４）個片化した半導体素子と基板と接合し同時にＢ−ステージ化したエポキシ樹脂組成物を加熱溶融させた後冷却することによる圧着工程、からなることを特徴とする半導体素子の組立方法。
（６）Ｂ−ステージ条件が１００℃以下で行なわれることを特徴とする請求項５記載の半導体素子の組立方法。
（７）エポキシ樹脂組成物を塗布する工程が、スピンコート法、印刷法、ディスペンス法のいずれかにより行われる請求項５、６記載の半導体素子の組立方法。 The object of the present invention can be achieved by the present invention described in the following (1) to (7).
(1) Epoxy resin which is liquid at 25 ° C. containing 2 or more epoxy groups per molecule (A) and epoxy resin containing 2 or more epoxy groups per molecule and solid at 25 ° C. and having an epoxy equivalent of 200 or more ( B) An epoxy resin composition comprising a curing agent (C) having both an aromatic carboxyl group and an aromatic hydroxyl group and having a melting point of 180 ° C. or higher.
(2) The epoxy resin composition according to claim 1, wherein the curing agent (C) is a compound having at least two aromatic hydroxyl groups per molecule and at least one aromatic carboxyl group per molecule.
(3) The epoxy resin composition according to claim 1 or 2, further comprising an inorganic filler having an average particle size of 0.5 μm to 12 μm and a maximum particle size of 50 μm or less.
(4) A semiconductor device manufactured using the epoxy resin composition according to any one of claims 1 to 3.
(5) 1) a step of applying the epoxy resin composition according to any one of claims 1 to 3 to a wafer on which a large number of semiconductor elements having solder bumps for electrical bonding with a substrate are formed, and 2) the epoxy resin Step of converting the composition into a B-stage, 3) Step of dicing the wafer to divide the semiconductor element, 4) Bonding the singulated semiconductor element and the substrate, and simultaneously B-staged epoxy resin composition A method of assembling a semiconductor device comprising: a pressure-bonding step by cooling after heating and melting.
(6) The method of assembling a semiconductor device according to claim 5, wherein the B-stage condition is 100 ° C. or lower.
(7) The method for assembling a semiconductor element according to claim 5 or 6, wherein the step of applying the epoxy resin composition is performed by any one of a spin coating method, a printing method, and a dispensing method.

本発明に従うと、Ｂ−ステージ後にタックフリー化が可能であり、はんだバンプ付き半導体素子の接合をボイドの無く且つ良好なはんだ接続状態の封止を実現させることができる。   According to the present invention, it is possible to make tack-free after the B-stage, and it is possible to realize a good solder connection state without voids in joining of semiconductor elements with solder bumps.

本発明に用いるエポキシ樹脂（Ａ）は2５℃で液状であり、平均エポキシ基が２以上であれば、使用することができる。その例としては、ビスフェノールＡジグリシジルエーテル型エポキシ、ビスフェノールＦジグリシジルエーテル型エポキシ、ビスフェノールＳジグリシジルエーテル型エポキシ、ｏ−アリルビスフェノールＡ型ジグリシジルエーテル、３，３’，５，５’−テトラメチル４，４’−ジヒドロキシビフェニルジグリシジルエーテル型エポキシ、４，４’−ジヒドロキシビフェニルジグリシジルエーテル型エポキシ、１，６−ジヒドロキシビフェニルジグリシジルエーテル型エポキシ、フェノールノボラック型エポキシ、臭素型クレゾールノボラック型エポキシ、ビスフェノールＤジグリシジルエーテル型エポキシ，１，６ナフタレンジオールのグリシジルエーテル、アミノフェノール類のトリグリシジルエーテル、等が挙げられる。これらは単独又は混合して用いても差し支えない。
エポキシ樹脂（Ｂ）は２５℃で固体であり、エポキシ当量が２００以上であることが必須である。１分子あたりのエポキシ基は２個以上であればかまわないが好ましくは二個である。二個以上であると、後で述べるＢ−ステージの際、硬化剤（Ｃ）との部分反応が進みすぎ、その後の接続安定性が損なわれる恐れがある。その例としては前記液状２官能エポキシ樹脂の高分子量タイプが好ましい。更にＮａ+、Ｃｌ-等のイオン性不純物はできるだけ少ないものが好ましい。
エポキシ樹脂（Ａ）とエポキシ樹脂(Ｂ)の好ましい配合量は、総仕込重量部（（Ａ）＋（Ｂ））に対する（Ａ）の割合が０．３−０．９であることが好ましい。０．９を越えるとＢ−ステージ後にタックフリーにならない恐れがあり、０．３を下回ると粘度が上がりすぎ、樹脂を塗布する際にボイドの巻き込み厚みの不均一等の問題が発生するおそれがあるからである。
エポキシ樹脂の混合方法は（Ａ）に（Ｂ）を加熱混合し溶解させる方法、（Ｂ）を微粉砕して混合させる方法何れの方法でも構わない。反応を均一に行なわせるために溶解させる方法がより好ましい。 The epoxy resin (A) used in the present invention is liquid at 25 ° C. and can be used if the average epoxy group is 2 or more. Examples include bisphenol A diglycidyl ether type epoxy, bisphenol F diglycidyl ether type epoxy, bisphenol S diglycidyl ether type epoxy, o-allyl bisphenol A type diglycidyl ether, 3,3 ′, 5,5′-tetra. Methyl 4,4'-dihydroxybiphenyl diglycidyl ether type epoxy, 4,4'-dihydroxybiphenyl diglycidyl ether type epoxy, 1,6-dihydroxybiphenyl diglycidyl ether type epoxy, phenol novolac type epoxy, bromine type cresol novolac type epoxy Bisphenol D diglycidyl ether type epoxy, 1,6-naphthalenediol glycidyl ether, aminophenol triglycidyl ether, and the like. These may be used alone or in combination.
The epoxy resin (B) is solid at 25 ° C., and it is essential that the epoxy equivalent is 200 or more. The number of epoxy groups per molecule may be two or more, but preferably two. If it is two or more, the partial reaction with the curing agent (C) proceeds excessively during the B-stage described later, and the subsequent connection stability may be impaired. For example, the high molecular weight type of the liquid bifunctional epoxy resin is preferable. Furthermore Na +, Cl - ionic impurities such as those as small as possible is preferable.
As for the preferable compounding quantity of an epoxy resin (A) and an epoxy resin (B), it is preferable that the ratio of (A) with respect to a total preparation weight part ((A) + (B)) is 0.3-0.9. If it exceeds 0.9, there is a possibility that it will not become tack-free after the B-stage, and if it is less than 0.3, the viscosity will increase excessively, and problems such as uneven void entrainment thickness may occur when resin is applied. Because there is.
The method for mixing the epoxy resin may be any method in which (B) is heated and mixed in (A) and dissolved, or (B) is finely pulverized and mixed. A method of dissolving in order to carry out the reaction uniformly is more preferable.

次に本発明に用いられる硬化剤（Ｃ）は少なくとも１個の芳香族水酸基と芳香族カルボキシル基を含むエポキシ樹脂の硬化剤であり、本質的にはんだ接合の際にフラックス活性を有することが必須の特性である。更に、融点が１８０度以上であることが必要である。１８０℃より低い融点を有する硬化剤の場合はＢ−ステージする際にエポキシ樹脂に硬化剤が溶解する量が多く、反応を制御することが困難となり、Ｂ−ステージ後の保存安定性に支障をきたす恐れがある。
更に好ましい硬化剤の例としては２個以上の芳香族水酸基を有することである。これらの条件を満たす例としては、ヒドロキシ安息香酸、ヒドロキシフタル酸、ジフェノール酸、フェノールフタリン、ジヒドロキシナフトエ酸、没食子酸などが挙げられる。これらはいすれもフラックス活性を有する。
また、Ｂ−ステージ化反応を促進するため硬化剤（Ｃ）より融点の低いポリカルボン酸を添加することも可能である。ポリカルボン酸はＢ−ステージの温度条件でエポキシ樹脂と容易に反応するため、タックフリー化をより短時間で行うことが可能となる。
また、これらの硬化剤は何れも吸湿し易くボイドの原因となるため用いる際は前もって乾燥を行うほうが好ましい。
本発明に用いるエポキシ樹脂組成物は、液状エポキシ樹脂と硬化剤の反応を促進するために硬化促進剤を添加することができる。その例としては一般的にエポキシ樹脂の硬化促進剤として用いられるものであり、イミダゾール類、リン化合物、ジアザ化合物、第三級アミン等を挙げることができる。 Next, the curing agent (C) used in the present invention is a curing agent for an epoxy resin containing at least one aromatic hydroxyl group and aromatic carboxyl group, and essentially has a flux activity at the time of soldering. It is a characteristic. Furthermore, the melting point needs to be 180 degrees or more. In the case of a curing agent having a melting point lower than 180 ° C., the amount of the curing agent dissolved in the epoxy resin is large during B-stage, making it difficult to control the reaction, and hindering storage stability after the B-stage. There is a risk of coming.
More preferable examples of the curing agent include two or more aromatic hydroxyl groups. Examples that satisfy these conditions include hydroxybenzoic acid, hydroxyphthalic acid, diphenolic acid, phenolphthaline, dihydroxynaphthoic acid, gallic acid, and the like. Both of these have flux activity.
It is also possible to add a polycarboxylic acid having a melting point lower than that of the curing agent (C) in order to promote the B-staging reaction. Since the polycarboxylic acid easily reacts with the epoxy resin under the B-stage temperature condition, tack-free can be achieved in a shorter time.
In addition, since these curing agents are easy to absorb moisture and cause voids, it is preferable to dry them before use.
In the epoxy resin composition used in the present invention, a curing accelerator can be added to accelerate the reaction between the liquid epoxy resin and the curing agent. Examples thereof are those generally used as curing accelerators for epoxy resins, and include imidazoles, phosphorus compounds, diaza compounds, tertiary amines and the like.

本発明では硬化物性を調節するため無機フィラーを添加することができる。その例としては、炭酸カルシウム、シリカ、アルミナ、窒化アルミ等が挙げられる。用途によりこれらを複数混合してもよいが、純度、信頼性、コストの点でシリカが好ましい。さらには硬化物の靭性を向上するためにカップリング剤等で予めフィラーの表面を反応、吸着処理し樹脂との密着性を強固にすることもできる。その添加量は特に制限がないが、封止用樹脂組成物としての特性（耐湿性、作業性等）を保つためエポキシ樹脂組成物の１０重量％以上、８０重量％以下であることが好ましい。より好ましくは３０重量％以上、７０重量％以下である。上限値を超えると、接合の際、絶縁性のフィラーが半導体素子のはんだ電極と回路板電極との接合を妨げるからである。下限値を越えた場合は線膨張係数が高くなるためパッケージの面積等に応じて信頼性の低下を招く恐れもある。   In the present invention, an inorganic filler can be added to adjust the cured material properties. Examples thereof include calcium carbonate, silica, alumina, aluminum nitride and the like. A plurality of these may be mixed depending on the application, but silica is preferable in terms of purity, reliability, and cost. Furthermore, in order to improve the toughness of the cured product, the surface of the filler can be reacted and adsorbed in advance with a coupling agent or the like to strengthen the adhesion to the resin. The addition amount is not particularly limited, but is preferably 10% by weight or more and 80% by weight or less of the epoxy resin composition in order to maintain the properties (humidity resistance, workability, etc.) as the sealing resin composition. More preferably, it is 30 weight% or more and 70 weight% or less. This is because if the upper limit is exceeded, the insulating filler prevents the bonding between the solder electrode of the semiconductor element and the circuit board electrode during bonding. When the lower limit is exceeded, the coefficient of linear expansion becomes high, and there is a risk that reliability will be reduced depending on the area of the package.

また本発明に無機フィラーを用いる場合、無機フィラーの形状は球状であることが好ましい。いわゆる破砕フィラーの場合はその鋭利な面により半導体素子表面の回路を破壊する恐れがあるからである。また、無機フィラーの粒径は平均粒径で０．５μｍ以上、６μｍ以下、最大粒径で３０μｍ以下が好ましい。この範囲を超えるとはんだ接合時にフィラーにより妨げられ、接続不良を起こす可能性がある。   Moreover, when using an inorganic filler for this invention, it is preferable that the shape of an inorganic filler is spherical. This is because in the case of so-called crushing filler, there is a risk of breaking the circuit on the surface of the semiconductor element due to its sharp surface. The inorganic filler preferably has an average particle size of 0.5 μm or more and 6 μm or less, and a maximum particle size of 30 μm or less. If this range is exceeded, the filler may be hindered at the time of soldering, and connection failure may occur.

本発明に用いるエポキシ樹脂組成物は、前記液状エポキシ樹脂、硬化剤、硬化促進剤、無機フィラー以外に、必要に応じて低応力剤、反応性希釈剤、顔料、染料、レベリング剤、消泡剤、カップリング剤等の添加剤を混合し、真空脱泡することにより製造することができる。これらの添加剤は何れもボイドの要因になってはならないため、耐熱性、揮発性、基材への濡れ性等確認の上添加することが好ましい。   The epoxy resin composition used in the present invention includes a low stress agent, a reactive diluent, a pigment, a dye, a leveling agent, and an antifoaming agent as necessary in addition to the liquid epoxy resin, curing agent, curing accelerator, and inorganic filler. It can be produced by mixing additives such as a coupling agent and vacuum defoaming. Any of these additives should not cause voids, so it is preferable to add them after confirming heat resistance, volatility, wettability to the substrate, and the like.

本発明のエポキシ樹脂組成物を用いて半導体素子を組み立てる方法の例としては、初めにはんだバンプが形成されたウエハー上に、前記エポキシ樹脂組成物を回路形成面のウエハー全体に塗布する(図１，２)。エポキシ樹脂組成物を塗布する方法は、印刷、ディスペンス、スピンコートが使用することができる。塗布後に樹脂をＢ−ステージ化する。その方法としては、オーブン、真空乾燥機等既存の方法を用いることができる。その場合、温度はエポキシ樹脂にフラックス作用を有する硬化剤が完全に溶解しない温度にすることが好ましい。より好ましい条件は１００℃以下である。硬化剤がＢ−ステージ中に溶解すると硬化剤中のカルボン酸とエポキシ樹脂が反応しやすくなるため、後で必須になるフラックス活性が発現しなくなり、且つ硬化剤の溶解により、Ｂ−ステージ後でも反応が徐々に進み保存安定性に支障がきたす。
次にウエハーをダイシングして素子を個片化する(図３)。次に塗布された素子を基板にフリップチップボンダーを用いてはんだバンプと対応する基板の電極とを位置決めし仮接合させる。
その場合、素子、または基板をＢ−ステージ樹脂が溶融または軟化する温度以上に加温することが好ましい。
その後、はんだの融点を越えるまで急速に温度を上昇させ、はんだを溶解させる。周囲は溶融したＢ−ステージ樹脂のフラックス活性により，はんだは基板電極に接合させることができる(図４，５)。同時にＢ−ステージ樹脂は硬化する。温度を上昇させる方法はパルスヒート、リフロー法等により行われる。パルスヒート法はフリップチップボンダー上でそのまま素子且つまたは基板を加熱する方法である。リフロー法はある温度プロファイルで制御された炉の中を一定時間通すことによりはんだを接合、樹脂を封止させる方法である。硬化が不十分な場合は接合後、後硬化（ポストベーク）を行うこともできる。 As an example of a method for assembling a semiconductor element using the epoxy resin composition of the present invention, the epoxy resin composition is applied to the entire wafer on the circuit forming surface on a wafer on which solder bumps are first formed (FIG. 1). , 2). Printing, dispensing, and spin coating can be used as a method of applying the epoxy resin composition. After application, the resin is B-staged. As the method, an existing method such as an oven or a vacuum dryer can be used. In that case, the temperature is preferably set to a temperature at which the curing agent having a flux action in the epoxy resin is not completely dissolved. More preferable conditions are 100 ° C. or lower. When the curing agent is dissolved in the B-stage, the carboxylic acid in the curing agent and the epoxy resin are likely to react with each other, so that the flux activity that becomes essential later does not appear, and even after the B-stage due to the dissolution of the curing agent. The reaction progresses gradually and the storage stability is hindered.
Next, the wafer is diced to separate the elements (FIG. 3). Next, the applied element is positioned and temporarily joined to the substrate by using a flip chip bonder to position the solder bump and the corresponding substrate electrode.
In that case, it is preferable that the element or the substrate is heated to a temperature higher than the temperature at which the B-stage resin is melted or softened.
Thereafter, the temperature is rapidly increased until the melting point of the solder is exceeded, and the solder is melted. Due to the flux activity of the melted B-stage resin, the solder can be bonded to the substrate electrode (FIGS. 4 and 5). At the same time, the B-stage resin is cured. The method for raising the temperature is performed by pulse heat, reflow method or the like. The pulse heat method is a method of heating an element and / or a substrate as it is on a flip chip bonder. The reflow method is a method of joining solder and sealing resin by passing through a furnace controlled by a certain temperature profile for a certain period of time. When the curing is insufficient, post-curing (post-baking) can be performed after joining.

当該エポキシ樹脂組成物の用途としては前記例の様なはんだ付半導体素子の接合および封止だけでなく、公知であるリードフレームへの半導体素子の接着、チップが積層されたスタックドパッケージのチップ−チップ間の接合等にも応用することもできる。 Applications of the epoxy resin composition include not only bonding and sealing of soldered semiconductor elements as in the above examples, but also known semiconductor chip adhesion to lead frames, stacked package chips with stacked chips, It can also be applied to bonding between chips.

本発明を実施例及び比較例で説明する。
＜実施例１＞
エポキシ樹脂（Ａ）として２５℃で液状のビスフェノールＦ型エポキシ樹脂（エポキシ当量１６５）６０重量部、エポキシ樹脂（Ｂ）として２５℃で固形のビスフェノールＡ型エポキシ樹脂（エポキシ当量４５０）４０重量部を１００℃にて均一溶解させた液状エポキシ樹脂混合物中に、硬化剤（Ｃ）として２，５−ジヒドロキシ安息香酸(融点２０２℃)２０重量部、硬化促進剤として２−フェニル−４−メチルイミダゾール０．２重量部を秤量し３本ロールにて分散混練し、真空下脱泡処理をしてエポキシ樹脂組成物を得た。次に、回路及びはんだバンプ（Ｓｎ−Ａｇ−Ｃｕ、高さ80μm）が具備された6インチのウエハー上に前記エポキシ樹脂組成物を印刷法にて９０ミクロンの厚みで塗布し、Ｂ−ステージ条件として９０℃、６０分部分硬化させた。硬化物はタックフリーであった。つぎにダイシングにて、１０ｍｍ角の半導体素子に個片化し、回路面にＢ−ステージ化した樹脂が塗布された素子を得た。上部よりフリップチップボンダーを用いて位置決めを行いながら融点２２１℃のＳｎ−Ａｇ系はんだが具備されたフリップチップを設置した。その際、フリップチップは約８０℃に加温させておいた。次に最大温度２４５℃を５秒間保持するような温度プロファイルを用いてはんだを溶融、接続を行った。合否の判定は接続率、ボイドの有無を10個の素子で行った。 The present invention will be described with reference to examples and comparative examples.
<Example 1>
As epoxy resin (A), liquid bisphenol F type epoxy resin (epoxy equivalent 165) 60 parts by weight at 25 ° C., and epoxy resin (B) 40 parts by weight solid bisphenol A type epoxy resin (epoxy equivalent 450) at 25 ° C. In a liquid epoxy resin mixture uniformly dissolved at 100 ° C., 20 parts by weight of 2,5-dihydroxybenzoic acid (melting point 202 ° C.) as a curing agent (C) and 2-phenyl-4-methylimidazole as a curing accelerator 0 .2 parts by weight were weighed and dispersed and kneaded with three rolls, and defoamed under vacuum to obtain an epoxy resin composition. Next, the epoxy resin composition was applied by a printing method to a thickness of 90 microns on a 6-inch wafer equipped with circuits and solder bumps (Sn-Ag-Cu, height 80 μm), and B-stage conditions were applied. As 90 ° C. for 60 minutes. The cured product was tack free. Next, a 10 mm square semiconductor element was diced by dicing, and an element having a circuit surface coated with a B-staged resin was obtained. A flip chip equipped with Sn—Ag solder having a melting point of 221 ° C. was placed while positioning from above using a flip chip bonder. At that time, the flip chip was heated to about 80 ° C. Next, the solder was melted and connected using a temperature profile that kept the maximum temperature of 245 ° C. for 5 seconds. The pass / fail judgment was made with 10 elements for connection rate and presence / absence of voids.

使用した半導体素子
バンプ数：４００
バンプ高さ：８０μｍ
チップサイズ：１０ｍｍ角
パッシベーション：ポリイミド
チップ厚み：５００μｍ
使用した基板：ＢＴ基板（接続パッド：金メッキ表面）
回路設計：デイジーチェーンにてすべてのバンプが電気的に繋がり接続性を確認できる仕様 Number of semiconductor element bumps used: 400
Bump height: 80μm
Chip size: 10 mm square Passivation: Polyimide chip thickness: 500 μm
Substrate used: BT substrate (connection pad: gold-plated surface)
Circuit design: Specification that all bumps are electrically connected in a daisy chain and connectivity can be confirmed.

（１）接続性試験（サンフ゜ル数10個/水準）
接続性はデイジーチェーンでつながった回路に対しテスターを用いて導通性を確認した。
（２）ボイド試験（サンプル数１０個/水準）
接続試験を行なったサンプルを超音波探傷装置によりボイドの有無を確認した。
（３）ライフ試験(サンプル数5個/水準)
Ｂ−ステージ化された樹脂が塗布された個片化した素子を25℃で一ヶ月保管したとき前記（１）、（２）の試験を行った。 (1) Connectivity test (10 samples / level)
The connectivity was confirmed using a tester for the circuit connected by daisy chain.
(2) Void test (10 samples / level)
The samples subjected to the connection test were checked for the presence of voids using an ultrasonic flaw detector.
(3) Life test (5 samples / level)
When the separated element coated with the B-staged resin was stored at 25 ° C. for one month, the tests (1) and (2) were performed.

＜実施例２＞
エポキシ樹脂（Ａ）として２５℃で液状のビスフェノールＦ型エポキシ樹脂（エポキシ当量１６５）５０重量部、エポキシ樹脂（Ｂ）として２５℃で固形のビフェニルアラルキル型エポキシ樹脂（エポキシ当量２７５、商品名ＮＣ−３０００/日本化薬工業社製）５０重量部を１００℃にて均一溶解させた液状エポキシ樹脂混合物中に、硬化剤（Ｃ）として２，５−ジヒドロキシ安息香酸(融点２０２℃)２０重量部、硬化促進剤として２−フェニル−４−メチルイミダゾール０．２重量部を秤量し３本ロールにて分散混練し、真空下脱泡処理をしてエポキシ樹脂組成物を得た。次に、回路及びはんだバンプ（Ｓｎ−Ａｇ−Ｃｕ、高さ80μm）が具備された6インチのウエハー上に前記エポキシ樹脂組成物を印刷法にて塗布し、Ｂ−ステージ条件として９０℃、６０分部分硬化させた。硬化物はタックフリーであった。つぎにダイシングにて、１０ｍｍ角の半導体素子に個片化し、回路面にＢ−ステージ化した樹脂が塗布された素子を得た。上部よりフリップチップボンダーを用いて位置決めを行いながら融点２２１℃のＳｎ−Ａｇ系はんだが具備されたフリップチップを設置した。その際、フリップチップは約８０℃に加温させておいた。次に最大温度２４５℃を５秒間保持するような温度プロファイルを用いてはんだを溶融、接続を行った。合否の判定は接続率、ボイドの有無を10個の素子で行った。 <Example 2>
50 parts by weight of a bisphenol F type epoxy resin (epoxy equivalent 165) which is liquid at 25 ° C. as an epoxy resin (A), and a biphenyl aralkyl type epoxy resin (epoxy equivalent 275, trade name NC-) which is solid at 25 ° C. as an epoxy resin (B) 3000 / Nippon Kayaku Kogyo Co., Ltd.) in a liquid epoxy resin mixture in which 50 parts by weight are uniformly dissolved at 100 ° C., 20 parts by weight of 2,5-dihydroxybenzoic acid (melting point 202 ° C.) as a curing agent (C), As a curing accelerator, 0.2 part by weight of 2-phenyl-4-methylimidazole was weighed and dispersed and kneaded with three rolls, and defoamed under vacuum to obtain an epoxy resin composition. Next, the epoxy resin composition was applied by a printing method onto a 6-inch wafer provided with circuits and solder bumps (Sn—Ag—Cu, height 80 μm), and B-stage conditions were 90 ° C., 60 Partially cured. The cured product was tack free. Next, a 10 mm square semiconductor element was diced by dicing, and an element having a circuit surface coated with a B-staged resin was obtained. A flip chip equipped with Sn—Ag solder having a melting point of 221 ° C. was placed while positioning from above using a flip chip bonder. At that time, the flip chip was heated to about 80 ° C. Next, the solder was melted and connected using a temperature profile that kept the maximum temperature of 245 ° C. for 5 seconds. The pass / fail judgment was made with 10 elements for connection rate and presence / absence of voids.

＜実施例３＞
実施例１において、Ｂ−ステージ条件を１２０℃、４５分(タックフリー化)とした以外は同様に試験を行った。 <Example 3>
The test was conducted in the same manner as in Example 1 except that the B-stage conditions were 120 ° C. and 45 minutes (tack-free).

＜比較例１＞
エポキシ樹脂（Ａ）として２５℃で液状のビスフェノールＦ型エポキシ樹脂（エポキシ当量１６５）１００重量部中に、硬化剤（Ｃ）として２，５−ジヒドロキシ安息香酸(融点２０２℃)２５重量部、硬化促進剤として２−フェニル−４−メチルイミダゾール０．２重量部を秤量し３本ロールにて分散混練し、真空下脱泡処理をしてエポキシ樹脂組成物を得た。次に、回路及びはんだバンプ（Ｓｎ−Ａｇ−Ｃｕ、高さ80μm）が具備された6インチのウエハー上に前記エポキシ樹脂組成物を印刷法にて塗布し、Ｂ−ステージ条件として９０℃、６０分部分硬化させた１時間としたところＢ−ステージ物はタックフリーになった。その後実施例１と同様の試験を行った。 <Comparative Example 1>
25 parts by weight of 2,5-dihydroxybenzoic acid (melting point 202 ° C.) as curing agent (C) in 100 parts by weight of bisphenol F type epoxy resin (epoxy equivalent 165) which is liquid at 25 ° C. as epoxy resin (A) As an accelerator, 0.2 part by weight of 2-phenyl-4-methylimidazole was weighed and dispersed and kneaded with three rolls, and defoamed under vacuum to obtain an epoxy resin composition. Next, the epoxy resin composition was applied by a printing method onto a 6-inch wafer provided with circuits and solder bumps (Sn—Ag—Cu, height 80 μm), and B-stage conditions were 90 ° C., 60 The B-stage product became tack-free after 1 hour of partial curing. Thereafter, the same test as in Example 1 was performed.

＜比較例２＞
エポキシ樹脂（Ｂ）として２５℃で固形のフェノールノボラック型エポキシ樹脂（エポキシ当量１９０）２００重量部を溶剤としてブチロセロソルブアセテートを６０重量部加え５０℃で均一に樹脂を溶解させたワニス１３０重量部、硬化剤（Ｃ）として２，５−ジヒドロキシ安息香酸２５重量部、硬化促進剤として２−フェニル−４−メチルイミダゾール０．２重量部を秤量し３本ロールにて分散混練し、真空下脱泡処理をしてエポキシ樹脂組成物を得た。次に、回路及びはんだバンプ（Ｓｎ−Ａｇ−Ｃｕ、高さ80μm）が具備された6インチのウエハー上に前記エポキシ樹脂組成物を印刷法にて塗布し、Ｂ−ステージ条件として９０℃、６０分部分硬化させた。Ｂ−ステージ物はタックフリーになった。その後実施例１と同様の試験を行った。 <Comparative example 2>
130 parts by weight of varnish obtained by adding 60 parts by weight of butyrocellosolve acetate as a solvent with 200 parts by weight of a phenol novolac type epoxy resin (epoxy equivalent 190) solid at 25 ° C. as an epoxy resin (B), and dissolving the resin uniformly at 50 ° C. Then, 25 parts by weight of 2,5-dihydroxybenzoic acid as a curing agent (C) and 0.2 parts by weight of 2-phenyl-4-methylimidazole as a curing accelerator were weighed and dispersed and kneaded with a three-roll, and then removed under vacuum. Foam treatment was performed to obtain an epoxy resin composition. Next, the epoxy resin composition was applied by a printing method onto a 6-inch wafer provided with circuits and solder bumps (Sn—Ag—Cu, height 80 μm), and B-stage conditions were 90 ° C., 60 Partially cured. B-Stage thing became tack free. Thereafter, the same test as in Example 1 was performed.

Figure 2006008755
Figure 2006008755

実施例１，２は良好な接続性ボイド性が。実施例３はＢ−ステージ条件が厳しいため、高化剤の溶解が進み保存性にやや劣る結果となった。
比較例１はタックフリー化するためにＢ−ステージ温度を上げたため更に液状エポキシ樹脂との組合せのため樹脂硬化剤の溶解が実施例３に比べ進んだため、フラックス活性が初期から低下した。比較例２は溶剤系のため残存溶媒の影響でボイド不良が発生した。 Examples 1 and 2 have good connectivity voids. In Example 3, because the B-stage conditions were severe, dissolution of the accelerating agent progressed and the storage stability was slightly inferior.
In Comparative Example 1, since the B-stage temperature was raised in order to make tack-free, the melting of the resin curing agent proceeded more than in Example 3 due to the combination with the liquid epoxy resin, and the flux activity decreased from the beginning. Since Comparative Example 2 was a solvent system, void defects occurred due to the influence of the residual solvent.

本発明のエポキシ樹脂組成物は、Ｂ−ステージ且つフラックス活性を有するためはんだ接合性を必要とされる用途、更に作業性を大幅に改善できる特性を有するため、半導体封止用樹脂、半導体固定用樹脂、半導体接着用樹脂、ＬＥＤなどの半導体を用いる表示素子などに用いられる。 The epoxy resin composition of the present invention has a B-stage and flux activity, and therefore has a characteristic that can greatly improve the workability because of its use requiring solder jointability. It is used for display elements using semiconductors such as resins, semiconductor bonding resins, and LEDs.

図１は、バンプ付ウエハーの断面図を示す。FIG. 1 shows a cross-sectional view of a bumped wafer.

図２は、エポキシ樹脂組成物を塗布したウエハーの断面図を示す。FIG. 2 shows a cross-sectional view of a wafer coated with an epoxy resin composition.

図３は、Ｂ−ステージ化後ウエハーから個片化した半導体素子の断面図を示す。FIG. 3 shows a cross-sectional view of a semiconductor element separated from a wafer after B-stage formation.

図４は、個片化した素子をフリップチップボンダーにて接合、封止を行う工程を示す。FIG. 4 shows a process of joining and sealing the separated elements with a flip chip bonder.

図５は、個片化した素子をフリップチップボンダーにて接合、封止を行う工程を示す。FIG. 5 shows a process of joining and sealing the separated elements with a flip chip bonder.

符号の説明Explanation of symbols

１ はんだバンプ
２ ウエハー
３ エポキシ樹脂組成物
４ 基板
５ フリッフ゜チッフ゜ホ゛ンタ゛ー固定冶具
６ 熱板 1 Solder bump 2 Wafer 3 Epoxy resin composition 4 Substrate 5 Flip chip bonder fixing jig 6 Hot plate

Claims (7)

１分子あたりエポキシ基を２個以上含む２５℃で液状のエポキシ樹脂（Ａ）、１分子あたりエポキシ基を２個以上含み２５℃で固体であり且つエポキシ当量が２００以上のエポキシ樹脂（Ｂ）、芳香族カルボキシル基、芳香族水酸基をともに有し、且つ融点が１８０℃以上の硬化剤（Ｃ）を含むことを特徴とするエポキシ樹脂組成物。 An epoxy resin (A) which is liquid at 25 ° C. containing two or more epoxy groups per molecule (B), an epoxy resin (B) which is solid at 25 ° C. and contains two or more epoxy groups per molecule and has an epoxy equivalent of 200 or more, An epoxy resin composition comprising a curing agent (C) having both an aromatic carboxyl group and an aromatic hydroxyl group and having a melting point of 180 ° C. or higher. 硬化剤（Ｃ）が、１分子あたり少なくとも２個以上の芳香族水酸基と１分子当たり少なくとも１個以上の芳香族カルボキシル基を有する化合物である請求項１記載のエポキシ樹脂組成物。 The epoxy resin composition according to claim 1, wherein the curing agent (C) is a compound having at least two aromatic hydroxyl groups per molecule and at least one aromatic carboxyl group per molecule. 請求項１〜２に記載のエポキシ樹脂組成物が更に、平均粒径が０．５μｍから１２μｍ、かつ最大粒径が５０μｍ 以下である無機フィラーを含むものであるエポキシ樹脂組成物。 The epoxy resin composition according to claim 1 or 2, further comprising an inorganic filler having an average particle size of 0.5 to 12 µm and a maximum particle size of 50 µm or less. 請求項１〜３に記載のエポキシ樹脂組成物を用いて製作された半導体装置。 A semiconductor device manufactured using the epoxy resin composition according to claim 1. １）基板と電気的接合させるための半田バンプを有する多数個の半導体素子が形成されたウエハーに請求項１〜３に記載のエポキシ樹脂組成物を塗布する工程、２）該エポキシ樹脂組成物をＢ−ステージにする工程、３）該ウエハーをダイシングし、半導体素子を個片化する工程、４）個片化した半導体素子と基板と接合し同時にＢ−ステージ化したエポキシ樹脂組成物を加熱溶融させた後冷却することによる圧着工程、からなることを特徴とする半導体素子の組立方法。 1) a step of applying the epoxy resin composition according to any one of claims 1 to 3 to a wafer on which a plurality of semiconductor elements having solder bumps for electrical bonding with a substrate are formed; 2) the epoxy resin composition; B-stage process, 3) the wafer is diced, and the semiconductor element is separated into individual pieces. 4) The separated semiconductor element and the substrate are bonded to the B-stage and heated and melted at the same time. A method of assembling a semiconductor device comprising: a crimping step by cooling after cooling. Ｂ−ステージ条件が１００℃以下で行なわれることを特徴とする請求項５記載の半導体素子の組立方法。 6. The method of assembling a semiconductor device according to claim 5, wherein the B-stage condition is 100 [deg.] C. or less. エポキシ樹脂組成物を塗布する工程が、スピンコート法、印刷法、ディスペンス法のいずれかにより行われる請求項５、６記載の半導体素子の組立方法。 7. The method for assembling a semiconductor element according to claim 5, wherein the step of applying the epoxy resin composition is performed by any one of a spin coating method, a printing method, and a dispensing method.
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